Dual-chip architecture screen projection method, vehicle, equipment and readable storage medium

Abstract

The invention provides a dual-chip architecture screen projection method, a vehicle, a system and a readable storage medium. The method comprises the following steps: writing picture data into a shared storage area; the shared storage area is used for a first chip to write the picture data and a second chip to read the picture data; the picture data is used for a second chip to determine a to-be-displayed target picture of a target display screen controlled by the second chip; generating a write-in completion message and sending the write-in completion message to the second chip; and the second chip is used for receiving and responding to the write-in completion message, reading the picture data in the shared storage area, and controlling the target display screen to display the target picture according to the picture data. According to the invention, the screen projection efficiency of the dual-chip architecture is improved.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of vehicle technology, and in particular, to a dual-chip architecture screen projection method, a vehicle, an electronic device, and a computer-readable storage medium. Background Art

[0002] The vehicle can provide navigation, entertainment, driving assistance and other functions. Different functions are provided by operating systems on different chips and displayed on different screens. For example, the Android system of chip 1 provides entertainment functions on the central control screen, and the QNX system (Quick Unix) of chip 2 displays the vehicle status on the instrument screen. In some scenarios, it is necessary to project the screen to the display controlled by the operating system of other chips.

[0003] In the related art, if the current operating system needs to project the screen onto a display screen corresponding to another operating system, the display screen is operated directly.

[0004] However, in the related art, if you want to directly operate the display screen corresponding to another operating system, cross-system communication is required, which leads to large delays and low screen projection efficiency. Summary of the invention

[0005] In view of the above problems, the embodiments of the present disclosure are proposed to provide a dual-chip architecture screen projection method, vehicle, electronic device and computer-readable storage medium that overcome the above problems or at least partially solve the above problems.

[0006] In a first aspect, an embodiment of the present disclosure discloses a dual-chip architecture screen projection method, the method comprising:

[0007] Writing screen data into a shared storage area; the shared storage area is used for the first chip to write the screen data and for the second chip to read the screen data; the screen data is used for the second chip to determine a target screen to be displayed on a target display screen controlled by the second chip;

[0008] A write completion message is generated and sent to the second chip; the second chip is used to receive and respond to the write completion message, read the screen data in the shared storage area, and control the target display screen to display the target screen according to the screen data.

[0009] In a second aspect, the present disclosure discloses a dual-chip architecture screen projection method, the method comprising:

[0010] receiving a write completion message sent by the first chip; the first chip is used to generate the write completion message after writing the screen data into the shared storage area;

[0011] In response to the write completion message, the screen data is read from the shared storage area; the screen data is used by the second chip to determine a target screen to be displayed on a target display screen controlled by the second chip;

[0012] The target display screen is controlled to display the target picture.

[0013] In a third aspect, an embodiment of the present disclosure discloses a vehicle, the vehicle comprising a first chip and a second chip;

[0014] The first chip is used to implement the steps of the dual-chip architecture screen projection method as described in the first aspect.

[0015] The second chip is used to implement the steps of the dual-chip architecture screen projection method as described in the second aspect.

[0016] In a fourth aspect, an embodiment of the present disclosure further discloses an electronic device, comprising a processor and a memory, wherein the memory stores programs or instructions that can be run on the processor, and when the programs or instructions are executed by the processor, the steps of the dual-chip architecture screen projection method described in the first aspect and the second aspect are implemented.

[0017] In a fourth aspect, an embodiment of the present disclosure further discloses a computer-readable storage medium, on which a program or instruction is stored. When the program or instruction is executed by a processor, the steps of the dual-chip architecture screen projection method as described in the first aspect and the second aspect are implemented.

[0018] In the disclosed embodiment, the first chip can write screen data to the shared storage area, generate a write completion message and send it to the second chip, the second chip receives and responds to the write completion message, reads the screen data in the shared storage area, and the second chip can then display the target screen corresponding to the screen data on the target display screen. The first chip can directly transfer the screen data to the second chip through the shared storage area, and the second chip directly controls the target display screen based on the screen data to display the target screen. If the first chip controls the target display screen, it is also necessary to perform cumbersome interactions with the second chip so that the first chip can start controlling the target display screen. Therefore, writing and reading based on the shared storage area effectively avoids the cross-system interaction process, and the second chip controls its corresponding target display screen, which reduces the control delay and ultimately improves the screen projection efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 This is a step diagram of a dual-chip architecture screen projection method provided by an embodiment of the present disclosure;

[0020] Figure 2 is a schematic diagram of a video memory and a shared storage area provided by an embodiment of the present disclosure;

[0021] Figure 3 It is a step diagram of another dual-chip architecture screen projection method provided by an embodiment of the present disclosure;

[0022] Figure 4 This is a step diagram of another dual-chip architecture screen projection method provided by an embodiment of the present disclosure;

[0023] Figure 5 is a schematic diagram of a vehicle provided by an embodiment of the present disclosure;

[0024] Figure 6 It is a block diagram of a dual-chip architecture screen projection device provided by an embodiment of the present disclosure;

[0025] Figure 7 is a block diagram of another dual-chip architecture screen projection device provided by an embodiment of the present disclosure;

[0026] Figure 8 It is a block diagram of an electronic device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0027] The exemplary embodiments of the present application will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0028] With the rapid development of technologies such as intelligent driving and vehicle networking, cars need more powerful computing capabilities and richer functions to support the application of these emerging technologies. In order to meet this demand, dual system-on-chip (SOC) architecture has begun to be adopted.

[0029] The dual SOC architecture integrates two independent chips, each of which is responsible for different tasks. One chip is used to run the in-vehicle entertainment system, navigation system and other basic functions, while the other chip is dedicated to processing complex tasks such as the Advanced Driving Assistance System (ADAS) and artificial intelligence algorithms.

[0030] Among them, the Android system (operating system) is usually used to run basic functions such as in-vehicle entertainment systems and navigation systems due to its wide application support and user-friendly interface design. The QNX system (operating system) is more suitable for processing complex real-time tasks and advanced algorithms such as autonomous driving, image recognition and voice control.

[0031] Different systems use their own screens to interact with users, but due to the needs of some business scenarios, some screen data of the Android system needs to be projected onto the screen of the QNX system. For example, since the QNX system does not have native applications related to map navigation, it is necessary to project the navigation-related screen data of the Android system onto the display screen of the QNX system.

[0032] In the related technology, the Android system directly operates the display screen of the QNX system, but before the Android system operates the display screen of the QNX system, the Android system needs to perform specific communication interactions with the QNX system so that the Android system can determine to start controlling the display screen of the QNX system. This interaction process involves cross-system communication, resulting in a large delay, which in turn leads to low screen projection efficiency.

[0033] Figure 1 : is a step diagram of a dual-chip architecture screen projection method provided by an embodiment of the present disclosure, the method comprising:

[0034] Step 101, write screen data into a shared storage area; the shared storage area is used for the first chip to write the screen data and for the second chip to read the screen data; the screen data is used for the second chip to determine the target screen to be displayed on the target display screen controlled by the second chip.

[0035] In an embodiment of the present disclosure, the steps of the dual-chip architecture screen projection method can be executed by the first chip corresponding to the first system, and the first system runs on the first chip. The first system can refer to an Android system, a QNX system, or other operating systems, and the second system can also refer to an Android system, a QNX system, or other operating systems. The second system runs on the second chip, and the first system and the second system can be different. It is understandable that the total number of chips or operating systems can be more than two, for example, three or four, but when screen projection is required between any two different operating systems, the steps of the dual-chip architecture screen projection method disclosed in the present disclosure are applicable.

[0036] Video Memory, also called Frame Buffer, is used to store rendering data that has been processed or is about to be extracted by the graphics processing unit (GPU).

[0037] An application may be made to the GPU to hold the video memory, thereby determining a specific storage area in the video memory. The storage area may be written by the first chip and read by the second chip, so the storage area is a shared storage area.

[0038] Figure 2It is a schematic diagram of the video memory and the shared storage area provided by the embodiment of the present disclosure; in the video memory 20, several storage areas 201 may be included, and the applied storage area 201 is a shared storage area.

[0039] The size of the shared memory area can be set directly or determined according to the size of the picture data. For a screen with a resolution of 1920×1080, each pixel may require 32 bits (4 bytes) to store information such as color, and one frame of image requires 1920×1080×4 bytes of video memory space, that is, 8MB of video memory.

[0040] The first chip or the first system may also control a corresponding display screen. Generally, the first system only needs to use the display screen for display.

[0041] The first chip can write screen data to the shared storage area, and the second chip can read the screen data written by the first chip in the shared storage area. The screen data includes the screen content that needs to be projected to the target display screen.

[0042] The second chip controls the target display screen. Generally, the second system on the second chip uses the target display screen to display the screen it needs. The second system on the second chip can determine the target screen to be displayed on the target display screen according to the read screen data.

[0043] Step 102, generating a write completion message and sending it to the second chip; the second chip is used to receive and respond to the write completion message, read the screen data in the shared storage area, and control the target display screen to display the target screen according to the screen data.

[0044] In the disclosed embodiment, the screen data can be written to the shared storage area, and after the writing is completed, a write completion message can be generated and sent to the second chip to notify the second chip running the second system that it can start reading the data in the shared storage area.

[0045] The second chip receives the write completion message and responds, reads the screen data in the shared storage area, and displays the target screen corresponding to the screen data on the target display screen.

[0046] It is understandable that after acquiring the screen data, the second system running on the second chip can make a judgment based on its own business needs to determine whether it is necessary to control the target display screen to display the corresponding content based on the screen data, or to control the target display screen to display the corresponding content based on only part of the screen data. That is, the second system does not have to control the target display screen based on all the screen data.

[0047] In summary, in the disclosed embodiment, the first chip can write screen data to the shared storage area, generate a write completion message and send it to the second chip, the second chip receives and responds to the write completion message, reads the screen data in the shared storage area, and the second chip can then display the target screen corresponding to the screen data on the target display screen. The first chip can directly transfer the screen data to the second chip through the shared storage area, and the second chip directly controls the target display screen based on the screen data to display the target screen. If the first chip controls the target display screen, it is also necessary to perform cumbersome interactions with the second chip so that the first chip can start controlling the target display screen. Therefore, writing and reading based on the shared storage area effectively avoids the cross-system interaction process, and the second chip controls its corresponding target display screen, which reduces the control delay and ultimately improves the screen projection efficiency.

[0048] refer to Figure 3 , which shows a step diagram of a dual-chip architecture screen projection method provided by an embodiment of the present disclosure, the method comprising:

[0049] Step 301, writing screen data into a shared storage area; the shared storage area is used for the first chip to write the screen data and for the second chip to read the screen data; the screen data is used for the second chip to determine the target screen to be displayed on the target display screen controlled by the second chip;

[0050] Step 302, generate a write completion message and send it to the second chip; the second chip is used to receive and respond to the write completion message, read the screen data in the shared storage area, and control the target display screen to display the target screen according to the screen data.

[0051] The above steps 301-302 can refer to the above Figure 1 The contents of the embodiments will not be described in detail here.

[0052] A storage area used to store data. Data must first be written to the storage area before it can be read. During this process, the specific status of the storage area must be clarified, such as whether data can be written, whether data is being written, whether writing is complete and can be read, otherwise the data interaction process will be confused or erroneous.

[0053] Optionally, the method further includes:

[0054] Step A, determining a pre-built shared management object; the shared management object includes storage area information of the shared storage area and state parameters associated with the storage area information;

[0055] The state parameter is a first parameter indicating that the corresponding shared storage area is in an idle state;

[0056] The state parameter is a second parameter indicating that the corresponding shared storage area is in a write state;

[0057] The state parameter is the third parameter indicating that the corresponding shared storage area is in a read state.

[0058] In the disclosed embodiment, a shared management object may be pre-constructed based on a successfully applied shared storage area. The shared management object may be constructed after a device with a dual-chip architecture is started and operated. The shared management object may be used throughout the operation of the device, and a new shared management object may be reconstructed after the device is restarted.

[0059] Constructing a shared management object can be achieved by instantiating a cache pool object. The cache pool is a container for storing a shared storage area (buffer). Instantiation is the process of creating an object of a class. A cache pool entity can be created in the video memory according to the definition of the cache pool class. The cache pool object can have the properties and methods defined in the class and can be operated and used.

[0060] The buffer pool object can be implemented as an array with {buffer, status} structures as units, where buffer represents the storage area information corresponding to the shared storage area, such as the identification, number or address of the storage area, etc. The storage area information can be used to identify the shared storage area.

[0061] Status is a status parameter, which can be used to indicate the current status of the buffer, such as whether it is available, whether it is being written, or whether it can be read. If the status parameter is the first parameter, it means that the corresponding shared storage area is in an idle state; if the status parameter is the second parameter, it means that the corresponding shared storage area is in a write state; if the status parameter is the first parameter, it means that the corresponding shared storage area is in a read state. The specific contents of the first parameter, the second parameter, and the third parameter are not limited here, as long as they can achieve the distinction.

[0062] The idle state indicates that the corresponding shared storage area can be written with data. The shared storage area that has just been successfully applied for is in the idle state. The write state indicates that the first chip is writing data to the corresponding shared storage area. The read state indicates that the first chip has completed writing and is waiting for the second chip to read.

[0063] In implementing the embodiments of the present disclosure, a shared management object is constructed based on the shared storage area. The shared management object includes storage area information of the shared storage area and status parameters associated with the storage area information. Different status parameters can represent the specific status of the shared storage area, thereby providing a basis for the data interaction process, avoiding confusion or errors in the data interaction process, and improving the accuracy and efficiency of data interaction.

[0064] During the data interaction process, the state of the shared storage area should be related to the specific operation of the data interaction and needs to be consistent with the actual data interaction operation, otherwise it will cause confusion or errors in the data interaction process.

[0065] Optionally, there are multiple shared storage areas; the step 301 of writing the screen data into the shared storage area includes:

[0066] Sub-step 3011, traversing the shared management object, and taking the first storage area information associated with the first parameter found during traversal as the target storage area information;

[0067] Sub-step 3012, setting the first parameter of the target storage area information as the second parameter, and writing the screen data to the target shared storage area pointed to by the target storage area information;

[0068] Sub-step 3013: setting the second parameter of the target storage area information to a third parameter, so that the target shared storage area is in the read state.

[0069] In the disclosed embodiment, there may be multiple shared storage areas, and since not every shared storage area may be idle for the first chip to write data, it is necessary to traverse the shared management object, for example, traverse an array with {buffer, status} structures as units.

[0070] The first storage area information associated with the first parameter is used as the target storage area information, that is, the first status parameter status which is the first parameter is searched, and then the target shared storage area information is determined. The target shared storage area information can be used to determine the target shared storage area.

[0071] After determining the target shared storage area, data can be written. The first parameter of the target storage area information needs to be set to the second parameter, indicating that the target shared storage area is in a writing state, and the screen data is written to the target shared storage area.

[0072] After the screen data is written, the second parameter of the target storage area information needs to be set to the third parameter, indicating that the target shared storage area is in a read state, and the second system can read the target shared storage area.

[0073] In the implementation of the embodiment of the present disclosure, by traversing the shared management object, the first storage area information associated with the first parameter is used as the target storage area information, the first parameter of the target storage area information is set as the second parameter, the screen data is written to the target shared storage area pointed to by the target storage area information, and the second parameter of the target storage area information is set as the third parameter, so that the second series chip reads the target shared storage area. The state parameters of the shared storage area can be adjusted in real time according to the data writing status of the first chip, ensuring the orderliness of the data writing process and the accuracy of the state parameters.

[0074] When there are multiple shared storage areas, the first chip has many options for writing to the shared storage areas, resulting in uncertainty in the shared storage area that actually stores the screen data, which may cause the second system to be unable to obtain the screen data, resulting in data interaction failure and screen projection failure.

[0075] Optionally, there are multiple shared storage areas; the step 302 of generating a write completion message and sending it to the second chip includes:

[0076] Sub-step 3021, determining the shared storage area where the screen data is written as the target shared storage area;

[0077] Sub-step 3022, determining a write address according to address information of the target shared storage area in the video memory;

[0078] Sub-step 3023, generating a write completion message carrying the write address, and sending the write completion message to the second chip; the second chip is used to read the target shared storage area according to the write address.

[0079] In the disclosed embodiment, there are multiple shared storage areas, such as 3, 4, 5 or other numbers, and the first chip can clearly read which shared storage area is the target shared storage area where the data is written. Then, the write address when writing the picture data can be determined according to the address information of the shared storage area in the video memory.

[0080] The write address can be added when generating the write completion message, so that the write completion message can carry the write address. After receiving the write completion message, the second chip determines the target shared storage area among the multiple shared storage areas according to the write address in the write completion message, and starts to read the target shared storage area.

[0081] It is understandable that, when there are multiple shared storage areas, each shared storage area may also have a corresponding identifier such as a number, and the number may be carried in the write completion message, and the target shared storage area storing the screen data may also be accurately determined. Other methods may also be used to distinguish the location where the screen data is written, which is not limited here.

[0082] In implementing the embodiments of the present disclosure, a shared storage area into which screen data is written is determined as a target shared storage area, a write address is determined based on address information of the target shared storage area in the video memory, a write completion message carrying the write address is generated and sent to a second chip, and the second chip reads the target shared storage area based on the write address, thereby accurately reading the display area in multiple shared storage areas, thereby improving the accuracy of screen data acquisition.

[0083] Although there are multiple shared storage areas, the screen data that the first chip needs to write may be greater than or much greater than the sum of the storage capacities of the multiple shared storage areas, which will cause the screen data to be unable to be written correctly or completely, leading to screen projection problems.

[0084] Optionally, the method further includes:

[0085] In the case where the second chip returns a read completion message, obtaining a read address carried in the read completion message; the read completion message is generated by the second chip after the read is completed based on the address information of the read storage area;

[0086] The read address is compared with the write address, and when the read address is consistent with the write address, the target shared storage area is updated to an idle state.

[0087] In the disclosed embodiment, the second chip can return a read completion message to the first chip after the read is completed. Similar to the write completion message, the write completion message carries the write address of the data write location, and the read completion message can also carry the read address of the data read location.

[0088] It is understandable that, in general, the second chip reads the target shared storage area based on the write address in the write completion message. However, in the process of receiving and parsing the write completion message, an error may occur in the write address, and an error may also occur when reading according to the write address. The specific circumstances in which the error may occur are not specifically limited here.

[0089] In the event of an error, the second chip may have read other storage areas. The second system can record the corresponding read address when it reads data, generate a read completion message carrying the read address, and then return the read completion message to the first system.

[0090] The first chip can compare the read address and the write address. When the read address is consistent with the write address, it indicates that the second system has successfully and correctly read the screen data in the target shared storage area. If the screen data has been successfully read, the target shared storage area can be updated to an idle state, so that the target updated storage area can continue to be used for the next data interaction.

[0091] In the implementation of the embodiment of the present disclosure, when the second chip returns a read completion message, the read address carried in the read completion message is obtained, the read address and the write address are compared, and when the read address and the write address are consistent, the target shared storage area is updated to an idle state. The shared storage area can be reused repeatedly, and data is transferred multiple times through the same shared storage area, thereby avoiding the situation where the capacity of the shared storage area is insufficient to transfer the screen data at one time, so that the screen data can still be effectively transferred in the case of less shared storage area, reducing the video memory demand for screen data transfer; at the same time, by comparing and checking the read address and the write address, it can be avoided that the second chip does not read the screen data before the next screen data transfer, so that the screen data is not missed when it is obtained, and the security of screen data transfer is improved.

[0092] Figure 4 This is a step diagram of a dual-chip architecture screen projection method provided by an embodiment of the present disclosure, including:

[0093] Step 401, receiving a write completion message sent by a first chip; the first chip is used to generate the write completion message after writing the screen data into the shared storage area;

[0094] Step 402, in response to the write completion message, reading the screen data in the shared storage area; the screen data is used by the second chip to determine a target screen to be displayed on a target display screen controlled by the second chip;

[0095] Step 403: Control the target display screen to display the target picture.

[0096] The contents of steps 401 to 403 can refer to the above Figure 1 to Figure 3 The embodiments of the present invention will not be described in detail.

[0097] Optionally, the method further includes:

[0098] When the reading is completed, determining the address information of the read storage area to determine the reading address;

[0099] A read completion message carrying the read address is generated, and the read completion message is sent to the first chip, so that the first chip performs address comparison.

[0100] The contents of the embodiments of the present disclosure can refer to the above Figure 1 to Figure 3 The embodiments of the present invention will not be described in detail here.

[0101] Figure 5 is a schematic diagram of a vehicle 50 provided in an embodiment of the present disclosure; the vehicle 50 includes a first chip 501 and a second chip 502;

[0102] The first chip 501 is used to write screen data into a shared storage area; the shared storage area is used for the first chip to write the screen data and for the second chip to read the screen data; the screen data is used for the second chip to determine the target screen to be displayed on the target display screen controlled by the second chip;

[0103] The first chip 501 is used to generate a write completion message and send it to the second chip;

[0104] The second chip 502 is used to receive a write completion message sent by the first chip;

[0105] The second chip 502 is used for reading the screen data in the shared storage area in response to the write completion message;

[0106] The second chip 502 is used to control the target display screen to display the target image.

[0107] The first chip is also used

[0108] Determine a pre-built shared management object; the shared management object includes storage area information of the shared storage area and state parameters associated with the storage area information;

[0109] The state parameter is a first parameter indicating that the corresponding shared storage area is in an idle state;

[0110] The state parameter is a second parameter indicating that the corresponding shared storage area is in a write state;

[0111] The state parameter is the third parameter indicating that the corresponding shared storage area is in a read state.

[0112] The first chip is used for

[0113] Traversing the shared management object, and taking the first storage area information associated with the first parameter found during traversal as the target storage area information;

[0114] The first parameter of the target storage area information is set as the second parameter, and the screen data is written to the target shared storage area pointed to by the target storage area information;

[0115] The second parameter of the target storage area information is set as a third parameter, so that the target shared storage area is in the read state.

[0116] The first chip is used for

[0117] Determine the shared storage area where the screen data is written as the target shared storage area;

[0118] Determine a write address according to address information of the target shared storage area in the video memory;

[0119] A write completion message carrying the write address is generated, and the write completion message is sent to the second chip; the second chip is used to read the target shared storage area according to the write address.

[0120] The first chip is also used

[0121] In the case where the second chip returns a read completion message, obtaining a read address carried in the read completion message; the read completion message is generated by the second chip after the read is completed based on the address information of the read storage area;

[0122] The read address is compared with the write address, and when the read address is consistent with the write address, the target shared storage area is updated to an idle state.

[0123] The first chip is further used to determine the address information of the read storage area in order to determine the read address when the reading is completed;

[0124] Based on the address information, generating a read completion message carrying the address information;

[0125] Sending the read completion message to the first chip so that the first chip performs address comparison;

[0126] The second chip is also used

[0127] When the reading is completed, determining the address information of the read storage area to determine the reading address;

[0128] A read completion message carrying the read address is generated, and the read completion message is sent to the first chip, so that the first chip performs address comparison.

[0129] In summary, in the disclosed embodiment, the first chip can write screen data to the shared storage area, generate a write completion message and send it to the second chip, the second chip receives and responds to the write completion message, reads the screen data in the shared storage area, and the second chip can then display the target screen corresponding to the screen data on the target display screen. The first chip can directly transfer the screen data to the second chip through the shared storage area, and the second chip directly controls the target display screen based on the screen data to display the target screen. If the first chip controls the target display screen, it is also necessary to perform cumbersome interactions with the second chip so that the first chip can start controlling the target display screen. Therefore, writing and reading based on the shared storage area effectively avoids the cross-system interaction process, and the second chip controls its corresponding target display screen, which reduces the control delay and ultimately improves the screen projection efficiency.

[0130] Figure 6 A dual-chip architecture screen projection device 60 provided in an embodiment of the present disclosure includes:

[0131] The data writing module 601 writes the screen data into the shared storage area; the shared storage area is used for the first chip to write the screen data and for the second chip to read the screen data; the screen data is used for the second chip to determine the target screen to be displayed on the target display screen controlled by the second chip;

[0132] The write completion module 602 is used to generate a write completion message and send it to the second chip; the second chip is used to receive and respond to the write completion message, read the screen data in the shared storage area, and control the target display screen to display the target screen according to the screen data.

[0133] Optionally, the device further comprises:

[0134] A management object module, used to determine a pre-built shared management object; the shared management object includes storage area information of the shared storage area and state parameters associated with the storage area information;

[0135] The state parameter is a first parameter indicating that the corresponding shared storage area is in an idle state;

[0136] The state parameter is a second parameter indicating that the corresponding shared storage area is in a write state;

[0137] The state parameter is the third parameter indicating that the corresponding shared storage area is in a read state.

[0138] Optionally, there are multiple shared storage areas; the data writing module includes:

[0139] A traversal submodule, used for traversing the shared management object, and taking the first traversed storage area information associated with the first parameter as the target storage area information;

[0140] The first second submodule is used to set the first parameter of the target storage area information to a second parameter, and write the picture data to the target shared storage area pointed to by the target storage area information;

[0141] The second third submodule is used to set the second parameter of the target storage area information to a third parameter, so that the target shared storage area is in the read state.

[0142] Optionally, there are multiple shared storage areas; the writing completion module includes:

[0143] A target writing submodule, used for determining the shared storage area into which the picture data is written as the target shared storage area;

[0144] A write address submodule, used to determine a write address according to address information of the target shared storage area in the video memory;

[0145] The address carrying submodule is used to generate a write completion message carrying the write address, and send the write completion message to the second chip; the second chip is used to read the target shared storage area according to the write address.

[0146] Optionally, the device further comprises:

[0147] A first read address module, configured to obtain a read address carried in a read completion message when the second chip returns the read completion message; the read completion message is generated by the second chip based on the address information of the read storage area after the second chip completes the reading;

[0148] The address checking module is used to compare the read address with the write address, and when the read address is consistent with the write address, update the target shared storage area to an idle state.

[0149] In the disclosed embodiment, the first chip can write screen data to the shared storage area, generate a write completion message and send it to the second chip, the second chip receives and responds to the write completion message, reads the screen data in the shared storage area, and the second chip can then display the target screen corresponding to the screen data on the target display screen. The first chip can directly transfer the screen data to the second chip through the shared storage area, and the second chip directly controls the target display screen based on the screen data to display the target screen. If the first chip controls the target display screen, it is also necessary to perform cumbersome interactions with the second chip so that the first chip can start controlling the target display screen. Therefore, writing and reading based on the shared storage area effectively avoids the cross-system interaction process, and the second chip controls its corresponding target display screen, which reduces the control delay and ultimately improves the screen projection efficiency.

[0150] Figure 7 A dual-chip architecture screen projection device 70 provided in an embodiment of the present disclosure includes:

[0151] The message receiving module 701 is used to receive a write completion message sent by the first chip; the first chip is used to generate the write completion message after writing the screen data into the shared storage area;

[0152] A data reading module 702 is used to read the screen data in the shared storage area in response to the write completion message; the screen data is used for the second chip to determine a target screen to be displayed on a target display screen controlled by the second chip;

[0153] The display control module 703 is used to control the target display screen to display the target picture.

[0154] Optionally, the device further comprises:

[0155] A second read address module is used to determine the address information of the read storage area to determine the read address when the reading is completed;

[0156] A read carrying module, used to generate a read completion message carrying the address information based on the address information;

[0157] The message returning module is used to send the read completion message to the first chip so that the first chip performs address comparison.

[0158] In the disclosed embodiment, the first chip can write screen data to the shared storage area, generate a write completion message and send it to the second chip, the second chip receives and responds to the write completion message, reads the screen data in the shared storage area, and the second chip can then display the target screen corresponding to the screen data on the target display screen. The first chip can directly transfer the screen data to the second chip through the shared storage area, and the second chip directly controls the target display screen based on the screen data to display the target screen. If the first chip controls the target display screen, it is also necessary to perform cumbersome interactions with the second chip so that the first chip can start controlling the target display screen. Therefore, writing and reading based on the shared storage area effectively avoids the cross-system interaction process, and the second chip controls its corresponding target display screen, which reduces the control delay and ultimately improves the screen projection efficiency.

[0159] The present application also provides an electronic device, such as Figure 8 As shown, it includes a processor 1001 , a communication interface 1002 , a memory 1003 and a communication bus 1004 , wherein the processor 1001 , the communication interface 1002 , and the memory 1003 communicate with each other via the communication bus 1004 .

[0160] The memory 1003 is used to store computer programs.

[0161] When the processor 1001 is used to execute the program stored in the memory 1003, the following steps are implemented: determining a shared storage area in the video memory; the shared storage area is used for the first chip to write screen data; writing the screen data into the shared storage area; the screen data is used for the second chip to determine the target screen to be displayed on the target display screen controlled by the second chip; generating a write completion message and sending it to the second chip; the second chip is used to receive and respond to the write completion message, read the screen data in the shared storage area, and control the target display screen to display the target screen according to the screen data.

[0162] Among them, processor 1001 can also implement other steps in the above-mentioned dual-chip architecture screen projection method, which will not be repeated here.

[0163] The communication bus mentioned in the above electronic device can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The communication bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, only one thick line is used in the figure, but it does not mean that there is only one bus or one type of bus.

[0164] The communication interface is used for communication between the above electronic devices and other systems.

[0165] The memory may include a random access memory (RAM) or a non-volatile memory, such as at least one disk memory. Optionally, the memory may also be at least one storage device located away from the aforementioned processor.

[0166] The above-mentioned processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0167] In another embodiment provided in the present application, a computer-readable storage medium is also provided, in which instructions are stored. When the computer-readable storage medium is run on a computer, the computer executes the dual-chip architecture screen projection method described in the above embodiment.

[0168] In another embodiment provided in the present application, a computer program product including instructions is also provided, which, when executed on a computer, enables the computer to execute the dual-chip architecture screen projection method described in the above embodiment.

[0169] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from a website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium may be any available medium that a computer can access or a data storage system such as a server, data center, etc. that includes one or more available media integrated. The available medium may be a magnetic medium, (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state hard disk Solid State Disk (SSD)), etc.

[0170] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or system including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or system. In the absence of further restrictions, the elements defined by the sentence "comprise one..." do not exclude the existence of other identical elements in the process, method, article or system including the elements.

[0171] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. For the embodiments of the device, electronic device, computer-readable storage medium and computer program products containing instructions, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiments.

[0172] The above description is only a preferred embodiment of the present application and is not intended to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application are included in the protection scope of the present application.

Claims

1. A dual-chip architecture screen projection method, characterized in that: The method comprises: Writing screen data into a shared storage area; the shared storage area is used for the first chip to write the screen data and for the second chip to read the screen data; the screen data is used for the second chip to determine a target screen to be displayed on a target display screen controlled by the second chip; A write completion message is generated and sent to the second chip; the second chip is used to receive and respond to the write completion message, read the screen data in the shared storage area, and control the target display screen to display the target screen according to the screen data.

2. The method according to claim 1, characterized in that The method further comprises: Determine a pre-built shared management object; the shared management object includes storage area information of the shared storage area and state parameters associated with the storage area information; The state parameter is a first parameter indicating that the corresponding shared storage area is in an idle state; The state parameter is a second parameter indicating that the corresponding shared storage area is in a write state; The state parameter is the third parameter indicating that the corresponding shared storage area is in a read state.

3. The method according to claim 2, characterized in that There are multiple shared storage areas; the step of writing the screen data into the shared storage area includes: Traversing the shared management object, and taking the first storage area information associated with the first parameter found during traversal as the target storage area information; The first parameter of the target storage area information is set as the second parameter, and the screen data is written to the target shared storage area pointed to by the target storage area information; The second parameter of the target storage area information is set as a third parameter, so that the target shared storage area is in the read state.

4. The method according to claim 1, characterized in that: There are multiple shared storage areas; the step of generating a write completion message and sending it to the second chip includes: Determine the shared storage area where the screen data is written as the target shared storage area; Determine a write address according to address information of the target shared storage area in the video memory; A write completion message carrying the write address is generated, and the write completion message is sent to the second chip; the second chip is used to read the target shared storage area according to the write address.

5. The method according to claim 4, characterized in that The method further comprises: In the case where the second chip returns a read completion message, obtaining a read address carried in the read completion message; the read completion message is generated by the second chip after the read is completed based on the address information of the read storage area; The read address is compared with the write address, and when the read address is consistent with the write address, the target shared storage area is updated to an idle state.

6. A dual-chip architecture screen projection method, characterized in that: The method comprises: receiving a write completion message sent by the first chip; the first chip is used to generate the write completion message after writing the screen data into the shared storage area; In response to the write completion message, the screen data is read from the shared storage area; the screen data is used by the second chip to determine a target screen to be displayed on a target display screen controlled by the second chip; According to the picture data, the target display screen is controlled to display the target picture.

7. The method according to claim 6, characterized in that The method further comprises: When the reading is completed, determining the address information of the read storage area to determine the reading address; A read completion message carrying the read address is generated, and the read completion message is sent to the first chip, so that the first chip performs address comparison.

8. A vehicle, characterized in that: The vehicle includes a first chip and a second chip; The first chip is used to execute the steps of the dual-chip architecture screen projection method according to any one of claims 1 to 5; The second chip is used to execute the steps of the dual-chip architecture screen projection method described in any one of claims 6 to 7.

9. An electronic device, characterized in that: include: A processor, a communication interface, a memory and a communication bus; wherein the processor, the communication interface and the memory communicate with each other via the communication bus; Memory, used to store computer programs; The processor is used to implement the steps in the dual-chip architecture screen projection method as described in any one of claims 1 to 7 when executing the program stored in the memory.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the steps in the dual-chip architecture screen projection method as described in any one of claims 1 to 7 are implemented.

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