Approximate floating-point multiplication and accumulation circuit and method

Abstract

The present application discloses an approximate floating-point multiplication and accumulation circuit and method, which belongs to the field of computer architecture and digital circuit design technology, including: an approximate floating-point multiplier precision arbitration module, which receives a preprocessed floating-point number and outputs a first precision control signal; an approximate floating-point multiplication module, which adopts an approximate addition scheme with different mantissa multiplications according to the first precision control signal and outputs an approximate floating-point multiplication result; an approximate floating-point adder precision arbitration module, which receives an approximate floating-point multiplication result and a partial sum result of the previous time and outputs a second precision control signal; an approximate floating-point addition module, which adopts an approximate addition scheme with different mantissa additions according to the second precision control signal and outputs a partial sum result. The present application dynamically adjusts the calculation process according to the characteristics of the input data. When the input data differs greatly, the circuit adopts precise calculation to ensure the accuracy of the calculation result; when the input data differs slightly, the circuit switches to an approximate calculation mode to simplify the calculation process.

Description

Technical Field

[0001] The present application relates to the field of digital circuit design, and more particularly to an approximate floating-point multiplication-accumulation circuit and method. Background Art

[0002] Floating-point numbers are a numerical format used in computers to represent real numbers. They can represent extremely large or small values within a limited bit width, and are therefore widely used in scientific computing, image processing, artificial intelligence, big data analysis, and other fields. Compared with fixed-point numbers, the main advantage of floating-point numbers is that they can dynamically adjust the decimal point position to represent a larger dynamic range. They still have an irreplaceable position in application scenarios that require dynamic range and high precision. However, due to the complexity of floating-point operations, their hardware design often consumes more resources. Floating-point calculations require complex mantissa alignment, exponent adjustment, and normalization processing. These processes not only increase the complexity of the hardware circuit, but also lead to higher power consumption and longer operation delays.

[0003] Approximate computing is a technique that actively introduces controllable errors into hardware design to improve computational efficiency. In recent years, with the rise of error-tolerant applications such as deep learning, neural networks, and image processing, approximate computing has garnered widespread attention as an optimization method. In particular, in floating-point calculations, approximate computing can significantly reduce hardware complexity, power consumption, and latency by simplifying the computational process or reducing precision requirements.

[0004] While approximate computing can improve the energy efficiency of floating-point operations, in practice, different scenarios have significantly different requirements for computational accuracy. For example, in scenarios like image processing or deep learning inference, lower computational accuracy is generally sufficient, while in precision-sensitive scenarios like scientific computing and financial simulation, strict computational accuracy is required. Summary of the Invention

[0005] The present application aims to provide an approximate floating-point multiplication-accumulation circuit to introduce a precision adaptive mechanism in floating-point operations, and to design a floating-point multiplication-accumulation unit that can dynamically adjust the calculation accuracy according to the characteristics of the input data, thereby meeting the needs of different application scenarios.

[0006] To achieve the above objectives, the technical solution of this application is:

[0007] An approximate floating-point multiplication and accumulation circuit, comprising:

[0008] Preprocessing module;

[0009] an approximate floating-point multiplier precision arbitration module connected to the preprocessing module;

[0010] an approximate floating-point multiplication module, connected to the preprocessing module and the approximate floating-point multiplier precision arbitration module respectively;

[0011] an approximate floating-point adder precision arbitration module connected to the approximate floating-point multiplication module;

[0012] an approximate floating-point addition module, connected to the approximate floating-point multiplication module and the approximate floating-point adder precision arbitration module respectively;

[0013] The partial sum storage module is connected to the approximate floating-point addition module.

[0014] Optionally, the approximate floating-point multiplier precision arbitration module includes: a floating-point multiplication exponent input analysis unit and a first approximate resolution configuration unit, and the floating-point multiplication exponent input analysis unit is connected to the first approximate resolution configuration unit.

[0015] Optionally, the floating-point multiplication exponent input analysis unit includes: a first exponent receiver, a first leading one detector, a first subtractor and a first multiplexer selector, and the first exponent receiver, the first leading one detector, the first subtractor and the first multiplexer selector are connected in sequence.

[0016] Optionally, the first approximate analysis configuration unit includes: a first shift controller and a first 4-bit shift register, and the first shift controller and the first 4-bit shift register are connected in sequence.

[0017] Optionally, the approximate floating-point multiplication module includes: an adder array, the adder array includes n adders, each adder includes two sub-adders, the sub-adders include: a first two-to-one selector, a first precise adder, and a first approximate adder, the first two-to-one selector is connected to the first precise adder and the first approximate adder respectively, the first precise adder is connected to the first approximate adder, the first two-to-one selector of each sub-adder is connected, the first precise adder of each sub-adder is connected, and the first approximate adder of each sub-adder is connected.

[0018] Optionally, the approximate floating-point adder precision arbitration module includes: a floating-point addition exponent input analysis unit and a second approximate resolution configuration unit, and the floating-point addition exponent input analysis unit is connected to the second approximate resolution configuration unit.

[0019] Optionally, the floating-point addition exponent input analysis unit includes: a second exponent receiver, a second leading one detector, a second subtractor and a second multiplexer selector, and the second exponent receiver, the second leading one detector, the second subtractor and the second multiplexer selector are connected in sequence.

[0020] Optionally, the second approximate analysis configuration unit includes: a second shift controller and a second 4-bit shift register, and the second shift controller and the second 4-bit shift register are connected in sequence.

[0021] Optionally, the approximate floating-point addition module includes: four sub-adders, each sub-adder includes: a second two-to-one selector, a second precise adder, and a second approximate adder, the second two-to-one selector is connected to the second precise adder and the second approximate adder respectively, the second precise adder is connected to the second approximate adder, the second two-to-one selector of each sub-adder is connected, the second precise adder of each sub-adder is connected, and the second approximate adder of each sub-adder is connected.

[0022] An approximate floating-point multiplication-accumulation method, applied to the approximate floating-point multiplication-accumulation circuit as described in any one of the above items, comprising:

[0023] Step S1: input floating point number;

[0024] Step S2: Input floating point number exponential analysis;

[0025] Step S3: Generate configuration code;

[0026] Step S4: Determine whether to use approximate calculation. If so, proceed to step S5; if not, proceed to step S6;

[0027] Step S5: approximate configuration;

[0028] Step S6: adopt mantissa multiplication;

[0029] Step S7: Input floating point number exponential analysis;

[0030] Step S8: Generate configuration code;

[0031] Step S9: Determine whether to use approximate calculation, if yes, go to step S10; if not, go to step S11;

[0032] Step S10: approximate configuration;

[0033] Step S11: adding the mantissas;

[0034] Step S12: Determine whether the accumulation is completed. If so, proceed to step S13; if not, return to step S8;

[0035] Step S13: Output the result.

[0036] This application designs a precision arbitration module for floating-point multipliers and adders to dynamically adjust the calculation process according to the characteristics of the input data, and flexibly choose to use approximate or precise calculation mode. When the input data differs greatly, the circuit prioritizes precise calculation to ensure the accuracy of the calculation results; when the input data differs less, the circuit switches to approximate calculation mode to simplify the calculation process, speed up the calculation speed and reduce power consumption. This dynamic adjustment mechanism can achieve the best balance between calculation accuracy and hardware resource utilization in different application scenarios, meet the calculation accuracy of different requirements, improve the calculation speed and reduce power consumption while maintaining a certain accuracy.

[0037] In order to make the above features and advantages of the application more obvious and easy to understand, the following embodiments are given and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 This is a module diagram of the approximate floating-point multiplication and accumulation circuit provided by this application.

[0039] Figure 2 This is a diagram of the approximate floating-point multiplier precision arbitration module of this application.

[0040] Figure 3 This is a module diagram of the approximate resolution configuration unit of the approximate floating-point multiplier precision arbitration module of the present application.

[0041] Figure 4 This is a block diagram of the adder array of the approximate floating-point multiplication module of the present application.

[0042] Figure 5 This is a block diagram of an adder in the adder array of the present application.

[0043] Figure 6 This is a diagram of the precision arbitration module of the approximate floating-point adder of this application.

[0044] Figure 7 This is a block diagram of the approximate mantissa adder of the approximate floating-point addition module of the present application.

[0045] Figure 8 This is a flowchart of the approximate floating-point multiplication and accumulation method proposed in this application. DETAILED DESCRIPTION

[0046] To make the purpose and technical solutions of the embodiments of the present application clearer, the technical solutions of the embodiments of the present application will be clearly and completely described below in conjunction with the drawings of the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the described embodiments of the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0047] In one embodiment of this application, please refer to Figure 1 , Figure 1 This is a module diagram of the approximate floating-point multiplication and accumulation circuit provided in this application. The approximate floating-point multiplication and accumulation circuit includes: an approximate floating-point multiplier precision arbitration module 1, an approximate floating-point multiplication module 2, an approximate floating-point adder precision arbitration module 3, an approximate floating-point addition module 4, a preprocessing module 5 and a partial sum storage module 6.

[0048] The approximate floating-point multiplier precision arbitration module 1 is connected to the approximate floating-point multiplication module 2, the approximate floating-point multiplication module 2 is connected to the approximate floating-point adder precision arbitration module 3 and the approximate floating-point addition module 4, the approximate floating-point adder precision arbitration module 3 is connected to the approximate floating-point addition module 4 and the partial sum storage module 6, the preprocessing module 5 is connected to the approximate floating-point multiplier precision arbitration module 1 and the approximate floating-point multiplication module 2 respectively, and the partial sum storage module 6 is connected to the approximate floating-point addition module 4.

[0049] As an example, the approximate floating-point multiplier precision arbitration module 1 is used to receive preprocessed floating-point numbers, input the exponent parts of the multiplier and the multiplicand, and have a bit width of 8 bits; and output a precision control signal for controlling the precision of the approximate floating-point multiplication module 2, with a bit width of 4 bits.

[0050] The approximate floating-point multiplication module 2 is used to receive the preprocessed floating-point number and the precision control signal output by the approximate floating-point multiplier precision arbitration module 1, adopt an approximate addition scheme with different mantissa multiplications to achieve controllable precision, and output the approximate floating-point multiplication result.

[0051] The approximate floating-point adder precision arbitration module 3 is used to receive the approximate floating-point multiplication result and the partial sum result obtained after the previous approximate floating-point addition calculation, and input the exponent part of the addend and the summand, with a bit width of 8 bits; and output the precision control signal for controlling the approximate floating-point addition module 4, with a bit width of 4 bits.

[0052] The approximate floating-point addition module 4 is used to receive the approximate floating-point multiplication result, the partial sum result obtained after the previous approximate floating-point addition calculation, and the precision control signal output by the approximate floating-point adder precision arbitration module 3, adopt an approximate addition scheme with different mantissa additions to achieve controllable precision, and output the partial sum result.

[0053] Preprocessing module 5 is configured to receive a floating-point number and perform preprocessing on the floating-point number, including: dividing the floating-point number by the number of bits according to the data format of the received floating-point number to obtain a sign bit, an exponent portion, and a mantissa portion. For example, a single-precision floating-point number is a 32-bit binary number, with the 32nd bit being the sign bit, bits 31 to 24 being the exponent portion, and bits 23 to 1 being the mantissa portion. Based on the floating-point number's data format, these three bits are extracted and input into approximate floating-point multiplier precision arbitration module 1 and approximate floating-point multiplication module 2.

[0054] The partial sum storage module 6 is used to store the partial sum result obtained by the approximate floating-point addition module 4.

[0055] Specifically, the partial sum result is the augend input to the approximate floating-point addition module 4 during the next approximate floating-point addition calculation, and the approximate floating-point multiplication result is the addend input to the approximate floating-point addition module 4 .

[0056] This application designs an accuracy arbitration module for approximate floating-point multipliers and approximate floating-point adders, dynamically adjusts the calculation process according to the characteristics of the input data, and flexibly chooses to use approximate or precise calculation mode. When the input data differs greatly, the circuit gives priority to precise calculation to ensure the accuracy of the calculation result; when the input data differs little, the circuit switches to approximate calculation mode to simplify the calculation process, speed up the calculation speed and reduce power consumption. This dynamic adjustment mechanism can achieve the best balance between calculation accuracy and hardware resource utilization in different application scenarios, meet the calculation accuracy of different requirements, improve the calculation speed and reduce power consumption while maintaining a certain accuracy.

[0057] As an example, see Figure 2 , Figure 2 This is a structural diagram of the approximate floating-point multiplier precision arbitration module 1 of the present application. The approximate floating-point multiplier precision arbitration module 1 includes: a floating-point multiplication exponent input analysis unit 11 and an approximate parsing configuration unit 12, and the floating-point multiplication exponent input analysis unit 11 is connected to the approximate parsing configuration unit 12; the floating-point multiplication exponent input analysis unit 11 includes: an exponent receiver 111, a leading one detector (LOD) 112, a subtractor 113 and a multiplexing selector 114, and the exponent receiver 111, the leading one detector 112, the subtractor 113 and the multiplexing selector 114 are connected in sequence, and the multiplexing selector 114 is connected to the approximate parsing configuration unit 12.

[0058] The floating-point multiplication exponent input analysis unit 11 is used to perform exponential analysis on the pre-processed floating-point number input. The exponential analysis includes: outputting different signals to process subsequent calculations in different ways according to the difference in the exponential magnitude of the input floating-point number.

[0059] The exponent receiver 111 is configured to receive an input pre-processed floating-point number exponent.

[0060] The leading one detector 112 is used to detect the most significant bit of the exponent of the received floating point number, that is, the number of bits where the first 1 is located from high to low, and input the result into the subtractor.

[0061] The subtractor 113 is used to receive the result of the number of bits of the highest bit of the exponent of the input preprocessed floating point number, and obtain the magnitude difference of the exponent of the input floating point number for subsequent magnitude division processing.

[0062] The multiplexer selector 114 is used to output different signals according to the magnitude difference of the exponents of the input floating-point numbers, and switch between different subsequent calculation schemes; when the magnitude difference of the exponents is 0, 1, or 2, the output signal is 10; when the magnitude difference of the exponents is 3, 4, or 5, the output signal is 01; when the magnitude difference of the exponents is 6 or 7, the output signal is 00.

[0063] The approximate parsing configuration unit 12 is used to parse the signal output by the floating-point multiplication exponent input analysis unit 11, generate a configuration code, interpret the parsed configuration code, generate a precision control signal for configuring the approximate floating-point multiplication module 2, and switch between precise and different approximate schemes.

[0064] Specifically, see Figure 3 , Figure 3 1 is a block diagram of the approximate parsing configuration unit of the present application. The approximate parsing configuration unit 12 includes a shift controller 121 and a 4-bit shift register 122. The shift controller 121 and the 4-bit shift register 122 are connected in sequence.

[0065] The shift controller 121 is configured to receive the signal output by the floating-point multiplication exponent input analysis unit 11, parse it into a corresponding decimal value, generate a corresponding number of "1" signals according to the value, and output them to the shift register through a shift operation;

[0066] The 4-bit shift register 122, using a parallel loading structure, receives a sequence of "1" signals from the shift controller 121 and performs a bit-by-bit right shift operation driven by shift pulses. When the number of shifts reaches the preset bit width, the binary number stored in the 4-bit shift register 122 is directly mapped to the first precision control signal output. That is, the number of 1s in the output precision control signal corresponds to the corresponding decimal value.

[0067] When the signal output by the floating-point multiplication exponent input analysis unit 11 is 00, the shift controller 121 parses the corresponding decimal value as 0, generates 0 "1" signals, and the 4-bit shift register 122 outputs the precision control signal 00 after shifting; when the signal is 01, the shift controller 121 parses the corresponding decimal value as 1, generates 1 "1" signal, and the 4-bit shift register 122 outputs the precision control signal 01 after shifting; when the signal is 10, the shift controller 121 parses the corresponding decimal value as 2, generates 2 "1" signals, and the 4-bit shift register 122 outputs the precision control signal 11 after shifting.

[0068] As an example, see Figure 4The approximate floating-point multiplication module 2 includes an adder array 21 , and the adder array 21 includes n adders 211 to 21 n . Figure 4 This is a schematic diagram of the adder array structure of the approximate floating-point multiplication module of the present application. Since addition is also required during the mantissa multiplication process, and the mantissa multiplication bit width is relatively wide, multiplying each bit will produce many results, which need to be added to obtain the final result. Therefore, an adder array is used. The adder array 21 of the approximate floating-point multiplication module 2 uses a block adder to perform approximate calculations to obtain the result. Each adder is divided into two sub-adders, each of which contains a precise adder and an approximate adder. Each adder in the adder array 21 is controlled by a precision control signal to determine whether to use a precise adder or an approximate adder. For example, in the case of 100 × 111, the multiplication of each bit in the multiplier and the multiplicand during the calculation will result in 100 + 1000 + 10000. Here, the adder array 21 is required to perform addition to obtain the mantissa multiplication result.

[0069] Please continue reading Figure 5 Taking the adder 211 as an example, the adder 211 includes a sub-adder 2111 and a sub-adder 2112, and the sub-adder 2111 is connected to the sub-adder 2112. Sub-adder 2111 includes a selector 21111, a precise adder 21112, and an approximate adder 21113. Selector 21111 is connected to precise adder 21112 and approximate adder 21113, respectively. Precise adder 21112 is connected to approximate adder 21113. Sub-adder 2112 includes a selector 21121, a precise adder 21122, and an approximate adder 21123. Selector 21121 is connected to precise adder 21122, approximate adder 21123, and selector 21111, respectively. Precise adder 21122 is connected to approximate adder 21123 and precise adder 21112, respectively. Both sub-adder 2111 and sub-adder 2112 have a bit width of 12 bits.

[0070] As an example, the two-to-one selector 21111 and the two-to-one selector 21121 are both MUXs.

[0071] As an example, the approximate floating-point multiplication module 2 receives a precision control signal from the approximate resolution configuration unit 12, and selects whether each adder uses an approximate adder or a precise adder. When the received precision control signal is 11, both sub-adders of each adder in the adder array 21 choose to use an approximate adder; when the received precision control signal is 01, the first sub-adder of each adder in the adder array 21 uses a precise adder, and the second sub-adder uses an approximate adder; when the received precision control signal is 00, both sub-adders of each adder in the adder array 21 choose to use a precise adder. The number of approximate adders is flexibly used according to the precision control signal, achieving the goal of controllable precision.

[0072] Furthermore, the exponential part of the input floating-point number is added by a precise adder and shifted to obtain the exponential addition result, the sign bit is XORed, and finally the approximate floating-point multiplication module 2 outputs the approximate floating-point multiplication result. The approximate floating-point multiplication result is a floating-point number.

[0073] As an example, see Figure 6 , Figure 6 This is a structural diagram of the approximate floating-point adder precision arbitration module 3 of the present application. The approximate floating-point adder precision arbitration module 3 includes: a floating-point addition exponent input analysis unit 31 and an approximate parsing configuration unit 32, and the floating-point addition exponent input analysis unit 31 is connected to the approximate parsing configuration unit 32; the floating-point addition exponent input analysis unit 31 includes: an exponent receiver 311, a leading one detector 312, a subtractor 313 and a multiplexing selector 314, and the exponent receiver 311, the leading one detector 312, the subtractor 313 and the multiplexing selector 314 are connected in sequence, and the multiplexing selector 314 is connected to the approximate parsing configuration unit 32.

[0074] The floating-point addition exponent input analysis unit 31 is used to perform exponential analysis on the input approximate floating-point multiplication result and the exponential part of the sum result obtained by the approximate floating-point addition module 4 after the previous approximate floating-point addition calculation. According to the difference in the exponential magnitude of the input floating-point number, different signals are output to process the subsequent calculation in different ways.

[0075] The exponent receiver 311 is used to receive the exponent part of the approximate floating-point multiplication result and the exponent part of the sum result obtained by the approximate floating-point addition module 4 after the last approximate floating-point addition calculation, and store the two exponent parts for subsequent processing.

[0076] The leading one detector 312 is used to detect the number of the highest bits of the two received exponential parts and input the result into the subtractor 313.

[0077] The subtractor 313 is used to obtain the magnitude difference between the two exponents, which is used for subsequent magnitude division processing to achieve the purpose of quickly obtaining the exponent difference.

[0078] The multiplexer selector 314 is used to output different signals according to the difference in the exponential magnitudes, and to switch between different subsequent calculation schemes. When the difference in the exponential magnitudes is 0, the output signal is 100; when the difference in the exponential magnitudes is 1 and 2, the output signal is 011; when the difference in the exponential magnitudes is 3 and 4, the output signal is 010; when the difference in the exponential magnitudes is 5 and 6, the output signal is 001; and when the difference in the exponential magnitudes is 7 and 8, the output signal is 000.

[0079] The approximate parsing configuration unit 32 is used to parse the signal output by the floating-point addition exponent input analysis unit 31, generate a configuration code, interpret the parsed configuration code, generate a precision control signal for configuring the approximate floating-point addition module 4, and switch between precise and different approximate schemes.

[0080] Specifically, the approximate analysis configuration unit 32 and Figure 3 The structure and function of the approximate analysis configuration unit 12 are the same, and include: a shift controller and a 4-bit shift register, which are connected in sequence. When the signal output by the floating-point addition exponent input analysis unit 31 is 000, the shift controller generates zero '1' signals, and the 4-bit shift register outputs a precision control signal of 0000 after shifting. When the signal is 001, the shift controller generates one '1' signal, and the 4-bit shift register outputs a precision control signal of 0001 after shifting. When the signal is 010, the shift controller generates two '1' signals, and the 4-bit shift register outputs a precision control signal of 0011 after shifting. When the signal is 011, the shift controller generates three '1' signals, and the 4-bit shift register outputs a precision control signal of 0111 after shifting. When the signal is 100, the shift controller generates four '1' signals, and the 4-bit shift register outputs a precision control signal of 1111 after shifting.

[0081] Furthermore, the approximate floating-point multiplication result and the maximum exponent in the sum result obtained by the approximate floating-point addition module 4 after the last approximate floating-point addition calculation are aligned to obtain the result of the exponential part, and the mantissa is shifted before the mantissa addition calculation is performed.

[0082] As an example, see Figure 7 The approximate floating-point addition module 4 includes an approximate mantissa adder 41 . Figure 7The block diagram of the approximate mantissa adder of the approximate floating-point addition module of the present application is shown. The approximate mantissa adder 41 of the approximate floating-point addition module 4 includes a sub-adder 411, a sub-adder 412, a sub-adder 413 and a sub-adder 414. The sub-adder 411, the sub-adder 412, the sub-adder 413 and the sub-adder 414 are connected in sequence. The sub-adder 411 includes: a selector 4111, an accurate adder 411 2. Approximate adder 4113, the two-choose-one selector 4111 is connected to the precise adder 4112 and the approximate adder 4113 respectively, and the precise adder 4112 is connected to the approximate adder 4113; the sub-adder 412 includes: a two-choose-one selector 4121, a precise adder 4122, an approximate adder 4123, a two-choose-one selector 4121 and the precise adder 4122, the approximate adder 4123 and the two-choose-one selector The selector 4111 is connected respectively, the precise adder 4122 is connected respectively to the approximate adder 4123 and the precise adder 4112; the sub-adder 413 includes: a two-choose-one selector 4131, a precise adder 4132, an approximate adder 4133, the two-choose-one selector 4131 is connected respectively to the precise adder 4132, the approximate adder 4133 and the two-choose-one selector 4121, the precise adder 4122 is connected respectively to the approximate adder 4133; The quasi-adder 4123 and the precise adder 4122 are connected respectively; the sub-adder 414 includes: a two-to-one selector 4141, a precise adder 4142, and an approximate adder 4143. The two-to-one selector 4141 is connected to the precise adder 4142, the approximate adder 4143 and the two-to-one selector 4131 respectively, and the precise adder 4142 is connected to the approximate adder 4143 and the precise adder 4132 respectively.

[0083] As an example, the two-to-one selector 4111 , the two-to-one selector 4121 , the two-to-one selector 4131 , and the two-to-one selector 4141 are all MUXs.

[0084] Specifically, two-choice selectors 4111, 4121, 4131, and 4141 receive precision control signals from the approximate resolution configuration unit 32. Each precision control signal controls the block adder selected by the two-choice selector in a one-to-one correspondence. Carries are not propagated between approximate adders. Only when the precision control signal is 0000 do all precise adders output precise results. Other precision control signals output addition results of varying degrees of approximation. When the precision control signal is 0001, the approximate adder is selected from the first sub-adder from the lowest to the highest bit. When the precision control signal is 0011, the approximate adder is selected from the first and second sub-adders from the lowest to the highest bit. When the precision control signal is 0111, the approximate adder is selected from the first, second, and third sub-adders from the lowest to the highest bit. When the precision control signal is 1111, all approximate adders are used to output approximate results. As the number of 1s in the precision control signal increases, it also indicates that the exponent difference between the two input floating-point numbers is too large, and more approximate adders can be used to achieve the purpose of precision control.

[0085] Furthermore, the sign bit is subjected to an exclusive-OR operation, and finally the approximate floating-point addition module 4 outputs the partial sum result. The approximate floating-point multiplication result is a floating-point number.

[0086] In this embodiment, two single-precision floating-point numbers are used as an example to perform an approximate floating-point multiplication and accumulation calculation using the approximate floating-point multiplication and accumulation circuit of this embodiment. Assume that there are multiple sets of data that have been multiplied and accumulated, and this time the calculation is performed on the next set of data.

[0087] First, the preprocessing module 5 inputs the single-precision floating-point number A (decimal 1.3867, binary 0011 1111 10110001 0111 1111 0110 0011) and the single-precision floating-point number B (decimal 0.895, binary 0011 1111 01100101 0001 1110 1011 1000), after data preprocessing, the sign bit sign_A (0), exponent part exp_A (01111111) and mantissa part mant_A (101100010111111101100011) of the single-precision floating-point number A, as well as the sign bit sign_B (0), exponent part exp_B (01111110) and mantissa part mant_B (111001010001111010111000) of the single-precision floating-point number B are obtained. The preprocessing results are all output to the approximate floating-point multiplication module 2.

[0088] Next, the exponent portion exp_A of the single-precision floating-point number A and the exponent portion exp_B of the single-precision floating-point number B enter the approximate floating-point multiplier precision arbitration module 1. The exponent receiver 111 receives the exponent portions of the two single-precision floating-point numbers and sends them to the leading-one detector 112, which obtains the highest-order bits (LOD_A(0111) and LOD_B(0111)) of the exponents of the two single-precision floating-point numbers. Subtracting the difference between the two exponents through the subtractor 113 yields a value of 0. Based on the difference being 0, the multiplexer selector 114 outputs a signal 10. The approximate resolution configuration unit 12 then interprets the signal 10 as a precision control signal 11.

[0089] Next, the precision control signal 11 is input into the approximate floating-point multiplication module 2, which performs mantissa multiplication, exponent addition, and sign bit determination on the single-precision floating-point numbers A and B. Based on the precision control signal 11, all 25-bit adders 211-21n in the adder array 21 in the approximate floating-point multiplication module 2 are configured with approximate adders for the lower 12 bits and approximate adders for the upper 13 bits. After passing through the adder array 21, the mantissa multiplication result is output as: 100111101111111100100000. The exponent part is added using a precise adder and shifted to obtain 011111111, and the sign bit is XORed to obtain 0. Finally, the approximate floating-point multiplication module 2 outputs the approximate floating-point multiplication result C (0011 1111 1001 1110 1111 1111 0010 0000).

[0090] Assuming that the partial sum D obtained by the previous approximate floating-point addition module 4 is stored in the partial sum register module 6, the approximate floating-point multiplication result C and the partial sum D (decimal 27.384, binary 0100 00011101 1011 0001 0010 0110 1111) obtained by the approximate floating-point multiplication module 2 enter the approximate floating-point addition module 4 for this floating-point addition calculation. The approximate floating-point multiplication result C includes: the exponent part exp_C (01111111), the sign bit sign_C (0), and the mantissa part mant_C (100111101111111100100000), and the partial sum D includes: the exponent part exp_D (10000011), the sign bit sign_D (0), and the mantissa part mant_D (110110110001001001101111).

[0091] Next, in the approximate floating-point adder precision arbitration module 3, the exponent receiver 311 receives the exponent portion of the approximate floating-point multiplication result C and the partial sum D, and sends it to the leading one detector 312, obtaining the highest bit LOD_C (0111) and LOD_D (1000) of the exponent bits of the approximate floating-point multiplication result C and the partial sum D. The difference obtained by subtraction through the subtractor is 1. The multiplexer selector 314 outputs a signal 011 based on the difference being 1. The approximate resolution configuration unit 32 then interprets the signal 011 as a precision control signal 0111.

[0092] Finally, the precision control signal 0111 is input to the approximate floating-point addition module 4. The sign bit is determined to be 00 based on the size of the exponent and mantissa. The exponent is aligned with the maximum exponent sign_D of the approximate floating-point multiplication result C and the partial sum D, resulting in the exponent result 10000011. The mantissa mant_C is then shifted to (100000011110111111110010), and the mantissa is then added. Based on the precision control signal 0111, the 24-bit mantissa adder is configured with a precise adder for the top 6 bits and three 8-bit approximate adders for the bottom 18 bits. The approximate output is 1010111001111000111011111. The exponent part is also adjusted again according to the range of the mantissa to obtain the final approximate adder output part and result of 10000010 (0 1000 0010 1010 1110 0111 1000 1110 11111).

[0093] This process is a multiplication-addition calculation. The partial sums obtained from each multiplication-addition calculation are stored in registers and used for the next multiplication-addition calculation. After multiple cycles, the multiplication-accumulation calculation is completed until the termination signal arrives, at which point the calculation stops and the final multiplication-accumulation result is output.

[0094] In another embodiment of the present application, the present application provides an approximate floating-point multiplication and accumulation method, which is applied to the above-mentioned approximate floating-point multiplication and accumulation circuit. Figure 8 , Figure 8 This is a flowchart of the approximate floating-point multiplication and accumulation method proposed in this application, including steps S1 to S13.

[0095] Step S1: input floating point number;

[0096] Step S2: Input floating point number exponential analysis;

[0097] Step S3: Generate configuration code;

[0098] Step S4: Determine whether to use approximate calculation. If so, proceed to step S5; if not, proceed to step S6;

[0099] Step S5: approximate configuration;

[0100] Step S6: adopt mantissa multiplication;

[0101] Step S7: Input floating point number exponential analysis;

[0102] Step S8: Generate configuration code;

[0103] Step S9: Determine whether to use approximate calculation, if yes, go to step S10; if not, go to step S11;

[0104] Step S10: approximate configuration;

[0105] Step S11: adding the mantissas;

[0106] Step S12: Determine whether the accumulation is completed. If so, proceed to step S13; if not, return to step S8;

[0107] Step S13: Output the result.

[0108] The input numbers of step S7 include: the approximate floating-point multiplication result and the partial sum result obtained after the last approximate floating-point addition calculation.

[0109] The approximate floating-point multiplication and accumulation circuit and method proposed in this application can dynamically adjust the calculation process according to the characteristics of the input data, and flexibly choose to use approximate calculation or precise calculation mode. When the input data differs greatly, the circuit gives priority to precise calculation to ensure the accuracy of the calculation result; when the input data differs less, the circuit switches to approximate calculation mode to simplify the calculation process, speed up the calculation speed and reduce power consumption. This dynamic adjustment mechanism can achieve the best balance between calculation accuracy and hardware resource utilization in different application scenarios, meet the calculation accuracy of different requirements, improve the calculation speed and reduce power consumption while maintaining a certain accuracy.

[0110] Although the present application has been disclosed above with reference to the embodiments, they are not intended to limit the present application. Anyone with ordinary knowledge in the technical field may make slight changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be determined by the scope of the appended patent application.

Claims

1. An approximate floating-point multiplication-accumulation circuit, characterized in that: include, Preprocessing module; an approximate floating-point multiplier precision arbitration module connected to the preprocessing module; an approximate floating-point multiplication module, connected to the preprocessing module and the approximate floating-point multiplier precision arbitration module respectively; an approximate floating-point adder precision arbitration module connected to the approximate floating-point multiplication module; an approximate floating-point addition module, connected to the approximate floating-point multiplication module and the approximate floating-point adder precision arbitration module respectively; a partial sum storage module connected to the approximate floating-point addition module; The approximate floating-point multiplier precision arbitration module is configured to receive a preprocessed floating-point number, input the exponents of the multiplier and the multiplicand, output different signals according to the magnitude difference of the exponents, parse the different signals into corresponding decimal values, generate a corresponding number of 1 signals according to the size of the decimal values, receive a sequence of 1 signals, perform a bit-by-bit right shift operation under the drive of a shift pulse, and output a precision control signal for controlling the approximate floating-point multiplication module when the number of shifts reaches a preset bit width. The precision control signal is used to switch between precise and different approximate schemes during mantissa multiplication. The approximate floating-point adder precision arbitration module is used to receive the approximate floating-point multiplication result and the partial sum result obtained after the previous approximate floating-point addition calculation, input the exponent part of the addend and the summand, output different signals according to the magnitude difference of the exponent, parse the different signals into corresponding decimal values, generate a corresponding number of 1 signals according to the size of the decimal value, receive a sequence of 1 signals, perform a bit-by-bit right shift operation under the drive of a shift pulse, and output a precision control signal for controlling the approximate floating-point addition module when the number of shifts reaches a preset bit width, wherein the precision control signal is used to switch between precise and different approximate schemes during mantissa addition; The approximate floating-point multiplication module receives a precision control signal and selects each adder in the addition array to use an approximate adder or a precise adder; The approximate floating-point addition module receives a precision control signal. In a one-to-one correspondence manner, each precision control signal controls a two-or-one selector to select the use of an exact sub-adder or an approximate sub-adder, and different numbers of approximate sub-adders are selected according to the precision control signal.

2. The approximate floating-point multiplication-accumulation circuit according to claim 1, wherein: The approximate floating-point multiplier precision arbitration module includes: a floating-point multiplication exponent input analysis unit and a first approximate resolution configuration unit, wherein the floating-point multiplication exponent input analysis unit is connected to the first approximate resolution configuration unit.

3. The approximate floating-point multiplication-accumulation circuit according to claim 2, wherein: The floating-point multiplication exponent input analysis unit includes: a first exponent receiver, a first leading one detector, a first subtractor and a first multiplexer selector, and the first exponent receiver, the first leading one detector, the first subtractor and the first multiplexer selector are connected in sequence.

4. The approximate floating-point multiplication-accumulation circuit according to claim 2, wherein: The first approximate analysis configuration unit includes: a first shift controller and a first 4-bit shift register, and the first shift controller and the first 4-bit shift register are connected in sequence.

5. The approximate floating-point multiplication-accumulation circuit according to claim 1, wherein: The approximate floating-point multiplication module includes: an adder array, the adder array includes n adders, each adder includes two sub-adders, and the sub-adders include: a first two-to-one selector, a first precise adder, and a first approximate adder. The first two-to-one selector is connected to the first precise adder and the first approximate adder respectively, the first precise adder is connected to the first approximate adder, the first two-to-one selector of each sub-adder is connected, the first precise adder of each sub-adder is connected, and the first approximate adder of each sub-adder is connected.

6. The approximate floating-point multiplication-accumulation circuit according to claim 1, wherein: The approximate floating-point adder precision arbitration module includes: a floating-point addition exponent input analysis unit and a second approximate resolution configuration unit, wherein the floating-point addition exponent input analysis unit is connected to the second approximate resolution configuration unit.

7. The approximate floating-point multiplication-accumulation circuit according to claim 6, wherein: The floating-point addition exponent input analysis unit includes: a second exponent receiver, a second leading one detector, a second subtractor and a second multiplexer, and the second exponent receiver, the second leading one detector, the second subtractor and the second multiplexer are connected in sequence.

8. The approximate floating-point multiplication-accumulation circuit according to claim 6, wherein: The second approximate analysis configuration unit includes: a second shift controller and a second 4-bit shift register, and the second shift controller and the second 4-bit shift register are connected in sequence.

9. The approximate floating-point multiplication-accumulation circuit according to claim 1, wherein: The approximate floating-point addition module includes: four sub-adders, each sub-adder includes: a second two-to-one selector, a second precise adder, and a second approximate adder, the second two-to-one selector is connected to the second precise adder and the second approximate adder respectively, the second precise adder is connected to the second approximate adder, the second two-to-one selector of each sub-adder is connected, the second precise adder of each sub-adder is connected, and the second approximate adder of each sub-adder is connected.

10. An approximate floating-point multiplication and accumulation method, characterized in that: The approximate floating-point multiplication-accumulation circuit according to any one of claims 1 to 9 comprises: Step S1: input floating point number; Step S2: Input floating point number exponential analysis; Step S3: Generate configuration code; Step S4: Determine whether to use approximate calculation. If so, proceed to step S5; if not, proceed to step S6; Step S5: approximate configuration; Step S6: adopt mantissa multiplication; Step S7: Input floating point number exponential analysis; Step S8: Generate configuration code; Step S9: Determine whether to use approximate calculation, if yes, go to step S10; if not, go to step S11; Step S10: approximate configuration; Step S11: adding the mantissas; Step S12: Determine whether the accumulation is completed. If so, proceed to step S13; if not, return to step S8; Step S13: output the result; Step S3 includes: outputting different signals according to the magnitude difference of the exponents, parsing the different signals into configuration codes, interpreting the parsed configuration codes, generating a corresponding number of 1 signals, receiving a sequence of 1 signals, performing a bit-by-bit right shift operation under the drive of a shift pulse, and generating a precision control signal when the number of shifts reaches a preset bit width to switch between precise and different approximate schemes; The input number of step S7 includes: the approximate floating-point multiplication result and the partial sum result obtained after the last approximate floating-point addition calculation; Step S8 includes: outputting different signals according to the magnitude difference of the exponents, parsing the different signals into configuration codes, interpreting the parsed configuration codes, generating a corresponding number of 1 signals, receiving a sequence of 1 signals, performing a bit-by-bit right shift operation under the drive of a shift pulse, and when the number of shifts reaches a preset bit width, generating a precision control signal to switch between precise and different approximate schemes.

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