Interruption detection method, device, electronic device and readable storage medium

Abstract

The present application discloses an interrupt detection method, apparatus, electronic device, and readable storage medium. The method comprises: when translating instructions included in each basic block of a source program in a client, obtaining the instruction type of a first instruction included at a preset position in the basic block when the translation reaches the first instruction; if the instruction type is the preset type, writing an interrupt detection instruction before a second instruction; the second instruction is the translation result of the first instruction; and executing the interrupt detection instruction before executing the second instruction, thereby performing an event response corresponding to the second instruction based on a detected interrupt signal. This can reduce the overall code space occupied and dynamic execution time of the target program, thereby improving translator performance.

Description

Technical Field

[0001] The present application belongs to the field of computer technology, and specifically relates to an interruption detection method, device, electronic device and readable storage medium. Background Art

[0002] Binary translation converts instructions from one instruction set architecture (ISA) into instructions from another ISA. During the binary translation process, if the system-level binary translator supports the client operating system, it must provide the necessary hardware device emulation. Typically, after a hardware device completes a requested operation, it sends an interrupt signal to the processor, which then handles the interrupt accordingly. Therefore, the system-level binary translator must also respond to the client's interrupt mechanism through emulation.

[0003] In related technologies, system-level binary translators usually insert a dynamic detection code with an interrupt flag bit into each basic block. However, this method will cause a significant increase in the amount of translated target program code, which not only generates more storage space and dynamic execution time, but also the frequent interrupt detection will cause the translator performance to degrade. Summary of the Invention

[0004] The present application aims to provide an interrupt detection method, device, electronic device and readable storage medium, which at least solves the problem in the prior art that the amount of target program code after translation increases significantly, occupies more storage space and dynamic execution time, and frequent interrupt detection also leads to a decline in translator performance.

[0005] In order to solve the above technical problems, this application is implemented as follows:

[0006] In a first aspect, an embodiment of the present application provides an interruption detection method, comprising:

[0007] When translating instructions included in each basic block of the source program in the client, when translating to a first instruction included in a preset position in the basic block, obtaining an instruction type of the first instruction;

[0008] In the case where the instruction type is a preset type, an interrupt detection instruction is written before the second instruction; the second instruction is a translation result of the first instruction;

[0009] The interrupt detection instruction is executed before executing the second instruction, so as to perform an event response corresponding to the second instruction according to the detected interrupt signal.

[0010] In a second aspect, an embodiment of the present application further provides an interruption detection device, comprising:

[0011] a translation module configured to, when translating instructions included in each basic block of a source program in a client, obtain an instruction type of a first instruction included in a preset position in the basic block when the translation reaches the first instruction;

[0012] A writing module, configured to write an interrupt detection instruction before a second instruction when the instruction type is a preset type; the second instruction is a translation result of the first instruction;

[0013] The detection module is configured to execute the interrupt detection instruction before executing the second instruction, thereby performing an event response corresponding to the second instruction according to the detected interrupt signal.

[0014] In a third aspect, an embodiment of the present application further provides an electronic device comprising a processor, a memory, and a program or instruction stored in the memory and executable on the processor, wherein the program or instruction, when executed by the processor, implements the method described in the first aspect.

[0015] In a fourth aspect, an embodiment of the present application further provides a readable storage medium, which, when the instructions in the readable storage medium are executed by a processor of an electronic device, enables the electronic device to execute the method described in the first aspect.

[0016] In summary, in this embodiment, during the translation of a basic block, it can be decided whether to insert an interrupt detection instruction based on the instruction type of the first instruction in the basic block, and the interrupt detection instruction can be inserted before an instruction of a preset type. In this way, when a key change occurs in the program execution path, interrupt detection can be performed in a timely manner to ensure that the interrupt request is responded to at the appropriate time without interfering with the normal program execution process. This can prevent redundant code from being inserted into most basic blocks that do not require interrupt detection, thereby effectively reducing the storage space and dynamic execution time of the target program obtained after translation and improving the performance of the translator. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 This is a schematic diagram of a binary translation provided by the background technology of this application;

[0018] Figure 2 This is a flow chart of an interruption detection method provided by an embodiment of the present application;

[0019] Figure 3 is a flow chart of another interruption detection method provided by an embodiment of the present application;

[0020] Figure 4 is a block diagram of an interruption detection device provided in an embodiment of the present application;

[0021] Figure 5is a block diagram of an electronic device according to an exemplary embodiment;

[0022] Figure 6 is a block diagram of another electronic device according to an exemplary embodiment. DETAILED DESCRIPTION

[0023] The method provided in the embodiment of the present application is described in detail below through specific embodiments and their application scenarios in conjunction with the accompanying drawings.

[0024] Before introducing the interrupt detection method, apparatus, electronic device, and readable storage medium provided by this application, the application scenarios involved in each embodiment of this application are first introduced. This application can be applied to the scenario of performing interrupt detection when the source program of the source architecture platform is running on the target architecture platform.

[0025] Currently, hardware designs for different instruction set architectures (ISAs) support many different instructions, resulting in incompatibility between executable files compiled for one ISA and other platforms. Binary translation technology can translate programs from one source architecture to run on a different target architecture.

[0026] In the embodiment of the present application, the binary translator can use the "translation and execution" method to translate the client architecture instructions into host architecture instructions and run them during execution. After the translator reads the binary file, it usually translates and executes it at the granularity of basic blocks (TB); Figure 1 As shown, an executable program developed based on a client architecture platform can be read from the executable program to read a basic block to be executed, and a translation result corresponding to the basic block to be executed is searched in a code cache area. If the basic block is not found, the basic block is translated, the translated translation result is stored in the code cache area, and the translated translation result is executed. If the translation result is found, the translation result of the basic block can be directly executed.

[0027] The system-level binary translator, included in the binary translator, supports the operation of the client operating system (the emulated operating system). This requires emulating the corresponding hardware devices in the client to adapt to the client operating system. For example, the simulated processor communicates with the hardware devices via an interrupt mechanism. When the hardware device completes the requested operation, it sends an interrupt signal to the processor, notifying it of an event requiring processing. Therefore, the system-level binary translator also needs to respond to the client's interrupt mechanism through emulation.

[0028] However, due to the basic block chaining technology used in binary translation, one translated basic block can jump directly to another translated code block for execution. This can cause the program's execution logic to spend extended periods of time executing the basic block code cached in the translator. To ensure responsiveness to interrupt signals in this situation and prevent untimely interrupt processing, system-level binary translators typically insert a dynamic interrupt flag detection code into the instruction code corresponding to each basic block. However, this interrupt detection code consumes additional code space and dynamic execution time, and frequent interrupt detection can also degrade translator performance.

[0029] In order to solve the above problems, the present application provides an interrupt detection method, device, electronic device and readable storage medium, which can determine whether to insert an interrupt detection instruction according to the instruction type of the first instruction in the basic block during the translation of the basic block, and can insert the interrupt detection instruction before the instruction of the preset type. In this way, when a key change occurs in the program execution path, interrupt detection can be performed in a timely manner to ensure that the interrupt request is responded to at the appropriate time without interfering with the normal program execution process. It can prevent most basic blocks that do not require interrupt detection from being inserted with redundant code, thereby effectively reducing the storage space and dynamic execution time of the target program obtained after translation, and improving the performance of the translator.

[0030] The method provided in the embodiment of the present application is described in detail below through specific embodiments and their application scenarios in conjunction with the accompanying drawings.

[0031] Figure 2 This is a flowchart of an interrupt detection method provided in an embodiment of the present application, and the method includes the following steps.

[0032] Step 101 : when translating instructions included in each basic block of a source program in a client, when translating to a first instruction included in a preset position in the basic block, obtaining an instruction type of the first instruction.

[0033] In this step, each basic block included in the source program in the client may be translated first, and the instructions included in each basic block may be translated into instructions corresponding to the host architecture.

[0034] The source program may represent an application developed based on a source architecture platform (client architecture platform). That is, the source program is a program developed based on a first instruction set architecture. The basic block refers to a sequence of instructions executed sequentially in the source program, and the source program may include multiple basic blocks.

[0035] First, when it is necessary to run a client program developed based on a source architecture platform (i.e., the source program in this application) on a host architecture platform, the source architecture instructions in each basic block included in the source program can be translated into host architecture instructions in real time based on the instructions actually executed on the basic block.

[0036] For example, the source architecture platform can be represented as an x86 architecture platform, the host architecture platform can be represented as another architecture platform, and the binary program can be represented as an x86 program. When an x86 program developed based on the x86 architecture platform is run on another architecture platform, a basic block in the x86 program can be translated for the instructions in the basic block.

[0037] For example, a basic block instruction sequence included in an x86 program can be expressed as follows.

[0038] MOV EAX,5; assign the immediate value 5 to the EAX register;

[0039] MOV EBX,3; assign the immediate value 3 to the EBX register;

[0040] ADD EAX,EBX; Add the values of EAX and EBX and store the result in EAX;

[0041] MOV DWORD PTR [0x1000],EAX; stores the value of EAX to the memory address [0x1000].

[0042] Since the register naming and instruction format in the instruction set of another architecture platform are different from those of x86, the general registers of the other architecture platform can be set to a0, a1, etc. When translating the basic block instruction into an instruction that can be executed on the other architecture platform, the translation result of the basic block can be expressed as follows.

[0043] li a0,5; load the immediate value 5 into the a0 register;

[0044] li a1,3; load the immediate value 3 into the a1 register;

[0045] add a0,a0,a1; add the values of a0 and a1 and store the result in a0;

[0046] sd a0,0x1000; stores the value of a0 to memory address 0x1000.

[0047] In this way, the instructions included in each basic block can be translated into instructions corresponding to the host machine architecture.

[0048] Then, when the translation reaches a first instruction included in a preset position in the basic block, the instruction type of the first instruction may be obtained.

[0049] Among them, the first instruction is an instruction that can change the execution order of the program. It can be implemented by jumping to other locations in the program to continue execution according to specific conditions or unconditionally when executing the program, rather than executing them in the order in which the instructions are stored in the memory.

[0050] In this step, during the translation of the basic block, the instruction sequence corresponding to the basic block in the source program can be first obtained, and then the corresponding instruction sequence in the source program can be translated in sequence. When translating to the instruction included in the preset position, the instruction corresponding to the preset position can be detected to obtain the instruction type of the first instruction.

[0051] A basic block is a sequence of instructions executed sequentially within a program, with a single entry and exit point. Within this sequence, instructions are executed sequentially, without any jumps (except at the end of the basic block). For example, in a simple program that calculates the sum of two numbers and outputs the result, the continuous instructions from the instruction that reads the two numbers to the instruction that completes the addition constitute a basic block.

[0052] Optionally, for executable programs developed for a specific architecture, a disassembly operation can be performed first. Disassembly tools convert the program's binary machine code into a sequence of instructions in assembly language. For example, under the x86 architecture, tools such as the Capstone disassembler (used to disassemble machine code into assembly instructions) can be used to disassemble executable files into human-readable assembly instructions. The disassembled instruction sequence can then be analyzed and divided using specified instructions to obtain basic blocks of the source program. These specified instructions can include jump instructions (such as JMP, CALL, RET, etc.) and conditional instructions (such as JE, JNE, etc.).

[0053] After obtaining the specific position of each basic block in the source program and the corresponding instruction sequence, the corresponding instruction sequence in the source program can be translated in sequence. When translating to the instruction included in the preset position, the corresponding instruction at the preset position can be detected to obtain the instruction type of the first instruction.

[0054] For example, for a basic block of a source program containing multiple instructions, the instruction position at offset 5 can be set as the preset position. In other words, counting from the start instruction of the instruction sequence, the sixth instruction is the preset location to be tested. For example, the instruction sequence of a basic block corresponding to the source program can be as follows.

[0055] Offset instructions

[0056] 0LI R0,5;

[0057] 1LI R2,3;

[0058] 2ADD R0,R0,R2;

[0059] 3LI R3,10;

[0060] 4SUB R3,R3,R2;

[0061] 5JMP target label; #preset position;

[0062] 6MUL R0,R0,R3;

[0063] 7SD R0,0x1000.

[0064] In a possible implementation, the first instruction is a jump instruction. When obtaining the instruction type of the first instruction, the jump type of the jump instruction may be obtained.

[0065] Considering that different instruction set architectures have specific jump instructions, for example, in the x86 architecture, common jump instructions include unconditional jump (JMP), jump if equal (JE), jump if not equal (JNE), jump if greater than (JG), etc. By comparing the opcode of the instruction at a preset position with the opcodes included in the known jump instruction set in the x86 architecture, it can be determined whether the instruction is a jump instruction.

[0066] For example, from the instruction sequence of the source program corresponding to the above basic block, it can be seen that when the instruction with offset 5 at the specified position is translated, it is found that the instruction is JMP target label, which means that when the processor executes the JMP target_label instruction, it will immediately jump to the other address identified by the target_label label to continue execution, and will no longer execute subsequent instructions (such as MUL R0,R0,R3 and SD R0,0x1000).

[0067] Jump instructions can be divided into unconditional jumps and conditional jumps. For example, unconditional jump instructions (such as JMP) will jump directly to the specified target address without satisfying any conditions; while conditional jump instructions (such as JE, JNE, etc.) can jump to a specified target address when the given conditions are met, and can jump to another specified target address when the given conditions are not met.

[0068] Therefore, the jump type of the first instruction can be determined based on the operation code of the first instruction. For example, if the operation code is JMP, it is an unconditional jump; if it is JE, JNE, etc., it is a conditional jump.

[0069] In some embodiments, the preset position may be located at any position in the instruction sequence. In this application, the position of the preset position in the instruction sequence is not limited. Optionally, the preset position may be set to the last instruction of the basic block at the end.

[0070] This is done to ensure the integrity of instructions during program execution. Since a basic block is typically a sequence of instructions executed sequentially with a single entry and exit, setting the preset position at the end of the basic block ensures that this sequence is fully executed without interruption, achieving its intended function. For example, in a basic block that calculates matrix multiplication, the instructions within it work together to complete part of the matrix multiplication calculation task. Interrupting the block in the middle will result in incomplete or erroneous calculation results. Only by setting the preset position at the end of the basic block can the entire calculation step be completed as an atomic operation.

[0071] Setting the preset position at the end of the basic block aligns with the program's sequential execution logic. This is because a basic block, as a sequence of instructions executed sequentially within a program, typically completes a series of related operations internally before deciding the next execution path based on conditional judgments or jump instructions. Setting the preset position at the end of a basic block aligns with this execution characteristic of basic blocks, enabling timely interrupt detection after a basic block completes its intended task. Based on the detection result, the program can then decide whether to continue executing the next basic block or perform interrupt processing, making the program's execution flow clearer and more organized.

[0072] For example, in a program that calculates factorials, the factorial calculation operation will be completed within a basic block. When the basic block is executed to the end position, it means that the factorial calculation is completed. At this time, an interrupt detection is performed, and then based on whether there is an interrupt signal, it is decided whether to continue to perform other calculation tasks or handle the interrupt. This conforms to the logical order of the program to complete the calculation first and then perform other operations.

[0073] Therefore, when translating to the first instruction included in the end position, the first instruction corresponding to the end position can be detected to obtain the instruction type of the first instruction.

[0074] For example, in the x86 architecture, the instruction sequence of a basic block of a source program containing multiple instructions can be expressed as follows.

[0075] MOV AX,10; assign 10 to register AX;

[0076] ADD AX,20; Add 20 to the value of AX;

[0077] CMP AX,30; Compare the values of AX and 30;

[0078] JE equal_label; conditional jump instruction, if equal, jump to equal_label;

[0079] JMP end_block; unconditional jump instruction, jump to end_block;

[0080] equal_label:

[0081] MOV AX,40; If they are equal, assign 40 to AX;

[0082] end_block:

[0083] MOV BX,AX; assign the value of AX to BX.

[0084] When it is detected that the last instruction is JE (Jump if Equa, conditional jump instruction), when the result of the previous comparison operation is equal (the zero flag ZF in the flag register is 1), the program will jump to the specified target address (for example, equal_label); if they are not equal (ZF=0), it will continue to execute the next instruction sequentially.

[0085] When the last instruction is detected as JMP (unconditional jump instruction), the program will jump directly to the specified target address (such as end_block) regardless of any conditions.

[0086] Step 102: When the instruction type is a preset type, write an interrupt detection instruction before the second instruction.

[0087] The second instruction is a translation result of the first instruction.

[0088] Considering that inserting a dynamic detection code for the interrupt flag bit in the instruction code corresponding to each basic block will result in additional code space and dynamic execution time, it is possible to determine whether to perform interrupt detection for different jump types based on the instruction type (i.e., jump type) of the first instruction in the basic block. It is possible to stop writing interrupt detection instructions in cases other than the preset types. This can reduce unnecessary interrupt detection and avoid inserting interrupt detection code in cases where the loop execution will not detect the interrupt in a timely manner or where the interrupt detection has already been performed in other related instructions. For example, the not taken (condition not met) branch of the conditional jump and the return-type indirect jump instruction can avoid unnecessary interrupt detection operations in these cases, thereby reducing the system's additional overhead and improving the execution efficiency of the translated program.

[0089] Step 103: Execute the interrupt detection instruction before executing the second instruction, so as to perform an event response corresponding to the second instruction according to the detected interrupt signal.

[0090] In this step, performing an interrupt detection operation before executing the second instruction can ensure that the system can respond to various interrupt events in a timely manner, avoid ignoring interrupts due to jump operations, and ensure the stability, reliability and real-time performance of the system.

[0091] During operation, operating systems may encounter various external or internal events, such as interrupt signals from hardware devices (such as keyboards, mice, and disks) or interrupts triggered by software exceptions (such as divide-by-zero errors and illegal instructions). If the operating system fails to respond to these interrupts in a timely manner, system errors such as data loss and program crashes may occur. By performing interrupt detection before the second instruction, these interrupts can be handled before the program control flow changes, thus ensuring stable system operation.

[0092] By adopting the above technical solution, during the translation of the basic block, it is possible to decide whether to insert an interrupt detection instruction based on the instruction type of the first instruction in the basic block, and the interrupt detection instruction can be inserted before the instruction of the preset type. In this way, when a key change occurs in the program execution path, interrupt detection can be performed in a timely manner to ensure that the interrupt request is responded to at the appropriate time without interfering with the normal program execution process. This can prevent redundant code from being inserted into most basic blocks that do not require interrupt detection, thereby effectively reducing the storage space and dynamic execution time of the target program obtained after translation, and improving the performance of the translator.

[0093] Figure 3 This is a flowchart of another interruption detection method provided in an embodiment of the present application, and the method includes the following steps.

[0094] Step 201: Translate the instructions included in each basic block of the source program in the client.

[0095] Optionally, each basic block included in the source program in the client may be translated, and the instructions included in each basic block may be translated into instructions corresponding to the host architecture.

[0096] Specifically, this step may refer to the above step 101 and will not be described in detail here.

[0097] Step 202: When translating to a first instruction included in a preset position in the basic block, obtain an operation code of the first instruction.

[0098] The first instruction is an instruction that can change the execution order of a program. This allows the program to continue execution by jumping to another location in the program based on a specific condition or unconditional jump instruction, rather than executing the instructions sequentially in the order in which they are stored in memory. The opcode is a binary code used to identify the jump type in the instruction set architecture corresponding to the client.

[0099] Furthermore, the opcode is a binary code used to identify the instruction type in the instruction set architecture corresponding to the client.

[0100] In this step, during the translation of the basic block, the instruction sequence corresponding to the basic block in the source program can be first obtained, and then the corresponding instruction sequence in the source program can be translated in sequence. When translating to the instruction included in the preset position, the instruction corresponding to the preset position can be detected to obtain the instruction type of the first instruction.

[0101] In a possible implementation, the first instruction is a jump instruction. When obtaining the instruction type of the first instruction, the jump type of the jump instruction may be obtained.

[0102] For example, for an instruction sequence of a basic block of a source program containing multiple instructions, the instruction position with an offset of 5 can be set as the preset position. In other words, counting from the beginning instruction of the instruction sequence, the position of the sixth instruction is the preset location to be tested. For example, the instruction sequence of a basic block corresponding to the source program can be as follows:

[0103] Offset instructions

[0104] 0LI R0,5;

[0105] 1LI R2,3;

[0106] 2ADD R0,R0,R2;

[0107] 3LI R3,10;

[0108] 4SUB R3,R3,R2;

[0109] 5JMP target label; #preset position;

[0110] 6MUL R0,R0,R3;

[0111] 7SD R0,0x1000.

[0112] In one possible implementation, considering that different instruction set architectures have specific jump instructions, for example, in the x86 architecture, common jump instructions include JMP (unconditional jump), JE (jump if equal), JNE (jump if not equal), and JG (jump if greater than), etc. By comparing the opcode of the instruction at a preset location with a set of known jump instructions, it can be determined whether the instruction is a jump instruction.

[0113] For example, from the instruction sequence of the source program corresponding to the above basic block, it can be seen that when the instruction with offset 5 is translated, it is found that the instruction is JMP target label, which means that when the processor executes the JMP target_label instruction, it will immediately jump to the address identified by the target_label label and continue execution, and will no longer execute subsequent instructions (such as MUL R0,R0,R3 and SD R0,0x1000).

[0114] When it is determined that the instruction at the end position is a jump instruction, the corresponding jump type, ie, unconditional jump or conditional jump, can be determined by obtaining the operation code of the jump instruction.

[0115] The opcode is a part of the instruction machine code, which defines the specific operation to be performed by the instruction.

[0116] It should be noted that the encoding method and length of opcodes vary in different instruction set architectures. Therefore, the method for obtaining opcodes is usually related to the specific implementation environment.

[0117] In a possible implementation, when translating the jump instruction, a disassembly operation may be performed on the jump instruction to convert the jump instruction into an instruction sequence in the form of assembly language.

[0118] For example, under the x86 architecture, tools such as Capstone Disassembler (used to disassemble machine code into assembly instructions) can be used to disassemble the executable file into human-readable assembly instructions and then extract the opcode of the jump instruction.

[0119] If a jump instruction is determined, the instruction decoder will parse the opcode according to the instruction encoding rules. Instructions typically consist of an opcode and operands, with the opcode occupying a fixed position in the instruction encoding. For example, in some simple instruction sets, the opcode is located in the first few bits of the instruction. The opcode is parsed from the instruction's binary encoding through bitwise and masking operations.

[0120] For example, taking the instruction stored in a 32-bit register and the opcode in the first 6 bits as an example, the right shift operation can be performed first. Specifically, the instruction code in the 32-bit register can be shifted right by 26 bits as a whole. This is because the opcode is in the first 6 bits. After shifting right by 26 bits, the opcode will be moved to the lowest 6 bits of the register, and the other high bits will be discarded. Then a mask operation can be performed. By performing an AND operation with 0x3F, all bits except the lowest 6 bits can be set to 0, and only the lowest 6 bits are retained. Among them, 0x3F is represented in hexadecimal and converted to binary as 00111111. This is because in the binary form of 0x3F, the lower 6 bits are all 1 and the upper 26 bits are all 0. The bitwise AND operation is performed with the instruction code after the right shift operation, and the opcode in the lowest 6 bits can be accurately extracted through the AND operation.

[0121] Step 203: Search the preset corresponding relationship for the operation type corresponding to the operation code to obtain the instruction type of the first instruction.

[0122] The preset correspondence relationship includes a correspondence relationship between different operation codes and corresponding instruction types.

[0123] In this step, when the first instruction is a jump instruction, a preset corresponding relationship may be first constructed. The preset corresponding relationship may be expressed in the form of a mapping, which stores the corresponding information between the operation code and the jump type.

[0124] Since the operation codes and types of jump instructions vary in different computer architectures, a simple preset correspondence relationship taking the x86 architecture as an example can be expressed as follows.

[0125] Opcode jump type

[0126] 0xE9 unconditional direct jump;

[0127] 0xEB unconditional short jump;

[0128] 0x74 conditional jump (equal jump, ZF=1);

[0129] 0x75 Conditional jump (not equal jump, ZF=0).

[0130] In code, you can also use a dictionary to represent the default opcode mapping. For example, you can use opcode_to_jump_type (used to determine the corresponding jump type based on the opcode) to represent this default mapping. The key is the opcode (expressed as a hexadecimal integer value) and the value is the corresponding jump type description. You can then use the if opcode inopcode_to_jump_type statement to check whether the opcode exists in the dictionary. If so, use opcode_to_jump_type[opcode] to get the corresponding jump type; if not, output a prompt similar to "not found."

[0131] In some embodiments, the jump type may include a conditional jump type, an indirect jump type, an unconditional jump type, and the like.

[0132] Specifically, the conditional jump type includes branches where the condition is satisfied (taken branches) and branches where the condition is not satisfied (not taken branches).

[0133] Because the jump target of conditional jump instructions (such as JE and JNE) depends on whether the condition is met, conditional jump instructions are often used in loop structures to control loop execution. The taken branch causes the program to jump back to the loop start position, forming a loop. If interrupts are not detected promptly during the loop, the interrupts will remain unprocessed for a long time. Therefore, inserting interrupt detection code before the instruction that jumps to the link target in the taken branch of the conditional jump instruction can prevent the problem of long execution time caused by untimely detection caused by the loop structure. The not taken branch indicates that the condition is not met, and the program will continue to execute sequentially, generally avoiding the untimely detection problem caused by the loop structure. Therefore, not inserting interrupt detection code avoids unnecessary detection overhead and improves the execution efficiency of the target program.

[0134] For example, the following instructions represent a loop of instruction sequence A:

[0135] MOV CX,5; Initialize the loop counter to 5;

[0136] loop_start:

[0137] ; Loop body code

[0138] DEC CX;Counter decrements by 1;

[0139] CMP CX,0; Compare the counter to see if it is 0;

[0140] JNE loop_start; If it is not 0 (that is, the condition is met and the taken branch is taken), jump back to loop_start.

[0141] From the above instruction sequence, we can see that JNEloop_start is a conditional jump instruction. When CX is not 0, it will jump back to loop_start through the taken branch, forming a loop.

[0142] During system operation, various external or internal events, such as user keyboard input and hard drive data read / write, can generate interrupt signals. To ensure system responsiveness and stability, these interrupts must be handled promptly. If interrupt detection isn't performed during loop execution, even if an interrupt signal is generated, the system won't be able to respond promptly, leading to data loss and no user feedback. Therefore, inserting detection code before the instruction that jumps to the link target in the taken branch of a conditional jump instruction ensures that an interrupt signal is checked before each loop jump. Once an interrupt is detected, it indicates that the interrupt handler needs to be executed. The host operating system pauses the current loop and switches to executing the interrupt handler. After processing, the loop resumes execution, thus preventing interrupts from remaining unhandled for extended periods of time.

[0143] Indirect jump instructions usually include: return type instructions (such as ret instruction), and non-return type indirect jump instructions (such as MP[eax] instruction).

[0144] Return-type instructions, such as the ret instruction, are used to indicate a function return and restore the execution environment prior to the function call. Since interrupt detection code has already been inserted at the function call instruction, re-checking at the ret instruction will result in duplicate checks. Therefore, the interrupt detection for the ret instruction can be optimized to reduce unnecessary performance loss. Non-return indirect jump instructions (such as JMP[eax]) have relatively complex jump behavior. To ensure that an interrupt can be processed before an indirect jump is performed, interrupt detection code is inserted before the instruction that jumps to the link target after the instruction is translated to detect the existence of an interrupt handler.

[0145] For example, for return-type instructions, an instruction sequence describing a function call and return process can be represented as follows.

[0146] MAIN:

[0147] ;Insert interrupt detection code before function call

[0148] CHECK_INTERRUPT

[0149] CALL SUBROUTINE

[0150] ;Subsequent code

[0151] MOV AX,10

[0152] JMP END_PROGRAM

[0153] ;Subroutine

[0154] SUBROUTINE:

[0155] ;Subroutine code

[0156] MOV BX, 20

[0157] RET; Function returns, no interrupt detection is performed here;

[0158] END_PROGRAM:

[0159] HLT.

[0160] As can be seen from the instruction sequence above, CALLSUBROUTINE is a function call instruction, with the interrupt check code CHECK_INTERRUPT inserted before the call. When the subroutine reaches the RET instruction, the interrupt check has already been performed at the function call, so it is not repeated here. This avoids duplication and reduces performance loss.

[0161] For another example, for a non-return indirect jump instruction, an instruction sequence for the non-return indirect jump instruction can be represented as follows.

[0162] MAIN:

[0163] MOV EAX,[TARGET_ADDRESS]; Load the target address into the EAX register;

[0164] ;Insert interrupt detection code before indirect jump

[0165] CHECK_INTERRUPT

[0166] JMP [EAX]; indirect jump;

[0167] ;Subsequent code

[0168] MOV AX,10

[0169] JMP END_PROGRAM

[0170] ;Code at the target address

[0171] TARGET_CODE:

[0172] MOV BX,20

[0173] JMP END_PROGRAM

[0174] END_PROGRAM:

[0175] HLT.

[0176] As can be seen from the above instruction sequence, JMP[EAX] is a non-return indirect jump instruction. Before executing this instruction, the interrupt check code "CHECK_INTERRUPT" is inserted. This ensures that before the program jumps to the address pointed to by the non-return indirect jump instruction, it checks whether an interrupt handler is available, ensuring the stability and execution response time of the translated target program.

[0177] In this way, by optimizing the interrupt detection of return-type indirect jump instructions and inserting interrupt detection code before non-return-type indirect jump instructions, we can avoid unnecessary repeated detection and reduce performance loss, and ensure that the interrupt handler responds in time before complex jump operations, thereby improving the overall performance and reliability of the target program obtained after translation.

[0178] Furthermore, unconditional jump instructions (such as JMP) will jump to the specified target address regardless of any condition, and the jump behavior is deterministic. Inserting interrupt detection code before the instruction that jumps to the link target after the instruction is translated ensures that the presence of an interrupt is detected before the program jumps, preventing the interrupt handler from being skipped during the jump process and ensuring the timely response of the system to interrupts.

[0179] In the case where the preset type includes a conditional jump type, execute steps 204 and 207 to 209; in the case of an indirect jump type, execute steps 205 to 209; in the case of an unconditional jump type, execute steps 207 and 209.

[0180] Step 204: During the process of translating the first instruction, obtain the instruction to be jumped in the first instruction.

[0181] The instruction to be jumped to includes the next instruction to be executed adjacent to the first instruction.

[0182] For example, taking the x86 architecture as an example, the JE instruction in the x86 architecture means jumping if "equal to" a given condition (i.e., jumping if the condition is met), and the JNE instruction means jumping if "not equal to" a given condition (i.e., jumping if the condition is not met). Therefore, when the first instruction is read, the meaning of the instruction representing the specific operation included in the first instruction can be identified. For example, when it is identified that the instruction representing the specific operation included in the first instruction is the JE instruction, the first instruction indicates that if the condition is met, it will jump to the instruction to be jumped included in the first instruction to execute the instruction to be jumped; and when it is identified that the instruction representing the specific operation included in the first instruction is the JNE instruction, the first instruction indicates that if the condition is not met, it will jump to the instruction to be jumped included in the first instruction to execute the instruction to be jumped. The instruction to be jumped refers to the next instruction to be executed after the execution of the first instruction.

[0183] If the first instruction indicates that the condition is satisfied, step 207 is executed; if the first instruction indicates that the condition is not satisfied, step 208 is executed.

[0184] Step 205: Obtain the operand included in the first instruction.

[0185] The operand is the data address involved in the operation in the first instruction.

[0186] In this step, an indirect jump instruction is first identified by identifying the operation code of the instruction, wherein the indirect jump instruction determines the instruction to be executed through the parameter value included in the second instruction.

[0187] Different instruction set architectures have specific indirect jump instructions. For example, in the x86 architecture, common indirect jump instructions include JMP[reg], JMP[mem+reg*scale+disp], and the RET instruction series (essentially a special indirect jump). The instruction is determined to be an indirect jump instruction by comparing the opcode of the instruction at a preset location with the opcodes included in the known jump instruction set in the x86 architecture.

[0188] For example, the JMP[EAX] instruction, the JMP[0x1000+EBX*4+8] instruction, and the RET instruction are all indirect jump instructions.

[0189] Then, when an indirect jump instruction is identified, the data address included in the indirect jump instruction can be checked to determine the register involved in the jump address calculation.

[0190] For example, for the JMP[reg] instruction form: the operand is a register, such as the EAX register in the JMP[EAX] instruction; for the JMP[mem+reg*scale+disp] instruction form: the operand involves multiple fields, and the registers need to be parsed out, such as the EBX register in the JMP[0x1000+EBX*4+8] instruction; and for the RET instruction: although there is no explicit operand on the surface, it is closely related to the stack pointer register (ESP or RSP, depending on 32-bit or 64-bit mode).

[0191] Step 206: Determine the register type corresponding to the operand.

[0192] In the case where the register involved in the jump address calculation is determined using step 205, step 206 may determine the corresponding register type according to the determined specific register.

[0193] The register type includes a first register type and a second register type, and the first register type includes a general register, and the second register type includes a stack pointer register.

[0194] In one possible implementation, non-return indirect jump instructions are often associated with general-purpose registers (such as EAX and EBX). This is because general-purpose registers can be flexibly assigned and modified during program execution. Non-return indirect jump instructions are often used to implement dynamic program flow control, such as determining the jump target address based on various conditions, runtime calculation results, or external input. By storing the calculated target address in a general-purpose register and then using an indirect jump instruction to jump to the address pointed to by the register, highly flexible jump logic can be implemented.

[0195] Typically, a non-return indirect jump instruction, for example, the JMP[EAX] instruction will jump to the memory address pointed to by the EAX register to execute code. Therefore, when it is determined that the register is a general register (such as EAX, EBX, etc.), it can be determined that the corresponding register type is the first register type.

[0196] In another possible implementation, since the indirect jump instruction of the return type is usually closely related to the stack operation, this is because the return address is pushed into the stack when the function is called, and the return address can be popped from the stack for jumping when the function returns.

[0197] Typically, return-type indirect jump instructions, such as the ret instruction, implicitly use the stack pointer register (ESP). For example, when the ret instruction is executed, it typically pops a value (i.e., the return address) from the top of the stack and loads it into the instruction pointer register (EIP) to return from the function. Therefore, if the register is determined to be the stack pointer register (ESP), the corresponding register type can be determined to be the second register type.

[0198] If the register type is the first register type, step 207 is executed; if the register type is the second register type, step 208 is executed.

[0199] Step 207: Write an interrupt detection instruction before the second instruction.

[0200] In this step, if the preset type is a conditional jump type, an interrupt detection instruction may be written before the to-be-jumped instruction included in the second instruction when the condition indicated in the first instruction is satisfied.

[0201] For example, in the case of inserting the interrupt detection code, the above instruction sequence A can be expressed as follows.

[0202] MOV CX,5; Initialize the loop counter to 5;

[0203] loop_start:

[0204] DEC CX; loop body code; counter decremented by 1;

[0205] CMP CX,0; Compare the counter to see if it is 0;

[0206] CHECK_INTERRUPT; insert interrupt detection code;

[0207] JNE loop_start; If it is not 0 (that is, the condition is met and the taken branch is taken), jump back to loop_start.

[0208] From the above instruction sequence, we can see that CHECK_INTERRUPT is the interrupt detection code inserted. Each time the loop executes to this step, the system will check whether there is an interrupt signal. If so, it will handle it accordingly. If not, it will continue to execute the loop process until the comparison counter reaches 0, and then jump out of the loop process.

[0209] Step 208: Stop before the second instruction and write an interrupt detection instruction.

[0210] In this step, if the preset type is a conditional jump type, then when the condition indicated in the first instruction is not satisfied, the interrupt detection instruction may be written before the to-be-jumped instruction included in the second instruction.

[0211] Step 209 : During the process of running the translation result, an interrupt detection operation is performed before executing the second instruction, thereby responding to the event that triggers the interrupt signal according to the detected interrupt signal.

[0212] In this step, the interrupt identification value stored in the interrupt register may be first obtained.

[0213] The interrupt identification value is an interrupt identification value stored in the interrupt register when an interrupt signal is detected; the interrupt identification value includes a first target value, such as 1, and a second target value, such as 0.

[0214] If the interrupt flag value is the first target value, the second instruction is executed. Alternatively, if the interrupt flag value is the second target value, an exit instruction is executed, where the exit instruction indicates that the execution of the instruction sequence corresponding to the basic block is stopped.

[0215] By adopting the above technical solution, during the translation of the basic block, it is possible to decide whether to insert an interrupt detection instruction based on the instruction type of the first instruction, and the interrupt detection instruction can be inserted before a specific type of instruction. In this way, when a key change occurs in the program execution path, interrupt detection can be performed in a timely manner to ensure that the interrupt is responded to at the appropriate time without interfering with the normal program execution process. Basic blocks that do not require interrupt detection will not be inserted with redundant code, thereby effectively reducing the overall code space occupied by the target program, and can reduce the dynamic execution time of the code, which can improve the performance of the translator.

[0216] Figure 4 This is a block diagram of an interrupt detection device provided by an embodiment of the present application. Figure 4 As shown, the device 300 includes:

[0217] The translation module 301 is configured to, when translating instructions included in each basic block of a source program in the client, obtain an instruction type of a first instruction included in a preset position in the basic block when the translation reaches the first instruction;

[0218] The writing module 302 is configured to write an interrupt detection instruction before a second instruction when the instruction type is a preset type; the second instruction is a translation result of the first instruction;

[0219] The detection module 303 is configured to execute the interrupt detection instruction before executing the second instruction, thereby performing an event response corresponding to the second instruction according to the detected interrupt signal.

[0220] Optionally, the translation module 301 is used to obtain the opcode of the first instruction; the opcode is a binary code used to identify the instruction type in the instruction set architecture corresponding to the client; the operation type corresponding to the opcode is searched in the preset correspondence relationship to obtain the instruction type of the first instruction; the preset correspondence relationship includes the correspondence between different opcodes and corresponding instruction types.

[0221] Optionally, the preset type includes a conditional jump type; the conditional jump type is an instruction type that determines the instruction to be executed by determining whether the condition included in the second instruction is satisfied; the write module 302 is used to obtain the instruction to be jumped in the first instruction during the translation of the first instruction, and the instruction to be jumped is included in the next instruction to be executed adjacent to the first instruction; when the condition is satisfied in the first instruction, start writing the interrupt detection instruction before the instruction to be jumped included in the second instruction; otherwise, stop writing the interrupt detection instruction before the instruction to be jumped included in the second instruction.

[0222] Optionally, the preset type includes an indirect jump type; the indirect jump type is an instruction type for determining the instruction to be executed through the parameter value included in the second instruction; the write module 302 is used to obtain the operand included in the first instruction; the operand is the address of the data involved in the operation in the first instruction; determine the register type corresponding to the operand; and according to the register type, execute the write operation corresponding to the interrupt detection instruction.

[0223] Optionally, the writing module 302 is used to start writing the interrupt detection instruction before the second instruction when the register type is the first register type; and stop writing the interrupt detection instruction before the second instruction when the register type is the second register type.

[0224] Optionally, the preset type includes an unconditional jump type; the writing module 302 is used to insert an interrupt detection instruction between a previous instruction adjacent to the second instruction and the second instruction.

[0225] Optionally, the detection module 303 is used to obtain the interrupt identification value stored in the interrupt register; the interrupt identification value is the mark information sent to the interrupt register by the interrupt detection instruction when the interrupt signal is detected; when the interrupt identification value is the first target value, the second instruction is executed; when the interrupt identification value is the second target value, the exit instruction is executed to stop executing the instruction sequence corresponding to the basic block.

[0226] In summary, this embodiment can determine whether to insert an interrupt detection instruction according to the instruction type of the first instruction in the basic block during the translation of the basic block, and can insert the interrupt detection instruction before the instruction of the preset type. In this way, when a key change occurs in the program execution path, interrupt detection can be performed in a timely manner to ensure that the interrupt request is responded to at the appropriate time without interfering with the normal program execution process. It can prevent redundant code from being inserted into most basic blocks that do not require interrupt detection, thereby effectively reducing the storage space and dynamic execution time of the target program obtained after translation, and improving the performance of the translator.

[0227] Figure 5 1 is a block diagram of an electronic device 500 according to an exemplary embodiment. For example, the electronic device 500 may be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc.

[0228] Reference Figure 5 , the electronic device 500 may include one or more of the following components: a processing component 502 , a memory 504 , a power component 506 , a multimedia component 508 , an audio component 510 , an input / output interface 512 , a sensor component 514 , and a communication component 516 .

[0229] The processing component 502 generally controls the overall operation of the electronic device 500, such as operations associated with display, phone calls, data communications, camera operation, and recording operations. The processing component 502 may include one or more processors 520 to execute instructions to perform all or part of the steps of the above-described method. In addition, the processing component 502 may include one or more modules to facilitate interaction between the processing component 502 and other components. For example, the processing component 502 may include a multimedia module to facilitate interaction between the multimedia component 508 and the processing component 502.

[0230] The memory 504 is used to store various types of data to support operations on the electronic device 500. Examples of such data include instructions for any application or method operating on the electronic device 500, contact data, phone book data, messages, pictures, multimedia, etc. The memory 504 can be implemented by any type of volatile or non-volatile storage device, or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk, or optical disk.

[0231] The power supply assembly 506 provides power to the various components of the electronic device 500. The power supply assembly 506 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the electronic device 500.

[0232] The multimedia component 508 includes a screen that provides an output interface between the electronic device 500 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, it may be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, slides, and gestures on the touch panel. The touch sensors can detect not only the demarcation of a touch or slide action, but also the duration and pressure associated with the touch or slide action. In some embodiments, the multimedia component 508 includes a front-facing camera and / or a rear-facing camera. When the electronic device 500 is in an operating mode, such as a capture mode or a multimedia mode, the front-facing camera and / or the rear-facing camera can receive external multimedia data. Each front-facing camera and the rear-facing camera can have a fixed optical lens system or have a variable focal length and optical zoom capability.

[0233] The audio component 510 is used to output and / or input audio signals. For example, the audio component 510 includes a microphone (MIC) that receives external audio signals when the electronic device 500 is in an operating mode, such as a call mode, a recording mode, or a voice recognition mode. The received audio signals may be further stored in the memory 504 or transmitted via the communication component 516. In some embodiments, the audio component 510 also includes a speaker for outputting audio signals.

[0234] The input / output interface 512 provides an interface between the processing component 502 and peripheral interface modules, such as a keyboard, a click wheel, buttons, etc. These buttons may include but are not limited to: a home button, a volume button, a start button, and a lock button.

[0235] The sensor assembly 514 includes one or more sensors for providing various aspects of status assessment for the electronic device 500. For example, the sensor assembly 514 can detect the open / closed state of the electronic device 500, the relative positioning of components, such as the display and keypad of the electronic device 500. The sensor assembly 514 can also detect changes in the position of the electronic device 500 or a component of the electronic device 500, the presence or absence of user contact with the electronic device 500, the orientation or acceleration / deceleration of the electronic device 500, and temperature changes of the electronic device 500. The sensor assembly 514 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. The sensor assembly 514 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 514 may also include an accelerometer, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0236] The communication component 516 is used to facilitate wired or wireless communication between the electronic device 500 and other devices. The electronic device 500 can access a wireless network based on a communication standard, such as WiFi, a carrier network (such as 2G, 3G, 4G, or 5G), or a combination thereof. In an exemplary embodiment, the communication component 516 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 516 also includes a near-field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0237] In an exemplary embodiment, the electronic device 500 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to implement an interrupt detection method provided in an embodiment of the present application.

[0238] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 504 including instructions, which can be executed by the processor 520 of the electronic device 500 to perform the above method. For example, the non-transitory storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, etc.

[0239] Figure 6FIG. 6 is a block diagram of another electronic device 600 according to an exemplary embodiment. For example, the electronic device 600 may be provided as a server. Figure 6 The electronic device 600 includes a processing component 622, which further includes one or more processors, and a memory resource represented by a memory 632 for storing instructions executable by the processing component 622, such as an application. The application stored in the memory 632 may include one or more modules, each corresponding to a set of instructions. In addition, the processing component 622 is configured to execute instructions to perform an interrupt detection method provided in an embodiment of the present application.

[0240] The electronic device 600 may further include a power supply component 626 configured to perform power management of the electronic device 600, a wired or wireless network interface 650 configured to connect the electronic device 600 to a network, and an input / output interface 658. The electronic device 600 may operate based on an operating system stored in the memory 632.

[0241] An embodiment of the present application also provides a computer program product, including a computer program, and an interrupt detection method implemented when the computer program is executed by a processor.

[0242] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0243] It should be understood that the present application is not limited to the exact structures described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A method for detecting an interruption, characterized in that: The method comprises: When translating instructions included in each basic block of the source program in the client, when translating to a first instruction included in a preset position in the basic block, obtaining an instruction type of the first instruction; When the instruction type is a preset type, an interrupt detection instruction is written before a second instruction; the second instruction is a translation result of the first instruction; when the preset type represents a conditional jump type of a loop type, an instruction to be jumped to in the first instruction is obtained; when the first instruction indicates that a condition is satisfied, the interrupt detection instruction is written before the instruction to be jumped to included in the second instruction; or when the preset type represents an indirect jump type of a non-return type, a register type corresponding to an operand included in the first instruction is obtained; and according to the register type, the interrupt detection instruction is written before the second instruction; The interrupt detection instruction is executed before executing the second instruction, so as to perform an event response corresponding to the second instruction according to the detected interrupt signal.

2. The method according to claim 1, characterized in that The instruction type for obtaining the first instruction includes: Obtaining an operation code of the first instruction; the operation code is a binary code for identifying an instruction type in an instruction set architecture corresponding to the client; The operation type corresponding to the operation code is searched in a preset corresponding relationship to obtain the instruction type of the first instruction; the preset corresponding relationship includes a corresponding relationship between different operation codes and corresponding instruction types.

3. The method according to claim 1, characterized in that The preset type includes a conditional jump type; the conditional jump type is an instruction type that determines an instruction to be executed by determining whether a condition included in the second instruction is satisfied; Then, writing the interrupt detection instruction before the second instruction includes: In the process of translating the first instruction, obtaining the instruction to be jumped in the first instruction; The instruction to be jumped to includes an instruction to be executed next to the first instruction; When the condition indicated in the first instruction is satisfied, the interrupt detection instruction starts to be written before the instruction to be jumped included in the second instruction; otherwise, the interrupt detection instruction stops to be written before the instruction to be jumped included in the second instruction.

4. The method according to claim 1, wherein The preset type includes an indirect jump type; the indirect jump type is an instruction type of an instruction to be executed determined by a parameter value included in the second instruction; Then, writing the interrupt detection instruction before the second instruction includes: Obtaining an operand included in the first instruction; the operand is an address of data involved in an operation in the first instruction; Determine the register type corresponding to the operand; According to the register type, a write operation corresponding to the interrupt detection instruction is executed.

5. The method according to claim 4, characterized in that The executing of the write operation corresponding to the interrupt detection instruction includes: When the register type is the first register type, writing the interrupt detection instruction before the second instruction begins; When the register type is the second register type, the interrupt detection instruction is written before the second instruction.

6. The method according to claim 1, characterized in that The preset type includes an unconditional jump type; Then, writing the interrupt detection instruction before the second instruction includes: An interrupt detection instruction is inserted between a previous instruction adjacent to the second instruction and the second instruction.

7. The method according to any one of claims 1 to 6, characterized in that Executing the interrupt detection instruction before executing the second instruction includes: Obtaining an interrupt identification value stored in an interrupt register; the interrupt identification value is marking information sent to the interrupt register by the interrupt detection instruction when the interrupt signal is detected; When the interrupt flag value is the first target value, executing the second instruction; When the interrupt flag value is the second target value, an exit instruction is executed to stop executing the instruction sequence corresponding to the basic block.

8. An interruption detection device, characterized in that: The device comprises: a translation module configured to, when translating instructions included in each basic block of a source program in a client, obtain an instruction type of a first instruction included in a preset position in the basic block when the translation reaches the first instruction; A writing module is configured to write an interrupt detection instruction before a second instruction when the instruction type is a preset type; the second instruction is a translation result of the first instruction; when the preset type represents a conditional jump type of a loop type, obtain a to-be-jumped instruction in the first instruction; when the first instruction indicates that a condition is satisfied, start writing the interrupt detection instruction before the to-be-jumped instruction included in the second instruction; or when the preset type represents an indirect jump type of a non-return type, obtain a register type corresponding to an operand included in the first instruction; and write the interrupt detection instruction before the second instruction based on the register type; The detection module is configured to execute the interrupt detection instruction before executing the second instruction, thereby performing an event response corresponding to the second instruction according to the detected interrupt signal.

9. An electronic device, characterized in that: The method comprises a processor, a memory, and a program or instruction stored in the memory and executable on the processor, wherein the program or instruction, when executed by the processor, implements the steps of the method according to any one of claims 1 to 7.

10. A readable storage medium, characterized in that: When the instructions in the readable storage medium are executed by a processor of an electronic device, the electronic device is enabled to perform the method according to any one of claims 1 to 7.

Images