Data processing method, data processing device, memory system and electronic device

Abstract

At least one embodiment of the invention provides a data processing method, a data processing device, a memory system and an electronic device. The data processing method comprises the steps that in the error correction process of data, whether a reference error position exists or not is determined, and the reference error position indicates a plurality of fixed error positions capable of correcting errors; in response to the existence of the reference error position, comparing whether the error position of the subsequent correctable error is consistent with the reference error position; and indicating an occurrence of a correctable error in response to the error location of the subsequent correctable error coinciding with the reference error location, or indicating an occurrence of an uncorrectable error in response to the error location of the subsequent correctable error not coinciding with the reference error location. According to the data processing method, inaccurate judgment and false alarm of correctable errors and uncorrectable errors can be avoided, and downtime and other problems caused by inaccurate judgment and false alarm are reduced.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a data processing method, a data processing device, a memory system, and an electronic device. Background Art

[0002] Data is easily disturbed by environmental factors during transmission, communication and storage, resulting in data errors. For example, memory (e.g., DDR memory) is inevitably disturbed by environmental factors such as electromagnetics during operation, resulting in memory errors. For users with high stability requirements, memory errors may cause fatal problems. Especially for servers, which have high requirements for DDR data reliability, DDR memory error correction technology can improve the stability and error correction capabilities of server memory. The ECC (Error Correcting Code, error checking and correction) technology used by mainstream DDR, such as chipkill, uses corresponding ECC algorithms (e.g., RS algorithm or other algorithms) for encoding, decoding, and error correction. Summary of the invention

[0003] At least one embodiment of the present disclosure provides a data processing method, comprising: during a data error correction process, determining whether there is a reference error position, wherein the reference error position indicates a fixed error position of multiple correctable errors; in response to the existence of the reference error position, comparing whether an error position of a subsequent correctable error is consistent with the reference error position; and in response to the error position of the subsequent correctable error being consistent with the reference error position, indicating the occurrence of a correctable error, or, in response to the error position of the subsequent correctable error being inconsistent with the reference error position, indicating the occurrence of an uncorrectable error.

[0004] At least one embodiment of the present disclosure provides a data processing device, including: a reference error position determination unit, configured to: determine whether there is a reference error position during a data error correction process, wherein the reference error position indicates a fixed error position of multiple correctable errors; a comparison unit, configured to: compare whether the error position of a subsequent correctable error is consistent with the reference error position in response to the existence of the reference error position; and a reporting unit, configured to: indicate the occurrence of a correctable error in response to the error position of a subsequent correctable error being consistent with the reference error position, or indicate the occurrence of an uncorrectable error in response to the error position of a subsequent correctable error being inconsistent with the reference error position.

[0005] At least one embodiment of the present disclosure provides a memory system, including: a data processing device as described above; and a memory configured to store data.

[0006] At least one embodiment of the present disclosure provides an electronic device, including: at least one processor; and at least one memory storing instructions, wherein when the instructions are executed by the processor, the processor executes the data processing method as described above.

[0007] At least one embodiment of the present disclosure provides a computer-readable storage medium having computer-readable instructions stored thereon, wherein when the computer-readable instructions are executed by a processor, the processor executes the data processing method as described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments of the present disclosure are briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, and are not intended to limit the present disclosure.

[0009] Figure 1 A schematic diagram showing an exemplary application scenario of the hardware history mechanism;

[0010] Figure 2 A schematic diagram showing an exemplary hardware history mechanism;

[0011] Figure 3 A flowchart of a data processing method according to at least one embodiment of the present disclosure is shown;

[0012] Figure 4 A schematic diagram showing an exemplary structure of a data processing method according to at least one embodiment of the present disclosure;

[0013] Figure 5 A schematic diagram showing a data processing device according to at least one embodiment of the present disclosure;

[0014] Figure 6 A schematic diagram showing a memory system according to at least one embodiment of the present disclosure is shown;

[0015] Figure 7 A schematic diagram showing an electronic device according to at least one embodiment of the present disclosure;

[0016] Figure 8 A schematic diagram showing a computer-readable storage medium according to at least one embodiment of the present disclosure; and

[0017] Fig. 9 A schematic diagram of another electronic device according to at least one embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0018] Reference will now be made in detail to specific embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Although the present disclosure will be described in conjunction with specific embodiments, it will be understood that it is not intended to limit the present disclosure to the described embodiments. On the contrary, it is intended to cover changes, modifications and equivalents included within the spirit and scope of the present disclosure as defined by the appended claims. It should be noted that the method operations described herein can be implemented by any functional block or functional arrangement, and any functional block or functional arrangement can be implemented as a physical entity or a logical entity, or a combination of the two.

[0019] In order to enable those skilled in the art to better understand the present disclosure, the present disclosure is further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0020] Note that the examples to be introduced below are only specific examples, and are not intended to limit the embodiments of the present disclosure to the specific shapes, hardware, connection relationships, operations, values, conditions, data, sequences, etc. shown and described. Those skilled in the art can apply the concepts of the present disclosure to construct more embodiments not mentioned in the present description by reading the present description.

[0021] The terms used in the present disclosure are those common terms currently widely used in the art in consideration of the functions of the present disclosure, but these terms may vary according to the intention of a person of ordinary skill in the art, precedents, or new technologies in the art. In addition, specific terms may be selected by the applicant, and in this case, their detailed meanings will be described in the detailed description of the present disclosure. Therefore, the terms used in the specification should not be understood as simple names, but rather as an overall description based on the meaning of the terms and the present disclosure.

[0022] Flowcharts are used in this disclosure to illustrate the operations performed by the system according to the embodiments of the present application. It should be understood that the preceding or following operations are not necessarily performed precisely in order. On the contrary, various steps may be processed in reverse order or simultaneously as required. At the same time, other operations may also be added to these processes, or one or more operations may be removed from these processes.

[0023] First, the abbreviations and related terms involved in this application are defined and explained.

[0024] DDR (Double Data Rate): double data rate.

[0025] DDR SDRAM: Double data rate synchronous dynamic random access memory, commonly known as DDR.

[0026] ECC (Error Check Correction): Error correction code or error correction coding is a technology that can implement "error checking and correction" to improve the stability of computer operation and increase reliability.

[0027] RS (Reed-Solomon): RS coding, also known as Reed-Solomon codes, is a forward error correction channel coding that is effective for polynomials generated by correcting oversampled data. RS code is a special type of non-binary BCH code with strong error correction capability. For any positive integer S, a corresponding q-based BCH code with a code length of n=qS-1 can be constructed, and q is a power of a prime number. When S=1, q>2, the q-based BCH code with a code length of n=q-1 established is called an RS code. When q=2 m (m>1), the binary RS code whose code element symbols are taken from F(2m) can be used to correct burst errors. It is the most commonly used RS code.

[0028] SDDC (Single Device Data Correction): Corrects the data on a particle

[0029] DDDC (Double Device Data Correction): Corrects the data on two particles

[0030] Channel: Memory channel. Each memory controller can have multiple memory channels, such as the common memory channel 0 (channel 0) and memory channel 1 (channel 1).

[0031] UE (Uncorrectable Error): Uncorrectable error.

[0032] CE (Correctable Error): Correctable error.

[0033] Data Device: Data particle, memory particle that stores data.

[0034] ECC Device: ECC particles, memory particles that store check bits.

[0035] Symbol: Symbol, also known as code element, is the smallest unit in ECC error correction. Generally, there are x4 and x8 particles, and the corresponding symbol is 4 bits and 8 bits of data.

[0036] Fixed Error: An error that occurs repeatedly at a specific location (e.g., pin, chip, etc.) of the memory due to hardware defects, aging, overheating, or other reasons. For example, these errors usually continue to occur during use and the error location is the same, and the error persists even after a restart or reset.

[0037] Fixed wrong position: Fixed the wrong position of the error.

[0038] Random Error: An error that does not recur at a specific location in the memory, but occurs at different locations. For example, this type of error is usually caused by external factors such as radiation, noise, voltage fluctuations, etc., and is unpredictable.

[0039] Random Error Location: Random error location.

[0040] It is understandable that the terms defined above are only exemplary definitions in specific application scenarios to facilitate a better understanding of the present application. For example, the exemplary definitions for specific memory described above can be extended to other types of memory or other storage.

[0041] The ECC algorithm can be used to detect and correct data errors. However, the ECC algorithm may not be comprehensive or perfect, and there is a certain error correction rate and / or error judgment rate. For example, when using x8 as a symbol unit, that is, when a minimum symbol unit is 8 bits of data, the corresponding RS algorithm has a certain algorithm error correction rate.

[0042] In other aspects, there are cases of miscorrection or misjudgment. For example, there is a case where a UE is misreported as a CE, or a CE is misreported as a UE, which causes the system to misjudge. For another example, there is a case where the location of the error is inconsistent with the location where the error is corrected, which causes the system to miscorrect.

[0043] As described above, the RS algorithm may cause misjudgment when using, for example, x8 as a symbol unit. An exemplary remedy is to avoid miscorrection and / or misjudgment by recording the current error position and comparing it (such as the hardware history mechanism described below). However, this method has certain defects. For example, in the case of system instability, the recording mechanism may have additional misjudgments, resulting in system screen flashing UE and possible downtime.

[0044] For example, RS algorithms such as x8 and x4 are currently widely used in DDR controllers. x4 means that the minimum symbol unit is 4 bits, and x8 means that the minimum symbol unit is 4 bits. Of course, there may be other minimum symbol units or other algorithms may be used.

[0045] At present, the RS algorithm of x4 is complete, but the error correction capability is limited. For example, a 128-bit data can only correct 4 bits of data, but there is no false correction or missed correction. In contrast, the error correction capability of the RS algorithm of x8 is twice that of the RS algorithm of x4. For example, 128 bits of data can correct 8 bits of data. However, the RS algorithm of x8 is not complete, such as there is a certain probability of false correction. For example, for a 2-byte error, the accurate error detection rate of the DDR4 chipkill-RS8(18, 16) code is (256-16) / 256=93.75%, and the false detection rate is 6.25%. For another example, for a 2-byte error, the accurate error detection rate of the DDR5 chipkill-RS8(10, 8) code is (256-8) / 256=96.875%, and the false detection rate is 3.125%.

[0046] To make up for this shortcoming, a hardware history mechanism is used exemplarily. The hardware history mechanism is only used in the RS algorithm of x8 to make up for the shortcoming that two errors cannot be detected 100%.

[0047] Figure 1 A schematic diagram showing an exemplary application scenario of the hardware history mechanism.

[0048] See also Figure 1 , the memory channel in the memory controller is shown as DDR5 Ch0, and its corresponding memory DDR5 may include 8 x4 data particles (shown as Figure 1 "x4") and 2 x4 ECC particles (shown as Figure 1 ”ecc” in .

[0049] exist Figure 1 , an exemplary chip fault is shown, in which a fixed error occurs in the data particle at the 4th position, and a random error occurs in the data particle at the 8th position.

[0050] The hardware history mechanism reports errors in cache lines. As long as the error locations of any two ECC words are inconsistent and UE is reported, the entire cache line is UE. If there are multiple CEs in a cache line and their error locations are different, UE will be reported instead.

[0051] See also Figure 1, the cache line size can be 64 bytes, that is, 512 bits. In order to perform ECC check with x8 as the symbol, multiple data (i.e., multiple beat / burst data) read from DDR5 can be combined in pairs to obtain several ECC words. For example, 16 data read from DDR5 (shown as Beat0 to Beat16) are combined in pairs to obtain 8 ECC words, namely Beat0&1, Beat2&3, Beat4&5, Beat6&7, Beat8&9, Beat10&11, Beat12&13, Beat14&15. Each ECC word can include 64 bits of data information and 16 bits of ECC information (shown as 64+16).

[0052] Continue to see Figure 1 , it can be determined that an error has occurred in the data particle at the 4th position based on Beat0&1, Beat2&3, Beat4&5, Beat8&9, Beat10&11, Beat12&13, and Beat14&15, and it can be determined that an error has occurred in the data particle at the 8th position based on Beat6&7.

[0053] exist Figure 1 In the example, since an error occurs in the data particle at the 8th position (for example, a random error), there is a certain probability that another x8 symbol error will be misjudged. After the entire cache line error correction is completed, the hardware history finds that the error position is not completely consistent and reports an uncorrectable error.

[0054] Combine the following Figure 2 Describes an exemplary working principle of the hardware history mechanism.

[0055] Figure 2 A schematic diagram showing an exemplary hardware history mechanism.

[0056] See also Figure 2 , 8 ECC modules (shown as ECC 0 to ECC 7) can perform ECC checks on the ECC words passed into them respectively, so as to determine whether the ECC words have UE or CE errors and the error locations (shown as L1 to L4 and M1 to M4).

[0057] exist Figure 2In the example, 512-bit data can be divided into two groups of 256-bit data, and each group of 256-bit data can be divided into 4 ECC words and thus transmitted to the corresponding ECC module, that is, each ECC module corresponds to a 64-bit ECC word. For example, the first group of 256-bit data can be divided into 4 ECC words and thus transmitted to ECC 0 to ECC 3 respectively, and the second group of 256-bit data can be divided into 4 ECC words and thus transmitted to ECC 4 to ECC 7 respectively. Each ECC module can operate in units of 64 bits.

[0058] It can be understood that the above-mentioned bit sizes are only exemplary, and the present disclosure is not limited thereto. For example, the above-mentioned 512-bit size corresponds to the size of a cache line, and the size of a cache line can be changed based on different processors (e.g., CPUs). For another example, a 256-bit size can correspond to the unit size of a memory controller operation, that is, the memory controller can operate in units of 256 bits, and thus the 256-bit size can be changed based on different memory controllers. For another example, a 64-bit size can correspond to the unit size of an ECC module operation, that is, the ECC module can perform ECC operations in units of 64 bits, and thus the 64-bit size can be changed based on different ECC modules.

[0059] After the error position is determined, the error position may be sent to a cross comparison module to compare the error position.

[0060] An exemplary cross-alignment process is described below.

[0061] The following cross-comparison operations can be performed on the first group of 256 bits of data:

[0062] If CE appears in the first ECC word and the error position is L1, L1 is recorded as the reference error position;

[0063] If CE appears in the second ECC word, the error position is L2. L2 is compared with L1. If they are inconsistent, they are marked as UE. If they are consistent, they are marked as CE.

[0064] If CE appears in the third ECC word, the error position is L3. L3 is compared with L1 and L2 respectively. If there is inconsistency, it is marked as UE. If it is completely consistent, it is marked as CE.

[0065] If CE appears in the fourth ECC word, the error position is L4. L4 is compared with L1, L2, and L3 respectively. If there is inconsistency, it is marked as UE. If it is completely consistent, it is marked as CE.

[0066] The following cross-comparison operations can be performed on the second set of 256-bit data:

[0067] Pass the basic error position L of the second group of 256 bits of data;

[0068] If CE appears in the first ECC word, the error position is M1. M compares M1 with L. If there is inconsistency, it is marked as UE. If it is completely consistent, it is marked as CE.

[0069] If CE appears in the second ECC word, the error position is M2. M2 is compared with L and M1 respectively. If there is inconsistency, it is marked as UE. If it is completely consistent, it is marked as CE.

[0070] If CE appears in the third ECC word, the error position is M3. M3 is compared with M1, M2, and L respectively. If there is inconsistency, it is marked as UE. If it is completely consistent, it is marked as CE.

[0071] If CE appears in the fourth ECC word, the error position is M4. M4 is compared with M1, M2, M3, and L respectively. If there is inconsistency, it is marked as UE. If it is completely consistent, it is marked as CE.

[0072] A correctable error is reported only if all cross comparisons of the two groups of 256-bit data are consistent, otherwise an uncorrectable error is reported.

[0073] After using the hardware history mechanism, in a stable environment, when only fixed errors occur, the overall miscorrection / false correction rate is almost reduced to 0. However, as mentioned above, in an unstable environment or when random errors are caused by other reasons, the hardware history mechanism may have additional misjudgments. In other aspects, misjudgments may lead to miscorrections; or misjudged errors may cause the cross-comparison object to include the wrong position of the misjudgment, resulting in false alarms of CE and UE.

[0074] At least one embodiment of the present disclosure proposes a data processing method, a data processing device, a memory system, an electronic device, and a computer-readable storage medium, which can avoid inaccurate judgment and false alarm of correctable errors and uncorrectable errors, and reduce downtime and other problems caused thereby.

[0075] Figure 3 FIG. 3 is a flow chart of a data processing method 300 according to at least one embodiment of the present disclosure. Figure 3 The described data processing method 300 and its additional aspects can be found below. Figure 4 The invention is implemented in the described data processing device, memory system, electronic device, hardware structure, software structure or hardware structure and software structure.

[0076] See also Figure 3 , the data processing method 300 includes steps S310 to S330.

[0077] In step S310, during the error correction process of data, it is determined whether there is a reference error position, wherein the reference error position indicates a fixed error position of a plurality of correctable errors.

[0078] The error correction process of data can detect and correct errors in, for example, a memory or data transmission process. For example, the error correction process of data can detect whether there is an error or, if there is an error, whether the error is a correctable error or an uncorrectable error and the error location of the error based on data obtained from the memory.

[0079] In some embodiments, the error location may be a particle or a bit of a memory, etc. In some embodiments, the error location may be a channel in a data transmission process.

[0080] Commonly used algorithms in the data error correction process may include Hamming Code algorithm, RS algorithm, low-density parity check code algorithm, Turbo code algorithm, convolutional coding algorithm, etc.

[0081] The multiple correctable errors here may be part or all of the historical correctable errors of the memory.

[0082] In step S320 , in response to the presence of a reference error position, the error position of the subsequent correctable error is compared with the reference error position to see whether they are consistent.

[0083] The error position of the subsequent correctable error may be the error position of any correctable error that needs to be compared with the reference error position for consistency after the reference error position is determined. The subsequent correctable errors may be one or more, and may be continuous or discontinuous in time.

[0084] In step S330, in response to the error location of the subsequent correctable error being consistent with the reference error location, the occurrence of a correctable error is indicated, or in response to the error location of the subsequent correctable error being inconsistent with the reference error location, the occurrence of an uncorrectable error is indicated.

[0085] As described above, according to at least one embodiment of the present disclosure, the data processing method can use the fixed position of the correctable error as the reference error position, and then compare whether the error position of the subsequent correctable error is consistent with the reference error position, so as to determine whether a correctable error and an uncorrectable error have occurred. In this way, it is possible to avoid the situation where the correctable error and the uncorrectable error are misreported by using the random error as the reference error position for comparison, thereby avoiding the inaccurate judgment and misreporting of the correctable error and the uncorrectable error, and reducing the downtime and other problems caused by it.

[0086] For example, factors such as interference or environmental instability may cause random errors to occur, and thus the data processing method according to at least one embodiment of the present disclosure can avoid inaccurate judgment and false alarms of correctable errors and uncorrectable errors caused by interference or environmental instability. For another example, an incomplete error correction algorithm may lead to misjudgment of the error position, thereby causing random errors to occur, and thus the data processing method according to at least one embodiment of the present disclosure can avoid inaccurate judgment and false alarms of correctable errors and uncorrectable errors caused by an incomplete error correction algorithm, thereby compensating for or improving the correctness and completeness of the error correction algorithm.

[0087] Some exemplary additional aspects of the data processing method according to at least one embodiment of the present disclosure are described below.

[0088] For example, according to the data processing method of at least one embodiment of the present disclosure, determining whether there is a baseline error position may include: counting the error positions of at least some of the correctable errors among multiple correctable errors; and in response to the existence of an error position with a count greater than or equal to a threshold number of times, determining the error position with a count greater than or equal to the threshold number of times as a baseline error position, or, in response to the absence of an error position with a count greater than or equal to the threshold number of times, determining that there is no baseline error position.

[0089] For example, the error position of each of the at least partially correctable errors may be the position of a particle among the 8 data particles and 2 ECC particles of the DDR5 corresponding to DDR5 Ch0. In one example, the error position of the first correctable error among the at least partially correctable errors may be the first data particle, the error position of the second correctable error among the at least partially correctable errors may be the first data particle, the error position of the third correctable error among the at least partially correctable errors may be the first data particle, and the error position of the fourth correctable error among the at least partially correctable errors may be the second data particle. In such an example, the result of counting the error positions of each of the at least partially correctable errors among the multiple correctable errors is that the number of errors of the first data particle is 3, the number of errors of the second data particle is 1, and the number of errors of the other data particles and the ECC particles is 0. Continuing with this example, assuming that the threshold number is 3, the first data particle can be used as the reference error position.

[0090] It can be understood that whether an error occurs, the error location, and various numerical values ​​in the above examples are only exemplary, and the embodiments of the present disclosure are not limited thereto.

[0091] In addition, it can be understood that the number of correctable errors and error positions corresponding to correctable errors may vary depending on the error correction capabilities of different error correction algorithms. Therefore, in the context of using one error position as a correctable error can be extended to using two or more error positions as correctable errors.

[0092] Thus, the data processing method according to at least one embodiment of the present disclosure can determine the reference error position by determining the relationship between the count of the error position and the threshold number. In addition, since the threshold number can be flexibly set (for example, via software), it can adapt to different application scenarios, for example, different thresholds can be adapted according to different application environments to improve the reliability and robustness of the system.

[0093] In addition, alternatively or additionally, the reference error position may be determined in other ways. For example, the error positions of at least some of the correctable errors in the plurality of correctable errors may be counted by the error positions of at least some of the correctable errors, and in response to the existence of error positions whose count accounts for a ratio of the total count of the error positions of at least some of the correctable errors that is greater than or equal to a threshold ratio, the error positions whose ratio is greater than or equal to the threshold ratio are determined as reference error positions, or, in response to the absence of error positions whose ratio is greater than or equal to the threshold ratio, it is determined that there is no reference error position (i.e., the reference error position is determined by the relationship between the ratio and the ratio threshold). For another example, a fixed error position obtained by experimenting with the corresponding memory and / or based on experience may be used as a reference error position (i.e., the reference error position is determined by experiment or experience).

[0094] For example, according to the data processing method of at least one embodiment of the present disclosure, counting the respective error positions of at least some of the correctable errors among multiple correctable errors may include: for the respective error positions, in response to at least some of the correctable errors among the multiple correctable errors appearing consecutively at the same error position, counting the number of times the multiple correctable errors appear consecutively at the same error position; and in response to at least some of the correctable errors among the multiple correctable errors not appearing consecutively at the same error position, clearing the count and recounting the number of times the multiple correctable errors appear consecutively at the same error position.

[0095] In the above embodiment, the continuous errors for each error position of the memory can be counted. For example, the continuous errors for each error position of the 8 data particles and 2 ECC particles included in DDR5 are counted. In one example, the error position of the first correctable error in at least some of the correctable errors can be the first data particle, in which case the count of the error position for the first data particle is 1, and the count of the error positions for the remaining particles is 0. Subsequently, the error position of the second correctable error in at least some of the correctable errors can be the second data particle, in which case the count of the error position for the first data particle is cleared (0), while the count of the error position for the second data particle is 1, and the count of the error positions for the remaining particles is 0. Subsequently, the error position of the third correctable error in at least some of the correctable errors can be the third data particle, in which case the count of the error position for the second data particle is cleared (0), the count of the error position for the third data particle is 1, and the count of the error positions for the remaining particles is 0. Subsequently, the error position of the fourth correctable error in at least some of the correctable errors can be the third data particle, in which case the count of the error position for the third data particle is 2, and the count of the error positions for the remaining particles is 0.

[0096] In this way, the data processing method according to at least one embodiment of the present disclosure can better eliminate random errors, because random errors are usually discontinuous with respect to a specific error position, thereby avoiding using random errors as reference error positions.

[0097] For example, according to the data processing method of at least one embodiment of the present disclosure, data can be organized into ECC words, and the error positions of multiple correctable errors and subsequent correctable errors can be determined by performing ECC checks on the ECC words passed into N error correction channels, where N is a positive integer.

[0098] The data retrieved from the memory may be organized into ECC words, which may include data information from data particles and ECC information from ECC particles. For example, see Figure 1 , the 16 data (shown as Beat0 to Beat16) read from the memory DDR5 can be combined in pairs to obtain 8 ECC words.

[0099] In some embodiments, the error correction channel may be or include an ECC module. Figure 4 In FIG. 4 , the error correction channel is shown as an ECC module. Of course, the embodiment is not limited thereto, and the error correction channel may also include other modules (eg, a cyclic redundancy check (CRC) module) or be replaced by other modules for performing error detection and correction.

[0100] Figure 4A schematic diagram showing an exemplary structure of a data processing method according to at least one embodiment of the present disclosure is shown. It can be understood that Figure 4 The foregoing is illustrative for the purpose of clearly describing one or more aspects of the data processing method according to at least one embodiment of the present disclosure, and the various aspects shown are not essential. For example, in some embodiments, one or more aspects may be omitted or modified.

[0101] See also Figure 4 , 8 ECC words can be sent to 8 ECC modules ECC 0 to ECC 7 respectively. In each ECC module, an ECC check can be performed on the ECC words sent thereto to determine whether there is a correctable error and the error location of the correctable error. In one example, combined with Figure 1 and Figure 4 , ECC 0 can perform ECC check on the ECC words corresponding to Beat0&1 passed into it, ECC 1 can perform ECC check on the ECC words corresponding to Beat2&3 passed into it, ECC 2 can perform ECC check on the ECC words corresponding to Beat4&5 passed into it, and so on, until ECC 7 can perform ECC check on the ECC words corresponding to Beat14&15 passed into it. In this way, the ECC check of the ECC words for a cache line can be completed. For the next cache line, the operation can be repeated, that is, the 8 ECC words of the next cache line are sent to the 8 ECC modules ECC 0 to ECC 7 respectively.

[0102] It can be understood that whether an error occurs, the error location, and various numerical values ​​in the above examples are only exemplary, and the embodiments of the present disclosure are not limited thereto.

[0103] For example, depending on the size of the symbol unit of different algorithms, more or fewer Beats can be organized into a single ECC word. In the above example, organizing two Beats into one ECC word is only an example of using an ECC algorithm with 8 bits as the minimum symbol unit size (such as the RS algorithm of x8). In this example, the size of each particle is x4, and the data of the two Beats corresponding to a single particle can be organized into an 8-bit symbol.

[0104] For another example, depending on the unit size of the ECC module performing the ECC check and the size of the cache line of the processor operating memory, the number of ECC modules can be changed. In the above example, 8 ECC modules are only an example that the size of the cache line of the processor operating memory is 512 bits and the unit size of the ECC module performing the ECC check is 64 bits (i.e., 8=512 bits / 64 bits).

[0105] In this way, according to at least one embodiment of the data processing method of the present disclosure, multiple ECC modules can perform parallel ECC checks on the ECC words transmitted thereto separately, thereby improving the efficiency of the ECC check operation.

[0106] Of course, the embodiment is not limited thereto. For example, multiple ECC words of a cache line may be sent to the same ECC module for ECC verification. For example, continuing the above example, the ECC words corresponding to Beat0&1 and the ECC words corresponding to Beat2&3 may be sent to one ECC module for ECC verification. In this way, the number of ECC modules to be set may be reduced.

[0107] For example, according to the data processing method of at least one embodiment of the present disclosure, the ECC check may adopt the RS algorithm with a minimum symbol unit of 8 bits.

[0108] In this way, the data processing method according to at least one embodiment of the present disclosure can be applied to the RS algorithm of x8, reduce the misjudgment rate of the RS algorithm of x8, and reduce the impact of the weak completeness of the x8 algorithm.

[0109] Of course, the embodiments of the present disclosure are not limited thereto. For example, the data processing method according to at least one embodiment of the present disclosure may be applicable to other ECC algorithms, such as other incomplete ECC algorithms.

[0110] For example, according to the data processing method of at least one embodiment of the present disclosure, counting the error positions of at least some of the correctable errors among multiple correctable errors may include: counting the error positions of multiple correctable errors determined by N error correction channels to obtain a global count; and determining the error position with a count greater than or equal to a threshold number of times as a reference error position may include: determining the error position with a global count greater than or equal to a threshold number of times as a reference error position.

[0111] For example, see Figure 4 , the error positions of the respective correctable errors determined by all 8 ECC modules ECC 0 to ECC 7 can be counted by a counter, and the counts obtained thereby are the error positions of the respective correctable errors determined by all 8 ECC modules, and are therefore referred to as global counts. In an example, ECC 0 to ECC 7 can determine that the number of times the first data particle in the memory DDR5 has errors is, for example, 5, 5, 5, 5, 6, 5, 5, respectively, and the number of times the second data particle has errors is, for example, 0, 0, 1, 0, 0, 0, 0, respectively, and that there are no errors at other positions. In this case, the global count of the first data particle is 5+5+5+5+5+6+5+5=41, the global count of the second data particle is 0+0+0+1+0+0+0+0=1, and the global count of other particles is 0.

[0112] Continuing with the example, if the threshold number is 40 (i.e. if Figure 4 =40), since the global count of the first data particle is 41, which is greater than 40, the counter can use the first data particle as the reference error position L. In addition, since the global count of the second data particle is 1, and the global counts of other particles are 0, which are all less than 40, the counter may not use the second data particle and other particles as reference error positions.

[0113] It can be understood that whether an error occurs, the error location, and various numerical values ​​in the above examples are only exemplary, and the embodiments of the present disclosure are not limited thereto.

[0114] In this way, the data processing method according to at least one embodiment of the present disclosure can determine the reference error position by considering the error positions of the correctable errors determined by all ECC modules, so that the determination of the reference error position is more accurate or reliable.

[0115] For example, according to the data processing method of at least one embodiment of the present disclosure, N≥2 and is an integer, counting the error positions of at least some of the correctable errors among multiple correctable errors may include: counting the error positions of the correctable errors determined by the first error correction channel among N error correction channels to obtain a first local count; and determining the error position with a count greater than or equal to a threshold number of times as a reference error position may include: determining the error position with a first local count greater than or equal to a threshold number of times as a reference error position.

[0116] For example, see Figure 4 , the error positions of the correctable errors determined by ECC 0 in the 8 ECC modules can be counted by a counter, and the count obtained is the error position of the correctable errors determined for one of all 8 ECC modules, and is therefore called a local count. In an example, ECC 0 can determine that the number of errors of the first data particle in the memory DDR5 is, for example, 6, the number of errors of the second data particle is, for example, 1, and no errors are made at other locations. In this case, the local count of the first data particle is 5, the local count of the second data particle is 1, and the local counts of the other particles are 0.

[0117] Continuing with this example, if the threshold number is 5, since the global count of the first data particle is 6, which is greater than 5, the counter can use the first data particle as the reference error position L. In addition, since the global count of the second data particle is 1, and the global counts of the other particles are 0, which are all less than 5, the counter may not use the second data particle and the other particles as the reference error positions.

[0118] It can be understood that whether an error occurs, the error location, and various numerical values ​​in the above examples are only exemplary, and the embodiments of the present disclosure are not limited thereto.

[0119] Thus, the data processing method according to at least one embodiment of the present disclosure can determine the reference error position by considering the error positions of the respective correctable errors determined by the local ECC module, and compared with the above-mentioned determination of the reference error position by global counting, the power consumption of counting can be reduced. In addition, considering that the fixed error position generally appears repeatedly at a specific position, the determination of the reference error position by local counting does not have much degradation in accuracy or reliability compared with the determination of the reference error position by global counting.

[0120] Of course, the embodiments of the present disclosure are not limited thereto. For example, local counts may be obtained for the error positions of the correctable errors determined for multiple of all eight ECC modules, and the error positions with local counts greater than or equal to the threshold number of times may be determined as reference error positions.

[0121] For example, the data processing method according to at least one embodiment of the present disclosure may further include: determining whether the error position of a subsequent correctable error is a local fixed error position, wherein the local fixed error position indicates a fixed error position of a correctable error within a channel determined within an error correction channel that determines the error position of the subsequent correctable error; in response to the error position of the subsequent correctable error being a local fixed error position, performing a comparison to determine whether the error position of the subsequent correctable error is consistent with a reference error position.

[0122] For the convenience of description, the above steps may be referred to as determination and comparison operations for the error correction channel.

[0123] For example, for the same cache line, each ECC word may have a sequence due to the different times at which the corresponding data is received. Figure 1 and Figure 4 , among Beat0 to Beat15, Beat0 may be received first, and Beat15 may be received last. Therefore, for the same cache line, the ECC word corresponding to Beat0&1 may first determine its error position in ECC 0, then the ECC word corresponding to Beat2&3 may determine its error position in ECC 1, and so on, until the ECC word corresponding to Beat14&15 may determine its error position in ECC 7. This may also be done for the next cache line.

[0124] Therefore, see Figure 4For the same cache line, after determining the reference error position L, it can be determined whether the error position L0 of the subsequent correctable error determined by ECC0 is the fixed error position of the correctable error determined by ECC 0, and after determining that the error position L0 is the fixed error position, the error position L0 is compared with the reference error position L to see whether they are consistent (i.e., determination and comparison operations for ECC 0). Subsequently, the operation can be repeated for the error positions of the subsequent correctable errors determined by other ECC modules to cross-check the error positions of the subsequent correctable errors with the reference error position L (i.e., determination and comparison operations for other ECC modules). The operation can also be repeated for the next cache line.

[0125] In addition, for the same cache line, if the reference error position L is determined by the local count of ECC 0, that is, L0 is the same as the reference error position L, then it is not necessary to compare whether L0 is consistent with the reference error position L, but whether the error position L1 of the subsequent correctable error determined by ECC1 is the fixed error position of the correctable error determined by ECC 1, and after determining that the error position L1 is the fixed error position, then compare whether the error position L1 is consistent with the reference error position L (that is, the determination and comparison operation for ECC 1), and so on. For the next cache line, the determination and comparison operation for ECC 0 can be performed again, as well as the subsequent determination and comparison operations for other ECC modules.

[0126] Thus, the data processing method according to at least one embodiment of the present disclosure can compare the subsequent error position with the reference error position only when the subsequent error position is a fixed error position determined by the corresponding error correction channel, thereby avoiding comparing the random error with the reference error position, thereby further avoiding inaccurate judgment and false alarm of correctable errors and uncorrectable errors, and reducing downtime and other problems caused by them.

[0127] For example, the data processing method according to at least one embodiment of the present disclosure may further include: after comparing whether the error position of the subsequent correctable error is consistent with the reference error position, whether the reference error position exists again. For example, after determining the reference error position L, the error positions of one or more subsequent correctable errors may be compared with the reference error position L, and then the reference error position may be determined again.

[0128] Considering that the reference error position L is generally fixed and unchanged, the data processing method according to at least one embodiment of the present disclosure can avoid the computational overhead caused by frequently determining the reference error position L.

[0129] For example, the data processing method according to at least one embodiment of the present disclosure may further include: in response to the error location of the subsequent correctable error not being a local fixed error location, not comparing whether the error location of the subsequent correctable error is consistent with the reference error location.

[0130] Thus, the data processing method according to at least one embodiment of the present disclosure can avoid comparing the subsequent error position with the reference error position when the subsequent error position is not a fixed error position determined by the corresponding error correction channel, thereby avoiding comparing the random error with the reference error position, thereby further avoiding inaccurate judgment and false alarm of correctable errors and uncorrectable errors, and reducing downtime and other problems caused by them.

[0131] For example, according to the data processing method of at least one embodiment of the present disclosure, determining whether the error position of a subsequent correctable error is a local fixed error position may include: counting the error positions of each correctable error in the channel to obtain a second local count; in response to the second local count being greater than or equal to a local threshold number of times, determining that the error position of the subsequent correctable error is a local fixed error position.

[0132] In an embodiment, determining the local fixed error position may be the same as or similar to the method of determining the reference error position by the first local count described above, which will not be described in detail here.

[0133] Thus, the data processing method according to at least one embodiment of the present disclosure can determine the local fixed error position by counting the error positions of the correctable errors in the channel and determining the relationship with the local threshold number. In addition, since the threshold number can be flexibly set (for example, via software), it can be adapted to different application scenarios to improve the reliability and robustness of the system.

[0134] In addition, alternatively or additionally, the local fixed error position may be determined by other means, for example, by the relationship between the ratio and the ratio threshold described above or by an experiment or experience.

[0135] In other aspects, because determining the local fixed error position can be the same or similar to the method of determining the reference error position by the first local count described above, the only difference is that the error position selected as the comparison reference is the reference error position, and the other error positions not selected as the comparison reference are the local fixed error positions. Therefore, the above-mentioned method of determining the reference error position and the local fixed error position by the local count can be performed for each error correction channel. For example, see Figure 4, the above-mentioned local counting can be performed on each of the eight ECC modules ECC 0 to ECC 8, and the error position whose local count in ECC 0 is greater than or equal to the local threshold number is determined as the reference error position, and the error positions whose local counts in the remaining ECCs are greater than or equal to the local threshold number are determined as the local fixed error positions. In this way, the data processing method according to at least one embodiment of the present disclosure can unify the operations of determining the reference error position and determining the local fixed error position, thereby reducing the complexity of system settings.

[0136] For example, according to the data processing method of at least one embodiment of the present disclosure, the threshold number may be equal to the local threshold number.

[0137] As described above, since determining the local fixed error position may be the same or similar to the method of determining the reference error position by the first local count described above, the threshold number of times may be set equal to or the same as the local threshold number of times.

[0138] In this way, the data processing method according to at least one embodiment of the present disclosure can reduce the number of settings of the threshold number and reduce the complexity of system settings.

[0139] For example, according to the data processing method of at least one embodiment of the present disclosure, N error correction channels can be divided into M subsets, M≥2 and is an integer, and comparing whether the error positions of subsequent correctable errors are consistent with the benchmark error positions may include: for each subset of the M subsets, separately comparing whether the error positions of subsequent correctable errors in each subset are consistent with the benchmark error positions.

[0140] For example, see Figure 4 , the 8 ECC modules ECC 0 to ECC 8 error correction channels are divided into 2 subsets, namely ECC 0 to ECC 3 as the first subset, and ECC 4 to ECC 7 as the second subset. Figure 4 In the example, after determining the reference error position L, the counter can transmit the reference error position L to the comparison unit. Figure 4 In the embodiment, the comparison unit is shown to include a first cross comparison module and a second cross comparison module. In the first cross comparison module, the error positions of subsequent correctable errors in the first subset (e.g., error positions L0 to L3 of correctable errors determined by ECC 0 to ECC 3) are compared to see if they are consistent with the reference error position L. In the second cross comparison module, the error positions of subsequent correctable errors in the second subset (e.g., error positions L4 to L7 of correctable errors determined by ECC4 to ECC 7) are compared to see if they are consistent with the reference error position L.

[0141] It will be appreciated that the number of modules cross-checked here may vary depending on the size of the unit operated by the memory controller (256 bits) and the size of the cache line (512 bits) of the processor operating the memory. Figure 4 In the example, the number of cross-matching modules is only an example in which the size of a cache line of a processor operating a memory is 512 bits and the size of a unit operated by a memory controller is 256 bits (ie, 2=512 bits / 256 bits).

[0142] In this way, the data processing method according to at least one embodiment of the present disclosure can perform cross-matching individually or independently for each subset in multiple subsets, so that the cross-matching can be executed in parallel, thereby improving the execution efficiency of the cross-matching.

[0143] Of course, the embodiments of the present disclosure are not limited thereto. For example, cross comparison may also be performed serially or sequentially for each subset in the plurality of subsets.

[0144] For example, the data processing method according to at least one embodiment of the present disclosure may also include: in response to the error position of a subsequent correctable error in each of the M subsets being consistent with a baseline error position, indicating the occurrence of an uncorrectable error; or in response to the error position of a subsequent correctable error in any of the M subsets being inconsistent with the baseline error position, indicating the occurrence of an uncorrectable error.

[0145] For example, see Figure 4 , when the first cross comparison module determines that the error positions L0 to L3 of the correctable errors of ECC 0 to ECC 3 are completely consistent with the reference error position L, a correctable error CE is output; when the first cross comparison module determines that any of the error positions L0 to L3 of the correctable errors of ECC0 to ECC 3 are inconsistent with the reference error position L, an uncorrectable error UE is output. When the second cross comparison module determines that the error positions L4 to L7 of the correctable errors of ECC 4 to ECC 7 are completely consistent with the reference error position L, a correctable error CE is output; when the first cross comparison module determines that any of the error positions L4 to L7 of the correctable errors of ECC 4 to ECC 7 are inconsistent with the reference error position L, an uncorrectable error UE is output.

[0146] The correctable error CE output by the first cross-comparison module and the correctable error CE output by the second cross-comparison module can be ANDed (shown as &), that is, the error position of the corresponding subsequent correctable error is determined in the first cross-comparison module and the second cross-comparison module to be completely consistent with the reference error position, and the correctable error CE can be output, indicating that the system has a correctable error.

[0147] The uncorrectable error UE output by the first cross-comparison module and the uncorrectable error UE output by the second cross-comparison module can be ORed (shown as OR), that is, in the first cross-comparison module and the second cross-comparison module, as long as it is determined that the error position of any subsequent correctable error is inconsistent with the reference error position, the uncorrectable error UE can be output, indicating that the system has an uncorrectable error.

[0148] In this way, the data processing method according to at least one embodiment of the present disclosure can comprehensively consider the results of the cross-comparison of each subset to determine whether the system has correctable errors or uncorrectable errors.

[0149] For example, in the case where the cross comparison is performed in parallel, once an uncorrectable error occurs in a cross comparison module, an uncorrectable error UE will be output, thereby indicating that the system has an uncorrectable error. In contrast, in the case where the cross comparison is performed in series, the cross comparison needs to be performed until a cross comparison module outputs an uncorrectable error. Therefore, the data processing method according to at least one embodiment of the present disclosure can indicate that the system has an uncorrectable error at a faster speed than the cross comparison is performed in series.

[0150] For example, the data processing method according to at least one embodiment of the present disclosure may further include: in response to the absence of a reference error position, not comparing whether the error position of the subsequent correctable error is consistent with the reference error position.

[0151] In this way, the data processing method according to at least one embodiment of the present disclosure can avoid the situation where random errors are used as benchmark error positions for comparison, resulting in false alarms of correctable errors and uncorrectable errors, thereby avoiding inaccurate judgment and false alarms of correctable errors and uncorrectable errors, and reducing downtime and other problems caused thereby.

[0152] Corresponding to the data processing method 300 according to at least one embodiment of the present disclosure, at least one embodiment of the present disclosure further provides a data processing device.

[0153] Figure 5 FIG. 5 is a schematic diagram of a data processing device 500 according to at least one embodiment of the present disclosure.

[0154] See also Figure 5 The data processing device 500 includes a reference error position determination unit 510 , a comparison unit 520 , and a reporting unit 530 .

[0155] The reference error position determination unit 510 is configured to: determine whether there is a reference error position in the error correction process for data, wherein the reference error position indicates a fixed error position of a plurality of correctable errors.

[0156] The comparison unit 520 is configured to: in response to the presence of a reference error position, compare whether the error position of the subsequent correctable error is consistent with the reference error position.

[0157] The reporting unit 530 is configured to indicate the occurrence of a correctable error in response to the error location of a subsequent correctable error being consistent with the reference error location, or to indicate the occurrence of an uncorrectable error in response to the error location of a subsequent correctable error being inconsistent with the reference error location.

[0158] As described above, according to at least one embodiment of the present disclosure, the data processing method can use the fixed position of the correctable error as the reference error position, and then compare whether the error position of the subsequent correctable error is consistent with the reference error position, so as to determine whether a correctable error and an uncorrectable error have occurred. In this way, it is possible to avoid the situation where the correctable error and the uncorrectable error are misreported by using the random error as the reference error position for comparison, thereby avoiding the inaccurate judgment and misreporting of the correctable error and the uncorrectable error, and reducing the downtime and other problems caused by it.

[0159] Some exemplary additional aspects of the data processing device according to at least one embodiment of the present disclosure are described below.

[0160] For example, in a data processing device according to at least one embodiment of the present disclosure, the reference error position determination unit may include a counter, which may be configured to: count the error positions of at least some of the correctable errors among a plurality of correctable errors; and in response to the existence of an error position with a count greater than or equal to a threshold number of times, determine the error position with a count greater than or equal to the threshold number of times as a reference error position; or, in response to the absence of an error position with a count greater than or equal to the threshold number of times, determine that there is no reference error position.

[0161] For example, according to a data processing device of at least one embodiment of the present disclosure, data can be organized into ECC words, and the data processing device can also include: N error correction channels, which are configured to perform ECC checks on the ECC words passed therein respectively to determine the error positions of multiple correctable errors and subsequent correctable errors, wherein N≥2 and is an integer, and the counter can also include: a first local counter, which is configured to: count the error positions of each correctable error determined by the first error correction channel in the N error correction channels to obtain a first local count; and determine the error position whose first local count is greater than or equal to a threshold number of times as a reference error position, and the counter can also include: a subsequent local counter, which is configured to: determine whether the error position of the subsequent correctable error is a local fixed error position, wherein the local fixed error position can indicate the fixed error position of the correctable error in the channel determined in the error correction channel that determines the error position of the subsequent correctable error; in response to the error position of the subsequent correctable error being a local fixed error position, perform a comparison to see whether the error position of the subsequent correctable error is consistent with the reference error position.

[0162] For example, according to the data processing device of at least one embodiment of the present disclosure, the subsequent local counter can also be configured to: count the error positions of each correctable error in the channel to obtain a second local count; in response to the second local count being greater than or equal to the local threshold number of times, determine that the error position of the subsequent correctable error is a local fixed error position.

[0163] Exemplarily, the counter of the data processing device 500 according to at least one embodiment of the present disclosure may be Figure 4 The error correction channel can be Figure 4 In the ECC modules ECC 0 to ECC 7, the comparison unit may include reference Figure 4 The first cross comparison module and the second cross comparison module described are described. Of course, the embodiments of the present disclosure are not limited thereto.

[0164] The above-mentioned additional aspects or other additional aspects of the data processing device 500 according to at least one embodiment of the present disclosure may correspond to the additional aspects of the data processing method 300 according to at least one embodiment of the present disclosure. Therefore, the technical effects of the additional aspects of the data processing method 300 according to at least one embodiment of the present disclosure can also be mapped to the additional aspects or other additional aspects of the data processing device 500 according to at least one embodiment of the present disclosure, and will not be repeated here.

[0165] In some embodiments, the data processing device 500 according to at least one embodiment of the present disclosure may be a memory controller, include a memory controller, or be included in a memory controller.

[0166] Figure 6A schematic diagram of a memory system 600 according to at least one embodiment of the present disclosure is shown.

[0167] See also Figure 6 , the memory system 600 includes Figure 5 The data processing device 500 and the memory 610 are described. The memory 610 is configured to store data, that is, data used for the error correction process.

[0168] At least one embodiment of the present disclosure further provides an electronic device. Figure 7 A schematic diagram of an electronic device 700 according to at least one embodiment of the present disclosure is shown.

[0169] like Figure 7 As shown, the electronic device 700 includes at least one processing unit 720 and a memory 710. The memory 710 stores computer-readable instructions and is in communication with the processing unit 720. The processing unit 720 executes the computer-readable instructions stored in the memory 710 to implement the data processing method and additional aspects thereof according to at least one embodiment of the present disclosure.

[0170] For example, the memory 710 and the processing unit 720 may communicate with each other directly or indirectly. Figure 7 As shown, the electronic device 700 may further include a system bus 730, and the memory 710 and the processing unit 720 may communicate with each other through the system bus 730. For example, the processing unit 720 may access the memory 710 through the system bus 730. For example, in other examples, the memory 710 and the processing unit 720 and other components may communicate through a network on chip (NOC) connection.

[0171] For example, the processing unit 720 can control other components in the electronic device 700 to perform desired functions. The processing unit 720 can be a device with data processing capabilities and / or program execution capabilities, such as a central processing unit (CPU), a tensor processing unit (TPU), a network processor (NP), or a graphics processing unit (GPU), and can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.

[0172] For example, the memory 710 may include any combination of one or more computer program products, and the computer program product may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory (cache), etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disk read-only memory (CD-ROM), USB memory, flash memory, etc.

[0173] For example, one or more computer-readable instructions may be stored on the memory 710, and the processing unit 720 may execute the computer-readable instructions to implement various functions. Various applications and various data may also be stored in the computer-readable storage medium, such as instruction processing codes and various data used and / or generated by the application.

[0174] For example, when some computer instructions stored in the memory 710 are executed by the processing unit 720 , one or more steps in the data processing method described above can be performed.

[0175] For example, Figure 7 As shown, the electronic device 700 may also include an input interface 740 that allows an external device to communicate with the electronic device 700. For example, the input interface 740 may be used to receive instructions from an external computer device, from a user, etc. The electronic device 700 may also include an output interface 750 that interconnects the electronic device 700 and one or more external devices. For example, the electronic device 700 may communicate with the external device through the output interface 750, etc.

[0176] It should be noted that the electronic device 700 according to at least one embodiment of the present disclosure is illustrative rather than restrictive, and according to actual application requirements, the electronic device 700 may also include other conventional components or structures. For example, to realize the necessary functions of the electronic device, those skilled in the art may set other conventional components or structures according to the specific application scenario, and the embodiments of the present disclosure are not limited to this.

[0177] At least one embodiment of the present disclosure also provides a computer-readable storage medium. Figure 8 A schematic diagram of a computer-readable storage medium 800 is shown, in accordance with at least one embodiment of the present disclosure.

[0178] For example, Figure 8 As shown, the computer-readable storage medium 800 stores computer-readable instructions 810. When the computer-readable instructions 810 are executed by a computer (including a processor), the data processing method and additional aspects thereof according to at least one embodiment of the present disclosure can be implemented.

[0179] For example, one or more computer-readable instructions may be stored on the computer-readable storage medium 800. Some of the computer-readable instructions stored on the computer-readable storage medium 800 may be, for example, instructions for implementing one or more steps in the above-mentioned data processing method.

[0180] For example, the computer-readable storage medium may include a storage component of a tablet computer, a hard disk of a personal computer, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a compact disk read-only memory (CD-ROM), a flash memory, or any combination of the above computer-readable storage media, or other applicable storage media. For example, the computer-readable storage medium 800 may include the memory 710 in the above electronic device 700.

[0181] At least some embodiments of the present disclosure also provide an electronic device. Fig. 9 A schematic diagram of another electronic device 900 according to at least one embodiment of the present disclosure is shown.

[0182] The electronic device according to at least one embodiment of the present disclosure can be implemented as but not limited to mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc.

[0183] Fig. 9 The electronic device 900 shown is merely an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0184] For example, Fig. 9 As shown, in some examples, the electronic device 900 includes a processor 901, which may include a processor implementing any of the above embodiments (e.g., an SMT processor), which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 902 or a program loaded from a storage device 908 to a random access memory (RAM) 903. Various programs and data required for the operation of the computer system are also stored in the RAM 903. The processor 901, the ROM 902, and the RAM 903 are connected to each other via a bus 904. An input / output (I / O) interface 905 is also connected to the bus 904.

[0185] For example, the following components may be connected to the I / O interface 905: an input device 906 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 907 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 908 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 909 which may also include, for example, a network interface card such as a LAN card, a modem, etc. The communication device 909 may allow the electronic device 900 to communicate with other devices wirelessly or by wire to exchange data, performing communication processing via a network such as the Internet. A drive 910 is also connected to the I / O interface 905 as needed. Removable media 911, such as magnetic disks, optical disks, magneto-optical disks, semiconductor memories, etc., are installed on the drive 910 as needed, so that the computer program read therefrom is installed into the storage device 908 as needed. Although Fig. 9 The electronic device 900 is shown to include various devices, but it should be understood that it is not required to implement or include all of the devices shown. More or fewer devices may be implemented or included instead.

[0186] For example, the electronic device 900 may further include a peripheral interface (not shown in the figure), etc. The peripheral interface may be various types of interfaces, such as a USB interface, a lightning interface, etc. The communication device 909 may communicate with a network and other devices through wireless communication, such as the Internet, an intranet and / or a wireless network such as a cellular phone network, a wireless local area network (LAN) and / or a metropolitan area network (MAN). Wireless communication may use any of a variety of communication standards, protocols, and techniques, including, but not limited to, Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging, and / or Short Message Service (SMS), or any other suitable communication protocol.

[0187] In addition to the above exemplary descriptions, the following points need to be explained for this disclosure:

[0188] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure. Other structures may refer to the general design.

[0189] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to obtain new embodiments.

[0190] The above description is merely an exemplary embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure. The protection scope of the present disclosure is determined by the appended claims.

Claims

1. A data processing method, comprising: In a data error correction process, determining whether a reference error position exists, wherein the reference error position indicates a fixed error position of a plurality of correctable errors; In response to the presence of the reference error position, comparing whether the error position of a subsequent correctable error is consistent with the reference error position; and In response to the error location of the subsequent correctable error being consistent with the reference error location, an occurrence of a correctable error is indicated, or in response to the error location of the subsequent correctable error being inconsistent with the reference error location, an occurrence of an uncorrectable error is indicated.

2. The data processing method according to claim 1, wherein: The determining whether there is a reference error position comprises: counting respective error locations of at least some of the plurality of correctable errors; and In response to the existence of an error position with the count greater than or equal to a threshold number of times, the error position with the count greater than or equal to the threshold number of times is determined as a reference error position, or, in response to the absence of an error position with the count greater than or equal to the threshold number of times, it is determined that the reference error position does not exist.

3. The data processing method according to claim 2, wherein: The step of counting respective error locations of at least some of the correctable errors among the plurality of correctable errors comprises: For their respective error locations, In response to at least some of the correctable errors in the plurality of correctable errors continuously appearing at the same error location, counting the number of times the plurality of correctable errors continuously appear at the same error location; and In response to at least some of the correctable errors in the plurality of correctable errors not continuously occurring at the same error location, the count is cleared and the number of times the plurality of correctable errors continuously occur at the same error location is recounted.

4. The data processing method according to claim 2, wherein: The data is organized into ECC words, and the error positions of the multiple correctable errors and the subsequent correctable errors are determined by performing ECC checks on the ECC words input into N error correction channels, respectively, where N is a positive integer.

5. The data processing method according to claim 4, wherein: The ECC check adopts the RS algorithm with a minimum symbol unit of 8 bits.

6. The data processing method according to claim 4, wherein: The step of counting respective error locations of at least some of the correctable errors among the plurality of correctable errors comprises: Counting the error positions of each of the plurality of correctable errors determined by the N error correction channels to obtain a global count; and The step of determining the error position whose count is greater than or equal to a threshold number of times as a reference error position comprises: The error position where the global count is greater than or equal to the threshold number of times is determined as a reference error position.

7. The data processing method according to claim 4, wherein: N ≥ 2 and is an integer, The step of counting respective error locations of at least some of the correctable errors among the plurality of correctable errors comprises: Counting the error positions of the correctable errors determined by the first error correction channel among the N error correction channels to obtain a first local count; and The step of determining the error position whose count is greater than or equal to a threshold number of times as a reference error position comprises: An error position where the first local count is greater than or equal to the threshold number of times is determined as a reference error position.

8. The data processing method according to claim 6 or 7, further comprising: determining whether the error position of the subsequent correctable error is a local fixed error position, wherein the local fixed error position indicates a fixed error position of an intra-channel correctable error determined within an error correction channel for determining the error position of the subsequent correctable error; In response to the error position of the subsequent correctable error being the local fixed error position, the comparing of whether the error position of the subsequent correctable error is consistent with the reference error position is performed.

9. The data processing method according to claim 8, further comprising: In response to the error position of the subsequent correctable error not being the local fixed error position, the comparing whether the error position of the subsequent correctable error is consistent with the reference error position is not performed.

10. The data processing method according to claim 8, wherein: The determining whether the error position of the subsequent correctable error is a local fixed error position includes: Counting the error positions of the respective correctable errors in the channel to obtain a second local count; In response to the second local count being greater than or equal to a local threshold number of times, determining the error location of the subsequent correctable error as the local fixed error location.

11. The data processing method according to claim 10, wherein: The threshold number is equal to the local threshold number.

12. The data processing method according to claim 8, wherein: The N error correction channels are divided into M subsets, where M≥2 and is an integer. The comparing whether the error position of the subsequent correctable error is consistent with the reference error position includes: For each of the M subsets, the error position of the subsequent correctable error in each subset is individually compared with the reference error position to see whether they are consistent.

13. The data processing method according to claim 12, further comprising: In response to an error location of the subsequent correctable error in each of the M subsets being consistent with the reference error location, indicating an occurrence of an uncorrectable error; or In response to the error location of the subsequent correctable error in any of the M subsets being inconsistent with the reference error location, an occurrence of an uncorrectable error is indicated.

14. The data processing method according to claim 1, further comprising: In response to the absence of the reference error position, the comparing whether the error position of the subsequent correctable error is consistent with the reference error position is not performed.

15. A data processing device, comprising: A reference error position determination unit is configured to: determine whether a reference error position exists during an error correction process of data, wherein the reference error position indicates a fixed error position of a plurality of correctable errors; A comparing unit configured to: in response to the existence of the reference error position, compare whether an error position of a subsequent correctable error is consistent with the reference error position; and The reporting unit is configured to: In response to the error location of the subsequent correctable error being consistent with the reference error location, an occurrence of a correctable error is indicated, or in response to the error location of the subsequent correctable error being inconsistent with the reference error location, an occurrence of an uncorrectable error is indicated.

16. The data processing apparatus according to claim 15, wherein: The reference error position determination unit comprises a counter, which is configured to: counting respective error locations of at least some of the plurality of correctable errors; as well as In response to the existence of an error position with the count greater than or equal to a threshold number of times, the error position with the count greater than or equal to the threshold number of times is determined as a reference error position, or, in response to the absence of an error position with the count greater than or equal to the threshold number of times, it is determined that the reference error position does not exist.

17. The data processing apparatus according to claim 16, wherein: The data is organized into ECC words, and the data processing device further comprises: N error correction channels are configured to perform ECC checks on the ECC words passed therein to determine error locations of the multiple correctable errors and the subsequent correctable errors, wherein N ≥ 2 and is an integer, The counter further includes: a first local counter configured to: Counting the error positions of the correctable errors determined by the first error correction channel among the N error correction channels to obtain a first local count; and determining the error position where the first local count is greater than or equal to the threshold number of times as a reference error position, and The counter further includes: a subsequent local counter configured to: determining whether the error position of the subsequent correctable error is a local fixed error position, wherein the local fixed error position indicates a fixed error position of an intra-channel correctable error determined within an error correction channel for determining the error position of the subsequent correctable error; In response to the error position of the subsequent correctable error being the local fixed error position, the comparing of whether the error position of the subsequent correctable error is consistent with the reference error position is performed.

18. The data processing apparatus according to claim 17, wherein: The subsequent local counter is further configured as: Counting the error positions of the respective correctable errors in the channel to obtain a second local count; In response to the second local count being greater than or equal to a local threshold number of times, determining the error location of the subsequent correctable error as the local fixed error location.

19. A memory system comprising: The data processing device according to any one of claims 15 to 18; as well as A memory is configured to store the data.

20. An electronic device comprising: at least one processor; at least one memory having instructions stored therein, When the instruction is executed by the processor, the processor executes the data processing method as claimed in any one of claims 1 to 14.

21. A computer-readable storage medium having computer-readable instructions stored thereon, in, When the computer-readable instructions are executed by a processor, the processor is caused to perform the data processing method according to any one of claims 1 to 14.

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