Large-scale chip code coverage rate acquisition method, electronic equipment and medium

Abstract

The invention relates to the technical field of chips, in particular to a large-scale chip code coverage rate obtaining method, electronic equipment and a medium, and the method comprises the following steps: S1, constructing different test clusters; s2, setting verification configuration information, test parameters and a to-be-verified interface set for the Giq; s3, generating a corresponding file list based on each Aiq in parallel, and compiling to generate a corresponding executable file Fiq; s4, transmitting the Biq to a test case in the Giq in parallel, executing a corresponding verification operation based on the Fiq, and obtaining a set Eiq of the interfaces to be verified which are overturned by the Giq; s5, after the Gq is completely executed, obtaining a union set GEiq of all Eiq corresponding to the Gq; and S6, after all Gq are executed, obtaining a union set GE of all GEiq, and determining the code coverage rate of the large-scale chip based on GE and GD. According to the method, the large-scale chip code coverage rate can be accurately and quickly obtained.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a large-scale chip code coverage acquisition method, electronic equipment and medium. Background Art

[0002] As the requirements for chip computing power continue to increase, the scale of chips is also increasing. As the scale of chips continues to increase, extremely high requirements are placed on the chip verification platform. In the prior art, the full-chip full-area verification method is often used to verify large-scale chips. However, the full-chip full-area verification method has a slow simulation time, consumes a lot of time, has poor operating stability, consumes a lot of resources, and is easily affected by uncertain factors. In view of the shortcomings of full-chip full-area verification, a modular verification method of module verification is further proposed in the prior art. Different verification platforms are built for different modules, the verification cost is high, and cross-module verification cannot be achieved. In addition, the above two methods are very difficult to collect large-scale chip code coverage, and it is impossible to accurately and quickly obtain large-scale chip code coverage. It can be seen from this that how to accurately and quickly obtain large-scale chip code coverage has become a technical problem that needs to be solved urgently. Summary of the invention

[0003] The object of the present invention is to provide a large-scale chip code coverage acquisition method, electronic equipment and medium, which can accurately and quickly acquire large-scale chip code coverage.

[0004] According to a first aspect of the present invention, a method for acquiring code coverage of a large-scale chip is provided, comprising:

[0005] Step S1: Build different test clusters {G1, G2, ..., G q ,...,G Q}, G q is the gth test cluster, the value of q ranges from 1 to Q, Q is the total number of test clusters, G q ={G1 q ,G2 q ,....,G i q ,...,G f(q) q},G i q G q The i-th test case group, i ranges from 1 to f(q), f(q) is G q The corresponding number of test case groups, different G i q Corresponding to different verification configuration information;

[0006] Step S2: for each G iq Set the corresponding verification configuration information A i q , corresponding test parameters B i q And the corresponding interface set D to be verified i q , the same G q Medium G i q The corresponding A i q All are different, different G q Medium G i q The corresponding A i q Probably the same, all D i q The union of is the set GD of all interfaces to be verified in large-scale chips;

[0007] Step S3: parallelly based on each G i q The corresponding A i q Generate G i q The corresponding file list is compiled and generated into the corresponding executable file F i q , each F i q Located in a separate file directory;

[0008] Step S4: parallelize B i q Transmit to the corresponding G i q The test cases in G i q The test cases in F are based on the corresponding i q Perform the corresponding verification operation to obtain G i q The corresponding flipped interface set E to be verified i q ;

[0009] Step S5: When G q The corresponding G i q After all executions are completed, obtain G q All corresponding E i q The union of GE i q ;

[0010] Step S6: When all Gq After all executions are completed, get all GE i q The union of GE and GD is used to determine the large-scale chip code coverage.

[0011] According to a second aspect of the present invention, there is provided an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to execute the method described in the first aspect of the present invention.

[0012] According to a third aspect of the present invention, there is provided a computer-readable storage medium storing computer-executable instructions, wherein the computer instructions are used to execute the method described in the first aspect of the present invention.

[0013] Compared with the prior art, the present invention has obvious advantages and beneficial effects. By means of the above technical solution, the large-scale chip code coverage acquisition method, electronic device and medium provided by the present invention can achieve considerable technical advancement and practicality, and has wide industrial utilization value, and has at least the following beneficial effects:

[0014] The method described in the present invention constructs different test clusters and sets corresponding verification configuration information for the test case groups in each test cluster, obtains the corresponding set of flipped interfaces to be verified based on the verification results of each test case group, and then obtains the corresponding set of flipped interfaces to be verified based on the verification results of a test cluster, and finally obtains the corresponding set of flipped interfaces to be verified based on the verification results of all clusters, thereby accurately and quickly obtaining large-scale chip code coverage. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0016] Figure 1 A flow chart of a method for acquiring large-scale chip code coverage provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0017] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0018] The embodiment of the present invention provides a method for obtaining code coverage of a large-scale chip. Figure 1 As shown, including:

[0019] Step S1: Build different test clusters {G1, G2, ..., G q ,...,G Q}, G q is the gth test cluster, the value of q ranges from 1 to Q, Q is the total number of test clusters, G q ={G1 q ,G2 q ,....,G i q ,...,G f(q) q},G i q G q The i-th test case group, i ranges from 1 to f(q), f(q) is G q The corresponding number of test case groups, different G i q Corresponding to different verification configuration information.

[0020] It should be noted that when q is different, the value of f(q) can also be different, that is, the number of test case groups corresponding to different test clusters may be different, and the number of test cases in each test case group may also be different. Test clusters are specifically divided based on chip functional attributes. Each test cluster corresponds to a chip functional attribute, and the chip functional attributes include power consumption, chip interconnection, virtual implementation, chip reset, etc. Different G i q Different verification configuration information corresponds to different verification targets. Each test cluster is used to execute a test regression.

[0021] Step S2: for each G i q Set the corresponding verification configuration information A i q , corresponding test parameters B i q And the corresponding interface set D to be verified i q , the same Gq Medium G i q The corresponding A i q All are different, different G q Medium G i q The corresponding A i q Probably the same, all D i q The union of is the set GD of all interfaces to be verified in large-scale chips.

[0022] It should be noted that the same G q Medium G i q The corresponding A i q Different means that the verification configuration information corresponding to the test case groups in the same test cluster is different, that is, the same G q Medium G i q Running on different verification configuration information, the corresponding verification targets are different. During the verification process, the interface to be verified flips, indicating that the interface to be verified has passed the verification. All interfaces to be verified on the large-scale chip are flipped, indicating that the code coverage of the large-scale chip has reached 100%. In order to ensure that all interfaces to be verified are involved in the verification, all D i q The union of is the set GD of all interfaces to be verified in large-scale chips.

[0023] Step S3: parallelly based on each G i q The corresponding A i q Generate G i q The corresponding file list is compiled and generated into the corresponding executable file F i q , each F i q Located in a separate file directory.

[0024] It should be noted that each verification configuration information contains the module type corresponding to each component module in the large-scale chip verification system. Different file lists are generated based on different verification configuration information. The file lists corresponding to each verification configuration information are compiled in parallel to produce different compilation environments. The file lists corresponding to each verification configuration information are isolated in different file directories and run in parallel, thereby running the verification of different verification targets in parallel.

[0025] Step S4: parallelize B i q Transmit to the corresponding Gi q The test cases in G i q The test cases in F are based on the corresponding i q Perform the corresponding verification operation to obtain G i q The corresponding flipped interface set E to be verified i q .

[0026] It should be noted that due to F i q Located in a separate file directory, so different from G i q The test cases in can be run in parallel. During the verification process, the interface that has passed the verification will be flipped to the interface to be verified.

[0027] Step S5: When G q The corresponding G i q After all executions are completed, obtain G q All corresponding E i q The union of GE i q .

[0028] It should be noted that a test cluster G q Corresponding to a test regression, after each test regression is completed, all flipped interfaces to be verified corresponding to the test cluster are merged.

[0029] Step S6: When all G q After all executions are completed, get all GE i q The union of GE and GD is used to determine the large-scale chip code coverage.

[0030] It should be noted that when all G q After all executions are completed, all flipped interfaces to be verified corresponding to all test clusters are merged, and then the code coverage of the large-scale chip can be determined by combining the number of interfaces in the set of all interfaces to be verified of the large-scale chip.

[0031] As an embodiment, in step S1, different test clusters {G1, G2, ..., G q ,...,G Q}, each G q Corresponding to a chip functional attribute, the chip functional attribute includes power consumption, chip interconnection, virtual implementation, and chip reset.

[0032] As an embodiment, each verification configuration information defines the model type of each component module in the large-scale chip verification system, and the large-scale chip verification system includes multiple engine modules, data path buses, configuration path buses, storage modules and PCIE modules. Each engine module is used to implement a chip function, such as image processing function, encryption and decryption function, computing function, etc. The PCIE module is a module that complies with the high-speed serial communication interconnection standard protocol (Peripheral Component Interconnect Express). Each engine module is used to implement a chip function, each engine module is connected to the data path bus and the configuration path bus respectively, the storage module is connected to the data path bus and the configuration path bus respectively, and the PCIE module is connected to the data path bus and the configuration path bus respectively; the engine module, the storage module and the PCIE module are all configurable modules, and the configurable module is set to a hardware module or a behavior-level functional model (Behavior Function Model) by configuring the module type. The data path bus and the configuration path bus are always set to hardware modules, which are non-configurable modules. The hardware module includes the complete internal logic and interface of the module, and the behavior-level functional model includes the module function logic and interface. The function logic is a logic in the complete internal logic, and the interface functions of the hardware module and the behavior-level functional model are consistent. The data path subsystem of a large-scale chip is formed from the engine module to the data path bus, and then to the storage module. The PCIE module can communicate with the CPU (Central Processing Unit) outside the large-scale chip through the PCIE slot, and the configuration path subsystem of the large-scale chip is formed from the PCIE module to the configuration path bus, and then to the engine module. The verification target is a subsystem or system composed of one module or multiple modules, that is, based on the system, verification of any component module can be achieved, such as any engine module, storage module, PCIE module. It can also be a subsystem composed of an engine module, a storage module, or an engine module and a storage module, or it can be the entire system composed of all component modules.

[0033] As an embodiment, if the verification target is one of the target engine modules or the interaction between multiple target engine modules, the verification configuration information sets the target engine module as a hardware module, sets the non-target engine module as well as the storage module and the PCIE module as behavioral-level functional models, and inputs corresponding test stimuli to the system through the target engine to verify the verification target.

[0034] As an embodiment, if the verification target is a storage module, the verification configuration information sets all engine modules and PCIE modules as behavioral-level functional models, sets the storage module as a hardware module, and inputs an external test stimulus to the storage module through the data path bus to verify the storage module.

[0035] As an embodiment, if the verification target is a PCIE module, the verification configuration information sets all engine modules and storage modules as behavioral-level functional models, sets the PCIE module as a hardware module, and the PCIE module receives test stimuli from an external CPU to verify the PCIE module.

[0036] As an embodiment, if the verification target is a data path subsystem, the verification configuration information selects at least one target engine module, sets the target engine module and the storage module as hardware modules, sets the non-target engine module and the PCIE module as behavioral-level functional models, and the target engine module transmits a test stimulus to a data path bus, and performs corresponding read or write operations in the storage module based on the transmitted test stimulus through the data path bus to verify the data path.

[0037] As an embodiment, if the verification target is a configuration path subsystem, the verification configuration information selects at least one target engine module, sets the target engine module and the PCIE module as hardware modules, sets the non-target engine module and the storage module as behavioral-level functional models, and an external CPU inputs a test stimulus to the PCIE module. The PCIE module executes corresponding configuration operations in the target engine module through the configuration path bus to verify the configuration path.

[0038] As an embodiment, the data path bus is pre-set with a corresponding hardware file list, the configuration path bus is pre-set with a corresponding hardware file list, and each configurable module is pre-set with a first file list and a second file list, the first file list is a file list corresponding to the hardware module of the configurable module, and the second file list is a file list corresponding to the behavioral level functional model of the configurable module; it should be noted that the size of the first file list of the same configurable module is larger than the size of the second file list. The step S3 includes:

[0039] Step S31, parallel analysis of each G i q The corresponding A i q , determine each G i q The module type identifier corresponding to each configurable module.

[0040] Step S32: If the module type identifier corresponding to the configurable module is the first identifier, then add the first file list corresponding to the configurable module to G i q In the corresponding file list, if the module type identifier corresponding to the configurable module is the second identifier, the second file list corresponding to the configurable module is added to G i q The corresponding file list.

[0041] Step S33: pre-set the data path bus with a corresponding hardware file list and pre-set the configuration path bus with a corresponding hardware file list to generate G i q The corresponding file list.

[0042] Step S34, compile G i q The corresponding file list generates the corresponding executable file F i q .

[0043] It should be noted that, through steps S31-S34, the configurable modules involved in the verification target are set as hardware modules, and the configurable modules not involved in the verification target are set as behavioral functional models. The data path bus and the configuration path bus are always set as hardware modules. The file list corresponding to each verification configuration information is different, and the generated compilation file list is also different, so the generated compilation environment is also different, isolated in different file directories, so different verification target processes can be executed in parallel without affecting each other.

[0044] As an embodiment, step S4 includes:

[0045] Step S41: parallelize B i q Transmit to the corresponding G i q The test cases in .

[0046] Step S42: parallelly based on the corresponding F i q Build a corresponding large-scale chip verification system.

[0047] Step S43: parallel based on G i q The test cases in the test are input into the corresponding large-scale chip verification system to perform the corresponding verification operations.

[0048] Step S43, parallel G i q Corresponding to all flipped interfaces to be verified, build the corresponding flipped interface set E to be verified iq .

[0049] It should be noted that G i q After the corresponding large-scale chip verification system is generated, the G i q The test cases in G are transferred to i q The corresponding large-scale chip verification system can realize the test cases with passed test parameters in G i q The corresponding large-scale chip verification system is running to achieve G i q Verification of the corresponding verification target.

[0050] As an embodiment, step S6 includes:

[0051] Step S61: When all G q After all executions are completed, get all GE i q The union of GE.

[0052] Step S62: Obtain the number NE of flipped interfaces to be verified in GE and the number ND of interfaces to be verified in GD.

[0053] Step S63: Determine the large-scale chip code coverage CV based on NE and ND:

[0054] CV=NE / ND.

[0055] It should be noted that some exemplary embodiments are described as processes or methods depicted as flow charts. Although the flow charts describe the steps as sequential processes, many of the steps can be implemented in parallel, concurrently or simultaneously. In addition, the order of the steps can be rearranged. The process can be terminated when its operation is completed, but it can also have additional steps not included in the accompanying drawings. The process can correspond to a method, function, procedure, subroutine, subprogram, etc.

[0056] An embodiment of the present invention also provides an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are configured to execute the method described in the embodiment of the present invention.

[0057] The embodiment of the present invention further provides a computer-readable storage medium storing computer-executable instructions, wherein the computer instructions are used to execute the method described in the embodiment of the present invention.

[0058] The method described in the embodiment of the present invention constructs different test clusters and sets corresponding verification configuration information for the test case groups in each test cluster, obtains the corresponding set of flipped interfaces to be verified based on the verification results of each test case group, and then obtains the corresponding set of flipped interfaces to be verified based on the verification results of a test cluster, and finally obtains the corresponding set of flipped interfaces to be verified based on the verification results of all clusters, thereby accurately and quickly obtaining large-scale chip code coverage.

[0059] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of the technical solution of the present invention.

Claims

1. A large-scale chip code coverage acquisition method, characterized in that: include: Step S1: Build different test clusters {G1, G2, ..., G q ,...,G Q }, G q is the gth test cluster, the value of q ranges from 1 to Q, Q is the total number of test clusters, G q ={G1 q ,G2 q ,....,G i q ,...,G f(q) q },G i q G q The i-th test case group, i ranges from 1 to f(q), f(q) is G q The corresponding number of test case groups, different G i q Corresponding to different verification configuration information; Step S2: for each G i q Set the corresponding verification configuration information A i q , corresponding test parameters B i q And the corresponding interface set D to be verified i q , the same G q Medium G i q The corresponding A i q All are different, different G q Medium G i q The corresponding A i q Probably the same, all D i q The union of is the set GD of all interfaces to be verified in large-scale chips; Step S3: parallelly based on each G i q The corresponding A i q Generate G i q The corresponding file list is compiled and generated into the corresponding executable file F i q , each F i q Located in a separate file directory; Step S4: parallelize B i q Transmit to the corresponding G i q The test cases in G i q The test cases in F are based on the corresponding i q Perform the corresponding verification operation to obtain G i q The corresponding flipped interface set E to be verified i q ; Step S5: When G q The corresponding G i q After all executions are completed, obtain G q All corresponding E i q The union of GE i q ; Step S6: When all G q After all executions are completed, get all GE i q The union of GE and GD is used to determine the large-scale chip code coverage.

2. The method according to claim 1, characterized in that In step S1, different test clusters {G1, G2, ..., G q ,...,G Q }, each G q Corresponding to a chip functional attribute, the chip functional attribute includes power consumption, chip interconnection, virtual realization, and chip reset.

3. The method according to claim 1, characterized in that Each verification configuration information defines a model type of each component module in a large-scale chip verification system. The large-scale chip verification system includes multiple engine modules, a data path bus, a configuration path bus, a storage module and a PCIE module. Each engine module is used to implement a chip function. Each engine module is connected to the data path bus and the configuration path bus respectively. The storage module is connected to the data path bus and the configuration path bus respectively. The PCIE module is connected to the data path bus and the configuration path bus respectively. The engine module, storage module and PCIE module are all configurable modules. The configurable module can be set as a hardware module or a behavioral-level functional model by configuring the module type; the data path bus and the configuration path bus are always set as hardware modules; the hardware module includes the complete internal logic and interface of the module, and the behavioral-level functional model includes the module functional logic and interface. The functional logic is a type of logic in the complete internal logic, and the interface functions of the hardware module and the behavioral-level functional model are consistent.

4. The method according to claim 3, characterized in that The data path bus is pre-set with a corresponding hardware file list, the configuration path bus is pre-set with a corresponding hardware file list, and each configurable module is pre-set with a first file list and a second file list, wherein the first file list is a file list corresponding to the hardware module of the configurable module, and the second file list is a file list corresponding to the behavioral level function model of the configurable module; The step S3 comprises: Step S31: parse each G in parallel i q The corresponding A i q , determine each G i q The module type identifier corresponding to each configurable module; Step S32: If the module type identifier corresponding to the configurable module is the first identifier, then add the first file list corresponding to the configurable module to G i q In the corresponding file list, if the module type identifier corresponding to the configurable module is the second identifier, the second file list corresponding to the configurable module is added to G i q In the corresponding file list; Step S33: pre-set the data path bus with a corresponding hardware file list and pre-set the configuration path bus with a corresponding hardware file list to generate G i q The corresponding file list; Step S34, compile G i q The corresponding file list generates the corresponding executable file F i q .

5. The method according to claim 1, characterized in that The step S4 comprises: Step S41: parallelize B i q Transmit to the corresponding G i q Test cases in ; Step S42: parallelly based on the corresponding F i q Build a corresponding large-scale chip verification system; Step S43: parallel based on G i q The test cases in the test are input into the corresponding large-scale chip verification system to perform the corresponding verification operations; Step S43, parallel G i q Corresponding to all flipped interfaces to be verified, build the corresponding flipped interface set E to be verified i q .

6. The method according to claim 1, characterized in that The step S6 comprises: Step S61: When all G q After all executions are completed, get all GE i q The union of GE; Step S62, obtaining the number NE of flipped interfaces to be verified in GE and the number ND of interfaces to be verified in GD; Step S63: Determine the large-scale chip code coverage CV based on NE and ND: CV=NE / ND.

7. An electronic device, characterized in that: include: at least one processor; and, a memory communicatively coupled to the at least one processor; The memory stores instructions executable by the at least one processor, wherein the instructions are configured to execute the method according to any one of claims 1 to 6.

8. A computer-readable storage medium, characterized in that: Computer executable instructions are stored, and the computer executable instructions are used to execute the method according to any one of the preceding claims 1-6.

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