Configuration Method and System for Starting a Slave Device Based on SPI Slave

Abstract

Configuration method and system for starting a slave device based on SPI Slave, which can solve the limitations of existing methods for loading FPGA programs and simplify user usage; the flexibility of configuration can be improved through externally controllable pause and interrupt methods. The method includes: (1) connecting an external master device to a slave device through the SPI communication protocol; (2) generating a configuration file for the slave device through EDA software; (3) the external master device transmits the configuration file to the slave device through the spi_slave interface; setting the spi_clk frequency and the amount of data transferred at one time; the external master device interacts with the slave device to query the idle state of the slave device; if a configuration pause command is received, the configuration is stopped and waits to continue the configuration from the pause position after receiving a configuration resume command; if a configuration interrupt name is received, the configuration is stopped and the configuration of other configuration files is restarted; (4) determining whether the configuration of the slave device is successful.

Description

Technical Field

[0001] The present invention relates to the technical field of chips, and in particular to a configuration method for starting a slave device based on SPI Slave, and a configuration system for starting a slave device based on SPI Slave. Background Art

[0002] Field Programmable Gate Array (FPGA) is a large-scale programmable device, which solves the deficiencies of custom circuits. Users can use a hardware description language to compile the description of the required function design into a bitstream file to configure the FPGA and implement the circuit functions required by the users. The advantages of programmability, reconfigurability, and simplicity of use make FPGA widely used in various fields.

[0003] However, the existing methods for loading chip programs such as FPGA and CPLD have the following defects:

[0004] 1. SPI Master configuration method (as shown in Figure 1 ): By externally connecting a flash, after power-on or Prog_b reset, the FPGA actively reads a certain amount of data from the external flash to configure the FPGA. The configuration process cannot be interrupted or paused and needs to wait until the configuration is completed.

[0005] 2. Passive Serial / Slave Select Map configuration method (as shown in Figure 2 ): There are many interface control signals, and it is not a general communication protocol. There is no backpressure solution mechanism, and the configuration clock cannot be too fast. If it is too fast, problems such as data loss due to the FPGA being unable to process will occur. Summary of the Invention

[0006] To overcome the defects of the prior art, the technical problem to be solved by the present invention is to provide a configuration method for starting a slave device based on SPI Slave, which can solve the limitations of the existing methods for loading FPGA programs. By transmitting the configuration file in a serial manner through fewer communication signals with the FPGA and a standard SPI communication protocol, it will simplify the user's use; and the flexibility of configuration can be improved through externally controllable pause and interruption methods, which has extremely high practical value.

[0007] The technical solution of the present invention is: This configuration method for starting a slave device based on SPI Slave includes the following steps:

[0008] (1) The external master device is connected to the slave device through the SPI communication protocol. The SPI mode is mode 0 or mode 3, and the SPI clock frequency is set by the external master device;

[0009] (2) Generate the configuration file of the slave device through EDA software;

[0010] (3) The external master device transmits the configuration file to the slave device through the spi_slave interface; set the clock frequency spi_clk of the SPI interface to transmit data and the amount of data transmitted at one time; the external master device interacts with the slave device to query the idle state of the slave device; if a configuration pause command is received, stop the configuration and wait to continue the configuration from the pause position after receiving the configuration continue command; if a configuration interrupt name is received, stop the configuration and start the configuration of other configuration files again;

[0011] (4) Determine whether the configuration of the slave device is successful and output the result of whether the configuration is successful or not.

[0012] The beneficial technical effects of the present invention are:

[0013] 1. The external SPI master device directly transmits the configuration file to the FPGA through the spi interface without a dedicated flash for storing the configuration file.

[0014] 2. Through the standard SPI communication protocol, there are fewer serial interface signals, which is convenient for users to use. And in the Slave mode, the frequency of the configuration clock can be flexibly changed externally, as well as the amount of data transmitted at one time, meeting the FPGA configuration requirements of various configuration time needs without the need to change the content of the configuration file additionally.

[0015] 3. Externally, by interacting with the FPGA to query the status of the FPGA, it can adaptively solve the problem that when configuring the FPGA with different SPI clock configurations, the FPGA receives data too fast due to backpressure from the external transmission, resulting in data loss when the FPGA cannot receive it.

[0016] 4. Configure the FPGA in the passive mode of spi slave. During the configuration process, the configuration can be paused at any time according to the sending of the host computer, and then continue to be configured after a period of time, or interrupt the current configuration and start a new configuration.

[0017] A configuration system for starting the slave device based on SPI Slave is also provided. The external master device is connected to the slave device through the SPI communication protocol. The SPI mode is mode 0 or mode 3, and the SPI clock frequency is set by the external master device. The configuration system for starting the slave device based on SPI Slave includes:

[0018] A configuration file generation module that generates the configuration file of the slave device through EDA software;

[0019] The configuration file transfer module is configured such that an external master device transfers a configuration file to a slave device through the spi_slave interface; sets the clock frequency spi_clk for data transfer through the SPI interface and the amount of data transferred at one time; the external master device interacts with the slave device to query the idle state of the slave device; if a configuration pause command is received, it stops the configuration and waits to continue the configuration from the paused position after receiving a configuration resume command; if a configuration interrupt name is received, it stops the configuration and starts configuring other configuration files anew;

[0020] The judgment module judges whether the configuration of the slave device is successful and outputs the result of whether the configuration is successful or not. Description of the Drawings

[0021] Figure 1 It is the SPI_Master configuration method of the prior art.

[0022] Figure 2 It is the Slave Serial / slave select map configuration method of the prior art.

[0023] Figure 3 It shows a schematic diagram of the SPI_Slave configuration method of the present invention.

[0024] Figure 4 It is a flowchart of the configuration method for starting a slave device based on SPI Slave according to the present invention. Detailed Embodiment

[0025] As Figure 3 、 Figure 4 shown, this configuration method for starting a slave device based on SPI Slave includes the following steps:

[0026] (1) The external master device is connected to the slave device through the SPI communication protocol, the SPI mode is mode 0 or mode 3, and the SPI clock frequency is set by the external master device;

[0027] (2) Generate a configuration file for the slave device through EDA software;

[0028] (3) The external master device transfers the configuration file to the slave device through the spi_slave interface; sets the clock frequency spi_clk for data transfer through the SPI interface and the amount of data transferred at one time; the external master device interacts with the slave device to query the idle state of the slave device; if a configuration pause command is received, it stops the configuration and waits to continue the configuration from the paused position after receiving a configuration resume command; if a configuration interrupt name is received, it stops the configuration and starts configuring other configuration files anew;

[0029] (4) Judge whether the configuration of the slave device is successful and output the result of whether the configuration is successful or not.

[0030] The beneficial technical effects of the present invention are as follows:

[0031] 1. The external SPI master device directly transmits the configuration file to the FPGA through the SPI interface, eliminating the need for a dedicated flash for storing the configuration file.

[0032] 2. Through the standard SPI communication protocol, there are fewer serial interface signals, making it convenient for users. In Slave mode, the frequency of the configuration clock and the amount of data transmitted at one time can be flexibly changed externally, meeting the FPGA configuration requirements for various configuration times without the need to additionally change the content of the configuration file.

[0033] 3. Externally, by interacting with the FPGA to query the status of the FPGA, it can adaptively solve the problem that when the FPGA is configured with different SPI clocks, the FPGA may experience backpressure due to too fast external data transmission, resulting in data loss because the FPGA cannot receive the data.

[0034] 4. Configure the FPGA in the passive SPI slave mode. During the configuration process, the configuration can be paused at any time according to the command sent by the host computer, and then continue the configuration after a period of time, or interrupt the current configuration and start a new configuration.

[0035] Preferably, in step (1), the external master device is a host computer, and the slave device is an FPGA.

[0036] Preferably, in step (2), the EDA software sequentially performs synthesis, placement and routing, and generates a configuration file according to the function program to be implemented by the FPGA written by the user.

[0037] Preferably, step (3) includes the following sub-steps:

[0038] (3.1) Set the configuration mode of the FPGA to the spi_slave mode;

[0039] (3.2) The host computer sets the SPI mode to mode 0 or mode 3; sets the SPI clock frequency spi_clk; starts sending prog_b reset to the FPGA;

[0040] (3.3) The host computer sends the corresponding control status register address and writes the starting bit value to be sent: sets the amount of data transmitted at one time to N, marking the start of the FPGA configuration loading;

[0041] (3.4) The host computer sends the corresponding control status register address to the FPGA, reads the value of this register. If the value of the 20th bit is 1, it indicates that the FPGA is in a busy state; if it is 0, it indicates that the FPGA is in an idle state. The host computer interacts with the FPGA by continuously repeating the reading of this control status register to query the status of the FPGA until the FPGA is in an idle state;

[0042] (3.5) When the FPGA is in an idle state, the host computer sequentially outputs and writes the N (N is set in step (3.2)) 8-bit (bit0~bit7) data in the configuration file to the corresponding data register address of the FPGA;

[0043] (3.6) Repeat steps (3.4) and (3.5) until the data transmission of the configuration file ends; if the end of the configuration file data is less than the amount of data for one transmission, the empty bits are filled with zeros;

[0044] (3.7) Repeat step (3.4);

[0045] (3.8) When the FPGA is in an idle state, the host computer writes the transmission end bit to the corresponding control status register address of the FPGA, indicating that the host computer has completed the transmission of the configuration file.

[0046] Preferably, in step (4), if the FPGA configuration is successful, then done = 1; if the configuration fails, done = 0; if the host computer selects to reconfigure, then execute step (3.1), otherwise end.

[0047] Preferably, in step (1), the external master device is the host computer, and the slave device is the CPLD (which can be used in product designs configured in the spi slave mode).

[0048] Those of ordinary skill in the art can understand that all or part of the steps in implementing the method of the above embodiments can be completed by instructing relevant hardware through a program. The program can be stored in a computer-readable storage medium. When this program is executed, it includes the steps of the method of the above embodiments, and the storage medium can be: ROM / RAM, magnetic disk, optical disk, memory card, etc. Therefore, corresponding to the method of the present invention, the present invention also simultaneously includes a configuration system for starting the slave device based on SPI Slave, which is usually represented in the form of functional modules corresponding to the steps of the method. The external master device is connected to the slave device through the SPI communication protocol. The SPI mode is mode 0 or mode 3, and the SPI clock frequency is set by the external master device. This configuration system for starting the slave device based on SPI Slave includes:

[0049] A configuration file generation module that generates a configuration file for the slave device through EDA software;

[0050] A configuration file transfer module, configured for an external master device to transfer a configuration file to a slave device through the spi_slave interface; set the clock frequency spi_clk for data transmission through the SPI interface and the amount of data transmitted at one time; the external master device interacts with the slave device to query the idle state of the slave device; if a configuration pause command is received, stop the configuration and wait to continue the configuration from the paused position after receiving a configuration resume command; if a configuration interrupt name is received, stop the configuration and start configuring other configuration files again;

[0051] A judgment module, which judges whether the configuration of the slave device is successful and outputs the result of whether the configuration is successful or not.

[0052] Preferably, the external master device is a host computer and the slave device is an FPGA.

[0053] Preferably, in the configuration file generation module, the EDA software sequentially performs synthesis, placement and routing, and generates a configuration file according to the functional program to be implemented by the FPGA written by the user.

[0054] Preferably, the configuration file transfer module performs the following steps:

[0055] (3.1) Set the configuration mode of the FPGA to the spi_slave mode;

[0056] (3.2) The host computer sets the SPI mode to mode 0 or mode 3; sets the clock frequency spi_clk of the SPI; starts to send a prog_b reset to the FPGA;

[0057] (3.3) The host computer sends the corresponding control status register address and writes the starting bit value for transmission: set the amount of data transmitted at one time to N, marking the start of FPGA configuration loading;

[0058] (3.4) The host computer sends the corresponding control status register address to the FPGA and reads the value of the register. If the value of the 20th bit is 1, it means the FPGA is in a busy state. If it is 0, it means the FPGA is in an idle state; the host computer interacts with the FPGA by continuously repeating the reading of the control status register to query the status of the FPGA until the FPGA is in an idle state;

[0059] (3.5) When the FPGA is in an idle state, the host computer sequentially outputs N 8-bit data in the configuration file to the corresponding data register address of the FPGA;

[0060] (3.6) Repeat steps (3.4) and (3.5) until the configuration file data transmission ends; if the end of the configuration file data is less than the amount of data transmitted at one time, fill the empty bits with zeros;

[0061] (3.7) Repeat step (3.4);

[0062] When the FPGA is in the idle state, the host computer writes the transmission end bit to the corresponding control status register address of the FPGA, indicating that the host computer has completed the transmission of the configuration file.

[0063] The above are only the preferred embodiments of the present invention, and do not impose any form of limitation on the present invention. Any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention still fall within the protection scope of the technical solution of the present invention.

Claims

1. A configuration method for starting a slave device based on SPI Slave, characterized in that: It includes the following steps: (1) The external master device is connected to the slave device through the SPI communication protocol. The SPI mode is mode 0 or mode 3, and the SPI clock frequency is set by the external master device; (2) Generate the configuration file of the slave device through EDA software; (3) The external master device transmits the configuration file to the slave device through the spi_slave interface; set the clock frequency spi_clk of the SPI interface to transmit data and the amount of data transmitted at one time; the external master device interacts with the slave device to query the idle state of the slave device; if the configuration pause command is received, the configuration is stopped, and the configuration continues from the paused position after receiving the configuration continue command; if the configuration interrupt name is received, the configuration is stopped and the configuration of other configuration files is restarted; (4) Judge whether the configuration of the slave device is successful and output the result of whether the configuration is successful or not; In the step (1), the external master device is the host computer and the slave device is the FPGA; In the step (2), the EDA software sequentially performs synthesis, placement and routing, and generates a configuration file according to the function program to be implemented by the FPGA written by the user; The step (3) includes the following sub-steps: (3.1) Set the configuration mode of the FPGA to the spi_slave mode; (3.2) The host computer sets the SPI mode to mode 0 or mode 3; set the clock frequency spi_clk of the SPI; start sending prog_b reset to the FPGA; (3.3) The host computer sends the corresponding control status register address and writes the starting bit value: set the amount of data transmitted at one time to N, indicating the start of the FPGA configuration loading; (3.4) The host computer sends the corresponding control status register address to the FPGA and reads the value of the register. If the value of the 20th bit is 1, it means the FPGA is in the busy state, and if it is 0, it means the FPGA is in the idle state; the host computer interacts with the FPGA by continuously repeating to read the control status register to query the status of the FPGA until the FPGA is in the idle state; (3.5) When the FPGA is in the idle state, the host computer sequentially outputs N 8-bit data in the configuration file and writes them to the corresponding data register address of the FPGA; (3.6) Repeat steps (3.4) and (3.5) until the data transmission of the configuration file ends; if the end of the configuration file data is less than the amount of data transmitted at one time, the empty bits are filled with zeros; (3.7) Repeat step (3.4); (3.8) When the FPGA is in the idle state, the host computer writes the transmission end bit to the corresponding control status register address of the FPGA, indicating that the host computer has completed transmitting the configuration file.

2. The configuration method for starting a slave device based on SPI Slave according to claim 1, wherein: In the step (4), if the FPGA configuration is successful, then done = 1; if the configuration fails, done = 0; if the host computer selects to reconfigure, then execute step (3.1), otherwise end.

3. The configuration method for starting a slave device based on SPI Slave according to claim 1, characterized in that: In the step (1), the external master device is the host computer and the slave device is the CPLD.

4. A configuration system for starting a slave device based on SPI Slave, characterized in that: The external master device is connected to the slave device through the SPI communication protocol. The SPI mode is mode 0 or mode 3, and the SPI clock frequency is set by the external master device. The configuration system for starting the slave device based on SPISlave includes: A configuration file generation module that generates a configuration file for the slave device through EDA software; A configuration file transmission module configured to transmit the configuration file from the external master device to the slave device through the spi_slave interface; set the clock frequency spi_clk for data transmission through the SPI interface and the amount of data transmitted at one time; the external master device interacts with the slave device to query the idle state of the slave device; if a configuration pause command is received, the configuration is stopped and waits to continue the configuration from the pause position after receiving a configuration continue command; if a configuration interrupt name is received, the configuration is stopped and the configuration of other configuration files is restarted; A judgment module that judges whether the configuration of the slave device is successful and outputs the result of whether the configuration is successful or not; The external master device is a host computer, and the slave device is an FPGA; In the configuration file generation module, the EDA software sequentially performs synthesis, placement and routing, and generates a configuration file according to the function program to be implemented by the FPGA written by the user; The configuration file transmission module performs the following steps: (3.1) Set the configuration mode of the FPGA to the spi_slave mode; (3.2) The host computer sets the SPI mode to mode 0 or mode 3; sets the clock frequency spi_clk of the SPI; starts to send a prog_b reset to the FPGA; (3.3) The host computer sends the corresponding control status register address and writes the starting bit value: sets the amount of data transmitted at one time to N, indicating the start of FPGA configuration loading; (3.4) The host computer sends the corresponding control status register address to the FPGA and reads the value of the register. If the value of the 20th bit is 1, it means the FPGA is in a busy state, and if it is 0, it means the FPGA is in an idle state; the host computer interacts with the FPGA by continuously repeating the reading of the control status register to query the status of the FPGA until the FPGA is in an idle state; (3.5) When the FPGA is in an idle state, the host computer sequentially outputs N 8-bit data in the configuration file to the corresponding data register address of the FPGA; (3.6) Repeat steps (3.4) and (3.5) until the transmission of the configuration file data ends; if the end of the configuration file data is less than the amount of data transmitted at one time, the empty bits are filled with zeros; (3.7) Repeat step (3.4); (3.8) When the FPGA is in an idle state, the host computer writes an end transmission bit to the corresponding control status register address of the FPGA, indicating that the host computer has completed the transmission of the configuration file.

Images