NAND graph generation method and device and computer equipment

Abstract

The invention relates to an NAND graph generation method and device and computer equipment. The method comprises the steps of generating a conditional probability distribution function corresponding to NAND graph data based on NAND graph data of a target circuit and a target distribution type obeyed by the NAND graph data; sampling potential distribution parameters from the conditional probability distribution function, and decoding the potential distribution parameters to obtain a node feature vector of each node, a graph feature matrix of the target graph and the non-graph, and probability features of edges between the nodes; for the target node, obtaining a node prediction type of the target node based on the graph feature matrix, a node feature vector of a previous node of the target node and a preset neural network model; determining an associated node of the target node based on the node prediction type and the edge probability feature of the target node; and based on each target node and each associated node corresponding to the target node, generating a target NAND graph corresponding to the target circuit. By adopting the method, the NAND graph generation efficiency can be improved.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a method, apparatus, and computer device for generating a non-AND graph. Background Art

[0002] In electronic design automation, a NAND graph is a graphical structure used to represent Boolean functions. It represents a Boolean logic function as a combination of AND and NOT gates. NAND graphs are widely used for optimization in digital circuit design. They effectively represent logical relationships and facilitate graphical operations such as simplifying logic, performing equivalence checks, and optimizing circuit area and delay.

[0003] Traditional methods for generating NAND graphs typically involve logic optimization methods based on Boolean algebra simplification or Karnaugh maps. However, these methods often require extensive computation and manual adjustments, making the process of generating and optimizing NAND graphs inefficient, especially when dealing with complex or large-scale circuits. Summary of the Invention

[0004] Based on this, it is necessary to provide a method, device, computer equipment, readable storage medium and program product for generating a non-AND graph that can improve the efficiency of non-AND graph generation in order to address the above technical problems.

[0005] In a first aspect, the present application provides a method for generating a non-graph, comprising:

[0006] Generate a conditional probability distribution function corresponding to the NAND graph data based on the target circuit's NAND graph data, the target distribution type obeyed by the NAND graph data, and a preset neural network model, wherein the NAND graph data reflects multiple nodes in the target NAND graph and edges connecting the nodes;

[0007] Sampling potential distribution parameters from the conditional probability distribution function, decoding the potential distribution parameters, and obtaining a node feature vector of each node, a graph feature matrix of the target and non-graph, and a probability feature of edges between each node;

[0008] For a target node, based on the graph feature matrix, the node feature vector of the previous node of the target node, and a preset neural network model, a node prediction type of the target node is obtained; based on the node prediction type and the edge probability characteristics of the target node, an associated node of the target node is determined;

[0009] A target NAND graph corresponding to the target circuit is generated based on each of the target nodes and each of the associated nodes corresponding to the target nodes.

[0010] In one embodiment, the method further comprises:

[0011] The target and the non-graph are tested to obtain a test result; if the test result does not meet the preset performance requirement, the step of sampling the potential distribution parameters from the conditional probability distribution function is continued until the target and the non-graph meet the preset performance requirement.

[0012] In one embodiment, the preset neural network model includes at least a decoder; decoding the potential distribution parameters to obtain a node feature vector of each node, a graph feature matrix of the target and non-graph, and an edge probability feature of each edge; including:

[0013] Decoding the potential distribution parameters by the decoder to obtain a node feature vector of each node, and concatenating the feature vectors of each node to obtain a graph feature matrix of the target and non-graph;

[0014] The graph feature matrix is ​​decoded by the decoder to obtain the probability feature of each edge.

[0015] In one embodiment, generating a target NAND graph corresponding to the target circuit based on each target node and each associated node corresponding to the target node includes:

[0016] For each target node, each of the associated nodes is connected to the target node through an edge of the target node to generate a sub-NAND graph;

[0017] A plurality of the sub-NAND graphs are combined to obtain a target NAND graph corresponding to the target circuit.

[0018] In one embodiment, the method further comprises:

[0019] By presetting a neural network model, the target node and the associated nodes corresponding to the target node, the node feature vector of the target node is updated; based on the updated node feature vector, the graph feature matrix is ​​updated to obtain an updated graph feature matrix.

[0020] In one embodiment, the method further comprises:

[0021] Acquiring sample logic data of a sample logic circuit based on a logic synthesis tool;

[0022] Converting the sample logic data through an encoder in an initial neural network model to obtain a sample graph feature matrix corresponding to the sample logic circuit, and embedding the sample graph feature matrix to obtain a sample embedding feature vector;

[0023] For each sample node, the sample embedded feature vector is extracted by the encoder to obtain a sample node feature vector; a sample conditional probability distribution function corresponding to the sample node feature vector is calculated based on a preset probability distribution formula; sample potential distribution parameters are sampled from the sample conditional probability distribution function, and the sample potential distribution parameters are decoded by the decoder in the initial neural network model to obtain a sample node feature vector of each sample node, a sample graph feature matrix of the sample logic circuit, and sample edge probability features of edges between each sample node;

[0024] For a sample target node, based on the sample graph feature matrix, the sample node feature vector of the previous node of the sample target node and the initial neural network model, the sample node prediction type of the sample target node is obtained; based on the sample node prediction type and the sample edge probability feature, the sample associated node with the sample target node is determined; based on multiple sample target nodes and the sample target node and each sample associated node, a sample target and non-graph corresponding to the sample logic circuit is generated.

[0025] In one embodiment, the calculating of the sample conditional probability distribution function corresponding to the sample node feature vector based on a preset probability distribution formula includes:

[0026] A preset distribution type is set for the feature vector of the sample node, and a first conditional probability distribution function of a potential distribution parameter corresponding to the feature vector of the sample node is determined based on the preset distribution type; a sample conditional probability distribution function is obtained based on the dependency relationship between the sample node and the predecessor node of the sample node, and the first conditional probability distribution function, and the sample conditional probability distribution function represents a target distribution type corresponding to non-graph data.

[0027] In one embodiment, the method further comprises:

[0028] Performing circuit simulation on the sample target and the non-graph to obtain a functional test result; performing performance testing on the sample target and the non-graph to obtain a performance test result;

[0029] The functional test results and the performance test results are compared with the target performance requirements to obtain a comparison result, and the parameters of the initial neural network model are optimized based on the comparison result to obtain a preset neural network model, and the target performance requirements are related to the attribute information of the sample logic circuit.

[0030] In a second aspect, the present application further provides a device for generating a non-AND graph, comprising:

[0031] A first generation module is configured to generate a conditional probability distribution function corresponding to the NAND graph data based on the NAND graph data of the target circuit, the target distribution type obeyed by the NAND graph data, and a preset neural network model, wherein the NAND graph data reflects multiple nodes in the target NAND graph and edges connecting the nodes;

[0032] a processing module, configured to sample potential distribution parameters from the conditional probability distribution function, decode the potential distribution parameters, and obtain a node feature vector of each node, a graph feature matrix of the target and non-graph, and a probability feature of the edges between each node;

[0033] A determination module is configured to obtain, for a target node, a node prediction type of the target node based on the graph feature matrix, a node feature vector of a previous node of the target node, and a preset neural network model; and determine associated nodes of the target node based on the node prediction type and edge probability characteristics of the target node;

[0034] The second generating module is configured to generate a target NAND graph corresponding to the target circuit based on each of the target nodes and each of the associated nodes corresponding to the target nodes.

[0035] In a third aspect, the present application further provides a computer device comprising a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the following steps are implemented:

[0036] Generate a conditional probability distribution function corresponding to the NAND graph data based on the target circuit's NAND graph data, the target distribution type obeyed by the NAND graph data, and a preset neural network model, wherein the NAND graph data reflects multiple nodes in the target NAND graph and edges connecting the nodes;

[0037] Sampling potential distribution parameters from the conditional probability distribution function, decoding the potential distribution parameters, and obtaining a node feature vector of each node, a graph feature matrix of the target and non-graph, and a probability feature of edges between each node;

[0038] For a target node, based on the graph feature matrix, the node feature vector of the previous node of the target node, and a preset neural network model, a node prediction type of the target node is obtained; based on the node prediction type and the edge probability characteristics of the target node, an associated node of the target node is determined;

[0039] A target NAND graph corresponding to the target circuit is generated based on each of the target nodes and each of the associated nodes corresponding to the target nodes.

[0040] In a fourth aspect, the present application further provides a computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the following steps are implemented:

[0041] Generate a conditional probability distribution function corresponding to the NAND graph data based on the target circuit's NAND graph data, the target distribution type obeyed by the NAND graph data, and a preset neural network model, wherein the NAND graph data reflects multiple nodes in the target NAND graph and edges connecting the nodes;

[0042] Sampling potential distribution parameters from the conditional probability distribution function, decoding the potential distribution parameters, and obtaining a node feature vector of each node, a graph feature matrix of the target and non-graph, and a probability feature of edges between each node;

[0043] For a target node, based on the graph feature matrix, the node feature vector of the previous node of the target node, and a preset neural network model, a node prediction type of the target node is obtained; based on the node prediction type and the edge probability characteristics of the target node, an associated node of the target node is determined;

[0044] A target NAND graph corresponding to the target circuit is generated based on each of the target nodes and each of the associated nodes corresponding to the target nodes.

[0045] In a fifth aspect, the present application further provides a computer program product, comprising a computer program, which, when executed by a processor, implements the following steps:

[0046] Generate a conditional probability distribution function corresponding to the NAND graph data based on the target circuit's NAND graph data, the target distribution type obeyed by the NAND graph data, and a preset neural network model, wherein the NAND graph data reflects multiple nodes in the target NAND graph and edges connecting the nodes;

[0047] Sampling potential distribution parameters from the conditional probability distribution function, decoding the potential distribution parameters, and obtaining a node feature vector of each node, a graph feature matrix of the target and non-graph, and a probability feature of edges between each node;

[0048] For a target node, based on the graph feature matrix, the node feature vector of the previous node of the target node, and a preset neural network model, a node prediction type of the target node is obtained; based on the node prediction type and the edge probability characteristics of the target node, an associated node of the target node is determined;

[0049] A target NAND graph corresponding to the target circuit is generated based on each of the target nodes and each of the associated nodes corresponding to the target nodes.

[0050] The above-mentioned method, device and computer equipment for generating a non-graph can effectively learn the logical constraints in the circuit by sampling potential distribution parameters from the conditional probability distribution function corresponding to the non-graph data, decoding the potential distribution parameters, and obtaining the node feature vector of each node, the graph feature matrix of the target non-graph and the probability characteristics of the edges between each node; for the target node, based on the graph feature matrix, the node feature vector of the previous node of the target node and the preset neural network model, the node prediction type of the target node is obtained; based on the node prediction type and the edge probability characteristics of the target node, the associated nodes of the target node are determined, and based on each target node and each associated node corresponding to the target node, the target non-graph corresponding to the target circuit is generated. The target non-graph satisfies logical consistency and feasibility, ensuring that an effective circuit can be generated, and automatically generating a non-graph, thereby improving the efficiency of non-graph generation. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following briefly introduces the drawings required for use in the embodiments of the present application or related technical descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying any creative work.

[0052] Figure 1 1 is a flow chart of a method for generating a non-AND graph in one embodiment;

[0053] Figure 2 A schematic diagram of the structure of a non-graph in one embodiment;

[0054] Figure 3 Schematic diagram of the target and non-graph generation process in one embodiment;

[0055] Figure 4 1 is a flow chart of a method for generating a non-AND graph in one embodiment;

[0056] Figure 5 Schematic diagram of the structure of a variational autoencoder in one embodiment;

[0057] Figure 6 is a structural block diagram of a device for generating a non-graph in one embodiment;

[0058] Figure 7 FIG. 1 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0059] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0060] In an exemplary embodiment, Figure 1 As shown, a method for generating a non-graph is provided. This embodiment uses the method applied to a terminal as an example for illustration. It is understandable that the method can also be applied to a server, or to a system including a terminal and a server, and implemented through interaction between the terminal and the server. In this embodiment, the method includes the following steps:

[0061] Step 101: Based on the NAND graph data of the target circuit, the target distribution type obeyed by the NAND graph data, and a preset neural network model, a conditional probability distribution function corresponding to the NAND graph data is generated.

[0062] Among them, the target circuit can be a logic circuit that needs to be designed, optimized or analyzed in a specific application scenario. The NAND graph data can be generated by the NAND graph to be generated or for the NAND graph to be optimized. The NAND graph to be generated can be determined by a Boolean logic expression, truth value information or other forms. The NAND graph can be a logic network that only contains two-input AND gates and NOT gates. The NAND graph data can reflect multiple nodes in the target NAND graph and the edges connecting each node. The target distribution type can be the probability distribution type obeyed. The target distribution type can be determined based on the actual distribution of the NAND graph during the training process. The edge can be a directed edge. The preset neural network model includes at least an encoder.

[0063] Specifically, the terminal can obtain the initial NAND graph data corresponding to the target circuit or the NAND graph to be optimized. If the target circuit is a NAND graph to be optimized, the terminal can extract the NAND graph data from the NAND graph to be optimized using a logic synthesis tool. The terminal can use an encoder to convert the NAND graph data into a graph feature matrix, embed the graph feature matrix using the encoder to obtain an embedded feature vector, and then determine the embedded feature vector as the NAND graph data. For example, the logic synthesis tool can be the ABC (A Berkeley Cross-Platform) tool. The expression corresponding to the NAND graph data can be G = (V, E), where V is the node set and E is the edge set.

[0064] The terminal may determine the target distribution type that the non-graph data obeys based on the type of the non-graph data. The terminal may use an encoder to calculate the conditional probability distribution function corresponding to the non-graph data based on the non-graph data and the target distribution type that the non-graph data obeys. For example, the terminal may perform feature extraction on the non-graph data through a neural network to obtain an initial node feature vector, and calculate the conditional probability distribution function based on the initial node feature vector and the target distribution type that the non-graph data obeys. The terminal may determine the mean function and variance function corresponding to each node corresponding to the non-graph data based on the conditional probability distribution function.

[0065] Step 102: Sample potential distribution parameters from the conditional probability distribution function, decode the potential distribution parameters, and obtain the node feature vector of each node, the graph feature matrix of the target and non-graph, and the probability feature of the edges between each node.

[0066] The target NAND graph may be a NAND graph to be output.

[0067] Specifically, the terminal can randomly obtain the non-graph data and the mean function and variance function corresponding to the non-graph data from the conditional probability distribution. The terminal can use a preset reparameterization formula to determine the potential distribution parameters. The preset reparameterization specific formula can be:

[0068]

[0069] Among them, z is the potential distribution parameter; x is the non-graph data, μ(x) is the mean function; σ(x) is the variance function, is a standard normal distribution.

[0070] The terminal decodes the underlying distribution parameters using a decoder in a pre-set neural network to obtain a node feature vector for each node. The node feature vectors for each node are concatenated to obtain a graph feature matrix corresponding to the target and non-graphs. The terminal decodes the graph feature matrix using a decoder to obtain the probabilistic features of the edges between each node.

[0071] Step 103: For the target node, based on the graph feature matrix, the node feature vector of the previous node of the target node and the preset neural network model, obtain the node prediction type of the target node; based on the node prediction type and the edge probability characteristics of the target node, determine the associated nodes of the target node.

[0072] Specifically, a NAND graph may include N nodes. The terminal may determine a starting node and determine the i-th node as a target node, where 1 < i ≤ N. For the i-th node, based on the graph feature matrix, the node feature vector of the i-1-th node, and a preset neural network model, the node prediction type of the target node is obtained. Based on the node prediction type and edge probability features, the terminal may determine nodes with a connection relationship with the target node if the edge probability feature between the nodes is greater than or equal to a probability threshold, and determine the nodes with a connection relationship with the target node as associated nodes of the target node.

[0073] Step 104 : Generate a target NAND graph corresponding to the target circuit based on each target node and each associated node corresponding to the target node.

[0074] Specifically, for each target node, each associated node is connected to the target node through the edge of the target node to generate a sub-NAND graph; multiple sub-NAND graphs are combined to obtain the target NAND graph corresponding to the target circuit. Figure 2 As shown, Figure 2 This is a structural diagram of a NAND graph, where black solid circles represent NOT gates, hollow circles represent AND gates, and arrows represent the logical relationships (edges) between nodes.

[0075] The aforementioned NAND graph generation method samples latent distribution parameters from the conditional probability distribution function corresponding to the NAND graph data, decodes the latent distribution parameters, and obtains node feature vectors for each node, a graph feature matrix for the target NAND graph, and probabilistic features of the edges between each node. This method effectively learns the logical constraints in the circuit. For the target node, the node prediction type is obtained based on the graph feature matrix, the node feature vector of the target node's previous node, and a preset neural network model. Based on the node prediction type and the target node's edge probabilistic features, the target node's associated nodes are determined. Based on each target node and its associated nodes, a target NAND graph corresponding to the target circuit is generated. The target NAND graph satisfies logical consistency and feasibility, ensuring its implementation as a valid circuit design. This method achieves automated NAND graph generation and improves its efficiency.

[0076] In an exemplary embodiment, the method for generating a NAND graph further includes:

[0077] The target and the non-graph are tested to obtain a test result; if the test result does not meet the preset performance requirement, the step of sampling the potential distribution parameters from the conditional probability distribution function is continued until the target and the non-graph meet the preset performance requirement.

[0078] The test results can reflect the functional and performance indicators of the target and non-graph components. Functional indicators can include logical correctness and timing, while performance indicators can include latency, power consumption, and area. The indicators for target and non-graph testing can be determined based on the needs of the actual application scenario and are not specifically limited here. Pre-set performance requirements can include functional correctness and compliance with performance indicators within a certain range.

[0079] Specifically, the terminal may perform circuit simulation on the target and non-graph to verify functional indicators of the target and non-graph and obtain verification results; the terminal may test performance indicators of the target and non-graph to obtain performance indicator test results. The terminal may determine the verification results and / or performance indicator test results as test results.

[0080] The terminal can determine the preset performance requirements based on the performance requirements of the AND-NOT graph. If the verification result is correct and the performance index test result is within the preset range of the performance index, the terminal determines that the test result meets the preset performance requirements, and determines that the target AND-NOT graph is the final required AND-NOT graph. If there is an inaccuracy in the verification result and / or the performance index test result exceeds the performance index compliance range, it is determined that at least one of the verification result and the performance index test result does not meet the preset performance requirements. The terminal can re-execute the step of sampling potential distribution parameters from the conditional probability distribution function to obtain a second target AND-NOT graph, and test the second target AND-NOT graph to obtain a second test result. If the second test result meets the preset performance requirements, the second target AND-NOT graph is determined to be the final required AND-NOT graph. If the second test result still does not meet the preset performance requirements, continue to re-execute the step of sampling potential distribution parameters from the conditional probability distribution function, and so on, until the target AND-NOT graph meets the preset performance requirements.

[0081] In this embodiment, multi-objective optimization is introduced by testing the target AND / NOT graph to ensure that the resulting target AND / NOT graph meets performance requirements. If the target AND / NOT graph does not meet performance requirements, a new target AND / NOT graph is obtained through resampling until the target AND / NOT graph meets performance requirements. By employing a generative model, this embodiment effectively learns the logical constraints in circuit design. Traditional logic synthesis testing methods are then introduced into the generated AND / NOT graph, ensuring that the generated graph not only meets logical correctness but also meets the implementation requirements of the circuit design.

[0082] In an exemplary embodiment, the specific implementation process of "decoding the potential distribution parameters to obtain the node feature vector of each node, the graph feature matrix of the target and non-graph, and the edge probability feature of each edge" in step 102 may include:

[0083] The decoder decodes the potential distribution parameters to obtain the node feature vector of each node, and concatenates the feature vectors of each node to obtain the graph feature matrix of the target and non-graph; the decoder decodes the graph feature matrix to obtain the probability characteristics of each edge.

[0084] Among them, the preset neural network model includes at least a decoder and an encoder, the encoder is a variational autoencoder, and the decoder is a multi-layer perceptron.

[0085] Specifically, the terminal can decode the potential distribution parameter z through the decoder to obtain the node feature vector of each node. The terminal can concatenate the feature vectors of each node to obtain the graph feature matrix of the target and non-graph. The terminal can decode the decoder through the decoder to obtain the probability feature of each edge. The specific formula for the terminal to generate the node feature vector of the node and the probability feature of the edge based on the decoder can be:

[0086]

[0087] Where p(x|z) is the probability distribution of x given the underlying distribution parameter z; It is the node feature vector and edge probability feature output by the decoder.

[0088] In this example, a high-dimensional representation of the latent space is used to generate probabilistic features for each node and edge of the NAND graph. This not only relies on local information but also leverages global information learned by the model, thereby optimizing the NAND graph generation process and avoiding the problem of local optimal solutions. By employing a variational autoencoder to optimize the NAND graph for multi-objective design, the limitations of traditional methods in multi-objective optimization are overcome, achieving an automated NAND graph generation process.

[0089] In an exemplary embodiment, the specific implementation process of step 104 may include:

[0090] For each target node, each associated node is connected to the target node through the edge of the target node to generate a sub-NAND graph; multiple sub-NAND graphs are combined to obtain the target NAND graph corresponding to the target circuit.

[0091] Specifically, for each target node, the terminal can connect each associated node to the target node through the edge of the target node. The terminal can combine the sub-graphs to obtain the target graph corresponding to the target circuit. Figure 3 As shown, Figure 3 It is a schematic diagram of the generation process of target and non-graph.

[0092] In an exemplary embodiment, the method for generating a NAND graph further includes:

[0093] By presetting a neural network model, a target node and associated nodes corresponding to the target node, a node feature vector of the target node is updated; and a graph feature matrix is ​​updated based on the updated node feature vector to obtain an updated graph feature matrix.

[0094] Among them, the preset neural network model can include a recurrent unit network and a graph neural network.

[0095] Specifically, the terminal can update the hidden state of the node through the recurrent unit network and update the node feature vector of the target node through the graph neural network. The terminal can update the graph feature matrix based on the updated node feature vector to obtain an updated graph feature matrix. The terminal can predict the type of the next node of the target node based on the updated node feature vector of the target node and the updated node feature vector.

[0096] In this embodiment, by updating the node feature vector and graph feature matrix, it is ensured that when predicting the next node, the node feature vector and graph feature matrix are both the latest features, and the type of the next node to be generated is predicted based on this, thereby improving the accuracy of predicting the node type.

[0097] In an exemplary embodiment, Figure 4 As shown, a method for generating a non-graph is also provided, which specifically includes the following steps:

[0098] Step 401: Acquire sample logic data of a sample logic circuit based on a logic synthesis tool.

[0099] The sample logic circuit may be a Boolean logic expression or an existing logic circuit, and the sample logic data may reflect each node in the sample logic circuit and the logical relationship (edge) between the nodes.

[0100] Specifically, the terminal may obtain sample logic data of the sample logic circuit through a logic synthesis tool. For example, the sample logic data may be G=(V,E), where V is a set of nodes in the sample logic circuit and E is a set of edges.

[0101] Step 402: Convert the sample logic data through the encoder in the initial neural network model to obtain a sample graph feature matrix corresponding to the sample logic circuit, and embed the sample graph feature matrix to obtain a sample embedded feature vector.

[0102] The sample graph feature matrix may be an adjacency matrix of the graph or a feature representation of the graph.

[0103] Specifically, the terminal can convert the sample logic through the encoder in the initial neural network model to obtain the sample graph feature matrix corresponding to the sample logic circuit. The terminal can use the graph neural network to embed the sample graph feature matrix to obtain the sample embedding feature vector.

[0104] Step 403: For each sample node, the sample embedded feature vector is extracted by the encoder in the initial neural network model to obtain the sample node feature vector; the sample conditional probability distribution function corresponding to the sample node feature vector is calculated based on the preset probability distribution formula; the sample potential distribution parameters are sampled from the sample conditional probability distribution function, and the sample potential distribution parameters are decoded by the decoder in the initial neural network model to obtain the sample node feature vector of each sample node, the sample graph feature matrix of the sample logic circuit, and the sample edge probability features of the edges between each sample node.

[0105] The initial neural network model may be a variational autoencoder, the variational autoencoder may include an encoder and a decoder, and the encoder may include a multi-layer neural network.

[0106] Specifically, the terminal can use the sample embedding feature vector as input to the encoder in the initial neural network model. The multi-layer neural network extracts features from the sample embedding feature vector to obtain the sample node feature vector. The terminal can calculate the sample conditional probability distribution function corresponding to the sample node feature vector using a preset probability distribution formula.

[0107] The terminal can randomly obtain a sample embedding feature vector and the corresponding mean and variance functions of the sample embedding feature vector from the conditional probability distribution. The terminal can use a preset reparameterization formula to determine the sample's latent distribution parameters. The terminal can decode the sample's latent distribution parameters using the decoder in the initial neural network model to obtain a sample node feature vector for each sample node. The terminal concatenates the sample node feature vectors of each sample node to obtain a sample graph feature matrix. The terminal also decodes the sample graph feature matrix using the decoder to obtain the sample edge probability features between each sample node.

[0108] Step 404: For the sample target node, based on the sample graph feature matrix, the sample node feature vector of the previous node of the sample target node, and the initial neural network model, obtain the sample node prediction type of the sample target node; based on the sample node prediction type and the sample edge probability characteristics, determine the sample associated node with the sample target node; based on multiple sample target nodes and the sample target node and each sample associated node, generate a sample target and non-graph corresponding to the sample logic circuit.

[0109] Specifically, the NAND graph may include M nodes. The terminal may determine the mth node as the sample target node, where 1<m≤M. For the mth node, based on the graph feature matrix, the sample node feature vector of the m-1th node, and the initial neural network model, the sample node prediction type of the sample target node is obtained. Based on the sample node prediction type and the sample edge probability feature, the terminal may determine nodes with a connection relationship with the sample target node if the sample edge probability feature between the sample nodes is greater than or equal to a probability threshold, and determine the nodes with a connection relationship with the sample target node as sample associated nodes of the sample target node.

[0110] For each sample target node, each sample associated node is connected to the sample target node through the edge of the target node to generate a sample sub-and non-graph; multiple sample sub-and non-graphs are combined to obtain the sample target and non-graph corresponding to the sample target circuit.

[0111] In addition, if Figure 5 As shown, Figure 5 This is a schematic diagram of the variational autoencoder structure. The terminal inputs the relevant data of the sample logic circuit into the variational autoencoder's encoder to obtain the conditional probability distribution function corresponding to the sample node feature vector. The terminal then uses the sampling module in the variational autoencoder to sample the sample's latent distribution parameters from the conditional probability distribution function. The terminal then uses the variational autoencoder's decoder to obtain the node probability features of each sample node and the sample edge probability features. Based on these node probability features and the sample edge probability features, the terminal generates a sample target and non-graph.

[0112] In this embodiment, an initial neural network model is trained using known logic circuits, enabling adaptive generation of NAND graphs based on the training data. The model can be trained on large-scale circuit data, learning how to automatically generate the most appropriate NAND graph for different design requirements, reducing reliance on manual input. The neural network model encodes and decodes the NAND graph, learning a latent space representation in the process. This allows the generation of NAND graphs that meet design constraints, improving generation efficiency, reducing manual intervention, and enhancing adaptability to large-scale designs.

[0113] In an exemplary embodiment, the specific implementation process of "calculating the sample conditional probability distribution function corresponding to the sample node feature vector based on the preset probability distribution formula" in step 403 includes:

[0114] A preset distribution type is set for the feature vector of the sample node, and a first conditional probability distribution function of the potential distribution parameter corresponding to the feature vector of the sample node is determined based on the preset distribution type; a sample conditional probability distribution function is obtained based on the dependency relationship between the sample node and the predecessor node of the sample node, and the first conditional probability distribution function.

[0115] Among them, the sample conditional probability distribution function can characterize the target distribution type corresponding to non-graph data.

[0116] Specifically, the terminal may set a preset distribution type that the sample node feature vector obeys, and the terminal may determine a first conditional probability distribution function of a potential distribution parameter corresponding to the sample node feature vector based on the preset distribution type. The specific expression of the first conditional probability distribution function may be:

[0117]

[0118] In the NAND graph, the potential distribution of each node can be represented by its dependent nodes through conditional independence based on the directed acyclic graph property of the NAND graph. The terminal can obtain the sample conditional probability distribution function based on the dependency relationship between the sample node and the predecessor node of the sample node and the first conditional probability distribution function. The specific expression of the sample conditional probability distribution function can be:

[0119]

[0120] Among them, i is the target node, j is the predecessor node of the target node, and p(i) is the predecessor node function.

[0121] In an exemplary embodiment, the method for generating a NAND graph further includes:

[0122] Perform circuit simulation on the sample target and the non-graph to obtain functional test results; test the performance of the sample target and the non-graph to obtain performance test results; compare the functional test results and the performance test results with the target performance requirements to obtain comparison results, and optimize the parameters of the initial neural network model based on the comparison results to obtain a preset neural network model.

[0123] The target performance requirements are related to the properties of the sample logic circuit. Functional test results can reflect the functional indicators of the sample target and non-graph, including logical correctness and timing. Performance test results can also reflect the performance indicators of the sample target and non-graph, including latency, power consumption, area, etc.

[0124] Specifically, the terminal can obtain attribute information of a sample logic circuit through a logic synthesis tool. This attribute information may include structural information, functional information, and physical characteristics of the sample logic circuit. The attribute information may also include the number of inputs / outputs, logic levels, area delay, testability, and other characteristics. The terminal may determine the attribute information as label data and determine target performance requirements based on the label data. The terminal may perform circuit simulation on the sample target and non-graph to obtain functional test results; the terminal may test the performance indicators of the sample target and non-graph to obtain performance test results. The terminal may compare the functional test results with the target performance requirements to obtain a first comparison result; and the terminal may compare the performance test results with the target performance requirements to obtain a second comparison result. The first comparison result may reflect the functional accuracy of the sample target and non-graph. The second result may reflect the difference between the performance of the sample target and non-graph and the actual performance of the non-graph. The terminal may determine the first and second comparison results as comparison results. The terminal may use the comparison results as a loss function to optimize the parameters of the initial neural network model to obtain a preset neural network.

[0125] This embodiment introduces the concept of multi-objective optimization. By training an initial neural network model, multiple design objectives (such as power consumption, latency, and area) can be simultaneously considered when generating the N / A graph. These objectives are balanced by optimizing the loss function, achieving multi-objective optimization. By learning from a large amount of historical data, the graph generation process can be automatically adjusted and optimized, reducing manual intervention and automatically adapting to different design requirements, alleviating the burden on engineers. This deep learning-based graph generation technology can automatically adjust the generation strategy to meet different circuit design requirements, providing greater flexibility and adaptability.

[0126] In one embodiment, this implementation improves the flexibility and scalability of the generation process. As the training dataset expands, the model can handle more complex and large-scale circuit design tasks, better addressing design requirements of varying scale and complexity. By combining traditional NAND graph generation techniques (such as AIG generation methods based on logic synthesis) with deep learning graph generation technology, a hybrid optimization solution is proposed. This innovative approach combines the strengths of traditional methods in accuracy and verifiability with the automation, scalability, and flexibility of deep learning methods.

[0127] It should be understood that, although the various steps in the flowcharts involved in the various embodiments described above are displayed in sequence according to the instructions of the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least a portion of the steps in the flowcharts involved in the various embodiments described above can include multiple steps or multiple stages, and these steps or stages are not necessarily executed and completed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a portion of steps or stages in other steps.

[0128] Based on the same inventive concept, embodiments of the present application also provide a device for generating a NAND graph for implementing the aforementioned method for generating a NAND graph. The solution provided by this device is similar to the solution described in the aforementioned method. Therefore, the specific limitations of one or more embodiments of the device for generating a NAND graph provided below can be found in the aforementioned limitations of the method for generating a NAND graph, and will not be repeated here.

[0129] In an exemplary embodiment, Figure 6 As shown, a device 60 for generating a NOT graph is provided, comprising: a first generating module 61, a processing module 62, a determining module 63, and a second generating module 64, wherein:

[0130] A first generating module 61 is configured to generate a conditional probability distribution function corresponding to the non-graph data based on the non-graph data of the target circuit, the target distribution type obeyed by the non-graph data, and a preset neural network model, wherein the non-graph data reflects multiple nodes in the target non-graph and edges connecting the nodes;

[0131] Processing module 62, configured to sample potential distribution parameters from the conditional probability distribution function, decode the potential distribution parameters, and obtain node feature vectors of each node, graph feature matrices of target and non-graphs, and probability features of edges between nodes;

[0132] Determination module 63 is used to obtain the node prediction type of the target node based on the graph feature matrix, the node feature vector of the previous node of the target node, and the preset neural network model; and determine the associated nodes of the target node based on the node prediction type and the edge probability characteristics of the target node;

[0133] The second generating module 64 is configured to generate a target NAND graph corresponding to the target circuit based on each target node and each associated node corresponding to the target node.

[0134] In one embodiment, the second generation module 64 is also used to test the target and the non-graph to obtain a test result; if the test result does not meet the preset performance requirements, the step of sampling potential distribution parameters from the conditional probability distribution function is continued until the target and the non-graph meet the preset performance requirements.

[0135] In one embodiment, the processing module 62 is specifically configured to decode the potential distribution parameters through a decoder to obtain a node feature vector of each node, and concatenate the feature vectors of each node to obtain a graph feature matrix of the target and non-graph;

[0136] The graph feature matrix is ​​decoded by the decoder to obtain the probability features of each edge.

[0137] In one embodiment, the second generating module 64 is specifically configured to connect each associated node to the target node through an edge of the target node to generate a sub-NAND graph;

[0138] Combine multiple sub-NAND graphs to obtain the target NAND graph corresponding to the target circuit.

[0139] In one embodiment, the processing module 62 is further used to update the node feature vector of the target node through a preset neural network model, the target node and the associated nodes corresponding to the target node; and update the graph feature matrix based on the updated node feature vector to obtain an updated graph feature matrix.

[0140] In one embodiment, the device for generating a NAND graph further includes: an acquisition module for acquiring sample logic data of a sample logic circuit based on a logic synthesis tool;

[0141] A conversion module is used to convert the sample logic data through the encoder in the initial neural network model to obtain a sample graph feature matrix corresponding to the sample logic circuit, and embed the sample graph feature matrix to obtain a sample embedding feature vector;

[0142] The encoding module is used to extract the sample embedded feature vector for each sample node through the encoder in the initial neural network model to obtain the sample node feature vector; calculate the sample conditional probability distribution function corresponding to the sample node feature vector based on a preset probability distribution formula; sample the sample potential distribution parameters from the sample conditional probability distribution function, and decode the sample potential distribution parameters through the decoder in the initial neural network model to obtain the sample node feature vector of each sample node, the sample graph feature matrix of the sample logic circuit, and the sample edge probability features of the edges between each sample node;

[0143] The generation module is used to obtain the sample node prediction type of the sample target node based on the sample graph feature matrix, the sample node feature vector of the previous node of the sample target node and the initial neural network model; determine the sample associated node with the sample target node based on the sample node prediction type and the sample edge probability feature; and generate a sample target and non-graph corresponding to the sample logic circuit based on multiple sample target nodes and the sample target node and each sample associated node.

[0144] In one embodiment, the encoding module is specifically used to set a preset distribution type that the sample node feature vector obeys, and determine the first conditional probability distribution function of the potential distribution parameter corresponding to the sample node feature vector based on the preset distribution type; based on the dependency relationship between the sample node and the predecessor node of the sample node, and the first conditional probability distribution function, a sample conditional probability distribution function is obtained, and the sample conditional probability distribution function represents the target distribution type corresponding to the non-graph data.

[0145] In one embodiment, the test module is used to perform circuit simulation on the sample target and the non-graph to obtain a functional test result; perform performance testing on the sample target and the non-graph to obtain a performance test result;

[0146] The functional test results and the performance test results are compared with the target performance requirements to obtain a comparison result. The parameters of the initial neural network model are optimized based on the comparison result to obtain a preset neural network model. The target performance requirement is related to the attribute information of the sample logic circuit.

[0147] Each module in the above-mentioned device for generating a non-AND graph can be implemented in whole or in part by software, hardware, or a combination thereof. Each of the above-mentioned modules can be embedded in or independent of a processor in a computer device in the form of hardware, or can be stored in a memory in the computer device in the form of software, so that the processor can call and execute the corresponding operations of each of the above modules.

[0148] In an exemplary embodiment, a computer device is provided. The computer device may be a terminal, and its internal structure diagram may be as shown in FIG. Figure 7As shown. The computer device includes a processor, memory, an input / output interface, a communication interface, a display unit, and an input device. The processor, memory, and input / output interface are connected via a system bus, and the communication interface, display unit, and input device are connected to the system bus via the input / output interface. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and computer program in the non-volatile storage medium. The input / output interface of the computer device is used to exchange information between the processor and external devices. The communication interface of the computer device is used to communicate with external terminals via wired or wireless means, and the wireless means can be implemented via Wi-Fi, a mobile cellular network, near field communication (NFC), or other technologies. When executed by the processor, the computer program implements a method for generating a non-graph. The display unit of the computer device is used to form a visually visible image, and can be a display screen, a projection device, or a virtual reality imaging device. The display screen can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device can be a touch layer covering the display screen, or a button, trackball or touchpad set on the computer device casing, or an external keyboard, touchpad or mouse.

[0149] Those skilled in the art will understand that Figure 7 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.

[0150] In an exemplary embodiment, a computer device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and when the processor executes the computer program, the following steps are implemented:

[0151] Based on the target circuit's NAND graph data, the target distribution type obeyed by the NAND graph data, and a preset neural network model, a conditional probability distribution function corresponding to the NAND graph data is generated, where the NAND graph data reflects multiple nodes in the target NAND graph and edges connecting the nodes;

[0152] Sample the potential distribution parameters from the conditional probability distribution function, decode the potential distribution parameters, and obtain the node feature vector of each node, the graph feature matrix of the target and non-graph, and the probability features of the edges between each node;

[0153] For the target node, the node prediction type of the target node is obtained based on the graph feature matrix, the node feature vector of the previous node of the target node, and the preset neural network model; based on the node prediction type and the edge probability characteristics of the target node, the associated nodes of the target node are determined;

[0154] Based on each target node and each associated node corresponding to the target node, a target and NOT graph corresponding to the target circuit is generated.

[0155] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0156] The target and the non-graph are tested to obtain a test result; if the test result does not meet the preset performance requirement, the step of sampling the potential distribution parameters from the conditional probability distribution function is continued until the target and the non-graph meet the preset performance requirement.

[0157] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0158] The decoder decodes the potential distribution parameters to obtain the node feature vector of each node, and concatenates the feature vectors of each node to obtain the graph feature matrix of the target and non-graph;

[0159] The graph feature matrix is ​​decoded by the decoder to obtain the probability features of each edge.

[0160] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0161] For each target node, connect each associated node to the target node through the edge of the target node to generate a sub-NAND graph;

[0162] Combine multiple sub-NAND graphs to obtain the target NAND graph corresponding to the target circuit.

[0163] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0164] By presetting a neural network model, a target node and associated nodes corresponding to the target node, a node feature vector of the target node is updated; and a graph feature matrix is ​​updated based on the updated node feature vector to obtain an updated graph feature matrix.

[0165] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0166] Acquiring sample logic data of a sample logic circuit based on a logic synthesis tool;

[0167] The sample logic data is converted by the encoder in the initial neural network model to obtain a sample graph feature matrix corresponding to the sample logic circuit, and the sample graph feature matrix is ​​embedded to obtain a sample embedding feature vector;

[0168] For each sample node, the sample embedded feature vector is extracted through the encoder in the initial neural network model to obtain the sample node feature vector; the sample conditional probability distribution function corresponding to the sample node feature vector is calculated based on the preset probability distribution formula; the sample potential distribution parameters are sampled from the sample conditional probability distribution function, and the sample potential distribution parameters are decoded through the decoder in the initial neural network model to obtain the sample node feature vector of each sample node, the sample graph feature matrix of the sample logic circuit, and the sample edge probability features of the edges between each sample node;

[0169] For the sample target node, the sample node prediction type of the sample target node is obtained based on the sample graph feature matrix, the sample node feature vector of the previous node of the sample target node and the initial neural network model; based on the sample node prediction type and the sample edge probability characteristics, the sample associated node with the sample target node is determined; based on multiple sample target nodes and the sample target node and each sample associated node, the sample target and non-graph corresponding to the sample logic circuit is generated.

[0170] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0171] A preset distribution type is set for the feature vector of the sample node, and a first conditional probability distribution function of the potential distribution parameter corresponding to the feature vector of the sample node is determined based on the preset distribution type; a sample conditional probability distribution function is obtained based on the dependency relationship between the sample node and the predecessor node of the sample node, and the first conditional probability distribution function, and the sample conditional probability distribution function represents the target distribution type corresponding to the non-graph data.

[0172] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0173] Conduct circuit simulation on the sample target and non-graph to obtain functional test results; conduct performance test on the sample target and non-graph to obtain performance test results;

[0174] The functional test results and the performance test results are compared with the target performance requirements to obtain a comparison result. The parameters of the initial neural network model are optimized based on the comparison result to obtain a preset neural network model. The target performance requirement is related to the attribute information of the sample logic circuit.

[0175] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the following steps are implemented:

[0176] Based on the target circuit's NAND graph data, the target distribution type obeyed by the NAND graph data, and a preset neural network model, a conditional probability distribution function corresponding to the NAND graph data is generated, where the NAND graph data reflects multiple nodes in the target NAND graph and edges connecting the nodes;

[0177] Sample the potential distribution parameters from the conditional probability distribution function, decode the potential distribution parameters, and obtain the node feature vector of each node, the graph feature matrix of the target and non-graph, and the probability features of the edges between each node;

[0178] For the target node, the node prediction type of the target node is obtained based on the graph feature matrix, the node feature vector of the previous node of the target node, and the preset neural network model; based on the node prediction type and the edge probability characteristics of the target node, the associated nodes of the target node are determined;

[0179] Based on each target node and each associated node corresponding to the target node, a target and NOT graph corresponding to the target circuit is generated.

[0180] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented:

[0181] The target and the non-graph are tested to obtain a test result; if the test result does not meet the preset performance requirement, the step of sampling the potential distribution parameters from the conditional probability distribution function is continued until the target and the non-graph meet the preset performance requirement.

[0182] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented:

[0183] The decoder decodes the potential distribution parameters to obtain the node feature vector of each node, and concatenates the feature vectors of each node to obtain the graph feature matrix of the target and non-graph;

[0184] The graph feature matrix is ​​decoded by the decoder to obtain the probability features of each edge.

[0185] In one embodiment, generating a target NAND graph corresponding to a target circuit based on each target node and each associated node corresponding to the target node includes:

[0186] For each target node, connect each associated node to the target node through the edge of the target node to generate a sub-NAND graph;

[0187] Combine multiple sub-NAND graphs to obtain the target NAND graph corresponding to the target circuit.

[0188] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented:

[0189] By presetting a neural network model, a target node and associated nodes corresponding to the target node, a node feature vector of the target node is updated; and a graph feature matrix is ​​updated based on the updated node feature vector to obtain an updated graph feature matrix.

[0190] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented:

[0191] Acquiring sample logic data of a sample logic circuit based on a logic synthesis tool;

[0192] The sample logic data is converted by the encoder in the initial neural network model to obtain a sample graph feature matrix corresponding to the sample logic circuit, and the sample graph feature matrix is ​​embedded to obtain a sample embedding feature vector;

[0193] For each sample node, the sample embedded feature vector is extracted through the encoder in the initial neural network model to obtain the sample node feature vector; the sample conditional probability distribution function corresponding to the sample node feature vector is calculated based on the preset probability distribution formula; the sample potential distribution parameters are sampled from the sample conditional probability distribution function, and the sample potential distribution parameters are decoded through the decoder in the initial neural network model to obtain the sample node feature vector of each sample node, the sample graph feature matrix of the sample logic circuit, and the sample edge probability features of the edges between each sample node;

[0194] For the sample target node, the sample node prediction type of the sample target node is obtained based on the sample graph feature matrix, the sample node feature vector of the previous node of the sample target node and the initial neural network model; based on the sample node prediction type and the sample edge probability characteristics, the sample associated node with the sample target node is determined; based on multiple sample target nodes and the sample target node and each sample associated node, the sample target and non-graph corresponding to the sample logic circuit is generated.

[0195] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented:

[0196] A preset distribution type is set for the feature vector of the sample node, and a first conditional probability distribution function of the potential distribution parameter corresponding to the feature vector of the sample node is determined based on the preset distribution type; a sample conditional probability distribution function is obtained based on the dependency relationship between the sample node and the predecessor node of the sample node, and the first conditional probability distribution function, and the sample conditional probability distribution function represents the target distribution type corresponding to the non-graph data.

[0197] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented:

[0198] Conduct circuit simulation on the sample target and non-graph to obtain functional test results; conduct performance test on the sample target and non-graph to obtain performance test results;

[0199] The functional test results and the performance test results are compared with the target performance requirements to obtain a comparison result. The parameters of the initial neural network model are optimized based on the comparison result to obtain a preset neural network model. The target performance requirement is related to the attribute information of the sample logic circuit.

[0200] In one embodiment, a computer program product is provided, comprising a computer program, which, when executed by a processor, implements the following steps:

[0201] Based on the target circuit's NAND graph data, the target distribution type obeyed by the NAND graph data, and a preset neural network model, a conditional probability distribution function corresponding to the NAND graph data is generated, where the NAND graph data reflects multiple nodes in the target NAND graph and edges connecting the nodes;

[0202] Sample the potential distribution parameters from the conditional probability distribution function, decode the potential distribution parameters, and obtain the node feature vector of each node, the graph feature matrix of the target and non-graph, and the probability features of the edges between each node;

[0203] For the target node, the node prediction type of the target node is obtained based on the graph feature matrix, the node feature vector of the previous node of the target node, and the preset neural network model; based on the node prediction type and the edge probability characteristics of the target node, the associated nodes of the target node are determined;

[0204] Based on each target node and each associated node corresponding to the target node, a target and NOT graph corresponding to the target circuit is generated.

[0205] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented:

[0206] The target and the non-graph are tested to obtain a test result; if the test result does not meet the preset performance requirement, the step of sampling the potential distribution parameters from the conditional probability distribution function is continued until the target and the non-graph meet the preset performance requirement.

[0207] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented:

[0208] The decoder decodes the potential distribution parameters to obtain the node feature vector of each node, and concatenates the feature vectors of each node to obtain the graph feature matrix of the target and non-graph;

[0209] The graph feature matrix is ​​decoded by the decoder to obtain the probability features of each edge.

[0210] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented:

[0211] For each target node, connect each associated node to the target node through the edge of the target node to generate a sub-NAND graph;

[0212] Combine multiple sub-NAND graphs to obtain the target NAND graph corresponding to the target circuit.

[0213] In one embodiment, the method further comprises:

[0214] By presetting a neural network model, a target node and associated nodes corresponding to the target node, a node feature vector of the target node is updated; and a graph feature matrix is ​​updated based on the updated node feature vector to obtain an updated graph feature matrix.

[0215] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented:

[0216] Acquiring sample logic data of a sample logic circuit based on a logic synthesis tool;

[0217] The sample logic data is converted by the encoder in the initial neural network model to obtain a sample graph feature matrix corresponding to the sample logic circuit, and the sample graph feature matrix is ​​embedded to obtain a sample embedding feature vector;

[0218] For each sample node, the sample embedded feature vector is extracted through the encoder in the initial neural network model to obtain the sample node feature vector; the sample conditional probability distribution function corresponding to the sample node feature vector is calculated based on the preset probability distribution formula; the sample potential distribution parameters are sampled from the sample conditional probability distribution function, and the sample potential distribution parameters are decoded through the decoder in the initial neural network model to obtain the sample node feature vector of each sample node, the sample graph feature matrix of the sample logic circuit, and the sample edge probability features of the edges between each sample node;

[0219] For the sample target node, the sample node prediction type of the sample target node is obtained based on the sample graph feature matrix, the sample node feature vector of the previous node of the sample target node and the initial neural network model; based on the sample node prediction type and the sample edge probability characteristics, the sample associated node with the sample target node is determined; based on multiple sample target nodes and the sample target node and each sample associated node, the sample target and non-graph corresponding to the sample logic circuit is generated.

[0220] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented:

[0221] A preset distribution type is set for the feature vector of the sample node, and a first conditional probability distribution function of the potential distribution parameter corresponding to the feature vector of the sample node is determined based on the preset distribution type; a sample conditional probability distribution function is obtained based on the dependency relationship between the sample node and the predecessor node of the sample node, and the first conditional probability distribution function, and the sample conditional probability distribution function represents the target distribution type corresponding to the non-graph data.

[0222] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented:

[0223] Conduct circuit simulation on the sample target and non-graph to obtain functional test results; conduct performance test on the sample target and non-graph to obtain performance test results;

[0224] The functional test results and the performance test results are compared with the target performance requirements to obtain a comparison result. The parameters of the initial neural network model are optimized based on the comparison result to obtain a preset neural network model. The target performance requirement is related to the attribute information of the sample logic circuit.

[0225] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant regulations.

[0226] Those skilled in the art will understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. In particular, any reference to memory, database, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The databases involved in the various embodiments provided herein may include at least one of a relational database and a non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the various embodiments provided herein may be, but are not limited to, general-purpose processors, central processing units (CPUs), graphics processing units (GPUs), digital signal processors (DSPs), programmable logic devices (PLDs), quantum computing-based data processing logic devices, artificial intelligence (AI) processors, and the like.

[0227] The technical features of the above embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0228] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present application shall be determined by the appended claims.

Claims

1. A method for generating a non-AND graph, characterized in that: The method comprises: Based on the NAND graph data of the target circuit, the target distribution type obeyed by the NAND graph data and a preset neural network model, a conditional probability distribution function corresponding to the NAND graph data is generated, wherein the NAND graph data reflects multiple nodes in the target NAND graph and edges connecting the nodes; Sampling potential distribution parameters from the conditional probability distribution function, decoding the potential distribution parameters, and obtaining a node feature vector of each node, a graph feature matrix of the target and non-graph, and a probability feature of edges between each node; For a target node, based on the graph feature matrix, the node feature vector of the previous node of the target node and a preset neural network model, a node prediction type of the target node is obtained; based on the node prediction type and the edge probability feature of the target node, an associated node of the target node is determined; Based on each of the target nodes and each of the associated nodes corresponding to the target nodes, a target AND-NOT graph corresponding to the target circuit is generated.

2. The method according to claim 1, characterized in that The method further comprises: The target and the non-graph are tested to obtain a test result; if the test result does not meet the preset performance requirement, the step of sampling potential distribution parameters from the conditional probability distribution function is continued until the target and the non-graph meet the preset performance requirement.

3. The method according to claim 1, characterized in that: The preset neural network model at least includes a decoder; the decoding process of the potential distribution parameters is performed to obtain the node feature vector of each node, the graph feature matrix of the target and non-graph, and the edge probability feature of each edge; including: Decoding the potential distribution parameters through the decoder to obtain a node feature vector of each node, and concatenating the feature vectors of each node to obtain a graph feature matrix of the target and non-graph; The graph feature matrix is ​​decoded by the decoder to obtain the probability feature of each edge.

4. The method according to claim 1, characterized in that: The generating a target AND-NOT graph corresponding to the target circuit based on each of the target nodes and each of the associated nodes corresponding to the target nodes comprises: For each target node, each of the associated nodes is connected to the target node through the edge of the target node to generate a sub-NAND graph; Combine a plurality of the sub-NAND graphs to obtain a target NAND graph corresponding to the target circuit.

5. The method according to claim 1, characterized in that The method further comprises: By presetting a neural network model, the target node and each associated node corresponding to the target node, the node feature vector of the target node is updated to obtain an updated node feature vector; based on the updated node feature vector, the graph feature matrix is ​​updated to obtain an updated graph feature matrix.

6. The method according to claim 1, characterized in that The method further comprises: Acquiring sample logic data of a sample logic circuit based on a logic synthesis tool; The sample logic data is converted by an encoder in the initial neural network model to obtain a sample graph feature matrix corresponding to the sample logic circuit, and the sample graph feature matrix is ​​embedded to obtain a sample embedding feature vector; For each sample node, the sample embedded feature vector is extracted by the encoder to obtain a sample node feature vector; a sample conditional probability distribution function corresponding to the sample node feature vector is calculated based on a preset probability distribution formula; sample potential distribution parameters are sampled from the sample conditional probability distribution function, and the sample potential distribution parameters are decoded by the decoder in the initial neural network model to obtain a sample node feature vector of each sample node, a sample graph feature matrix of the sample logic circuit, and a sample edge probability feature of the edge between each sample node; For a sample target node, based on the sample graph feature matrix, the sample node feature vector of the previous node of the sample target node and the initial neural network model, the sample node prediction type of the sample target node is obtained; based on the sample node prediction type and the sample edge probability characteristics, the sample associated node with the sample target node is determined; based on a plurality of the sample target nodes and the sample target node and each of the sample associated nodes, a sample target and non-graph corresponding to the sample logic circuit is generated.

7. The method according to claim 6, characterized in that The calculating the sample conditional probability distribution function corresponding to the sample node feature vector based on a preset probability distribution formula includes: A preset distribution type is set for the feature vector of the sample node to obey, and a first conditional probability distribution function of a potential distribution parameter corresponding to the feature vector of the sample node is determined based on the preset distribution type; a sample conditional probability distribution function is obtained based on a dependency relationship between the sample node and a predecessor node of the sample node, and the first conditional probability distribution function, wherein the sample conditional probability distribution function represents a target distribution type corresponding to non-graph data.

8. The method according to claim 6, characterized in that The method further comprises: Conducting circuit simulation on the sample target and the non-graph to obtain a functional test result; conducting performance testing on the sample target and the non-graph to obtain a performance test result; The functional test results and the performance test results are compared with the target performance requirements to obtain a comparison result, and the parameters of the initial neural network model are optimized based on the comparison result to obtain a preset neural network model, wherein the target performance requirements are related to the attribute information of the sample logic circuit.

9. A device for generating a non-AND graph, characterized in that: The device comprises: A first generating module is used to generate a conditional probability distribution function corresponding to the non-AND graph data based on the non-AND graph data of the target circuit, the target distribution type obeyed by the non-AND graph data and a preset neural network model, wherein the non-AND graph data reflects multiple nodes in the target non-AND graph and edges connecting the nodes; A processing module, used for sampling potential distribution parameters from the conditional probability distribution function, decoding the potential distribution parameters, and obtaining a node feature vector of each node, a graph feature matrix of the target and non-graph, and a probability feature of an edge between each node; A determination module, for obtaining, for a target node, a node prediction type of the target node based on the graph feature matrix, a node feature vector of a previous node of the target node, and a preset neural network model; and determining an associated node of the target node based on the node prediction type and an edge probability feature of the target node; The second generating module is used to generate a target AND-NOT graph corresponding to the target circuit based on each of the target nodes and each of the associated nodes corresponding to the target nodes.

10. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 8 are implemented.

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