NAND graph generation method, device, and computer equipment

Abstract

The present application relates to a method, apparatus, and computer device for generating a NAND graph. The method includes: generating a conditional probability distribution function corresponding to the NAND graph data based on the NAND graph data of the target circuit and the type of target distribution that the NAND graph data follows; sampling latent distribution parameters from the conditional probability distribution function, and performing decoding processing on the latent distribution parameters to obtain the node feature vectors of each node, the graph feature matrix of the target NAND graph, and the probability features of the edges between each node; for a target node, obtaining the node prediction type of the target node based on the graph feature matrix, the node feature vector of the previous node of the target node, and a preset neural network model; determining the associated nodes of the target node based on the node prediction type and the edge probability features of the target node; and generating the target NAND graph corresponding to the target circuit based on each target node and each associated node corresponding to the target node. Using this method can improve the efficiency of NAND graph generation.

Description

Technical Field

[0001] This application relates to the field of electronic technologies, and particularly to a method, apparatus, and computer device for generating a NAND graph. Background Art

[0002] In electronic design automation, a NAND graph is a graphical structure used to represent Boolean functions, which represents a Boolean logic function as a combination of a set of AND gates and NOT gates. NAND graphs are widely used in digital circuit design for optimization. It can effectively represent logical relationships and is easy to perform graphical operations, such as simplifying logic, performing equivalence checking, optimizing circuit area and delay, etc.

[0003] In traditional technologies, the method for generating a NAND graph usually includes a logical optimization method based on Boolean algebra simplification method or Karnaugh map. However, the logical optimization method based on Boolean algebra simplification method or Karnaugh map usually requires a large amount of calculation and manual adjustment. Especially when dealing with complex or large-scale circuits, the process of generating and optimizing the NAND graph is inefficient. Summary of the Invention

[0004] Based on this, it is necessary to provide a method, apparatus, computer device, readable storage medium, and program product for generating a NAND graph that can improve the efficiency of generating the NAND graph in view of the above technical problems.

[0005] In a first aspect, this application provides a method for generating a NAND graph, including:

[0006] Based on the NAND graph data of the target circuit, the target distribution type that the NAND graph data follows, and a preset neural network model, generate a conditional probability distribution function corresponding to the NAND graph data, where the NAND graph data reflects multiple nodes in the target NAND graph and the edges connecting the nodes;

[0007] Sample potential distribution parameters from the conditional probability distribution function, and perform decoding processing on the potential distribution parameters to obtain node feature vectors of each node, a graph feature matrix of the target NAND graph, and probability features of the edges between the nodes;

[0008] For a target node, based on the graph feature matrix, the node feature vector of the previous node of the target node, and a preset neural network model, obtain the node prediction type of the target node; based on the node prediction type and the edge probability feature of the target node, determine the associated node of the target node;

[0009] Based on each of the target nodes and each of the associated nodes corresponding to the target nodes, generate the target NAND graph corresponding to the target circuit.

[0010] In one of the embodiments, the method further includes:

[0011] Test the target AND-NOT graph to obtain a test result; if the test result does not meet the preset performance requirements, continue to execute the step of sampling potential distribution parameters from the conditional probability distribution function until the target AND-NOT graph meets the preset performance requirements.

[0012] In one embodiment, the preset neural network model includes at least a decoder; the decoding process of the potential distribution parameters to obtain the node feature vectors of each node, the graph feature matrix of the target AND-NOT graph, and the edge probability features of each edge includes:

[0013] Decode the potential distribution parameters through the decoder to obtain the node feature vectors of each node, and splice the feature vectors of each node to obtain the graph feature matrix of the target AND-NOT graph;

[0014] Decode the graph feature matrix through the decoder to obtain the probability features of each edge.

[0015] In one embodiment, generating the target AND-NOT graph corresponding to the target circuit based on each of the target nodes and each of the associated nodes corresponding to the target nodes includes:

[0016] For each target node, connect each of the associated nodes to the target node through the edges of the target node to generate a sub AND-NOT graph;

[0017] Combine multiple sub AND-NOT graphs to obtain the target AND-NOT graph corresponding to the target circuit.

[0018] In one embodiment, the method further includes:

[0019] Update the node feature vectors of the target nodes through a preset neural network model, the target nodes, and each of the associated nodes corresponding to the target nodes; update the graph feature matrix based on the updated node feature vectors to obtain an updated graph feature matrix.

[0020] In one embodiment, the method further includes:

[0021] Obtain sample logic data of a sample logic circuit based on a logic synthesis tool;

[0022] Convert the sample logic data through an encoder in an initial neural network model to obtain a sample graph feature matrix corresponding to the sample logic circuit, and embed the sample graph feature matrix to obtain a sample embedding feature vector;

[0023] For each sample node, the encoder is used to extract the sample embedding feature vector to obtain the sample node feature vector; based on a preset probability distribution formula, the sample conditional probability distribution function corresponding to the sample node feature vector is calculated; sample latent distribution parameters are sampled from the sample conditional probability distribution function, and the decoder in the initial neural network model is used to perform decoding processing on the sample latent distribution parameters to obtain the sample node feature vectors of each sample node, the sample graph feature matrix of the sample logic circuit, and the sample edge probability features of the edges between each sample node;

[0024] For the sample target node, based on the sample graph feature matrix, the sample node feature vector of the previous node of the sample target node, and the initial neural network model, the sample node prediction type of the sample target node is obtained; based on the sample node prediction type and the sample edge probability features, the sample associated nodes corresponding to the sample target node are determined; based on a plurality of the sample target nodes and the sample target nodes and each of the sample associated nodes, a sample target NAND graph corresponding to the sample logic circuit is generated.

[0025] In one embodiment, the calculating the sample conditional probability distribution function corresponding to the sample node feature vector based on a preset probability distribution formula includes:

[0026] Set the preset distribution type that the sample node feature vector follows, and determine the first conditional probability distribution function of the latent distribution parameters corresponding to the sample node feature vector based on the preset distribution type; based on the dependency relationship between the sample node and the previous node of the sample node, and the first conditional probability distribution function, obtain the sample conditional probability distribution function, and the sample conditional probability distribution function represents the target distribution type corresponding to the NAND graph data.

[0027] In one embodiment, the method further includes:

[0028] Perform circuit simulation on the sample target NAND graph to obtain a function detection result; perform performance testing on the performance of the sample target NAND graph to obtain a performance test result;

[0029] Compare the function detection result and the performance test result with the target performance requirements to obtain a comparison result, and optimize the parameters of the initial neural network model based on the comparison result to obtain a preset neural network model, and the target performance requirements are related to the attribute information of the sample logic circuit.

[0030] In a second aspect, the present application further provides a NAND graph generation device, including:

[0031] A first generation module, configured to generate a conditional probability distribution function corresponding to the NAND graph data based on the NAND graph data of the target circuit, the target distribution type to which the NAND graph data conforms, and a preset neural network model, where the NAND graph data reflects multiple nodes in the target NAND graph and the edges connecting the nodes;

[0032] A processing module, configured to sample latent distribution parameters from the conditional probability distribution function, perform decoding processing on the latent distribution parameters to obtain node feature vectors of each node, a graph feature matrix of the target NAND graph, and probability features of the edges between the nodes;

[0033] A determination module, configured to, for a target node, obtain a node prediction type of the target node based on the graph feature matrix, the node feature vector of the previous node of the target node, and a preset neural network model; and determine an associated node of the target node based on the node prediction type and the edge probability feature of the target node;

[0034] A second generation module, configured to generate a target NAND graph corresponding to the target circuit based on each of the target nodes and each of the associated nodes corresponding to the target nodes.

[0035] In a third aspect, the present application further provides a computer device, including a memory and a processor, where the memory stores a computer program, and when the processor executes the computer program, the following steps are implemented:

[0036] Generate a conditional probability distribution function corresponding to the NAND graph data based on the NAND graph data of the target circuit, the target distribution type to which the NAND graph data conforms, and a preset neural network model, where the NAND graph data reflects multiple nodes in the target NAND graph and the edges connecting the nodes;

[0037] Sample latent distribution parameters from the conditional probability distribution function, perform decoding processing on the latent distribution parameters to obtain node feature vectors of each node, a graph feature matrix of the target NAND graph, and probability features of the edges between the nodes;

[0038] For a target node, obtain a node prediction type of the target node based on the graph feature matrix, the node feature vector of the previous node of the target node, and a preset neural network model; and determine an associated node of the target node based on the node prediction type and the edge probability feature of the target node;

[0039] Generate a target NAND graph corresponding to the target circuit based on each of the target nodes and each of the associated nodes corresponding to the target nodes.

[0040] Fourthly, the present application also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the following steps are implemented:

[0041] Based on the NAND graph data of the target circuit, the target distribution type to which the NAND graph data conforms, and a preset neural network model, generate a conditional probability distribution function corresponding to the NAND graph data, where the NAND graph data reflects multiple nodes in the target NAND graph and the edges connecting the nodes;

[0042] Sample latent distribution parameters from the conditional probability distribution function, and perform decoding processing on the latent distribution parameters to obtain the node feature vectors of each node, the graph feature matrix of the target NAND graph, and the probability features of the edges between the nodes;

[0043] For a target node, based on the graph feature matrix, the node feature vector of the previous node of the target node, and a preset neural network model, obtain the predicted node type of the target node; based on the predicted node type and the edge probability feature of the target node, determine the associated node of the target node;

[0044] Based on each of the target nodes and each of the associated nodes corresponding to the target nodes, generate a target NAND graph corresponding to the target circuit.

[0045] Fifthly, the present application also provides a computer program product, including a computer program. When the computer program is executed by a processor, the following steps are implemented:

[0046] Based on the NAND graph data of the target circuit, the target distribution type to which the NAND graph data conforms, and a preset neural network model, generate a conditional probability distribution function corresponding to the NAND graph data, where the NAND graph data reflects multiple nodes in the target NAND graph and the edges connecting the nodes;

[0047] Sample latent distribution parameters from the conditional probability distribution function, and perform decoding processing on the latent distribution parameters to obtain the node feature vectors of each node, the graph feature matrix of the target NAND graph, and the probability features of the edges between the nodes;

[0048] For a target node, based on the graph feature matrix, the node feature vector of the previous node of the target node, and a preset neural network model, obtain the predicted node type of the target node; based on the predicted node type and the edge probability feature of the target node, determine the associated node of the target node;

[0049] Based on each of the target nodes and each of the associated nodes corresponding to the target nodes, generate a target NAND graph corresponding to the target circuit.

[0050] The above NAND graph generation method, device, and computer device sample potential distribution parameters from the conditional probability distribution function corresponding to the NAND graph data, perform decoding processing on the potential distribution parameters to obtain the node feature vectors of each node, the graph feature matrix of the target NAND graph, and the probability features of the edges between each node, and can effectively learn the logical constraints in the circuit; for the target node, based on the graph feature matrix, the node feature vector of the previous node of the target node, and a preset neural network model, obtain the node prediction type of the target node; based on the node prediction type and the edge probability features of the target node, determine the associated nodes of the target node, and generate the target NAND graph corresponding to the target circuit based on each target node and each associated node corresponding to the target node. The target NAND graph satisfies logical consistency and realizability, ensuring that an effective circuit can be generated, and realizing the automatic generation of the NAND graph, improving the efficiency of NAND graph generation. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following will briefly introduce the drawings required for describing the embodiments of the present application or related technologies. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other related drawings can also be obtained based on these drawings.

[0052] Figure 1 It is a schematic flowchart of the NAND graph generation method in an embodiment;

[0053] Figure 2 It is a schematic structural diagram of the NAND graph in an embodiment;

[0054] Figure 3 It is a schematic diagram of the generation process of the target NAND graph in an embodiment;

[0055] Figure 4 It is a schematic flowchart of the NAND graph generation method in an embodiment;

[0056] Figure 5 It is a schematic structural diagram of the variational autoencoder in an embodiment;

[0057] Figure 6 It is a structural block diagram of the NAND graph generation device in an embodiment;

[0058] Figure 7 It is an internal structural diagram of a computer device in an embodiment. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0059] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0060] In an exemplary embodiment, as Figure 1 shown, a method for generating a NAND graph is provided. In this embodiment, the method is exemplified by being applied to a terminal. It can be understood that the method can also be applied to a server, and can also be applied to a system including a terminal and a server, and is implemented through the interaction between the terminal and the server. In this embodiment, the method includes the following steps:

[0061] Step 101: Generate a conditional probability distribution function corresponding to the NAND graph data based on the NAND graph data of the target circuit, the target distribution type that the NAND graph data follows, and a preset neural network model.

[0062] Among them, the target circuit can be a logic circuit that needs to be designed, optimized or analyzed in a specific application scenario. The NAND graph data can be generated by the NAND graph to be generated or the NAND graph to be optimized. The NAND graph to be generated can be determined by a Boolean logic expression, truth value information or other forms. The NAND graph can be a logic network that only includes two-input AND gates and NOT gates. The NAND graph data can reflect multiple nodes in the target NAND graph and the edges connecting the nodes. The target distribution type can be the probability distribution type that it follows. The target distribution type can be determined according to the actual distribution of the NAND graph during the training process. The edge can be a directed edge. The preset neural network model includes at least an encoder.

[0063] Specifically, the terminal can obtain the initial NAND graph data corresponding to the target circuit or the NAND graph to be optimized. If the target circuit is the NAND graph to be optimized, the terminal can extract the NAND graph data from the NAND graph to be optimized through a logic synthesis tool. The terminal can use the encoder to convert the NAND graph data into a graph feature matrix, embed the graph feature matrix using the encoder to obtain an embedded feature vector, and determine the embedded feature vector as the NAND graph data. For example, the logic synthesis tool can be the ABC (A Berkeley Cross-Platform) tool. The expression corresponding to the NAND graph data can be G = (V, E), where V is the set of nodes and E is the set of edges.

[0064] The terminal can determine the type of the target distribution that the NAND graph data follows according to the type of the NAND graph data. The terminal can use an encoder to calculate the conditional probability distribution function corresponding to the NAND graph data based on the NAND graph data and the type of the target distribution that the NAND graph data follows. For example, the terminal can extract features from the NAND graph data through a neural network to obtain an initial node feature vector, and calculate the conditional probability distribution function based on the initial node feature vector and the type of the target distribution that the NAND graph data follows. The terminal can determine the mean function and variance function corresponding to each node of the NAND graph data based on the conditional probability distribution function.

[0065] Step 102: Sample latent distribution parameters from the conditional probability distribution function, and perform decoding processing on the latent distribution parameters to obtain the node feature vectors of each node, the graph feature matrix of the target NAND graph, and the probability features of the edges between each node.

[0066] Among them, the target NAND graph can be the NAND graph to be output.

[0067] Specifically, the terminal can randomly obtain the NAND graph data, the mean function, and the variance function corresponding to the NAND graph data from the conditional probability distribution. The terminal can use a preset reparameterization formula to determine the latent distribution parameters. The specific preset reparameterization formula can be:

[0068]

[0069] where z is the latent distribution parameter; x is the NAND graph data, μ(x) is the mean function; σ(x) is the variance function, is the standard normal distribution.

[0070] The terminal can perform decoding processing on the latent distribution parameters through a decoder in the preset neural network to obtain the node feature vectors of each node. Concatenate the node feature vectors of each node to obtain the graph feature matrix corresponding to the target NAND graph. The terminal performs decoding processing on the graph feature matrix through the decoder to obtain the probability features of the edges between each node.

[0071] Step 103: For the target node, based on the graph feature matrix, the node feature vector of the previous node of the target node, and the preset neural network model, obtain the node prediction type of the target node; based on the node prediction type and the edge probability feature of the target node, determine the associated nodes of the target node.

[0072] Specifically, the NAND graph may include N nodes. The terminal may determine a starting node and determine the i-th node as the target node, where 1 < i ≤ N. For the i-th node, based on the graph feature matrix, the node feature vector of the (i - 1)-th node, and a preset neural network model, the predicted node type of the target node is obtained. The terminal may, based on the predicted node type and the edge probability feature, determine the nodes whose edge probability feature between nodes is greater than or equal to the probability threshold as the nodes having a connection relationship with the target node, and determine the nodes having a connection relationship with the target node as the associated nodes of the target node.

[0073] Step 104: Generate a target NAND graph corresponding to the target circuit based on each target node and each associated node corresponding to the target node.

[0074] Specifically, for each target node, connect each associated node to the target node through the edge of the target node to generate a sub-NAND graph; combine multiple sub-NAND graphs to obtain the target NAND graph corresponding to the target circuit. As Figure 2 shown, Figure 2 is a schematic structural diagram of the NAND graph, where the black solid circle represents a NOT gate, the hollow circle represents an AND gate, and the arrow represents the logical relationship (edge) between each node.

[0075] The above method for generating a NAND graph samples potential distribution parameters from the conditional probability distribution function corresponding to the NAND graph data, decodes the potential distribution parameters to obtain the node feature vectors of each node, the graph feature matrix of the target NAND graph, and the probability features of the edges between each node, and can effectively learn the logical constraints in the circuit; for the target node, based on the graph feature matrix, the node feature vector of the previous node of the target node, and a preset neural network model, the predicted node type of the target node is obtained; based on the predicted node type and the edge probability feature of the target node, the associated nodes of the target node are determined, and based on each target node and each associated node corresponding to the target node, a target NAND graph corresponding to the target circuit is generated. The target NAND graph satisfies logical consistency and realizability, ensuring that it can be implemented as an effective circuit design. The automatic generation of the NAND graph is realized, and the efficiency of NAND graph generation is improved.

[0076] In an exemplary embodiment, the method for generating a NAND graph further includes:

[0077] Test the target NAND graph to obtain a test result; if the test result does not meet the preset performance requirements, continue to execute the step of sampling potential distribution parameters from the conditional probability distribution function until the target NAND graph meets the preset performance requirements.

[0078] Among them, the test results can reflect the functional and performance indicators of the target NAND graph. The functional indicators may include logical correctness, timing, etc., and the performance indicators may include latency, power consumption, area, etc. The indicators for testing the target NAND graph can be determined according to the requirements of the actual application scenario, and no specific limitations are made here. The preset performance requirements may include correct functionality and performance indicators within a range.

[0079] Specifically, the terminal can perform circuit simulation on the target NAND graph to verify the functional indicators of the target NAND graph and obtain a verification result; the terminal can test the performance indicators of the target NAND graph to obtain a performance indicator test result. The terminal can determine the verification result and / or the performance indicator test result as the test result.

[0080] The terminal can determine the preset performance requirements based on the performance requirements of the NAND graph. If the verification result is correct and the performance indicator test result is within the preset range of the performance indicators, the terminal determines that the test result meets the preset performance requirements and determines that the target NAND graph is the final required NAND graph. If there is an incorrect verification result and / or the performance indicator test result exceeds the range of the performance indicators, it is determined that at least one of the verification result and the performance indicator test result does not meet the preset performance requirements. The terminal can re-execute the step of sampling the latent distribution parameters from the conditional probability distribution function to obtain a second target NAND graph, and test the second target NAND graph to obtain a second test result. If the second test result meets the preset performance requirements, the second target NAND graph is determined as the final required NAND graph. If the second test result still does not meet the preset performance requirements, continue to re-execute the step of sampling the latent distribution parameters from the conditional probability distribution function, and so on, until the target NAND graph meets the preset performance requirements.

[0081] In this embodiment, by testing the target NAND graph, multi-objective optimization is introduced to ensure that the finally generated target NAND graph meets the performance requirements. If the target NAND graph does not meet the performance requirements, a new target NAND graph is obtained by re-sampling until the target NAND graph meets the performance requirements. This embodiment can effectively learn the logical constraints in the circuit design by adopting a generative model, and introduce a traditional logic synthesis detection method after the generated NAND graph, ensuring that the generated graph not only meets the logical correctness but also conforms to the implementation requirements of the circuit design.

[0082] In an exemplary embodiment, the specific implementation process of "decoding the latent distribution parameters to obtain the node feature vectors of each node, the graph feature matrix of the target NAND graph, and the edge probability features of each edge" in step 102 may include:

[0083] The decoder decodes the latent distribution parameters to obtain the node feature vectors of each node, and splices the feature vectors of each node to obtain the graph feature matrix of the target and non-graph; the decoder decodes the graph feature matrix to obtain the probability features of each edge.

[0084] Among them, the preset neural network model includes at least a decoder and an encoder. The encoder is a variational autoencoder, and the decoder is a multi-layer perceptron.

[0085] Specifically, the terminal can decode the latent distribution parameter z through the decoder to obtain the node feature vectors of each node. The terminal can splice the feature vectors of each node to obtain the graph feature matrix of the target and non-graph. The terminal can decode the decoder through the decoder to obtain the probability features of each edge. The specific formulas for the terminal to generate the node feature vectors of the nodes and the probability features of the edges based on the decoder can be:

[0086]

[0087] Among them, p(x|z) is the probability distribution of x under the condition of the given latent distribution parameter z; is the node feature vector and the probability feature of the edge output by the decoder.

[0088] In this embodiment, by the high-dimensional expression in the latent space, generating the probability features of each node and each edge of the non-graph not only depends on local information, but also uses the global information learned by the model, thereby optimizing the generation process of the non-graph and avoiding the problem of local optimal solutions. By using a variational autoencoder to optimize the non-graph of multi-objective design, the limitations of traditional methods in multi-objective optimization are solved. An automated non-graph generation process is realized.

[0089] In an exemplary embodiment, the specific implementation process of step 104 may include:

[0090] For each target node, connect each associated node to the target node through the edge of the target node to generate a sub non-graph; combine multiple sub non-graphs to obtain the target non-graph corresponding to the target circuit.

[0091] Specifically, for each target node, the terminal can connect each associated node and the target node through the edge of the target node. The terminal can combine the sub non-graphs to obtain the target non-graph corresponding to the target circuit. As Figure 3 shown, Figure 3 is a schematic diagram of the generation process of the target non-graph.

[0092] In an exemplary embodiment, the non-graph generation method further includes:

[0093] Update the node feature vector of the target node through a preset neural network model, the target node, and each associated node corresponding to the target node; update the graph feature matrix based on the updated node feature vector to obtain an updated graph feature matrix.

[0094] Among them, the preset neural network model may include a recurrent unit network and a graph neural network.

[0095] Specifically, the terminal can update the hidden state of the node through the recurrent unit network and update the node feature vector of the target node through the graph neural network. The terminal can update the graph feature matrix based on the updated node feature vector to obtain an updated graph feature matrix. The terminal predicts the type of the next node of the target node, and can predict the node type of the next node according to the updated node feature vector of the target node and the updated node feature vector.

[0096] In this embodiment, by updating the node feature vector and the graph feature matrix, it is ensured that when predicting the next node, both the node feature vector and the graph feature matrix are the latest features, and the type of the next node generated is predicted based on this, improving the accuracy of predicting the node type.

[0097] In an exemplary embodiment, as Figure 4 shown, a method for generating a NAND graph is further provided, which specifically includes the following steps:

[0098] Step 401: Obtain sample logic data of the sample logic circuit based on a logic synthesis tool.

[0099] Among them, the sample logic circuit may be a Boolean logic expression or an existing logic circuit. The sample logic data can reflect each node in the sample logic circuit and the logical relationship (edge) between each node.

[0100] Specifically, the terminal can obtain the sample logic data of the sample logic circuit through a logic synthesis tool. For example, the sample logic data may be G=(V,E), where V is the set of each node in the sample logic circuit and E is the edge set.

[0101] Step 402: Convert the sample logic data through the encoder in the initial neural network model to obtain a sample graph feature matrix corresponding to the sample logic circuit, and embed the sample graph feature matrix to obtain a sample embedded feature vector.

[0102] Among them, the sample graph feature matrix may be an adjacency matrix of the graph or a feature representation of the graph.

[0103] Specifically, the terminal can convert the sample logic through the encoder in the initial neural network model to obtain the sample graph feature matrix corresponding to the sample logic circuit. The terminal can use a graph neural network to perform embedding representation on the sample graph feature matrix to obtain the sample embedding feature vector.

[0104] Step 403: For each sample node, extract the sample node feature vector from the sample embedding feature vector through the encoder in the initial neural network model; calculate the sample conditional probability distribution function corresponding to the sample node feature vector based on the preset probability distribution formula; sample the sample latent distribution parameters from the sample conditional probability distribution function, and perform decoding processing on the sample latent distribution parameters through the decoder in the initial neural network model to obtain the sample node feature vectors of each sample node, the sample graph feature matrix of the sample logic circuit, and the sample edge probability features of the edges between each sample node.

[0105] Among them, the initial neural network model can be a variational autoencoder. The variational autoencoder can include an encoder and a decoder, and the encoder can include a multi-layer neural network.

[0106] Specifically, the terminal can use the sample embedding feature vector as input and input it into the encoder in the initial neural network model. The multi-layer neural network is used to extract features from the sample embedding feature vector to obtain the sample node feature vector. The terminal can calculate the sample conditional probability distribution function corresponding to the sample node feature vector through the preset probability distribution formula.

[0107] The terminal can randomly obtain the sample embedding feature vector and the corresponding mean function and variance function of the sample embedding feature vector from the conditional probability distribution. The terminal can use the preset reparameterization formula to determine the sample latent distribution parameters. The terminal can perform decoding processing on the sample latent distribution parameters through the decoder in the initial neural network model to obtain the sample node feature vectors of each sample node. The terminal splices the sample node feature vectors of each sample node to obtain the sample graph feature matrix. The terminal performs decoding processing on the sample graph feature matrix through the decoder to obtain the sample edge probability features between each sample node.

[0108] Step 404: For the sample target node, based on the sample graph feature matrix, the sample node feature vector of the previous node of the sample target node, and the initial neural network model, obtain the sample node prediction type of the sample target node; based on the sample node prediction type and the sample edge probability features, determine the sample associated nodes of the sample target node; based on multiple sample target nodes and the sample target nodes and their respective sample associated nodes, generate the sample target and non-graph corresponding to the sample logic circuit.

[0109] Specifically, the NAND graph may include M nodes. The terminal may determine the m-th node as the sample target node, where 1 < m ≤ M. For the m-th node, based on the graph feature matrix, the sample node feature vector of the (m - 1)-th node, and the initial neural network model, the sample node prediction type of the sample target node is obtained. The terminal may, based on the sample node prediction type and the sample edge probability feature, determine the nodes whose sample edge probability feature between the sample nodes is greater than or equal to the probability threshold as the nodes having a connection relationship with the sample target node, and determine the nodes having a connection relationship with the sample target node as the sample associated nodes of the sample target node.

[0110] For each sample target node, connect each sample associated node to the sample target node through the edge of the target node to generate a sample sub-NAND graph; combine multiple sample sub-NAND graphs to obtain the sample target NAND graph corresponding to the sample target circuit.

[0111] In addition, as Figure 5 shown, Figure 5 is a schematic structural diagram of a variational autoencoder. The terminal inputs the relevant data of the sample logic circuit into the encoder of the variational autoencoder to obtain the conditional probability distribution function corresponding to the sample node feature vector. The terminal may, through the sampling module in the variational autoencoder, sample the sample latent distribution parameters from the conditional probability distribution function. The terminal may, through the decoder in the variational autoencoder, obtain the node probability feature and the sample edge probability feature of each sample node. The terminal may generate the sample target NAND graph based on the node probability feature and the sample edge probability feature.

[0112] In this embodiment, by training the initial neural network model with known logic circuits, a NAND graph can be adaptively generated according to the training data. The model can be trained on large-scale circuit data to learn how to automatically generate the most suitable NAND graph from different design requirements, reducing the dependence on manual input. Use the neural network model to encode and decode the NAND graph, and learn the latent space representation during this process, so that a NAND graph that meets the design constraints can be generated, thereby improving the generation efficiency, reducing manual intervention, and enhancing the adaptability to large-scale designs.

[0113] In an exemplary embodiment, the specific implementation process of "calculating the sample conditional probability distribution function corresponding to the sample node feature vector based on the preset probability distribution formula" in step 403 includes:

[0114] Set the preset distribution type followed by the sample node feature vector, and determine the first conditional probability distribution function of the latent distribution parameters corresponding to the sample node feature vector based on the preset distribution type; based on the dependence relationship between the sample node and the predecessor node of the sample node, and the first conditional probability distribution function, obtain the sample conditional probability distribution function.

[0115] Among them, the sample conditional probability distribution function can characterize the target distribution type corresponding to the non-graph data.

[0116] Specifically, the terminal can set the preset distribution type that the sample node feature vector follows. The terminal can determine the first conditional probability distribution function of the potential distribution parameters corresponding to the sample node feature vector based on the preset distribution type. The specific expression of the first conditional probability distribution function can be:

[0117]

[0118] In the NAND graph, the potential distribution of each node can be represented by its dependent nodes through conditional independence according to the directed acyclic graph property of the NAND graph. The terminal can obtain the sample conditional probability distribution function based on the dependency relationship between the sample node and the predecessor node of the sample node, and the first conditional probability distribution function. The specific expression of the sample conditional probability distribution function can be:

[0119]

[0120] Among them, i is the target node, j is the predecessor node of the target node, and p(i) is the predecessor node function.

[0121] In an exemplary embodiment, the method for generating a NAND graph further includes:

[0122] Performing circuit simulation on the sample target NAND graph to obtain a function detection result; testing the performance of the sample target NAND graph to obtain a performance test result; comparing the function detection result and the performance test result with the target performance requirements to obtain a comparison result, and optimizing the parameters of the initial neural network model based on the comparison result to obtain a preset neural network model.

[0123] Among them, the target performance requirements are related to the attribute information of the sample logic circuit. The function detection result can reflect the function indicators of the sample target NAND graph, and the function indicators can include logical correctness and timing, etc. The performance test result can reflect the performance indicators of the sample target NAND graph, and the performance indicators can include delay, power consumption, area, etc.

[0124] Specifically, the terminal can obtain the attribute information of the sample logic circuit through a logic synthesis tool. The attribute information can include the structural information, functional information, and physical characteristics of the sample logic circuit. The attribute information can also include: the number of inputs / outputs, logical hierarchy, area delay, testability, etc. The terminal can determine the attribute information as label data, and the terminal can determine the target performance requirements based on the label data. The terminal can perform circuit simulation on the sample target and non-graph to obtain a function detection result; the terminal can test the performance indicators of the sample target and non-graph to obtain a performance test result. The terminal can compare the function detection result with the target performance requirements to obtain a first comparison result; the terminal can compare the performance test result with the target performance requirements to obtain a second comparison result. The first comparison result can reflect the accuracy of the function of the sample target and non-graph. The second result can reflect the difference between the performance of the sample target and non-graph and the actual performance of the non-graph. The terminal can determine the first comparison result and the second comparison result as the comparison result. The terminal can use the comparison result as a loss function to optimize the parameters of the initial neural network model to obtain a preset neural network.

[0125] In this embodiment, the idea of multi-objective optimization is introduced. By training the initial neural network model, when generating the non-graph, multiple design objectives (such as power consumption, delay, area, etc.) can be considered simultaneously, and these objectives can be balanced by optimizing the loss function, so as to achieve the optimization of multiple objectives. Through learning a large amount of historical data, the generation process of the graph can be automatically adjusted and optimized, thereby reducing manual intervention and being able to automatically adapt to different design requirements, reducing the burden on engineers. The graph generation technology based on deep learning can automatically adjust the generation strategy when facing different circuit design requirements, with higher flexibility and adaptability.

[0126] In one embodiment, this embodiment improves the flexibility and scalability of the generation process. As the training data set expands, the model can handle more complex and large-scale circuit design tasks and better cope with design requirements of different scales and complexities. By combining traditional non-graph generation technologies (such as the AIG generation method based on logic synthesis) with deep learning graph generation technologies, a hybrid optimization solution is proposed. This innovative method can combine the advantages of both: the strong capabilities of traditional methods in terms of accuracy and verifiability, and the advantages of deep learning methods in terms of automation, large-scale generation, and flexibility.

[0127] It should be understood that although the steps in the flowcharts involved in the above-described embodiments are sequentially shown in the direction of the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps has no strict order limit, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-described embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be executed alternately or in turn with at least a part of other steps or steps or stages in other steps.

[0128] Based on the same inventive concept, an embodiment of the present application further provides a NAND graph generation device for implementing the NAND graph generation method described above. The solution provided by this device to solve the problem is similar to the solution described in the above method. Therefore, the specific limitations in one or more embodiments of the NAND graph generation device provided below can refer to the limitations on the NAND graph generation method in the above text, and will not be repeated here.

[0129] In an exemplary embodiment, as Figure 6 shown, a NAND graph generation device 60 is provided, including: a first generation module 61, a processing module 62, a determination module 63, and a second generation module 64, where:

[0130] The first generation module 61 is configured to generate a conditional probability distribution function corresponding to the NAND graph data based on the NAND graph data of the target circuit, the target distribution type that the NAND graph data obeys, and a preset neural network model. The NAND graph data reflects multiple nodes in the target NAND graph and the edges connecting the nodes.

[0131] The processing module 62 is configured to sample latent distribution parameters from the conditional probability distribution function, perform decoding processing on the latent distribution parameters to obtain node feature vectors of each node, a graph feature matrix of the target NAND graph, and probability features of the edges between the nodes.

[0132] The determination module 63 is configured to, for a target node, obtain a node prediction type of the target node based on the graph feature matrix, the node feature vector of the previous node of the target node, and a preset neural network model; determine an associated node of the target node based on the node prediction type and the edge probability feature of the target node.

[0133] The second generation module 64 is configured to generate a target NAND graph corresponding to the target circuit based on each target node and the associated nodes corresponding to the target nodes.

[0134] In one embodiment, the second generation module 64 is further configured to test the target AND-NOT graph, and obtain a test result; if the test result does not meet the preset performance requirements, continue to execute the step of sampling the latent distribution parameters from the conditional probability distribution function until the target AND-NOT graph meets the preset performance requirements.

[0135] In one embodiment, the processing module 62 is specifically configured to decode the latent distribution parameters through a decoder to obtain the node feature vectors of each node, and splice the feature vectors of each node to obtain the graph feature matrix of the target AND-NOT graph;

[0136] Decode the graph feature matrix through a decoder to obtain the probability features of each edge.

[0137] In one embodiment, the second generation module 64 is specifically configured to, for each target node, connect each associated node to the target node through the edge of the target node to generate a sub AND-NOT graph;

[0138] Combine multiple sub AND-NOT graphs to obtain the target AND-NOT graph corresponding to the target circuit.

[0139] In one embodiment, the processing module 62 is further configured to update the node feature vector of the target node through a preset neural network model, the target node, and each associated node corresponding to the target node; update the graph feature matrix based on the updated node feature vector to obtain an updated graph feature matrix.

[0140] In one embodiment, the AND-NOT graph generation device further includes: an acquisition module, configured to acquire sample logic data of a sample logic circuit based on a logic synthesis tool;

[0141] A conversion module, configured to convert the sample logic data through an encoder in an initial neural network model to obtain a sample graph feature matrix corresponding to the sample logic circuit, and embed the sample graph feature matrix to obtain a sample embedding feature vector;

[0142] An encoding module, configured to, for each sample node, extract the sample embedding feature vector through an encoder in the initial neural network model to obtain a sample node feature vector; calculate a sample conditional probability distribution function corresponding to the sample node feature vector based on a preset probability distribution formula; sample sample latent distribution parameters from the sample conditional probability distribution function, and perform decoding processing on the sample latent distribution parameters through a decoder in the initial neural network model to obtain the sample node feature vectors of each sample node, the sample graph feature matrix of the sample logic circuit, and the sample edge probability features of the edges between each sample node;

[0143] A generation module, configured to obtain a predicted sample node type of a sample target node based on a sample graph feature matrix, a sample node feature vector of the previous node of the sample target node, and an initial neural network model; determine a sample associated node of the sample target node based on the predicted sample node type and sample edge probability features; generate a sample target NAND graph corresponding to the sample logic circuit based on a plurality of sample target nodes and the sample target nodes and their respective sample associated nodes.

[0144] In one embodiment, the encoding module is specifically configured to set a preset distribution type followed by the sample node feature vector, and determine a first conditional probability distribution function of potential distribution parameters corresponding to the sample node feature vector based on the preset distribution type; obtain a sample conditional probability distribution function based on the dependency relationship between the sample node and the previous node of the sample node and the first conditional probability distribution function, where the sample conditional probability distribution function represents a target distribution type corresponding to NAND graph data.

[0145] In one embodiment, the testing module is configured to perform circuit simulation on the sample target NAND graph to obtain a function detection result; test the performance of the sample target NAND graph to obtain a performance test result;

[0146] Compare the function detection result and the performance test result with the target performance requirements to obtain a comparison result, and optimize the parameters of the initial neural network model based on the comparison result to obtain a preset neural network model, where the target performance requirements are related to the attribute information of the sample logic circuit.

[0147] Each module in the above NAND graph generation device can be implemented in whole or in part by software, hardware, and their combination. The above modules can be embedded in the processor of the computer device in hardware form or be independent of it, or be stored in the memory of the computer device in software form, so that the processor can call and execute the operations corresponding to the above respective modules.

[0148] In an exemplary embodiment, a computer device is provided. The computer device can be a terminal, and its internal structure diagram can be as Figure 7As shown in the figure. The computer device includes a processor, a memory, an input / output interface, a communication interface, a display unit, and an input device. Among them, the processor, the memory, and the input / output interface are connected through a system bus, and the communication interface, the display unit, and the input device are connected to the system bus through the input / output interface. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The input / output interface of the computer device is used to exchange information between the processor and external devices. The communication interface of the computer device is used to communicate with external terminals in a wired or wireless manner, and the wireless manner can be implemented through WIFI, a mobile cellular network, near field communication (NFC), or other technologies. When the computer program is executed by the processor, it implements a method for generating a NAND graph. The display unit of the computer device is used to form a visually visible picture, which can be a display screen, a projection device, or a virtual reality imaging device. The display screen can be a liquid crystal display screen or an electronic ink display screen. The input device of the computer device can be a touch layer covered on the display screen, or a button, a trackball, or a touchpad provided on the computer device housing, or an external keyboard, touchpad, or mouse, etc.

[0149] Those skilled in the art can understand that Figure 7 the structure shown in the figure is only a block diagram of some structures related to the solution of this application, and does not constitute a limitation on the computer device to which the solution of this application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine some components, or have a different component layout.

[0150] In an exemplary embodiment, a computer device is provided, including a memory and a processor. A computer program is stored in the memory. When the processor executes the computer program, the following steps are implemented:

[0151] Based on the NAND graph data of the target circuit, the target distribution type to which the NAND graph data belongs, and a preset neural network model, generate a conditional probability distribution function corresponding to the NAND graph data. The NAND graph data reflects multiple nodes in the target NAND graph and the edges connecting the nodes;

[0152] Sample potential distribution parameters from the conditional probability distribution function, and perform decoding processing on the potential distribution parameters to obtain the node feature vectors of each node, the graph feature matrix of the target NAND graph, and the probability features of the edges between the nodes;

[0153] For a target node, based on the graph feature matrix, the node feature vector of the previous node of the target node, and a preset neural network model, obtain the predicted node type of the target node; based on the predicted node type and the edge probability feature of the target node, determine the associated nodes of the target node.

[0154] Based on each target node and the associated nodes corresponding to the target node, generate a target NAND graph corresponding to the target circuit.

[0155] In one embodiment, when the processor executes the computer program, the following steps are further implemented:

[0156] Test the target NAND graph to obtain a test result; if the test result does not meet the preset performance requirements, continue to execute the step of sampling the latent distribution parameters from the conditional probability distribution function until the target NAND graph meets the preset performance requirements.

[0157] In one embodiment, when the processor executes the computer program, the following steps are further implemented:

[0158] Decode the latent distribution parameters through a decoder to obtain the node feature vectors of each node, and splice the feature vectors of each node to obtain the graph feature matrix of the target NAND graph.

[0159] Decode the graph feature matrix through a decoder to obtain the probability features of each edge.

[0160] In one embodiment, when the processor executes the computer program, the following steps are further implemented:

[0161] For each target node, connect the associated nodes to the target node through the edges of the target node to generate a sub-NAND graph.

[0162] Combine multiple sub-NAND graphs to obtain the target NAND graph corresponding to the target circuit.

[0163] In one embodiment, when the processor executes the computer program, the following steps are further implemented:

[0164] Update the node feature vector of the target node through the preset neural network model, the target node, and the associated nodes corresponding to the target node; update the graph feature matrix based on the updated node feature vector to obtain the updated graph feature matrix.

[0165] In one embodiment, when the processor executes the computer program, the following steps are further implemented:

[0166] Obtain the sample logic data of the sample logic circuit based on a logic synthesis tool.

[0167] Convert the sample logic data through the encoder in the initial neural network model to obtain the sample graph feature matrix corresponding to the sample logic circuit, and embed the sample graph feature matrix to obtain the sample embedded feature vector;

[0168] For each sample node, extract the sample embedded feature vector through the encoder in the initial neural network model to obtain the sample node feature vector; calculate the sample conditional probability distribution function corresponding to the sample node feature vector based on the preset probability distribution formula; sample the sample latent distribution parameters from the sample conditional probability distribution function, and perform decoding processing on the sample latent distribution parameters through the decoder in the initial neural network model to obtain the sample node feature vectors of each sample node, the sample graph feature matrix of the sample logic circuit, and the sample edge probability features of the edges between each sample node;

[0169] For the sample target node, based on the sample graph feature matrix, the sample node feature vector of the previous node of the sample target node, and the initial neural network model, obtain the sample node prediction type of the sample target node; based on the sample node prediction type and the sample edge probability features, determine the sample associated nodes of the sample target node; based on multiple sample target nodes and the sample target nodes and their respective sample associated nodes, generate the sample target and non-graph corresponding to the sample logic circuit.

[0170] In one embodiment, when the processor executes the computer program, the following steps are further implemented:

[0171] Set the preset distribution type followed by the sample node feature vector, and determine the first conditional probability distribution function of the latent distribution parameters corresponding to the sample node feature vector based on the preset distribution type; based on the dependency relationship between the sample node and the previous node of the sample node, and the first conditional probability distribution function, obtain the sample conditional probability distribution function, and the sample conditional probability distribution function represents the target distribution type corresponding to the AND-NOT graph data.

[0172] In one embodiment, when the processor executes the computer program, the following steps are further implemented:

[0173] Perform circuit simulation on the sample target and non-graph to obtain the function detection result; test the performance of the sample target and non-graph to obtain the performance test result;

[0174] Compare the function detection result and the performance test result with the target performance requirements to obtain a comparison result, and optimize the parameters of the initial neural network model based on the comparison result to obtain the preset neural network model, where the target performance requirements are related to the attribute information of the sample logic circuit.

[0175] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the following steps are implemented:

[0176] Generate a conditional probability distribution function corresponding to the NAND graph data based on the NAND graph data of the target circuit, the type of target distribution that the NAND graph data follows, and a preset neural network model, where the NAND graph data reflects multiple nodes in the target NAND graph and the edges connecting the nodes to each other.

[0177] Sample latent distribution parameters from the conditional probability distribution function, and perform decoding processing on the latent distribution parameters to obtain the node feature vectors of each node, the graph feature matrix of the target NAND graph, and the probability features of the edges between the nodes.

[0178] For a target node, based on the graph feature matrix, the node feature vector of the previous node of the target node, and a preset neural network model, obtain the predicted node type of the target node; based on the predicted node type and the edge probability feature of the target node, determine the associated nodes of the target node.

[0179] Generate a target NAND graph corresponding to the target circuit based on each target node and the associated nodes corresponding to the target node.

[0180] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented:

[0181] Test the target NAND graph to obtain a test result; if the test result does not meet the preset performance requirements, continue to execute the step of sampling latent distribution parameters from the conditional probability distribution function until the target NAND graph meets the preset performance requirements.

[0182] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented:

[0183] Decode the latent distribution parameters through a decoder to obtain the node feature vectors of each node, and splice the feature vectors of each node to obtain the graph feature matrix of the target NAND graph;

[0184] Decode the graph feature matrix through a decoder to obtain the probability features of each edge.

[0185] In one of the embodiments, generating a target NAND graph corresponding to the target circuit based on each target node and the associated nodes corresponding to the target node includes:

[0186] For each target node, connect the associated nodes to the target node through the edges of the target node to generate a sub-NAND graph;

[0187] Combine multiple sub-NAND graphs to obtain a target NAND graph corresponding to the target circuit.

[0188] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented:

[0189] Update the node feature vector of the target node through a preset neural network model, the target node, and each associated node corresponding to the target node; update the graph feature matrix based on the updated node feature vector to obtain an updated graph feature matrix.

[0190] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented:

[0191] Obtain the sample logic data of the sample logic circuit based on a logic synthesis tool;

[0192] Convert the sample logic data through an encoder in the initial neural network model to obtain a sample graph feature matrix corresponding to the sample logic circuit, and embed the sample graph feature matrix to obtain a sample embedded feature vector;

[0193] For each sample node, extract the sample embedded feature vector through an encoder in the initial neural network model to obtain a sample node feature vector; calculate the sample conditional probability distribution function corresponding to the sample node feature vector based on a preset probability distribution formula; sample sample latent distribution parameters from the sample conditional probability distribution function, and perform decoding processing on the sample latent distribution parameters through a decoder in the initial neural network model to obtain the sample node feature vectors of each sample node, the sample graph feature matrix of the sample logic circuit, and the sample edge probability features of the edges between each sample node;

[0194] For the sample target node, based on the sample graph feature matrix, the sample node feature vector of the previous node of the sample target node, and the initial neural network model, obtain the sample node prediction type of the sample target node; based on the sample node prediction type and the sample edge probability features, determine the sample associated nodes of the sample target node; based on multiple sample target nodes and the sample target nodes and their respective sample associated nodes, generate a sample target and non-graph corresponding to the sample logic circuit.

[0195] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented:

[0196] Set the preset distribution type followed by the sample node feature vector, and determine the first conditional probability distribution function of the latent distribution parameters corresponding to the sample node feature vector based on the preset distribution type; based on the dependency relationship between the sample node and the previous node of the sample node, and the first conditional probability distribution function, obtain the sample conditional probability distribution function, and the sample conditional probability distribution function represents the target distribution type corresponding to the non-graph data.

[0197] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented:

[0198] Perform circuit simulation on the sample target and the non-diagram to obtain the functional detection result; test the performance of the sample target and the non-diagram to obtain the performance test result;

[0199] Compare the functional detection result and the performance test result with the target performance requirement to obtain a comparison result, and optimize the parameters of the initial neural network model based on the comparison result to obtain a preset neural network model, where the target performance requirement is related to the attribute information of the sample logic circuit.

[0200] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the following steps:

[0201] Based on the NAND diagram data of the target circuit, the target distribution type that the NAND diagram data follows, and the preset neural network model, generate a conditional probability distribution function corresponding to the NAND diagram data, where the NAND diagram data reflects multiple nodes in the target NAND diagram and the edges connecting the nodes;

[0202] Sample potential distribution parameters from the conditional probability distribution function, and perform decoding processing on the potential distribution parameters to obtain the node feature vectors of each node, the graph feature matrix of the target NAND diagram, and the probability features of the edges between the nodes;

[0203] For a target node, based on the graph feature matrix, the node feature vector of the previous node of the target node, and the preset neural network model, obtain the node prediction type of the target node; based on the node prediction type and the edge probability feature of the target node, determine the associated node of the target node;

[0204] Based on each target node and the associated nodes corresponding to the target node, generate the target NAND diagram corresponding to the target circuit.

[0205] In one embodiment, when the computer program is executed by the processor, the following steps are further implemented:

[0206] Test the target NAND diagram to obtain a test result; if the test result does not meet the preset performance requirement, continue to execute the step of sampling potential distribution parameters from the conditional probability distribution function until the target NAND diagram meets the preset performance requirement.

[0207] In one embodiment, when the computer program is executed by the processor, the following steps are further implemented:

[0208] Decode the potential distribution parameters through a decoder to obtain the node feature vectors of each node, and splice the feature vectors of each node to obtain the graph feature matrix of the target NAND diagram;

[0209] Decode the graph feature matrix through a decoder to obtain the probability features of each edge.

[0210] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented:

[0211] For each target node, connect the associated nodes to the target node through the edges of the target node to generate a sub-NAND graph.

[0212] Combine multiple sub-NAND graphs to obtain the target NAND graph corresponding to the target circuit.

[0213] In one of the embodiments, the method further includes:

[0214] Update the node feature vector of the target node through a preset neural network model, the target node, and the associated nodes corresponding to the target node; update the graph feature matrix based on the updated node feature vector to obtain an updated graph feature matrix.

[0215] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented:

[0216] Obtain the sample logic data of the sample logic circuit based on a logic synthesis tool.

[0217] Convert the sample logic data through the encoder in the initial neural network model to obtain the sample graph feature matrix corresponding to the sample logic circuit, and embed the sample graph feature matrix to obtain a sample embedded feature vector.

[0218] For each sample node, extract the sample embedded feature vector through the encoder in the initial neural network model to obtain a sample node feature vector; calculate the sample conditional probability distribution function corresponding to the sample node feature vector based on a preset probability distribution formula; sample the sample latent distribution parameters from the sample conditional probability distribution function, and perform decoding processing on the sample latent distribution parameters through the decoder in the initial neural network model to obtain the sample node feature vectors of the sample nodes, the sample graph feature matrix of the sample logic circuit, and the sample edge probability features of the edges between the sample nodes.

[0219] For the sample target node, obtain the sample node prediction type of the sample target node based on the sample graph feature matrix, the sample node feature vector of the previous node of the sample target node, and the initial neural network model; determine the sample associated nodes of the sample target node based on the sample node prediction type and the sample edge probability features; generate the sample target NAND graph corresponding to the sample logic circuit based on multiple sample target nodes and the sample target nodes and their sample associated nodes.

[0220] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented:

[0221] Set the preset distribution type that the sample node feature vector follows, and determine the first conditional probability distribution function of the potential distribution parameters corresponding to the sample node feature vector based on the preset distribution type; based on the dependency relationship between the sample node and the predecessor node of the sample node, and the first conditional probability distribution function, obtain the sample conditional probability distribution function, where the sample conditional probability distribution function characterizes the target distribution type corresponding to the non-graph data.

[0222] In one embodiment, when the computer program is executed by the processor, the following steps are further implemented:

[0223] Perform circuit simulation on the sample target and the non-graph to obtain a function detection result; test the performance of the sample target and the non-graph to obtain a performance test result;

[0224] Compare the function detection result and the performance test result with the target performance requirements to obtain a comparison result, and optimize the parameters of the initial neural network model based on the comparison result to obtain a preset neural network model, where the target performance requirements are related to the attribute information of the sample logic circuit.

[0225] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved in this application are all information and data that have been authorized by the user or fully authorized by all parties, and the collection, use, and processing of relevant data need to comply with relevant regulations.

[0226] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above methods. Among them, any reference to a memory, database, or other medium used in the embodiments provided in the present application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc. The databases involved in the embodiments provided in the present application can include at least one of relational databases and non-relational databases. Non-relational databases can include distributed databases based on blockchain, etc., without limitation. The processors involved in the embodiments provided in the present application can be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, data processing logics based on quantum computing, artificial intelligence (AI) processors, etc., without limitation.

[0227] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered to be within the scope recorded in the present application.

[0228] The above-described embodiments merely represent several implementation manners of the present application. The description thereof is relatively specific and detailed, but it should not be construed as a limitation to the patent scope of the present application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all fall within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the appended claims.

Claims

1. A method for generating a non-AND graph, characterized in that: The method comprises: Generate a conditional probability distribution function corresponding to the NAND graph data based on the NAND graph data of the target circuit, the target distribution type obeyed by the NAND graph data, and a preset neural network model, wherein the NAND graph data reflects multiple nodes in the target NAND graph and edges connecting the nodes, and the preset neural network model includes at least a decoder; Randomly obtain the AND-non-graph data from the conditional probability distribution function, and determine the mean difference function and variance function corresponding to the AND-non-graph data; determine the potential distribution parameters based on a preset reparameterization formula, the AND-non-graph data, the mean difference function and the variance function; decode the potential distribution parameters through the decoder to obtain the node feature vector of each node, and concatenate the feature vectors of each node to obtain the graph feature matrix of the target AND-non-graph; decode the graph feature matrix through the decoder to obtain the probability characteristics of the edges between the nodes; For a target node, based on the graph feature matrix, the node feature vector of the previous node of the target node and a preset neural network model, a node prediction type of the target node is obtained; based on the node prediction type and the edge probability feature of the target node, an associated node of the target node is determined; Based on each of the target nodes and each of the associated nodes corresponding to the target nodes, a target AND-NOT graph corresponding to the target circuit is generated.

2. The method according to claim 1, characterized in that The method further comprises: The target and the non-graph are tested to obtain a test result; if the test result does not meet the preset performance requirement, the step of sampling potential distribution parameters from the conditional probability distribution function is continued until the target and the non-graph meet the preset performance requirement.

3. The method according to claim 1, characterized in that The generating a target AND-NOT graph corresponding to the target circuit based on each of the target nodes and each of the associated nodes corresponding to the target nodes comprises: For each target node, each of the associated nodes is connected to the target node through the edge of the target node to generate a sub-NAND graph; Combine a plurality of the sub-NAND graphs to obtain a target NAND graph corresponding to the target circuit.

4. The method according to claim 1, characterized in that: The method further comprises: By presetting a neural network model, the target node and each associated node corresponding to the target node, the node feature vector of the target node is updated to obtain an updated node feature vector; based on the updated node feature vector, the graph feature matrix is ​​updated to obtain an updated graph feature matrix.

5. The method according to claim 1, characterized in that The method further comprises: Acquire sample logic data of a sample logic circuit based on a logic synthesis tool; The sample logic data is converted by an encoder in the initial neural network model to obtain a sample graph feature matrix corresponding to the sample logic circuit, and the sample graph feature matrix is ​​embedded to obtain a sample embedding feature vector; For each sample node, the sample embedded feature vector is extracted by the encoder to obtain a sample node feature vector; a sample conditional probability distribution function corresponding to the sample node feature vector is calculated based on a preset probability distribution formula; sample potential distribution parameters are sampled from the sample conditional probability distribution function, and the sample potential distribution parameters are decoded by the decoder in the initial neural network model to obtain a sample node feature vector of each sample node, a sample graph feature matrix of the sample logic circuit, and a sample edge probability feature of the edge between each sample node; For a sample target node, based on the sample graph feature matrix, the sample node feature vector of the previous node of the sample target node and the initial neural network model, the sample node prediction type of the sample target node is obtained; based on the sample node prediction type and the sample edge probability characteristics, the sample associated node with the sample target node is determined; based on a plurality of the sample target nodes and the sample target node and each of the sample associated nodes, a sample target and non-graph corresponding to the sample logic circuit is generated.

6. The method according to claim 5, characterized in that The calculating the sample conditional probability distribution function corresponding to the sample node feature vector based on a preset probability distribution formula includes: A preset distribution type is set for the feature vector of the sample node to obey, and a first conditional probability distribution function of a potential distribution parameter corresponding to the feature vector of the sample node is determined based on the preset distribution type; a sample conditional probability distribution function is obtained based on a dependency relationship between the sample node and a predecessor node of the sample node, and the first conditional probability distribution function, wherein the sample conditional probability distribution function represents a target distribution type corresponding to non-graph data.

7. The method according to claim 5, characterized in that The method further comprises: Conducting circuit simulation on the sample target and the non-graph to obtain a functional test result; conducting performance testing on the sample target and the non-graph to obtain a performance test result; The functional test results and the performance test results are compared with the target performance requirements to obtain a comparison result, and the parameters of the initial neural network model are optimized based on the comparison result to obtain a preset neural network model, wherein the target performance requirements are related to the attribute information of the sample logic circuit.

8. A device for generating a non-AND graph, characterized in that: The device comprises: A first generating module is used to generate a conditional probability distribution function corresponding to the NAND graph data based on the NAND graph data of the target circuit, the target distribution type obeyed by the NAND graph data and a preset neural network model, wherein the NAND graph data reflects multiple nodes in the target NAND graph and edges connecting the nodes, and the preset neural network model at least includes a decoder; A processing module, used to randomly obtain the non-graph data and the mean difference function and variance function corresponding to the non-graph data from the conditional probability distribution function, and determine the potential distribution parameters based on a preset reparameterization formula, the non-graph data, the mean difference function and the variance function; decode the potential distribution parameters through the decoder to obtain the node feature vector of each node, and concatenate the feature vectors of each node to obtain the graph feature matrix of the target non-graph; decode the graph feature matrix through the decoder to obtain the probability characteristics of the edges between each node; A determination module, for obtaining, for a target node, a node prediction type of the target node based on the graph feature matrix, a node feature vector of a previous node of the target node, and a preset neural network model; and determining an associated node of the target node based on the node prediction type and an edge probability feature of the target node; The second generating module is used to generate a target AND-NOT graph corresponding to the target circuit based on each of the target nodes and each of the associated nodes corresponding to the target nodes.

9. The device according to claim 8, characterized in that The device comprises: The second generation module is also used to test the target and the non-graph to obtain a test result; if the test result does not meet the preset performance requirements, continue to execute the step of sampling potential distribution parameters from the conditional probability distribution function until the target and the non-graph meet the preset performance requirements.

10. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 7 are implemented.

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