On-chip network simulation information analysis method, device, equipment and storage medium

Abstract

The present application provides a method, apparatus, electronic device and computer-readable storage medium for analyzing on-chip network simulation information. When verifying an on-chip network design file, the simulation signal data generated during the verification process is obtained and stored in a hard disk. During integrity detection, the simulation data signal stored in the hard disk is read to achieve integrity detection, without the need to maintain communication with the verification platform during integrity detection, thereby realizing offline parsing of the simulation signal data. Completing the integrity detection in the offline state also eliminates the need to integrate the checker on the verification platform, thus avoiding the restrictions on resource performance and compatibility caused by integrating the checker on the verification platform. Using an offline checker can avoid the above restrictions, thereby reducing the components integrated on the verification platform, reducing system complexity, and improving operation efficiency. At the same time, since it gets rid of the dependence on the verification platform, it can more flexibly select the development method and reduce the development cost.

Description

Technical Field

[0001] This application relates to the field of computer technologies, and particularly to a method, apparatus, electronic device, and computer-readable storage medium for analyzing on-chip network simulation information. Background Art

[0002] When validating the design file of a network-on-chip (NOC), it is necessary to analyze the integrity of the simulation run while the design file is running in simulation, so as to determine whether each module designed in the design file works on schedule.

[0003] When analyzing the integrity of the simulation run, a checker is required to collect data for integrity detection, so the checker is often integrated into the verification platform.

[0004] However, as the functions implemented by the design file become more and more complex and the components integrated in the verification platform become more and more numerous, there are compatibility problems among the components, making it difficult to integrate the checker and thus difficult to perform integrity detection. Summary of the Invention

[0005] Embodiments of this application provide a method, apparatus, electronic device, and computer-readable storage medium for analyzing on-chip network simulation information to solve the problems in the related technologies.

[0006] In a first aspect, embodiments of this application provide a method for analyzing on-chip network simulation information, the method including:

[0007] During the process of validating the on-chip network design file, obtaining simulation signal data and storing it in a hard disk; the simulation signal data records the signal change situation of the on-chip network design file during the simulation run;

[0008] Parsing the simulation signal data stored in the hard disk offline to obtain the correspondence between the request data and the response result in the simulation signal data;

[0009] Performing integrity detection on the simulation signal data according to the correspondence between the request data and the response result.

[0010] In a second aspect, embodiments of this application provide an apparatus for analyzing on-chip network simulation information, the apparatus including:

[0011] A storage module, configured to obtain simulation signal data and store it in a hard disk during the process of validating the on-chip network design file; the simulation signal data records the signal change situation of the on-chip network design file during the simulation run;

[0012] A parsing module, configured to offline parse the simulation signal data stored in a hard disk to obtain the correspondence between the request data and the response result in the simulation signal data;

[0013] An integrity detection module, configured to perform integrity detection on the simulation signal data according to the correspondence between the request data and the response result.

[0014] In a third aspect, an embodiment of the present application provides an electronic device, including a processor and a memory. The memory stores a program or instruction that can run on the processor. When the program or instruction is executed by the processor, the steps of one or more of the methods in the embodiments of the present application are implemented.

[0015] In a fourth aspect, an embodiment of the present application provides a readable storage medium. When the instructions in the readable storage medium are executed by a processor of an electronic device, the electronic device can execute one or more of the methods in the embodiments of the present application.

[0016] In the embodiment of the present application, when verifying a network-on-chip design file, the simulation signal data generated during the verification process is obtained and stored in a hard disk. When performing integrity detection, the simulation data signal stored in the hard disk is read to implement integrity detection, without the need to maintain communication with the verification platform during integrity detection, so as to realize offline parsing of the simulation signal data. And since the integrity detection is completed in an offline state, there is no need to integrate the checker on the verification platform, thus avoiding the restrictions in terms of interface protocol, system complexity, resource performance, and compatibility caused by integrating the checker on the verification platform. Using an offline checker can avoid the above restrictions, thereby reducing the components integrated on the verification platform, reducing system complexity, improving operation efficiency. At the same time, because it gets rid of the dependence on the verification platform, it can more flexibly select the development method and reduce the development cost.

[0017] The above description is only an overview of the technical solution of the present application. In order to be able to understand the technical means of the present application more clearly, it can be implemented according to the content of the specification. And in order to make the above and other purposes, features, and advantages of the present application more obvious and understandable, the specific embodiments of the present application are specifically described below. Description of the Drawings

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained according to these drawings.

[0019] Figure 1It is a flowchart of steps of a method for analyzing on-chip network simulation information provided by an embodiment of the present application;

[0020] Figure 2 It is a flowchart of steps of another method for analyzing on-chip network simulation information provided by an embodiment of the present application;

[0021] Figure 3 It is a schematic diagram of data parsing provided by an embodiment of the present application;

[0022] Figure 4 It is a flowchart of integrity detection provided by an embodiment of the present application;

[0023] Figure 5 It is a flowchart of performance analysis provided by an embodiment of the present application;

[0024] Figure 6 It is a flowchart of analyzing on-chip network simulation information provided by an embodiment of the present application;

[0025] Figure 7 It is a block diagram of a device for analyzing on-chip network simulation information provided by an embodiment of the present application;

[0026] Figure 8 It is a block diagram of an electronic device provided by an embodiment of the present application;

[0027] Figure 9 It is a block diagram of another electronic device of another embodiment of the present application. Detailed implementation manners

[0028] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0029] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally a class, and the number of objects is not limited. For example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the association relationship of associated objects, indicating that three kinds of relationships can exist, for example, A and / or B can be represented: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the front and back associated objects are a kind of "or" relationship. In the embodiment of the present application, the term "multiple" refers to two or more, and other quantifiers are similar.

[0030] With the rapid development of semiconductor technology, the scale of multi-core processors and system-level chips continues to expand. As the core communication infrastructure in multi-core systems, the network on chip (NoC) undertakes the important tasks of inter-core data exchange and system collaboration. However, with the improvement of chip integration and the reduction of process size, the network on chip faces increasingly severe signal integrity challenges. Specifically, due to the influence of process deviations, electromagnetic interference, crosstalk noise and other factors, bit errors, timing deviations, routing failures and other problems may occur during data transmission, and in severe cases, even system function failures. Therefore, how to effectively verify the integrity of the network on chip and ensure the correctness, consistency and reliability of data transmission has become a technical problem that needs to be solved urgently in this field.

[0031] In some related technologies, the verification method based on simulation simulates the behavior of the on-chip network to verify the correctness of data transmission and the functional integrity. Through hardware description languages, such as SystemVerilog, an accurate model of the on-chip network is constructed. Designers make accurate logical descriptions based on the various components in the on-chip network, such as routers, links, processing units, etc., to form a complete hardware model. For example, for router components, HDL code is used to describe its routing algorithm, data packet forwarding logic, and cache mechanism. At the same time, when verifying the on-chip network design file, it is necessary to integrate the checker to collect simulation signal data, so as to complete the integrity detection of the simulation signal data. However, when integrating the checker, due to the large number of components of the verification platform, the checker is restricted by compatibility and other reasons. Integration on the verification platform will cause the verification platform to reduce its operating efficiency. At the same time, after the integrity detection, the on-chip network design file is analyzed again. When determining the cause of the problem, other components need to be integrated, which further reduces the efficiency of the on-chip network verification.

[0032] Figure 1It is a flowchart of the steps of a method for analyzing on-chip network simulation information provided by an embodiment of the present application. As Figure 1 shown, the method may include:

[0033] Step 101, during the verification of the on-chip network design file, obtain simulation signal data and store it in the hard disk.

[0034] Among them, the simulation signal data records the signal changes of the on-chip network design file during the simulation operation. During the operation of the on-chip network, various electrical signals will be generated by each node and link, such as clock signals, data signals, control signals, etc. By recording and storing these signals that change over time, it is convenient to analyze the working state and performance of the on-chip network later.

[0035] In some embodiments, a waveform file is used as the simulation signal data. A waveform file is a file used to record and store the changes of electrical signals over time and has a wide range of applications in the fields of electronic design, testing, verification, etc. The waveform file records the amplitude values of electrical signals (such as voltage, current, etc.) within a continuous time in a specific data structure and format in chronological order, enabling people to intuitively observe and analyze the characteristics of the signals, such as frequency, amplitude, phase, pulse width, etc.

[0036] In the embodiment of the present application, by storing the obtained simulation signal data in the hard disk during the verification of the on-chip network design file, the simulation signal data can be persistently saved. When it is necessary to perform integrity detection on the simulation signal data, it can be read from the hard disk, reducing the real-time data transmission between the verification platform and the checker for implementing integrity detection, thereby alleviating the data transmission pressure during the verification process of the on-chip network design file and investing more performance resources in the verification process to improve the verification efficiency.

[0037] Step 102, offline parse the simulation signal data stored in the hard disk to obtain the correspondence between the request data and the response result in the simulation signal data.

[0038] Among them, the simulation signal data is the continuously changing signal data generated during the verification of the on-chip network design file. The data types of the simulation signal data can be divided into request type, response type, transmission type, and listening type. The simulation signal data of the request type is the request data, and the response results corresponding to the request data are scattered in the other data in the simulation signal data except the request data.

[0039] In an embodiment of the present application, offline reading of the simulation signal data is completely realized by offline parsing the simulation signal data stored in the hard disk. Therefore, when the simulation signal data is obtained offline, offline integrity detection can be realized. When performing integrity detection, there is no need to transmit real-time data with the verification platform. Therefore, there is no need to integrate a checker in the verification platform, thereby avoiding concessions for compatibility, performance, resources, interface protocols and system complexity due to the integration of the checker in the verification platform. Not only the labor cost of the integrated checker is reduced, but also the complexity of the verification platform is reduced, the operating efficiency is improved, and the cost of debugging is reduced due to the simplification of the components integrated on the verification platform.

[0040] In some embodiments, since there is no need to integrate a checker on the verification platform, there is no need to develop a checker using a hardware description language bound to the on-chip network framework as in the related art, and the function of performing offline integrity detection can be developed in a variety of ways. For example, the integrity detection function can be developed using the Python language. Compared with the hardware description language bound to the on-chip network framework, Python as a software language has richer open source resources, which facilitates the implementation of more complex logical functions, thereby reducing R&D costs.

[0041] Step 103: Perform integrity detection of the simulation signal data according to the corresponding relationship between the request data and the response result.

[0042] It should be noted that the integrity detection of simulation signal data is a key technical means to ensure the normal and efficient operation of the network on chip (NoC), which is of great significance in the field of integrated circuit design. From the perspective of functional integrity, it is necessary to verify whether the network on chip can accurately transmit data according to established protocols and rules. It is necessary to ensure the accurate transmission of data packets from the source node to the target node, eliminate data loss, errors or disorder, and ensure the normal functioning of functions such as routing and flow control. For example, in a multi-core processor chip, the data interaction between the cores depends on the network on chip. If the function is incomplete, the calculation result will be wrong; from the performance integrity aspect, the main evaluation is whether the performance indicators of the network on chip meet the design requirements. Bandwidth utilization, delay time and throughput are all key indicators. High bandwidth utilization means that the network can make full use of resources, low latency can ensure fast data transmission, and sufficient throughput can meet the processing needs of large amounts of data. For example, in image and video processing chips, if the performance of the network on chip is poor, problems such as screen freeze will occur; reliability focuses on the ability of the network on chip to cope with interference and anomalies. It needs to have an effective error detection and correction mechanism that can automatically adjust the route when some nodes or links fail to maintain the continuity of communication. For example, for chips working in complex electromagnetic environments, a reliable on-chip network can ensure that data transmission is not interfered with.

[0043] In the embodiment of the present application, by parsing the request data in the simulation signal data, which includes key information such as the source address, destination address, data content, timestamp, etc., then performing a format check, and according to the communication protocol adopted by the network-on-chip, checking whether the format of the request data is compliant. Finally, analyze whether there is a response return for the request data and whether there is data return. Specifically, it is necessary to carefully analyze whether there is a response return for the request data. If there is a response, further check whether it carries valid data. At the same time, pay attention to whether the request data triggers a retry request. When there is neither a retry return nor other forms of response return for the request data, this is very likely to mean that there are problems such as communication failures, node anomalies, or protocol errors in the network-on-chip. At this time, the error reporting processing mechanism should be immediately started, and the error reporting information should be accurately recorded, including the characteristics of the request data, the occurrence time, etc., for subsequent in-depth troubleshooting and repair to ensure the stable and reliable operation of the network-on-chip.

[0044] Among them, Retry is an important mechanism to cope with data transmission anomalies and ensure communication reliability. The retry mechanism means that during the data transmission process, when the sender detects that the data packet fails to be successfully transmitted to the receiver, the data packet will be resent until the data is correctly received or the maximum number of retries is reached. Although retry guarantees the stability of communication, because each retry requires additional time, it increases the data transmission delay, and at the same time, it will also occupy a certain amount of network bandwidth resources, reducing the overall efficiency of the network.

[0045] In summary, in the embodiment of the present application, when verifying the network-on-chip design file, the simulation signal data generated during the verification process is obtained and stored in the hard disk. When performing integrity detection, the simulation data signal stored in the hard disk is read to achieve integrity detection, and there is no need to communicate with the verification platform during integrity detection, so as to realize offline parsing of the simulation signal data. And completing the integrity detection in the offline state also eliminates the need to integrate the checker on the verification platform, thus avoiding the restrictions on interface protocols, system complexity, resources, performance, and compatibility when integrating the checker on the verification platform. Using an offline checker can avoid the above restrictions, thereby reducing the components integrated on the verification platform, reducing system complexity, and improving operation efficiency. At the same time, because it gets rid of the dependence on the verification platform, it can more flexibly select the development method and reduce the development cost.

[0046] Figure 2 , is the specific step flowchart of a network-on-chip simulation information analysis method provided by the embodiment of the present application, as Figure 2 shown, the method may include:

[0047] Step 201, during the verification of the on-chip network design file, obtain the simulation signal data and store it in the hard disk. The simulation signal data records the signal changes of the on-chip network design file during the simulation run.

[0048] This step can specifically refer to the above-mentioned step 101 and will not be elaborated here.

[0049] Optionally, step 201 can specifically include:

[0050] Sub-step 2011, detect the clock signal of the on-chip network.

[0051] Sub-step 2012, when the clock signal jumps from low level to high level, detect the control signal of the simulation signal data. The high level indicates that the simulation task is in the execution end state, so as to ensure that the simulation signal data is in a data consistent state.

[0052] Sub-step 2013, when the control signal of the simulation signal data is in an effective state, read the simulation signal data from the verification platform and store it in the hard disk.

[0053] Regarding sub-steps 2011 - 2013, the clock signal of the on-chip network is a periodic electrical signal that provides a unified time reference for each component of the on-chip network. It is generated by a clock generator and changes regularly at a fixed frequency and phase. When data is transmitted, the receiving end needs to sample the data at the appropriate moment, and the clock signal is required to provide an accurate time point for data sampling. In addition, the states of each module of the on-chip network also need to be converted and updated according to the clock signal. For example, the cache module determines when new data can be written or the stored data can be read based on the clock signal to maintain the correct read and write order of the data.

[0054] In the embodiments of the present application, for the detected change characteristics of the clock signal, the clock signal has two signal characteristics: rising edge and falling edge. Among them, the rising edge refers to the clock signal jumping from low level to high level, while the falling edge refers to the clock signal jumping from high level to low level. The present application detects the rising edge characteristic of the clock signal. In some embodiments, the falling edge characteristic can also be detected, and the present application does not make any restrictions here.

[0055] It should be noted that the rising edge and falling edge are the critical moments of the clock signal change, which can provide a unified time reference for each module. By triggering data sampling, storage, or transmission operations at the rising edge or falling edge, each module can work at the same beat, avoiding data chaos caused by inconsistent time. For example, in a synchronization circuit of a network-on-chip, multiple components can sample the input simulation signal data simultaneously at the rising edge of the clock signal, ensuring that the simulation signal data obtained by each component is at the same moment, thus maintaining the consistency of the simulation signal data.

[0056] In addition, the control signal (valid) of the simulation signal data is used to indicate whether the data is valid. During the data transmission process in the network-on-chip, the simulation signal data is not valid in every clock cycle. As a control flag, the control signal clearly indicates whether the simulation signal data transmitted at the current moment is meaningful. When the control signal is in the valid state, it indicates that the simulation signal data transmitted at this time is valid and can be sampled and processed subsequently; while when the control signal is in the invalid state, it means that the current simulation signal data may be random, uninitialized, or useless, and no sampling operation is performed at this time, thus avoiding processing invalid data and saving system resources.

[0057] In the embodiment of the present application, the simulation signal data is sampled when the clock signal jumps from low level to high level to ensure that the received simulation signal data is consistent with the data received by other components. At the same time, when the control signal of the simulation signal data is in the valid state, sampling is performed to ensure the validity of the sampled simulation signal data and increase the reliability of the sampled data.

[0058] Optionally, step 201 may specifically include:

[0059] Sub-step 2014: Obtain the data units that make up the simulation signal data and record the acquisition time of each data unit.

[0060] Sub-step 2015: Arrange the data units in the time order of the acquisition time to obtain the simulation signal data and store it in the hard disk.

[0061] For sub - step 2014 - sub - step 2015, when transmitting simulation signal data on the network - on - chip, since the simulation signal data is too long, in order to facilitate routing and transmission in the network - on - chip, the simulation signal data is segmented into basic segmentation units that are easy to transmit, namely data units (flits). The smaller flit size makes the router more flexible and efficient when making routing decisions. The router can quickly determine its forwarding direction based on the header information of each flit without waiting for the arrival of the entire data packet, thus improving the network throughput and response speed. In addition, in the network - on - chip, the bandwidth resources are limited. Transmitting data in units of flits can allocate and manage resources more precisely. For example, when a link is congested, only the transmission of the current flit can be paused without affecting the scheduling of other flits.

[0062] In the embodiment of the present application, when obtaining a flit, the acquisition time of each flit is recorded simultaneously. For example, the obtained data format is in the form of "time + data unit". By sorting the recorded acquisition times, flits with correct timing can be obtained, and integrating these flits together can obtain the simulation signal data, and the simulation signal data is stored on the hard disk.

[0063] Step 202, offline - parse the simulation signal data stored on the hard disk to obtain the correspondence between the request data and the response result in the simulation signal data.

[0064] This step can specifically refer to the above - mentioned step 102 and will not be elaborated here.

[0065] Optionally, step 202 may specifically include:

[0066] Sub - step 2021, classify the simulation signal data according to the data type.

[0067] Sub - step 2022, according to the data type, split the simulation signal data and store it in a file corresponding to the data type. The files include a request file, a response file, a transmission file, and a listening file.

[0068] Sub - step 2023, read the request file to obtain the request data.

[0069] For sub - step 2021 - sub - step 2023, as Figure 3As shown, when storing the simulation signal data of the on-chip network, the simulation signal data can be split according to the on-chip network design concept and the organization method of the architecture, that is, the hierarchy, and the corresponding data types can be stored in the corresponding request file, response file, transmission file, and listening file according to the data types included in the simulation signal, such as the request type, transmission type, response type, and listening type.

[0070] In the embodiment of the present application, when performing integrity detection on the simulation signal data, it is necessary to obtain the request data in the simulation signal data and query whether there is a response result corresponding to the request data in the remaining data of the simulation signal data, and perform integrity detection according to the request data and its corresponding response result. When obtaining the request data in the simulation signal data, it is only necessary to read the data content stored in the request file.

[0071] Step 203: According to the corresponding relationship between the request data and the response result, count the request data with corresponding response results and the target request data without corresponding response results from all the request data, and locate the position of the target request data in the simulation signal data.

[0072] In the embodiment of the present application, according to the corresponding relationship between the request data and the response result, count the request data with corresponding response results from the request data, where the response result records information such as the delay value obtained by the request data for integrity detection. In addition, there is a situation where the request result does not have a corresponding response result after querying. In this case, the reason for the non-response of the request data needs to be investigated, and the request data is used as the target request data and located in the simulation signal data.

[0073] It should be noted that when determining the request data and the corresponding response results for integrity detection, it is necessary to determine the latency value of the request data, request retries, and outstanding requests, etc. These situations will affect the performance and reliability of the on-chip network. Among them, the latency value refers to the time it takes for the request data to be transmitted from the source node to the target node in the on-chip network, which includes the time of transmission in the link, the time of making routing decisions and queuing in the router, etc.; request retry is a mechanism to handle abnormal data transmission situations. When the sender detects that the request data fails to be successfully transmitted to the receiver, it will resend the request data until the request data is correctly received or the maximum number of retries is reached; outstanding requests indicate that the request data is in an "uncompleted", "unprocessed", or "unresponded" state. When a request data is sent out and the corresponding response has not been received yet, this request is called an "outstanding" request; for the request data being transmitted, it is also in the "outstanding" state before it reaches the destination and is confirmed.

[0074] In some embodiments, performing integrity analysis on the latency value of the request data to obtain the response result, request retries, and outstanding requests, etc., can detect whether the latency value is stable and reasonable when the request data is transmitted in the on-chip network, so as to ensure the efficient operation of the on-chip network. By detecting the integrity of the latency value, problems such as congestion points and link failures can be discovered in a timely manner, which helps to optimize the on-chip network topology and routing algorithm, and improve the overall performance of the on-chip network; by performing integrity detection on request retries, the root causes of data transmission errors, such as link noise and node failures, can be found, and then targeted measures can be taken to solve them, improving the reliability of the network; by performing integrity detection on outstanding requests, network resources can be effectively managed, network congestion can be avoided, and the stable operation of the network can be ensured.

[0075] For example, for applications with high real-time requirements, the latency value needs to be strictly controlled within a very small range. When the network load suddenly increases, the latency value may increase accordingly, but it should be within an acceptable range.

[0076] Optionally, the request data includes a first target field for finding the corresponding response result, and the first target field represents the task identifier of the request data. Step 203 may specifically include:

[0077] Sub-step 2031, set the number of concurrencies.

[0078] Sub-step 2032, for one of the query tasks executed simultaneously, send the request data to the data tracking process to obtain the completion signal of the current query task.

[0079] Sub-step 2033: When the corresponding response result is found according to the first target field of the request data, the tracking process converts the completion signal into a completed signal.

[0080] Regarding sub-steps 2031 - 2033, in the embodiments of the present application, by storing the simulation signal data in the hard disk and also reading it from the hard disk during reading, the offline integrity detection of the simulation signal data is realized. Therefore, the function of integrity detection does not need to be integrated on the on-chip network, and the integrity detection can be realized offline through Python. By setting the number of concurrency, the number of query tasks executed simultaneously is controlled. The query task is the task of finding the response result according to the request data. Simulating the outstanding state of the request sent by the central processing unit (CPU, Central Processing Unit) makes the offline realization of integrity detection closer to the real situation, and obtaining the outstanding state of the request data can more comprehensively evaluate the on-chip network design file.

[0081] In the embodiments of the present application, the request data is sent to the tracking process, and the tracking process tracks the response result corresponding to the request data in the current query task. In the current query task (transaction), there is a unique number assigned to the current transaction, that is, the transaction identifier (txnid, Transaction ID). This transaction identifier remains unchanged throughout the life cycle of the query task and is used to uniquely identify the query task in the integrity detection. Among them, the first target field can be the transaction identifier. When the corresponding response result is found according to the first target field of the request data, the tracking process converts the completion signal into completed, and the task of finding the response result corresponding to the request data in the query task is completed through the tracking process, increasing the cohesion of the tracking process.

[0082] As Figure 4 shown in the integrity detection flowchart, when the corresponding type of data is read from the four types of files and stored in the buffer queue, the request data is sent to the tracking process. The tracking process searches for the response result in other types of data according to the first target field, and sends the corresponding relationship between the searched request data and the response result to the integrity detection module for detection, and finally exports the integrity report.

[0083] Optionally, the method further includes:

[0084] Sub-step 2034: When the corresponding response result is not found from the first target field of the request data, the tracking process converts the completion signal into an uncompleted signal.

[0085] Sub-step 2035: Mark the request data with the unfinished signal as the target request data, and locate the request position of the target request data.

[0086] Regarding sub-step 2034 - sub-step 2035, when the corresponding response result cannot be found according to the first target field of the request data, it indicates that the request data may have exceeded the maximum number of request retries at this time, or the request data has been in an unfinished state for a long time, and there may be a problem with this request. The tracking process converts the completion signal for which the corresponding response result cannot be found into an unfinished signal. Since the request data at this time has a large deviation from the expectation, this request data is used as the target request data, and the request position of the target request data is initially located to facilitate subsequent investigation of the reasons for the unexpected situation.

[0087] Optionally, the request data includes a second target field for finding the corresponding response result, and the method further includes:

[0088] Sub-step 2036: When performing the query task, when the corresponding response result is found according to the first target field or the second target field of the request data, the tracking process converts the completion signal into a completed signal.

[0089] Sub-step 2037: When the corresponding response result cannot be found according to the first target field and the second target field of the request data, the tracking process converts the completion signal into an unfinished signal.

[0090] Regarding sub-step 2036 - sub-step 2037, in the query task of the on-chip network, the query task also includes a database identifier (dbid, Database ID). The dbid is a unique identifier used to identify the database or data storage area associated with the query task. Through the dbid, the specific database or storage area where the data to be accessed is located can be quickly and accurately located. For example, when a transaction needs to read specific type of data, the database storing this type of data can be directly found using the dbid, improving the data access efficiency. The second target field can be the database identifier.

[0091] In the embodiments of the present application, by using the first target field and the second target field to find the corresponding response result of the request data, similar to using the first target field to find the response result, when the corresponding response result is found according to the first target field and the second target field, the tracking process converts the completion signal into a completed signal, and when the corresponding response result cannot be found, the tracking process converts the completion signal into an unfinished signal. By using two target fields for searching, the search process can be shortened and the operation efficiency can be improved.

[0092] For example, first, the database storing the corresponding response data is located through the database identifier (dbid) of the requested data, and then the transaction identifier (txnid) is used for the lookup, avoiding ineffective lookups in areas where the response results are not stored, shortening the time required for the lookup, and improving the lookup efficiency.

[0093] Optionally, the method further includes:

[0094] Step 204: Send all the requested data to a performance statistics module, and the performance statistics module calculates the performance data of all the requested data.

[0095] The performance statistics module is used to receive the requested data and calculate the performance data of all the requested data. The performance data includes the latency value of the requested data to obtain a response, the retry situation of the requested data, the incomplete situation of the requested data, data throughput, packet loss rate, bandwidth utilization rate, and so on.

[0096] In the embodiments of the present application, by calculating the performance data of all the requested data, the quality and stability of data transmission during on-chip network verification can be grasped. By analyzing the latency value, the efficiency of the system during data transmission can be understood, and potential performance bottlenecks in the system, such as network congestion and insufficient device processing capabilities, can also be discovered. Analyzing the retry times and frequencies can understand the reliability of data transmission in the system. If the retry times are too many, it may indicate problems such as an unstable network environment, device failures, or unreasonable protocol designs. Analyzing the quantity and status of the incomplete situation of the requested data helps to reasonably allocate system resources, evaluate and optimize the processing capabilities of the system, and ensure that the system can efficiently process various requests. Analyzing the throughput can evaluate the overall performance and processing capabilities of the system and determine whether the system meets the business requirements. Analyzing the packet loss rate can identify the reasons for packet loss, such as network interference and link failures, and take corresponding measures for repair and optimization to improve the reliability of data transmission. Analyzing the bandwidth utilization rate can understand whether the network bandwidth is fully utilized and whether there is resource waste or insufficiency.

[0097] Step 205: Analyze the on-chip network design file based on the request locations of the requested data for which no corresponding response results are obtained in the integrity detection and the performance data, to obtain a performance analysis result.

[0098] In the embodiments of the present application, the request location is determined based on the request data for which no corresponding response result is obtained. There may be certain problems at this request location that result in no response result. Combining with the performance data, the on-chip network design file can be analyzed to find the reason for the lack of response result. According to the retry situation and packet loss rate of the request data, it can be analyzed whether there are unreasonable designs in the design file, and whether there are faults and interferences in the design. By analyzing performance data such as the retry situation and packet loss rate, the reliability of on-chip network data transmission can be improved; by analyzing performance data such as the incomplete situation of the request data and the bandwidth utilization rate, the resource allocation strategy can be optimized and the system operation efficiency can be improved.

[0099] As Figure 5 shown in the performance analysis flowchart, after reading the corresponding type of data from the four files, it is stored in the buffer queue. The request data is sent to the global counting module, and the performance data of the simulation running data is obtained through the global counting module, and all the performance data is sent to the performance statistics module for integration, and finally the performance analysis report is exported.

[0100] Step 206, determine the defects existing in the on-chip network design file according to the performance analysis result.

[0101] In some embodiments, for the performance analysis of the simulation signal data of the on-chip network design file, in addition to integrating the checker component in the verification platform, it is also necessary to integrate the performance analysis component to implement the function of analyzing performance. The more components integrated on the verification platform, the greater the impact on compatibility, and at the same time the complexity of verification will also increase, affecting the verification efficiency. However, in this application, the integrity detection of the simulation signal data is performed offline, and at the same time the performance data of the simulation signal data is statistically analyzed offline to achieve offline analysis without real-time data interaction with the verification platform. Therefore, there is no need to integrate the performance analysis component on the verification platform, which reduces the burden of integrating components on the verification platform and optimizes the operation efficiency of the verification environment.

[0102] As Figure 6 shown in the flowchart for realizing integrity detection and performance analysis, after collecting the simulation signal data generated by the verification environment, the simulation signal data is parsed and then integrity detection and performance analysis are performed. The location of the request location where no corresponding response data is found is obtained through the integrity detection, and then the problem location where no corresponding response data is found is sent to the performance problem location module. Combining with the performance data in this module, the defects of the on-chip network design file are finally analyzed and optimized.

[0103] In summary, in the embodiment of the present application, when verifying the on-chip network design file, the simulation signal data generated during the verification process is obtained and stored in the hard disk. When performing integrity detection, the simulation signal data stored in the hard disk is read to achieve integrity detection, without the need to maintain communication with the verification platform during integrity detection, thereby realizing offline parsing of the simulation signal data, and at the same time using the simulation signal data for offline performance analysis. Completing integrity detection and performance analysis in the offline state also eliminates the need for the checker to be integrated on the verification platform, reducing the burden of integrating the checker and performance analysis components on the verification platform. There is no need to consider compatibility, interface protocols, etc. when integrating the checker and performance analysis components, reducing development costs, and getting rid of the dependence on the verification platform, allowing for a more flexible choice of development methods. At the same time, due to reducing the components integrated on the verification platform, the system complexity is reduced and the operation efficiency is improved.

[0104] Figure 7 FIG. 4 is a block diagram of an on-chip network simulation information analysis device provided by an embodiment of the present application. The device includes:

[0105] A storage module 301, configured to obtain simulation signal data and store it in the hard disk during the process of verifying the on-chip network design file. The simulation signal data records the signal change situation of the on-chip network design file during the simulation operation.

[0106] An analysis module 302, configured to offline analyze the simulation signal data stored in the hard disk to obtain the correspondence between the request data and the response result in the simulation signal data.

[0107] An integrity detection module 303, configured to perform integrity detection of the simulation signal data according to the correspondence between the request data and the response result.

[0108] Optionally, the integrity detection module 303 may specifically include:

[0109] An integrity detection sub-module, configured to count, according to the correspondence between the request data and the response result, the request data with corresponding response results and the target request data without corresponding response results from all the request data, and locate the position of the target request data in the simulation signal data

[0110] Optionally, the storage module 301 may specifically include:

[0111] A clock sub-module, configured to detect the clock signal of the on-chip network.

[0112] The high-level sub-module is used to detect the control signal of the simulation signal data when the clock signal jumps from low level to high level. The high level indicates that the simulation task is in an execution end state, thus ensuring that the simulation signal data is in a data consistent state.

[0113] The valid state sub-module is used to read the simulation signal data from the verification platform and store it in the hard disk when the control signal of the simulation signal data is in a valid state.

[0114] Optionally, the storage module 301 may specifically include:

[0115] The data unit sub-module is used to obtain the data units that make up the simulation signal data and record the acquisition time of each data unit. The data unit is the smallest segmentation unit for the transmission of the simulation signal data.

[0116] The storage sub-module is used to arrange the data units in the chronological order of the acquisition time to obtain the simulation signal data and store it in the hard disk.

[0117] Optionally, the parsing module 302 may specifically include:

[0118] The data type sub-module is used to classify the simulation signal data according to the data type. The data type includes request type, transmission type, response type, and listening type.

[0119] The classified storage sub-module is used to split the simulation signal data according to the data type and store it in the file corresponding to the data type. The file includes a request file, a response file, a transmission file, and a listening file.

[0120] The request reading sub-module is used to read the request file to obtain the request data.

[0121] Optionally, the integrity detection sub-module may specifically include:

[0122] The concurrent unit is used to set the concurrent number, which is used to control the number of query tasks executed simultaneously. The query task is a task of finding the response result according to the request data.

[0123] The query unit is used to send the request data to the data tracking process for one of the query tasks executed simultaneously to obtain the completion signal of the current query task.

[0124] The first completed unit is used to convert the completion signal into a completed signal by the tracking process when the corresponding response result is found according to the first target field of the request data.

[0125] Optionally, the apparatus further comprises:

[0126] A first unfinished unit, configured to convert the completion signal into an unfinished signal by the tracking process when no corresponding response result is found in the first target field of the request data.

[0127] A positioning unit, configured to mark the request data with the unfinished signal as the target request data and locate the request position of the target request data.

[0128] Optionally, the apparatus further comprises:

[0129] A second completed unit, configured to convert the completion signal into a completed signal by the tracking process when a corresponding response result is found according to the first target field or the second target field of the request data when the query task is executed.

[0130] A second unfinished unit, configured to convert the completion signal into an unfinished signal by the tracking process when no corresponding response result is found according to the first target field and the second target field of the request data.

[0131] Optionally, the apparatus further comprises:

[0132] A performance statistics module, configured to send all the request data to the performance statistics module, and the performance statistics module statistics the performance data of all the request data.

[0133] A performance analysis module, configured to analyze the on-chip network design file according to the request position of the request data for which no corresponding response result is obtained in the integrity detection and the performance data, and obtain a performance analysis result.

[0134] A troubleshooting module, configured to determine the defects existing in the on-chip network design file according to the performance analysis result.

[0135] In summary, in the embodiment of the present application, when verifying the on-chip network design file, the simulation signal data generated during the verification process is acquired and stored in the hard disk. When performing the integrity detection, the simulation data signal stored in the hard disk is read to implement the integrity detection, without the need to communicate with the verification platform during the integrity detection, thereby realizing offline parsing of the simulation signal data. And since the integrity detection is completed in the offline state, there is no need to integrate the checker on the verification platform, thus avoiding the restrictions on the interface protocol, system complexity, resource performance, and compatibility when integrating the checker on the verification platform. Using the offline checker can avoid the above restrictions, thereby reducing the components integrated on the verification platform, reducing system complexity, improving operation efficiency. At the same time, because it gets rid of the dependence on the verification platform, it can more flexibly select the development method and reduce the development cost.

[0136] For the apparatus embodiments, since they are basically similar to the method embodiments, the description is relatively simple. For related parts, please refer to the corresponding descriptions in the method embodiments.

[0137] Each embodiment in this specification is described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts among the embodiments, reference can be made to each other.

[0138] Regarding the apparatus in the above embodiments, the specific manners in which each module performs operations have been described in detail in the embodiments related to the method, and will not be elaborated herein.

[0139] The embodiments of the present application provide a data row protection device for a dynamic random access memory, including a memory and one or more programs. The one or more programs are stored in the memory and configured to be executed by one or more processors. The one or more programs include those for performing the methods described in the above one or more embodiments.

[0140] Figure 8 FIG. is a block diagram of an electronic device 600 shown according to an exemplary embodiment. For example, the electronic device 600 may be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc.

[0141] Referring to Figure 8 , the electronic device 600 may include one or more of the following components: a processing component 602, a memory 604, a power supply component 606, a multimedia component 608, an audio component 610, an input / output (I / O) interface 612, a sensor component 614, and a communication component 616.

[0142] The processing component 602 generally controls the overall operation of the electronic device 600, such as operations associated with display, telephone call, data communication, camera operation, and recording operation. The processing component 602 may include one or more processors 620 to execute instructions to complete all or part of the steps of the above methods. In addition, the processing component 602 may include one or more modules to facilitate the interaction between the processing component 602 and other components. For example, the processing component 602 may include a multimedia module to facilitate the interaction between the multimedia component 608 and the processing component 602.

[0143] The memory 604 is used to store various types of data to support the operation of the electronic device 600. Examples of such data include instructions for any application or method operating on the electronic device 600, contact data, phone book data, messages, pictures, multimedia, and the like. The memory 604 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, a magnetic disk, or an optical disk.

[0144] The power supply component 606 provides power to various components of the electronic device 600. The power supply component 606 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power for the electronic device 600.

[0145] The multimedia component 608 includes a screen that provides an output interface between the electronic device 600 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen can be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors can not only sense the boundaries of touch or swipe actions but also detect the duration and pressure associated with the touch or swipe operation. In some embodiments, the multimedia component 608 includes a front camera and / or a rear camera. When the electronic device 600 is in an operating mode, such as a shooting mode or a multimedia mode, the front camera and / or the rear camera can receive external multimedia data. Each of the front camera and the rear camera can be a fixed optical lens system or have a focal length and optical zoom capabilities.

[0146] The audio component 610 is used to output and / or input audio signals. For example, the audio component 610 includes a microphone (MIC) that is used to receive external audio signals when the electronic device 600 is in an operating mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signals can be further stored in the memory 604 or transmitted via the communication component 616. In some embodiments, the audio component 610 further includes a speaker for outputting audio signals.

[0147] The I / O interface 612 provides an interface between the processing component 602 and a peripheral interface module, which can be a keyboard, a click wheel, buttons, etc. These buttons can include, but are not limited to: a home button, a volume button, a power-on button, and a lock button.

[0148] The sensor assembly 614 includes one or more sensors for providing a status assessment of various aspects for the electronic device 600. For example, the sensor assembly 614 can detect the on / off state of the electronic device 600, the relative positioning of components, such as the display and keypad of the electronic device 600. The sensor assembly 614 can also detect a change in the position of the electronic device 600 or a component of the electronic device 600, the presence or absence of user contact with the electronic device 600, the orientation or acceleration / deceleration of the electronic device 600, and the temperature change of the electronic device 600. The sensor assembly 614 can include a proximity sensor configured to detect the presence of nearby objects without any physical contact. The sensor assembly 614 can also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 614 can further include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0149] The communication component 616 is used to facilitate communication between the electronic device 600 and other devices in a wired or wireless manner. The electronic device 600 can access a wireless network based on communication standards, such as WiFi, a carrier network (such as 2G, 3G, 4G, or 5G), or a combination thereof. In an exemplary embodiment, the communication component 616 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 616 further includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0150] In an exemplary embodiment, the electronic device 600 can be implemented by one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to implement the methods provided in the embodiments of the present application.

[0151] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 604 including instructions, and the above instructions can be executed by the processor 620 of the electronic device 600 to complete the above methods. For example, the non-transitory storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, and an optical data storage device, etc.

[0152] Figure 9is a block diagram of an electronic device 700 shown in accordance with an exemplary embodiment. For example, the electronic device 700 may be provided as a server. Referring to Figure 9 , the electronic device 700 includes a processing component 722, which further includes one or more processors, and memory resources represented by a memory 732 for storing instructions executable by the processing component 722, such as application programs. The application programs stored in the memory 732 may include one or more modules each corresponding to a set of instructions. In addition, the processing component 722 is configured to execute instructions to perform the methods provided by the embodiments of the present application.

[0153] The electronic device 700 may also include a power component 726 configured to perform power management of the electronic device 700, a wired or wireless network interface 750 configured to connect the electronic device 700 to a network, and an input / output (I / O) interface 758. The electronic device 700 may operate based on an operating system stored in the memory 732, such as Windows ServerTM, Mac OS XTM, UnixTM, LinuxTM, FreeBSD TM or the like.

[0154] The embodiments of the present application also provide a computer program product, including a computer program, where the computer program, when executed by a processor, implements the methods described in the above embodiments.

[0155] Those skilled in the art will readily conceive of other embodiments of the present application after considering the specification and practicing the application disclosed herein. The present application is intended to cover any variations, uses, or adaptations of the present application, which follow the general principles of the present application and include known common knowledge or conventional technical means in the technical field not disclosed in the present disclosure. The specification and embodiments are only to be considered as exemplary, and the true scope and spirit of the present application are pointed out by the following claims.

[0156] It should be understood that the present application is not limited to the exact structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present application is only limited by the appended claims.

Claims

1. A method for analyzing on-chip network simulation information, characterized in that The method includes: During the process of verifying the on-chip network design file, acquiring simulation signal data and storing it in a hard disk; the simulation signal data records the signal change situation of the on-chip network design file during the simulation operation; Parsing the simulation signal data stored in the hard disk offline to obtain the correspondence between the request data and the response result in the simulation signal data; Performing integrity detection on the simulation signal data according to the correspondence between the request data and the response result; The performing integrity detection on the simulation signal data according to the correspondence between the request data and the response result includes: According to the correspondence between the request data and the response result, counting the request data with corresponding response results and the target request data without corresponding response results from all the request data, and locating the position of the target request data in the simulation signal data; the request data includes a first target field for finding the corresponding response result, and the first target field represents the task identifier of the request data. The counting the request data with corresponding response results from all the request data according to the correspondence between the request data and the response result includes: Setting the concurrency number, where the concurrency number is used to control the number of query tasks executed simultaneously, and the query task is a task of finding the response result according to the request data; For one of the query tasks executed simultaneously, sending the request data to a data tracking process to obtain the completion signal of the current query task; When the corresponding response result is found according to the first target field of the request data, the tracking process converts the completion signal into a completed signal.

2. The method according to claim 1, wherein The acquiring simulation signal data and storing it in a hard disk during the process of verifying the on-chip network design file includes: Detecting the clock signal of the on-chip network; When the clock signal jumps from a low level to a high level, detecting the control signal of the simulation signal data; the high level indicates that the simulation task is in an execution end state, so as to ensure that the simulation signal data is in a data consistent state; When the control signal of the simulation signal data is in an effective state, reading the simulation signal data from the verification platform and storing it in the hard disk.

3. The method according to claim 1, wherein The acquiring simulation signal data and storing it in a hard disk during the process of verifying the on-chip network design file includes: Acquiring the data units that make up the simulation signal data and recording the acquisition time of each data unit; the data unit is a segmentation unit for the transmission of the simulation signal data; Arranging the data units in the time sequence of the acquisition time to obtain the simulation signal data and storing it in the hard disk.

4. The method according to claim 1, wherein The parsing the simulation signal data stored in the hard disk offline includes: Classifying the simulation signal data according to the data type; the data type includes request type, transmission type, response type, and listening type; According to the data type, splitting the simulation signal data and storing it in files corresponding to the data type; the files include request file, response file, transmission file, and listening file. Read the request file to obtain the request data.

5. The method according to claim 1, wherein The method further includes: When the corresponding response result cannot be found in the first target field of the request data, the tracking process converts the completion signal into an incomplete signal; Mark the request data with the incomplete signal as the target request data and locate the request position of the target request data.

6. The method according to claim 1, characterized in that The request data includes a second target field for finding the corresponding response result, and the method further includes: When executing the query task, when the corresponding response result is found according to the first target field or the second target field of the request data, the tracking process converts the completion signal into a completed signal; When the corresponding response result cannot be found according to the first target field and the second target field of the request data, the tracking process converts the completion signal into an incomplete signal.

7. The method according to claim 1, wherein The method further includes: Send all the request data to the performance statistics module, and the performance statistics module statistics the performance data of all the request data; Analyze the on-chip network design file according to the request position of the request data without corresponding response results in the integrity detection and the performance data to obtain a performance analysis result; Determine the defects existing in the on-chip network design file according to the performance analysis result.

8. An on-chip network simulation information analysis device, characterized in that The device includes: A storage module for obtaining simulation signal data and storing it in the hard disk during the verification of the on-chip network design file; the simulation signal data records the signal change situation of the on-chip network design file during the simulation operation; A parsing module for offline parsing the simulation signal data stored in the hard disk to obtain the correspondence between the request data and the response result in the simulation signal data; An integrity detection module for performing integrity detection of the simulation signal data according to the correspondence between the request data and the response result; The integrity detection module includes: An integrity detection sub-module for counting the request data with corresponding response results and the target request data without corresponding response results from all the request data according to the correspondence between the request data and the response result, and locating the position of the target request data in the simulation signal data; The integrity detection sub-module specifically includes: A concurrency unit for setting the concurrency number, which is used to control the number of query tasks executed simultaneously, and the query task is a task of finding the response result according to the request data; A query unit for sending the request data to the data tracking process for one of the query tasks executed simultaneously to obtain the completion signal of the current query task; A first completed unit for when the corresponding response result is found according to the first target field of the request data, the tracking process converts the completion signal into a completed signal.

9. An electronic device, characterized in that, It includes a processor and a memory, and the memory stores a program or instruction that can run on the processor. When the program or instruction is executed by the processor, the steps of the method according to any one of claims 1 to 7 are implemented.

10. A readable storage medium, characterized in that, When the instructions in the readable storage medium are executed by a processor of an electronic device, the electronic device is enabled to execute the method according to any one of claims 1 to 7 of the method claims.

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