Display device and electronic apparatus

Abstract

The invention discloses a display device and electronic equipment. The display device comprises data lines, the multiple data lines are arranged in the first direction and extend in the second direction, the first direction and the second direction intersect, the data lines comprise first data lines, the first data lines are electrically connected with first sub-pixel columns, the first sub-pixel columns comprise first sub-pixels and second sub-pixels which are alternately arranged in the second direction, and the first sub-pixels are electrically connected with the second sub-pixels. The first sub-pixels and the second sub-pixels in the same row are alternately arranged in the first direction, the first sub-pixels and the second sub-pixels are different in light emitting color, and a first transistor is electrically connected between at least two first data lines; and the driving chip comprises a first signal end, the first signal end is electrically connected with the first data line, and when the first transistor is conducted, the first signal end does not output the data signal. According to the display device and the electronic equipment provided by the embodiment of the invention, the power consumption of the driving chip in the display device can be reduced.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display device and an electronic device. Background Art

[0002] With the development of display technology, the application of display devices is becoming more and more common, and users have more and more performance requirements for display devices. For example, users hope that display devices have longer battery life. Therefore, how to reduce the power consumption of display devices and improve the battery life of display devices is a technical problem faced by those skilled in the art. Summary of the invention

[0003] Embodiments of the present application provide a display device and an electronic device, which can reduce the power consumption of a driving chip in the display device.

[0004] In a first aspect, an embodiment of the present application provides a display device, comprising: a data line, a plurality of data lines are arranged in a first direction, the data lines extend along a second direction, the first direction and the second direction intersect, the data lines include a first data line, the first data line is electrically connected to a first sub-pixel column, the first sub-pixel column includes a first sub-pixel and a second sub-pixel alternately arranged in the second direction, and the first sub-pixel and the second sub-pixel in the same row are alternately arranged in the first direction, the first sub-pixel and the second sub-pixel have different luminous colors, and a first transistor is electrically connected between at least two first data lines; a driving chip, comprising a first signal terminal, the first signal terminal is electrically connected to the first data line, and when the first transistor is turned on, the first signal terminal does not output a data signal.

[0005] In a second aspect, an embodiment of the present application provides an electronic device, comprising a display device as described in the embodiment of the first aspect.

[0006] According to the display device and electronic device provided by the embodiments of the present application, when the first transistor is turned on, the two first data lines are short-circuited, so that the charges on the two first data lines are first shared, and then the drive signal provides charges to charge or discharge the two first data lines, thereby achieving the target data voltage required by each, which can reduce the amount of charge output by the driver chip, thereby reducing the power consumption of the driver chip and improving the battery life of the display device. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Other features, objects and advantages of the present application will become more apparent by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals represent the same or similar features and the accompanying drawings are not drawn to scale.

[0008] Figure 1 A schematic diagram showing a structure of a display device provided in an embodiment of the present application is shown;

[0009] Figure 2 A timing diagram of a display device provided by an embodiment of the present application is shown;

[0010] Figure 3 Another schematic diagram showing the structure of the display device provided by the embodiment of the present application is shown;

[0011] Figure 4 Another structural schematic diagram of a display device provided in an embodiment of the present application is shown;

[0012] Figure 5 Another structural schematic diagram of a display device provided in an embodiment of the present application is shown;

[0013] Figure 6 A schematic diagram showing a working mode of a display device provided in an embodiment of the present application is shown;

[0014] Figure 7 A schematic diagram showing another working mode of the display device provided in an embodiment of the present application;

[0015] Figure 8 Another timing diagram of the display device provided by the embodiment of the present application is shown;

[0016] Fig. 9 A schematic diagram showing a circuit structure of a sub-pixel in a display device provided in an embodiment of the present application is shown;

[0017] Fig.10 Show Fig. 9 A timing diagram of

[0018] Fig.11 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0019] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain the present application and are not configured to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.

[0020] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0021] It should be understood that when describing the structure of a component, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may mean that it is directly on the other layer or another region, or that other layers or regions are included between it and the other layer or another region. Moreover, if the component is turned over, the layer or a region will be "below" or "beneath" another layer or another region.

[0022] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0023] In the embodiments of the present application, the term “electrically connected” may refer to a direct electrical connection between two components, or may refer to an electrical connection between two components via one or more other components.

[0024] It is obvious to those skilled in the art that various modifications and changes can be made in the present application without departing from the spirit or scope of the present application. Therefore, the present application is intended to cover modifications and changes of the present application that fall within the scope of the corresponding claims (technical solutions for protection) and their equivalents. It should be noted that the implementation methods provided in the embodiments of the present application can be combined with each other without contradiction.

[0025] Embodiments of the present application provide a display device and an electronic device. Embodiments of the display device and the electronic device will be described below in conjunction with the accompanying drawings.

[0026] like Figure 1 As shown, the display device 100 provided in the embodiment of the present application includes a data line 10 , a sub-pixel 20 and a driving chip 30 .

[0027] The driving chip 30 is used to output a data signal. The data signal output by the driving chip is transmitted to the sub-pixel 20 via the data line 10. The sub-pixel 20 emits light or is in a black state according to the received data signal.

[0028] A plurality of data lines 10 are arranged in a first direction X, and the data lines 10 extend along a second direction Y, and the first direction X intersects with the second direction Y. For example, the first direction X is a row direction, and the second direction Y is a column direction.

[0029] The plurality of sub-pixels 20 are arranged in an array in a first direction X and a second direction Y. The display device includes a first sub-pixel column 20a, and the first sub-pixel column 20a includes first sub-pixels 21 and second sub-pixels 22 alternately arranged in the second direction Y, and the first sub-pixels 21 and the second sub-pixels 22 have different luminous colors. The first sub-pixels 21 and the second sub-pixels 22 in the same row are arranged in an overlapping manner in the first direction X.

[0030] Exemplarily, one of the first sub-pixel 21 and the second sub-pixel 22 is a red sub-pixel, and the other is a blue sub-pixel.

[0031] The data line 10 includes a first data line 11, which is electrically connected to the first sub-pixel column 20a. The first data line 11 is electrically connected to the first sub-pixel 21 and the second sub-pixel 22, and transmits the data signals required by the first sub-pixel 21 and the second sub-pixel 22 in a time-sharing manner.

[0032] The display device includes a plurality of first sub-pixel columns 20a arranged in a first direction X. The plurality of first sub-pixel columns 20a correspond one-to-one to a plurality of first data lines 11. A first transistor T1 is electrically connected between at least two first data lines 11.

[0033] A first electrode of the first transistor T1 is electrically connected to one of the first data lines 11, and a second electrode of the first transistor T2 is electrically connected to another first data line 11. A gate of the first transistor T1 is electrically connected to the first control signal line SW1.

[0034] Exemplarily, every two first data lines 11 form a first data line group, a first transistor T1 is electrically connected between two first data lines 11 in the same first data line group, and first data lines in different first data line groups are not connected. For example, the total number of first data lines 11 is 2m, the total number of first transistors T1 is m, and a first transistor T1 is electrically connected between every two first data lines 11.

[0035] The driving chip 30 includes a first signal terminal 31, which is electrically connected to the first data line 11. The first signal terminal 31 is used to output data signals required by the first sub-pixel 21 and the second sub-pixel 22. When the first transistor T1 is turned on, the first signal terminal 31 does not output data signals.

[0036] Exemplarily, the display device includes a display area AA and a non-display area NA, the sub-pixel 10 is located in the display area AA, and the first transistor T1 is located in the non-display area NA.

[0037] The gates of multiple first transistors T1 are electrically connected to the same first control signal line SW1, and the first control signal line SW1 is electrically connected to the driving chip 30 (not shown in the figure). The driving chip 30 outputs a first control signal which is transmitted to the gate of the first transistor T1 via the first control signal line SW1, thereby controlling the state of the first transistor T1.

[0038] When the first transistor T1 is turned on, the two first data lines 11 connected to the first transistor T1 are connected, the charges on the two first data lines 11 are shared, and the voltages on the two first data lines 11 are pulled to an average position. For example, the initial voltages on the two first data lines 11 are V1 and V2, respectively, V1 is greater than V2, the first transistor T1 is turned on, the voltage on the first data line 11 with the initial voltage V1 is pulled down to V1-((V1-V2) / 2), and the voltage on the first data line 11 with the initial voltage V2 is pulled up to V2+((V1-V2) / 2).

[0039] The following takes the case where the first sub-pixel 21 is a red sub-pixel, the second sub-pixel 22 is a blue sub-pixel, and the display device needs to display a pure red image as an example to describe the working process of the display device.

[0040] When displaying a pure red image, the target data voltage required by the first sub-pixel 21 is, for example, 3.5V, and the target data voltage required by the second sub-pixel 22 is, for example, 7V (7V is the black state voltage of the second sub-pixel 22). Figure 1 From left to right in the figure, the first first data line to the last first data line are arranged respectively. In one frame, the sub-pixels of each row are scanned row by row from top to bottom. In the scanning stage corresponding to each row of sub-pixels, the voltage of the first first data line 11_1 in one frame needs to be 3.5V, 7V, 3.5V, 7V...3.5V, 7V, and the voltage of the second first data line 11_2 in one frame needs to be 7V, 3.5V, 7V...7V, 3.5V.

[0041] The first transistor may be turned on before each row of sub-pixels is scanned, wherein when the sub-pixels are scanned, the signal on the data line is written into the sub-pixels.

[0042] Please refer to Figure 1 and Figure 2, along the second direction Y and in the direction close to the driving chip 30, the first row of sub-pixels to the last row of sub-pixels are arranged in sequence. Taking the second row of sub-pixels as an example, before scanning the second row of sub-pixels, the first transistor T1 is turned on in time period d1, and the time period d0 before the time period d1 is the time period after the first row of sub-pixels are scanned, and the time period d2 after the time period d1 includes the time period when the second row of sub-pixels are scanned.

[0043] In the period d0 , the voltage of the first first data line 11_1 is 3.5V, and the voltage of the second first data line 11_2 is 7V.

[0044] In the period d1 , the first transistor T1 is turned on, and the charge is shared between the first first data line 11_1 and the second first data line 11_2 . The voltage of the first first data line 11_1 is pulled up to 5.25V, and the voltage of the second first data line 11_2 is pulled down to 5.25V.

[0045] In time period d2, the first transistor T1 is turned off, the first signal terminal 31 of the driving chip 30 outputs a 7V voltage to the first first data line 11_1 and a 3.5V voltage to the second first data line 11_2, the voltage of the first first data line 11_1 is charged from 5.25V to 7V, and the voltage of the second first data line 11_2 is discharged from 5.25V to 3.5V.

[0046] If the first transistor does not short-circuit the first data line 11_1 and the second data line 11_2 in the time period d1, the voltage provided by the first signal terminal 31 of the driving chip 30 needs to charge the voltage of the first data line 11_1 from 3.5V to 7V, and discharge the voltage of the second data line 11_2 from 7V to 3.5V. It can be seen that when the first transistor short-circuits the first data line 11_1 and the second data line 11_2 in the time period d1, the charges on the two first data lines are first shared, and then the driving signal provides the charges to charge or discharge the two first data lines, so as to achieve the target data voltages required by each, and the amount of charge output by the driving chip can be reduced, thereby reducing the power consumption of the driving chip and improving the endurance of the display device.

[0047] In some embodiments, Figure 1 As shown, the data line 10 further includes a second data line 12, the second data line 12 is electrically connected to the second sub-pixel column 20b, and the second sub-pixel column 20b includes a plurality of third sub-pixels 23 arranged in the second direction Y. The first sub-pixel 21, the second sub-pixel 22, and the third sub-pixel 23 have different luminous colors. For example, one of the first sub-pixel 21 and the second sub-pixel 22 is a red sub-pixel, and the other is a blue sub-pixel; the third sub-pixel 23 is a green sub-pixel.

[0048] Exemplarily, in two adjacent rows of sub-pixels, the arrangement order of the sub-pixels in one row is: first sub-pixel, third sub-pixel, second sub-pixel, third sub-pixel; the arrangement order of the sub-pixels in the other row is: second sub-pixel, third sub-pixel, first sub-pixel, third sub-pixel. For example, the arrangement order of the sub-pixels in one row is RGBG, and the arrangement order of the sub-pixels in the other row is GBRG, where RGB represents red sub-pixels, green sub-pixels, and blue sub-pixels, respectively.

[0049] The driving chip 30 further includes a second signal terminal 32 , which is electrically connected to the second data line 12 . When the first transistor T1 is turned on, the second signal terminal 32 outputs a data signal.

[0050] The second data lines 12 are electrically connected to sub-pixels of the same luminous color, and when displaying a pure red image or a pure blue image, there is no voltage jump in the second data lines 12. Therefore, charge sharing between different second data lines 12 is not required.

[0051] When the first transistor T1 is turned on, the second signal terminal 32 still outputs a data signal, and the data signal charges the second data line 12 , thereby increasing the charging time of the third sub-pixel 23 and ensuring that the data voltage of the third sub-pixel 23 can be fully written.

[0052] In some embodiments, Figure 3 or Figure 4 As shown, the second data line 12 is connected to a compensation structure 4 , and the compensation structure 4 is used to compensate for the load of the second data line 12 .

[0053] When displaying a white screen, the first transistor T1 is turned off. However, the first transistor T1 connected to the first data line 11 will constitute a load of the first data line 11. If the second data line 12 does not add a load compensation structure, the loads on the first data line 11 and the second data line 12 will be different, resulting in uneven display.

[0054] In this embodiment, the second data line is connected to a load compensation structure to balance the loads of the first data line and the second data line, thereby improving display uniformity.

[0055] Exemplarily, the compensation structure is located in the non-display area. For example, the compensation structure is located on a side of the display area close to the driver chip.

[0056] As an example, Figure 3 As shown, the compensation structure 4 includes a second transistor T2, and the second transistor T2 is electrically connected between at least two second data lines 12, and the second transistor T2 remains in a disconnected state.

[0057] The first electrode of the second transistor T2 is connected to one of the second data lines 12, the second electrode of the second transistor T2 is connected to the other second data line 12, the gate of the second transistor T2 is connected to the second control signal line SW2, and the signal on the second control signal line SW2 is maintained at a non-enable level (for example, the second transistor is a P-type transistor, and the non-enable level is a high level).

[0058] Exemplarily, every two first data lines 11 form a first data line group, a first transistor T1 is electrically connected between the two first data lines 11 in the same first data line group, and first data lines in different first data line groups are not connected; similarly, every two second data lines 12 form a second data line group, a second transistor T2 is electrically connected between the two second data lines 12 in the same second data line group, and second data lines in different second data line groups are not connected.

[0059] Exemplarily, the characteristics of the first transistor T1 and the second transistor T2 are the same. For example, both are P-type transistors and have the same size, where "size" includes channel width-to-length ratio, channel area, channel length, channel width, etc.

[0060] As another example, Figure 4 As shown, the compensation structure 4 includes a capacitor C1, and the other end of the capacitor C1 is electrically connected to a fixed signal terminal, such as a power signal terminal PVDD, a common signal terminal PVEE, a reference signal terminal Vref, a high level signal terminal VGH, a low level signal terminal VGL, and the like.

[0061] Exemplarily, the capacitance of capacitor C1 is set according to requirements.

[0062] As described in the above embodiment, when the first transistor T1 is turned on, the first signal terminal 31 of the driving chip does not output a data signal, but the second signal terminal 32 still outputs a data signal.

[0063] In some embodiments, the display device 100 further includes a first demultiplexing circuit 51 and a second demultiplexing circuit 52 .

[0064] An input terminal of the first demultiplexing circuit 51 is electrically connected to the first signal terminal 31 , and a plurality of output terminals of the first demultiplexing circuit 51 are electrically connected to a plurality of first data lines 11 in a one-to-one correspondence.

[0065] An input terminal of the second demultiplexing circuit 52 is electrically connected to the second signal terminal 32 , and a plurality of output terminals of the second demultiplexing circuit 52 are electrically connected to a plurality of second data lines 12 in a one-to-one correspondence.

[0066] The first demultiplexing circuit 51 and the second demultiplexing circuit 52 each include an input terminal and multiple output terminals, so that a first signal terminal can output data signals to multiple first data lines in a time-sharing manner through the first demultiplexing circuit, and a second signal terminal can output data signals to multiple second data lines in a time-sharing manner through the second demultiplexing circuit, thereby reducing the number of signal terminals of the driving chip and reducing the cost of the driving chip.

[0067] As an example, the first demultiplexing circuit 51 includes a third transistor T3 and a fourth transistor T4, a first electrode of the third transistor T3 and a first electrode of the fourth transistor T4 are electrically connected to the first signal terminal 31, and a second electrode of the third transistor T3 and a second electrode of the fourth transistor T4 are respectively electrically connected to different first data lines 11. The third transistor T3 and the fourth transistor T4 are turned on in time division.

[0068] The second demultiplexing circuit 52 includes a fifth transistor T5 and a sixth transistor T6, wherein a first electrode of the fifth transistor T5 and a first electrode of the sixth transistor T6 are electrically connected to the second signal terminal 32, and a second electrode of the fifth transistor T5 and a second electrode of the sixth transistor T6 are electrically connected to different second data lines 12. The fifth transistor T5 and the sixth transistor T6 are turned on in time division.

[0069] In addition, when the first transistor T1 is turned on, the third transistor T3 and the fourth transistor T4 are turned off, and the fifth transistor T5 and the sixth transistor T6 are turned on in time division. In this way, the data signal output by the second signal terminal 32 can be transmitted to different second data lines 12 in time division through the fifth transistor T5 and the sixth transistor T6.

[0070] In some embodiments, Figure 6 or Figure 7 As shown, the display device includes a plurality of sub-pixel rows 20c arranged in the second direction Y. The operation process of the display device includes a first mode and a second mode. The sub-pixel row operating in the first mode is a first sub-pixel row 20c1, and the sub-pixel row operating in the second mode is a second sub-pixel row 20c2. c The turn-on time length of the first transistor corresponding to the second sub-pixel row 20c1 is the first time length, the turn-on time length of the first transistor corresponding to the second sub-pixel row 20c2 is the second time length, and the first time length is not equal to the second time length.

[0071] For example, in a frame, each row of sub-pixels is scanned row by row from top to bottom. In the scanning phase corresponding to each row of sub-pixels, the first transistor may be turned on before each row of sub-pixels is scanned. c1, can be understood as: the on-time length of the first transistor before the first sub-pixel row 20c1 is scanned. The on-time length of the first transistor corresponding to the second sub-pixel row 20c2 can be understood as: the on-time length of the first transistor before the second sub-pixel row 20c2 is scanned. c 1 includes the second row of sub-pixels, and the turn-on time length of the first transistor corresponding to the second row of sub-pixels is: the turn-on time length of the first transistor before the second row of sub-pixels are scanned and after the first row of sub-pixels are scanned.

[0072] In this embodiment, in different modes, the conduction time of the first transistor is different, which can flexibly adapt to different requirements of different modes to achieve better power saving effect.

[0073] As an example, Figure 6 As shown, the first sub-pixel row 20c1 and the second sub-pixel row 20c2 are sub-pixel rows at different positions.

[0074] For example, the display area of ​​the display device includes a first display area A1 and a second display area A2, the sub-pixel row in the first display area A1 is a first sub-pixel row 20c1, and the sub-pixel row in the second display area A2 is a second sub-pixel row 20c2.

[0075] For example, the first display area A1 and the second display area A2 display different images. For example, the first display area A1 displays a pure red image with a gray scale of 100, and the second display area A2 displays a pure red image with a gray scale of 200.

[0076] As another example, Figure 7 As shown, the first sub-pixel row 20c1 is a sub-pixel row in the first frame, and the second sub-pixel row 20c2 is a sub-pixel row in the second frame.

[0077] For example, in the first frame, all sub-pixel rows of the display device display a pure red image with a grayscale of 255; in the second frame, all sub-pixel rows of the display device display a pure red image with a grayscale of 100; when displaying the first frame, all sub-pixel rows of the display device serve as the first sub-pixel row 20 c 1; when displaying the second frame, all sub-pixel rows of the display device are used as the second sub-pixel rows 20c2.

[0078] As another example, the first sub-pixel row is refreshed at a first refresh frequency, and the second sub-pixel row is refreshed at a second refresh frequency. The first refresh frequency and the second refresh frequency are different.

[0079] For example, Figure 6 As shown, the first subpixel row 20 cThe first sub-pixel row 20c1 and the second sub-pixel row 20c2 are sub-pixel rows at different positions, and the first sub-pixel row 20c1 and the second sub-pixel row 20c2 are refreshed at different refresh frequencies.

[0080] For example, the display area of ​​the display device includes a first display area A1 and a second display area A2, the sub-pixel row in the first display area A1 is a first sub-pixel row 20c1, and the sub-pixel row in the second display area A2 is a second sub-pixel row 20c2.

[0081] Example 1: The first display area A1 and the second display area A2 display the same pure color picture, and the first display area A1 and the second display area A2 have different refresh rates. For example, the first display area A1 and the second display area A2 both display a 200 grayscale pure red picture, the refresh rate of the first display area A1 is 90HZ, and the refresh rate of the second display area A2 is 15HZ.

[0082] Example 2: The display images of the first display area A1 and the second display area A2 are different, and the refresh frequencies of the first display area A1 and the second display area A2 are different. For example, the first display area A1 displays a pure red image with a grayscale of 50, and the second display area A2 displays a pure red image with a grayscale of 150. The refresh frequencies of the first display area A1 and the second display area A2 are 120 Hz and 30 Hz, respectively.

[0083] For example, Figure 7 As shown, the first sub-pixel row 20c1 is a sub-pixel row in the first frame, and the second sub-pixel row 20c2 is a sub-pixel row in the second frame, and the first sub-pixel row 20c1 and the second sub-pixel row 20c2 are refreshed at different refresh frequencies.

[0084] Example 3: The grayscale images of the first frame and the second frame are the same (for example, both are 210 grayscale pure red images). In the first frame, all sub-pixel rows of the display device are scanned at a refresh rate of 90 Hz; in the second frame, all sub-pixel rows of the display device are scanned at a refresh rate of 60 Hz. When displaying the first frame, all sub-pixel rows of the display device are used as the first sub-pixel row 20 c 1; when displaying the second frame, all sub-pixel rows of the display device are used as the second sub-pixel rows 20c2.

[0085] Example 4: The grayscale images of the first frame and the second frame are different and have different refresh frequencies. In the first frame, all sub-pixel rows of the display device display a 15-grayscale pure red image and are scanned at a refresh frequency of 15HZ; in the second frame, all sub-pixel rows of the display device display a 90-grayscale pure red image and are scanned at a refresh frequency of 60HZ. When displaying the first frame, all sub-pixel rows of the display device serve as the first sub-pixel row 20c1; when displaying the second frame, all sub-pixel rows of the display device serve as the second sub-pixel row 20c2.

[0086] In some embodiments, the first sub-pixel row is refreshed at a first refresh frequency, the second sub-pixel row is refreshed at a second refresh frequency, and when the first refresh frequency is less than the second refresh frequency, the first duration is greater than the second duration.

[0087] The smaller the refresh frequency is, the longer the scanning time allocated to the sub-pixel row is. In this case, the turn-on time of the first sub-pixel can be appropriately lengthened to ensure better charge sharing between the first data lines.

[0088] The higher the refresh frequency, the shorter the scanning time allocated to the sub-pixel row. In this case, the on-time of the first sub-pixel can be appropriately shortened to ensure that there is enough time for the signal on the first data line to be fully written into the sub-pixel.

[0089] In some embodiments, Figure 1 As shown, the display device includes a plurality of sub-pixel rows 20c arranged in the second direction Y; the sub-pixel rows include a next sub-pixel row and a previous sub-pixel row; after the previous sub-pixel row is scanned, the next sub-pixel row is scanned.

[0090] The kth first transistor is electrically connected between the i-th first data line and the j-th first data line.

[0091] The data voltages that need to be written into the first subpixel and the second subpixel in the next subpixel row and electrically connected to the kth first transistor are the first target data voltage and the second target data voltage, respectively; the data voltages that have been written into the second subpixel and the first subpixel in the previous subpixel row and electrically connected to the kth first transistor are the first current data voltage and the second current data voltage, respectively; the difference between the first target data voltage and the first current data voltage corresponding to the i-th first data line is the first difference, and the difference between the second target data voltage and the second current data voltage corresponding to the j-th first data line is the second difference; the larger the sum of the absolute value of the first difference and the absolute value of the second difference, the longer the conduction time of the kth first transistor after the previous subpixel row is scanned and before the current subpixel row is scanned.

[0092] Please refer to Figure 1 and Figure 8For example, the previous sub-pixel row is the first sub-pixel row 20c_1, the next sub-pixel row is the second sub-pixel row 20c_2, the i-th first data line 11_i is the first first data line 11_1, the j-th first data line 11_j is the second first data line 11_2, and the k-th first transistor T1 is electrically connected between the first first data line 11_1 and the second first data line 11_2. _ k.

[0093] In the first sub-pixel row 20c _ 1 is scanned, the voltage on the first first data line 11_1 is the first current data voltage V1_current, and the voltage on the second first data line 11_2 is the second current data voltage V2_current. The sub-pixels connected to the first first data line 11_1 in the second sub-pixel row 20c_2 need to be written with the first target data voltage V1_target, and the sub-pixels connected to the second first data line 11_2 in the second sub-pixel row 20c_2 need to be written with the second target data voltage V2_target, the first difference ΔV1=V1_target-V1_current, and the second difference ΔV2=V2_target-V2current.

[0094] For example, V1_target>V1_current, V2_target<V2_current, the greater the sum of the absolute value of the first difference ΔV1 and the absolute value of the second difference ΔV2, the more the voltage on the first first data line 11_1 needs to be pulled up, and the more the voltage on the second first data line 11_2 needs to be pulled down. In this embodiment, the greater the sum of the absolute value of the first difference ΔV1 and the absolute value of the second difference ΔV2, the greater the conduction time of the corresponding first transistor is designed, so that there is a longer time for charge sharing between the two first data lines, thereby better ensuring that the voltages of the two first data lines are pulled to an average level, so as to reduce the amount of charge required to be output by the driver chip, thereby reducing the power consumption of the driver chip.

[0095] In some embodiments, Figure 1 As shown, the display device includes a plurality of sub-pixel rows 20c arranged in the second direction Y.

[0096] Please refer to Figure 1 , Fig. 9 and Fig.10 Each subpixel in the subpixel row is electrically connected to the first scan line S1, and when the first scan signal of the first scan line S1 is at the on level, the signal on the data line 10 is written into the subpixel. The on time of the first transistor is less than the on level time of the first scan signal.

[0097] Exemplarily, the sub-pixel is also electrically connected to the second scan line S2 and the light emitting control signal line Emit. The following takes the example that the first transistor and the transistors in the sub-pixel are all P-type transistors to illustrate the working process of the sub-pixel.

[0098] Please refer to Fig. 9 and Fig.10 The working process of the sub-pixel includes stage t1, stage t2, and stage t3.

[0099] In phase t1 , the signal on the second scan line S2 is at a low level, the transistor M5 in the sub-pixel is turned on, and the reset signal at the reset signal terminal Vref resets the gate of the driving transistor M3 .

[0100] In phase t2, the signal on the first scan line S1 is at a low level, the transistors M2 and M4 are turned on, the data signal on the data line 10 is written into the gate of the driving transistor M3, and the transistor M4 compensates for the threshold voltage of the driving transistor M3.

[0101] In phase t3, the signal on the light-emitting control signal line Emit is at a low level, transistors M1 and M6 are turned on, driving transistor M3 to generate a driving current, and the sub-pixel enters the light-emitting phase. When the driving current is not zero, the sub-pixel emits light. When the driving current is zero, the sub-pixel is in a black state.

[0102] The first transistor may be turned on at phase t0 , for example, phase t0 is before phase t1 .

[0103] The duration of phase t0 is shorter than the duration of phase t2.

[0104] In phase t2, the data signal of the data line is written into the sub-pixel. If the time in phase t2 is longer, the sufficiency of the data signal writing can be guaranteed to avoid affecting the luminous effect of the sub-pixel.

[0105] The present application also provides an electronic device, including the display device provided by the present application. Fig.11 , Fig.11 It is a structural schematic diagram of a display device provided in an embodiment of the present application. Fig.11 The provided electronic device 1000 includes the display device 100 provided by any of the above embodiments of the present application. Fig.11 The embodiment only takes a mobile phone as an example to illustrate the electronic device 1000. It can be understood that the electronic device provided in the embodiment of the present application can be a wearable product, a computer, a television, a car display device, or other electronic devices with display functions, and the present application does not specifically limit this. The electronic device provided in the embodiment of the present application has the beneficial effects of the display device provided in the embodiment of the present application. For details, please refer to the specific description of the display device in the above embodiments, and this embodiment will not be repeated here.

[0106] According to the embodiments described above in the present application, these embodiments do not describe all the details in detail, nor do they limit the present application to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and the modifications based on the present application. The present application is limited only by the claims and their full scope and equivalents.

Claims

1. A display device, characterized in that: include: Data lines, a plurality of the data lines are arranged in a first direction, the data lines extend along a second direction, the first direction and the second direction intersect, the data lines include a first data line, the first data line is electrically connected to a first sub-pixel column, the first sub-pixel column includes a first sub-pixel and a second sub-pixel alternately arranged in the second direction, and the first sub-pixels and the second sub-pixels in the same row are alternately arranged in the first direction, the first sub-pixels and the second sub-pixels have different luminous colors, and a first transistor is electrically connected between at least two of the first data lines; The driving chip comprises a first signal terminal, wherein the first signal terminal is electrically connected to the first data line, and when the first transistor is turned on, the first signal terminal does not output a data signal.

2. The display device according to claim 1, characterized in that The data line further includes a second data line, the second data line is electrically connected to a second sub-pixel column, and the second sub-pixel column includes a plurality of third sub-pixels arranged in the second direction; The driving chip further includes a second signal terminal, the second signal terminal is electrically connected to the second data line, and when the first transistor is turned on, the second signal terminal outputs a data signal.

3. The display device according to claim 2, characterized in that: The second data line is connected to a compensation structure, and the compensation structure is used to compensate for a load of the second data line.

4. The display device according to claim 3, characterized in that: The compensation structure includes a second transistor, the second transistor is electrically connected between at least two of the second data lines, and the second transistor remains in a disconnected state.

5. The display device according to claim 3, characterized in that: The compensation structure includes a capacitor, and the other end of the capacitor is electrically connected to the fixed signal end.

6. The display device according to claim 2, characterized in that: The display device further includes: a first demultiplexing circuit, wherein an input terminal of the first demultiplexing circuit is electrically connected to the first signal terminal, and a plurality of output terminals of the first demultiplexing circuit are electrically connected to a plurality of the first data lines in a one-to-one correspondence; A second demultiplexing circuit, wherein an input terminal of the second demultiplexing circuit is electrically connected to the second signal terminal, and a plurality of output terminals of the second demultiplexing circuit are electrically connected to a plurality of second data lines in a one-to-one correspondence.

7. The display device according to claim 1, characterized in that: The display device comprises a plurality of sub-pixel rows arranged in the second direction, the sub-pixel rows comprising first sub-pixels and second sub-pixels alternately arranged in the first direction; The operation process of the display device includes a first mode and a second mode, the sub-pixel row operating in the first mode is a first sub-pixel row, the sub-pixel row operating in the second mode is a second sub-pixel row, the turn-on time of the first transistor corresponding to the first sub-pixel row is a first time, the turn-on time of the first transistor corresponding to the second sub-pixel row is a second time, and the first time is not equal to the second time.

8. The display device according to claim 7, characterized in that: The first sub-pixel row and the second sub-pixel row are sub-pixel rows at different positions.

9. The display device according to claim 7, characterized in that: The first sub-pixel row is a sub-pixel row in a first frame, and the second sub-pixel row is a sub-pixel row in a second frame.

10. The display device according to claim 7, characterized in that: The first sub-pixel row is refreshed at a first refresh frequency, and the second sub-pixel row is refreshed at a second refresh frequency.

11. The display device according to claim 10, characterized in that: The first refresh frequency is lower than the second refresh frequency, and the first duration is greater than the second duration.

12. The display device according to claim 1, characterized in that: The display device comprises a plurality of sub-pixel rows arranged in the second direction, wherein the first sub-pixels and the second sub-pixels in the sub-pixel rows are alternately arranged in the first direction; The sub-pixel row includes a next sub-pixel row and a previous sub-pixel row; After the previous sub-pixel row is scanned, the next sub-pixel row is scanned; The kth first transistor is electrically connected between the i-th first data line and the j-th first data line; The data voltages to be written into the first sub-pixel and the second sub-pixel in the next sub-pixel row and electrically connected to the kth first transistor are respectively the first target data voltage and the second target data voltage; The data voltages written into the second sub-pixel and the first sub-pixel in the previous sub-pixel row and electrically connected to the kth first transistor are respectively the first current data voltage and the second current data voltage; The difference between the first target data voltage and the first current data voltage corresponding to the i-th first data line is a first difference, and the difference between the second target data voltage and the second current data voltage corresponding to the j-th first data line is a second difference; The larger the sum of the absolute value of the first difference and the absolute value of the second difference is, the longer the turn-on time of the kth first transistor is after the previous sub-pixel row is scanned and before the current sub-pixel row is scanned.

13. The display device according to claim 1, characterized in that The display device comprises a plurality of sub-pixel rows arranged in the second direction, wherein the first sub-pixels and the second sub-pixels in the sub-pixel rows are alternately arranged in the first direction; The sub-pixel row is electrically connected to a first scan line, and when a first scan signal of the first scan line is at an on level, a signal on the data line is written into the sub-pixel; The on-time of the first transistor is shorter than the on-time of the first scanning signal.

14. An electronic device, characterized in that: The invention comprises a display device as claimed in any one of claims 1 to 13.

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