Micro LED display device

Abstract

The present invention discloses a micro-LED display device, which includes a display panel and a plurality of micro-LED driving circuits. The display panel includes a plurality of pixels. Each micro-LED driving circuit is respectively coupled to at least one pixel of the display panel. The plurality of micro-LED driving circuits include a first micro-LED driving circuit and a second micro-LED driving circuit connected in series with each other. The first micro-LED driving circuit receives a zeroth data signal, a zeroth enable signal and a zeroth clock signal and outputs a first data signal, a first enable signal and a first clock signal to the second micro-LED driving circuit. The zeroth clock signal and the first clock signal are inverted to each other and the phase difference between the zeroth data signal and the first data signal is less than one clock signal cycle.

Description

Technical Field

[0001] The present invention relates to a display device, and in particular to a micro light emitting diode (uLED) display device. Background Art

[0002] Please refer to Figure 1 In the conventional micro-LED display device 1, the column input signal COL inputted to the display panel PL in the vertical direction is a data signal, and the row input signal ROW inputted to the display panel PL in the horizontal direction is a clock signal. When the column input signal COL and the row input signal ROW are transmitted to the display panel PL having a high resistance value (such as a glass substrate), their waveforms are affected by parasitic resistance and capacitance and distorted, resulting in the conventional uLED display system 1 being unable to operate smoothly at high frequencies, thereby limiting the resolution and size of the display panel PL. Summary of the invention

[0003] Therefore, the present invention proposes a micro light emitting diode display device to effectively solve the above problems encountered in the prior art.

[0004] A preferred specific embodiment of the present invention is a micro-LED display device. In this embodiment, the micro-LED display device includes a display panel and a plurality of micro-LED driving circuits. The display panel includes a plurality of pixels. Each micro-LED driving circuit is respectively coupled to at least one pixel of the display panel. The plurality of micro-LED driving circuits include a first micro-LED driving circuit and a second micro-LED driving circuit connected in series with each other. The first micro-LED driving circuit receives a zeroth data signal, a zeroth enable signal and a zeroth clock signal and outputs a first data signal, a first enable signal and a first clock signal to the second micro-LED driving circuit. The zeroth clock signal and the first clock signal are inverted to each other and the phase difference between the zeroth data signal and the first data signal is less than one clock signal cycle.

[0005] In one embodiment, the micro LED display device further includes: a data driver coupled to the first micro LED driving circuit and providing a zeroth data signal, a zeroth enable signal and a zeroth clock signal to the first micro LED driving circuit.

[0006] In one embodiment, the first micro LED driving circuit includes: a D-type flip-flop for generating a first data signal according to a zeroth data signal and a zeroth clock signal; and a gate for generating a first clock signal according to the zeroth clock signal.

[0007] In one embodiment, the phase difference between the positive edge or the negative edge of the zeroth clock signal and the zeroth data signal is between 0.3 and 0.7 clock signal cycles.

[0008] In one embodiment, the phase difference between the zeroth data signal and the first data signal is 0.5 clock signal period.

[0009] In one embodiment, the waveform of the zeroth clock signal changes from a low level to a high level and the waveform of the first clock signal changes from a high level to a low level.

[0010] In one embodiment, the waveform of the zeroth clock signal changes from a high level to a low level and the waveform of the first clock signal changes from a low level to a high level.

[0011] In one embodiment, the start time of the zeroth enable signal corresponds to the start time of the zeroth data cycle of the zeroth data signal, and the start time of the first enable signal corresponds to the start time of the first data cycle of the first data signal.

[0012] In one embodiment, the second micro-LED driving circuit receives a first data signal, a first enable signal and a first clock signal and outputs a second data signal, a second enable signal and a second clock signal, the first clock signal and the second clock signal are inverted to each other and the phase difference between the first data signal and the second data signal is less than one clock signal cycle.

[0013] In one embodiment, the second micro LED driving circuit includes: a D-type flip-flop for generating a second data signal according to a first data signal and a first clock signal; and a gate for generating a second clock signal according to the first clock signal.

[0014] In one embodiment, a phase difference between a positive edge or a negative edge of the first clock signal and the first data signal is between 0.3 and 0.7 clock signal cycles.

[0015] In one embodiment, the phase difference between the first data signal and the second data signal is 0.5 clock signal period.

[0016] In one embodiment, the waveform of the first clock signal changes from a low level to a high level and the waveform of the second clock signal changes from a high level to a low level.

[0017] In one embodiment, the waveform of the first clock signal changes from a high level to a low level and the waveform of the second clock signal changes from a low level to a high level.

[0018] In one embodiment, the start time of the second enable signal corresponds to the start time of the second data period of the second data signal.

[0019] Compared with the prior art, the micro-LED display device of the present invention divides the traditional row input signal (ROW) into an enable signal (EN) and a clock signal (CLK). When the enable signal (EN), the clock signal (CLK) and the data signal (DATA) are input together into a display panel PL (such as a glass substrate) having a high resistance value, the enable signal (EN), the clock signal (CLK) and the data signal (DATA) are sequentially transmitted to a plurality of micro-LED driving circuits connected in series, and the enable signal (EN) and the data signal (DATA) are re-timed in each micro-LED driving circuit to have the same delay and the clock signal (CLK) is inverted and transmitted to the next micro-LED driving circuit to avoid signal distortion due to parasitic resistance and capacitance, so that the micro-LED display device of the present invention can operate smoothly at high frequencies and the resolution and size of its display panel are not limited. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 Schematic diagram of a conventional micro light emitting diode display device.

[0021] Figure 2 FIG. 4 is a schematic diagram of a micro light emitting diode display device in a preferred embodiment of the present invention.

[0022] Figure 3 The diagram is a schematic diagram of signal transmission between a data driver and a micro-LED driving circuit connected in series with each other.

[0023] Figure 4 and Figure 5 They are timing diagrams of the zeroth data signal, the zeroth clock signal, the first data signal, and the first clock signal in different embodiments respectively.

[0024] Figure 6 and Figure 7 They are schematic diagrams of a first micro LED driving circuit and a second micro LED driving circuit respectively.

[0025] Figure 8 and Fig. 9 The timing diagrams are respectively the zeroth data signal, the zeroth enable signal, the zeroth clock signal, the row input signal, the first data signal, the first enable signal, the first clock signal, the second data signal, the second enable signal, and the second clock signal in different embodiments.

[0026] Description of main component symbols:

[0027] u I C00~u I Cmn…Micro LED driving circuit

[0028] uIC00~uIC77…Micro LED driver circuit

[0029] COL…column input signal

[0030] ROW...row input signal

[0031] DATA0…0th data signal

[0032] EN0…0th enable signal

[0033] CLK0…0th clock signal

[0034] DATA1…First data signal

[0035] EN1…First enable signal

[0036] CLK1…First clock signal

[0037] DATA2…Second data signal

[0038] EN2…Second enable signal

[0039] CLK2…Second clock signal

[0040] DATAI…Data signal input terminal

[0041] EN I…Enable signal input terminal

[0042] CLKI…clock signal input terminal

[0043] DATAO…data signal output terminal

[0044] ENO…Enable signal output terminal

[0045] CLKO…clock signal output terminal

[0046] D0…0th data cycle

[0047] D1…First data cycle

[0048] D2…Second data cycle

[0049] t0~t6…time

[0050] DFF…D-type flip-flop

[0051] CLK…Clock port

[0052] NOT...Reverse lock

[0053] DL0…0th data line data

[0054] DL1…First data line data

[0055] DL2…Second data line data

[0056] DL3…The third data line data

[0057] PX0…zeroth pixel data

[0058] PX1…First pixel data

[0059] PX2…Second pixel data

[0060] PX3…Third pixel data

[0061] I(L)…First data bit

[0062] I(M)…Second data bit

[0063] R0…0th red sub-pixel data

[0064] G0…zeroth green sub-pixel data

[0065] B0…zeroth blue sub-pixel data

[0066] R1…First red sub-pixel data

[0067] G1…First green sub-pixel data

[0068] B1…first blue sub-pixel data

[0069] R2…Second red sub-pixel data

[0070] G2…Second green sub-pixel data

[0071] B2…Second blue sub-pixel data

[0072] R3…The third red sub-pixel data

[0073] G3…The third green sub-pixel data

[0074] B3…The third blue sub-pixel data

[0075] D0[0]~D0[n], D1[0]~D1[n], D2[0]~D2[n], D3[0]~D3[n]…data bits DETAILED DESCRIPTION

[0076] A preferred embodiment of the present invention is a micro-LED display device. Figure 2 , Figure 2 This is a schematic diagram of a micro light emitting diode display device in this embodiment.

[0077] like Figure 2As shown, the micro-LED display device 2 includes a data driver DD, a display panel PL, and a plurality of micro-LED driving circuits uIC00-uIC77. The display panel PL includes a plurality of pixels (not shown). The plurality of micro-LED driving circuits uIC00-uIC77 are arranged in a (8*8) matrix form, but not limited thereto. Each of the micro-LED driving circuits uIC00-uIC77 is respectively coupled to at least one pixel of the display panel PL and is used to drive the at least one pixel (for example, 16 pixels, but not limited thereto).

[0078] In this embodiment, the plurality of micro LED driving circuits uIC00-uIC77 include a plurality of rows of micro LED driving circuits uIC00-uIC70, uIC01-uIC71, uIC02-uIC72, uIC03-uIC73, ..., uIC06-uIC76, uIC07-uIC77 connected in series.

[0079] The data driver DD is respectively coupled to the micro LED driving circuits u I C00, u I C01, u I C02, u I C03, …, u I C06, and u I C07 in the multiple micro LED driving circuits u I C00~u I C77, that is, the data driver DD is respectively coupled to the first micro LED driving circuit u I C00, u I C01, u I C02, u I C03, …, u I C06, and u I C07 in each row of micro LED driving circuits u I C00~u I C70, u I C01~u I C71, u I C02~u I C72, u I C03~u I C73, …, u I C06~u I C76, u I C07~u I C77, but is not limited to this.

[0080] like Figure 3 As shown, if the first row of micro LED driving circuits u I C00~u I C70 is taken as an example for explanation, the data driver DD is coupled to the data signal input terminal DATAI, the enable signal input terminal EN I and the clock signal input terminal CLKI of the micro LED driving circuit u I C00 and provides the zeroth data signal DATA0, the zeroth enable signal EN0 and the zeroth clock signal CLK0 to the data signal input terminal DATAI, the enable signal input terminal EN I and the clock signal input terminal CLKI of the first micro LED driving circuit u I C00 respectively.

[0081] When the data signal input terminal DATAI, the enable signal input terminal EN I and the clock signal input terminal CLKI of the first micro LED driving circuit u I C00 respectively receive the zeroth data signal DATA0, the zeroth enable signal EN0 and the zeroth clock signal CLK0, the data signal output terminal DATAO, the enable signal output terminal ENO and the clock signal output terminal CLKO of the first micro LED driving circuit u I C00 respectively output the first data signal DATA1, the first enable signal EN1 and the first clock signal CLK1 to the data signal input terminal DATAI, the enable signal input terminal EN I and the clock signal input terminal CLKI of the second micro LED driving circuit u I C10.

[0082] It should be noted that the zeroth clock signal CLK0 output by the data driver DD and the first clock signal CLK1 output by the first micro LED driving circuit u I C00 are inverted to each other, and the phase difference between the zeroth data signal DATA0 output by the data driver DD and the first data signal DATA1 output by the first micro LED driving circuit u I C00 is less than one clock signal cycle.

[0083] Similarly, when the data signal input terminal DATAI, the enable signal input terminal EN1 and the clock signal input terminal CLKI of the second micro LED driving circuit u I C10 receive the first data signal DATA1, the first enable signal EN1 and the first clock signal CLK1 respectively, the data signal output terminal DATAO, the enable signal output terminal ENO and the clock signal output terminal CLKO of the second micro LED driving circuit u I C10 respectively output the second data signal DATA2, the second enable signal EN2 and the second clock signal CLK2 to the next micro LED driving circuit (the third micro LED driving circuit u I C20). The rest can be deduced in the same way.

[0084] It should be noted that the first clock signal CLK1 output by the first micro LED driving circuit u I C00 and the second clock signal CLK2 output by the second micro LED driving circuit u I C10 are inverted to each other, and the phase difference between the first data signal DATA1 output by the first micro LED driving circuit u I C00 and the second data signal DATA2 output by the second micro LED driving circuit u I C10 is less than one clock signal cycle.

[0085] Please refer to Figure 4 and Figure 5 , Figure 4 and Figure 5They are timing diagrams of the zeroth data signal DATA0 , the zeroth clock signal CLK0 , the first data signal DATA1 , and the first clock signal CLK1 in different embodiments respectively.

[0086] like Figure 4 As shown, assuming that one clock signal cycle is from time t0 to t2, the phase difference between the positive edge or negative edge of the zeroth clock signal CLK0 and the zeroth data signal DATA0 can be between 0.3 and 0.7 clock signal cycles; the phase difference between the zeroth data signal DATA0 and the first data signal DATA1 is 0.5 clock signal cycles, that is, from time t0 to t1 or from time t1 to t2.

[0087] The zeroth clock signal CLK0 and the first clock signal CLK1 are in opposite phases. For example, during the period from time t0 to t2, the waveform of the zeroth clock signal CLK0 changes from a low level to a high level and the waveform of the first clock signal CLK1 changes from a high level to a low level; during the period from time t1 to t3, the waveform of the zeroth clock signal CLK0 changes from a high level to a low level and the waveform of the first clock signal CLK1 changes from a low level to a high level.

[0088] As for Figure 5 Although the zeroth clock signal CLK0 is also in opposite phase to the first clock signal CLK1, Figure 5 and Figure 4 The difference is that: during the period from t0 to t2, the waveform of the zeroth clock signal CLK0 changes from a high level to a low level and the waveform of the first clock signal CLK1 changes from a low level to a high level; during the period from t1 to t3, the waveform of the zeroth clock signal CLK0 changes from a low level to a high level and the waveform of the first clock signal CLK1 changes from a high level to a low level.

[0089] Figure 6 and Figure 7 They are schematic diagrams of the first micro LED driving circuit u I C00 and the second micro LED driving circuit u I C10 respectively.

[0090] like Figure 6 As shown, the first micro LED driving circuit uIC00 includes a D-type flip-flop DFF and a gate NOT. The D-type flip-flop DFF is used to generate a first data signal DATA1 according to the zeroth data signal DATA0 and the zeroth clock signal CLK0 and then output it. The phase difference between the zeroth data signal DATA0 and the first data signal DATA1 is less than one clock signal cycle. The gate NOT is used to generate a first clock signal CLK1 that is inverted to the zeroth clock signal CLK0 according to the zeroth clock signal CLK0 and then output it.

[0091] like Figure 7As shown, the second micro LED driving circuit uIC10 includes a D-type flip-flop DFF and a gate NOT. The D-type flip-flop DFF is used to generate a second data signal DATA2 according to the first data signal DATA1 from the first micro LED driving circuit uIC00 and the first clock signal CLK1 and then output it. The phase difference between the first data signal DATA1 and the second data signal DATA2 is less than one clock signal cycle. The gate NOT is used to generate a second clock signal CLK2 that is inverted to the first clock signal CLK1 according to the first clock signal CLK1 from the first micro LED driving circuit uIC00 and then output it. The rest can be deduced in the same way.

[0092] Please refer to Figure 8 and Fig. 9 , Figure 8 and Fig. 9 The timing diagrams of the zeroth data signal DATA0, the zeroth enable signal EN0, the zeroth clock signal CLK0, the row input signal ROW, the first data signal DATA1, the first enable signal EN1, the first clock signal CLK1, the second data signal DATA2, the second enable signal EN2, and the second clock signal CLK2 in different embodiments are shown in FIG. 1 , wherein the row input signal ROW is an internal row input signal generated according to the enable signal and the clock signal.

[0093] like Figure 8 As shown, the zeroth data signal DATA0 output by the data driver DD is the zeroth data signal DATA0 received by the first micro LED driving circuit u I C00. The first data signal DATA1 output by the first micro LED driving circuit u I C00 is the first data signal DATA1 received by the second micro LED driving circuit u I C10. The second data signal DATA2 output by the second micro LED driving circuit u I C10 is the second data signal DATA2 received by the third micro LED driving circuit u I C20. The rest can be deduced in the same way.

[0094] Similarly, the zeroth clock signal CLK0 output by the data driver DD is the zeroth clock signal CLK0 received by the first micro LED driving circuit uIC00. The first clock signal CLK1 output by the first micro LED driving circuit uIC00 is the first clock signal CLK1 received by the second micro LED driving circuit uIC10. The second clock signal CLK2 output by the second micro LED driving circuit uIC10 is the second clock signal CLK2 received by the third micro LED driving circuit uIC20. The rest can be deduced in the same way.

[0095] The zeroth data signal DATA0, the first data signal DATA1, and the second data signal DATA2 may sequentially include the zeroth data line data DL0, the zeroth pixel data PX0, the first data line data DL1, the first pixel data PX1, the second data line data DL2, the second pixel data PX2, the third data line data DL3, and the third pixel data PX3.

[0096] The zeroth data signal DATA0, the first data signal DATA1, and the second data signal DATA2 may all be five-bit data. The first data line data DL1, the second data line data DL2, and the third data line data DL3 may all be two-bit data, for example, the first data line data DL1, the second data line data DL2, and the third data line data DL3 may include a first data bit I (L) and a second data bit I (M).

[0097] The zeroth pixel data PX0, the first pixel data PX1 and the second pixel data PX2 may be three-bit data, for example, the zeroth pixel data PX0 may include the zeroth red sub-pixel data R0, the zeroth green sub-pixel data G0 and the zeroth blue sub-pixel data B0; the first pixel data PX1 may include the first red sub-pixel data R1, the first green sub-pixel data G1 and the first blue sub-pixel data B1; the second pixel data PX2 may include the second red sub-pixel data R2, the second green sub-pixel data G2 and the second blue sub-pixel data B2; the third pixel data PX3 may include the third red sub-pixel data R3, the third green sub-pixel data G3 and the third blue sub-pixel data B3. The rest may be deduced in the same manner.

[0098] The start time (positive edge) of the zeroth enable signal EN0 corresponds to the start time of the zeroth data line data DL0 of the zeroth data signal DATA0, which is time t0. The period during which the zeroth enable signal EN0 changes from a low level to a high level at time t0 and the zeroth enable signal EN0 remains at a high level is the period during which the first micro LED driving circuit uIC00 is activated.

[0099] After the first enable signal EN1 is re-timed, the start time (positive edge) of the first enable signal EN1 corresponds to the start time of the first data cycle D1 of the first data signal DATA1, which is time t3. The period during which the first enable signal EN1 changes from a low level to a high level at time t3 and the first enable signal EN1 is maintained at a high level is the period during which the second micro LED driving circuit uIC10 is activated.

[0100] Similarly, after the second enable signal EN2 is re-timed, the start time (positive edge) of the second enable signal EN2 corresponds to the start time of the second data cycle D2 of the second data signal DATA2, which is time t5. The period during which the second enable signal EN2 changes from a low level to a high level at time t5 and the second enable signal EN2 is maintained at a high level is the period during which the third micro LED driving circuit uIC20 is activated. The rest can be deduced in the same way.

[0101] Assuming that the time from t0 to t2 is one clock signal cycle, the phase difference between the positive edge or negative edge of the zeroth clock signal CLK0 and the zeroth data signal DATA0 may be between 0.3 and 0.7 clock signal cycles, but not limited thereto; the phase difference between the zeroth data signal DATA0 and the first data signal DATA1 may be 0.5 clock signal cycles, for example, the start time of the zeroth data signal DATA0 corresponds to time t0 and the start time of the first data signal DATA1 corresponds to time t1 and the period from time t0 to t1 is 0.5 clock signal cycles, but not limited thereto.

[0102] The zeroth clock signal CLK0 and the first clock signal CLK1 are in opposite phases. When the waveform of the zeroth clock signal CLK0 changes from a low level to a high level, the waveform of the first clock signal CLK1 changes from a high level to a low level; when the waveform of the zeroth clock signal CLK0 changes from a high level to a low level, the waveform of the first clock signal CLK1 changes from a low level to a high level.

[0103] Similarly, the phase difference between the positive edge or negative edge of the first clock signal CLK1 and the first data signal DATA1 may be between 0.3 and 0.7 clock signal cycles, but is not limited thereto; the phase difference between the first data signal DATA1 and the second data signal DATA2 may be 0.5 clock signal cycles, for example, the start time of the first data signal DATA1 corresponds to time t1 and the start time of the second data signal DATA2 corresponds to time t2 and the period from time t1 to t2 is 0.5 clock signal cycles, but is not limited thereto.

[0104] The first clock signal CLK1 and the second clock signal CLK2 are in opposite phases. When the waveform of the first clock signal CLK1 changes from a low level to a high level, the waveform of the second clock signal CLK2 changes from a high level to a low level; when the waveform of the first clock signal CLK1 changes from a high level to a low level, the waveform of the second clock signal CLK2 changes from a low level to a high level. The rest can be deduced in the same way.

[0105] like Fig. 9As shown, the zeroth data signal DATA0 output by the data driver DD is the zeroth data signal DATA0 received by the first micro LED driving circuit u I C00. The first data signal DATA1 output by the first micro LED driving circuit u I C00 is the first data signal DATA1 received by the second micro LED driving circuit u I C10. The second data signal DATA2 output by the second micro LED driving circuit u I C10 is the second data signal DATA2 received by the third micro LED driving circuit u I C20. The rest can be deduced in the same way.

[0106] Similarly, the zeroth clock signal CLK0 output by the data driver DD is the zeroth clock signal CLK0 received by the first micro LED driving circuit uIC00. The first clock signal CLK1 output by the first micro LED driving circuit uIC00 is the first clock signal CLK1 received by the second micro LED driving circuit uIC10. The second clock signal CLK2 output by the second micro LED driving circuit uIC10 is the second clock signal CLK2 received by the third micro LED driving circuit uIC20. The rest can be deduced in the same way.

[0107] The zeroth data signal DATA0 , the first data signal DATA1 , and the second data signal DATA2 may include the zeroth pixel data PX0 , the first pixel data PX1 , the second pixel data PX2 , and the third pixel data PX3 in sequence.

[0108] The zeroth pixel data PX0, the first pixel data PX1 and the second pixel data PX2 may all be (n+1)-bit data, for example, the zeroth pixel data PX0 may include (n+1) data bits D0[0]-D0[n], the first pixel data PX1 may include (n+1) data bits D1[0]-D1[n], the second pixel data PX2 may include (n+1) data bits D2[0]-D2[n], and the third pixel data PX3 may include (n+1) data bits D3[0]-D3[n]. The rest may be deduced in the same manner.

[0109] The start time (positive edge) of the zeroth enable signal EN0 corresponds to the start time of the data bit D0[0] of the zeroth data signal DATA0, which is time t0. The period during which the zeroth enable signal EN0 changes from a low level to a high level at time t0 and the zeroth enable signal EN0 remains at a high level is the period during which the first micro LED driving circuit uIC00 is activated.

[0110] After the first enable signal EN1 is re-timed, the start time (positive edge) of the first enable signal EN1 corresponds to the start time of the data bit D1[0] of the first data signal DATA1, which is time t3. The period during which the first enable signal EN1 changes from a low level to a high level at time t3 and the first enable signal EN1 is maintained at a high level is the period during which the second micro LED driving circuit uIC10 is activated.

[0111] Similarly, after the second enable signal EN2 is re-timed, the start time (positive edge) of the second enable signal EN2 corresponds to the start time of the data bit D2[0] of the second data signal DATA2, which is time t5. The period during which the second enable signal EN2 changes from a low level to a high level at time t5 and the second enable signal EN2 is maintained at a high level is the period during which the third micro LED driving circuit uIC20 is activated. The rest can be deduced in the same way.

[0112] Assuming that the time from t0 to t2 is one clock signal cycle, the phase difference between the positive edge or negative edge of the zeroth clock signal CLK0 and the zeroth data signal DATA0 may be between 0.3 and 0.7 clock signal cycles, but not limited thereto; the phase difference between the zeroth data signal DATA0 and the first data signal DATA1 may be 0.5 clock signal cycles, for example, the start time of the zeroth data signal DATA0 corresponds to time t0 and the start time of the first data signal DATA1 corresponds to time t1 and the period from time t0 to t1 is 0.5 clock signal cycles, but not limited thereto.

[0113] The zeroth clock signal CLK0 and the first clock signal CLK1 are in opposite phases. When the waveform of the zeroth clock signal CLK0 changes from a low level to a high level, the waveform of the first clock signal CLK1 changes from a high level to a low level; when the waveform of the zeroth clock signal CLK0 changes from a high level to a low level, the waveform of the first clock signal CLK1 changes from a low level to a high level.

[0114] Similarly, the phase difference between the positive edge or negative edge of the first clock signal CLK1 and the first data signal DATA1 may be between 0.3 and 0.7 clock signal cycles, but is not limited thereto; the phase difference between the first data signal DATA1 and the second data signal DATA2 may be 0.5 clock signal cycles, for example, the start time of the first data signal DATA1 corresponds to time t1 and the start time of the second data signal DATA2 corresponds to time t2 and the period from time t1 to t2 is 0.5 clock signal cycles, but is not limited thereto.

[0115] The first clock signal CLK1 and the second clock signal CLK2 are in opposite phases. When the waveform of the first clock signal CLK1 changes from a low level to a high level, the waveform of the second clock signal CLK2 changes from a high level to a low level; when the waveform of the first clock signal CLK1 changes from a high level to a low level, the waveform of the second clock signal CLK2 changes from a low level to a high level. The rest can be deduced in the same way.

[0116] Compared with the prior art, the micro-LED display device of the present invention divides the traditional row input signal (ROW) into an enable signal (EN) and a clock signal (CLK). When the enable signal (EN), the clock signal (CLK) and the data signal (DATA) are input together into a display panel PL (such as a glass substrate) having a high resistance value, the enable signal (EN), the clock signal (CLK) and the data signal (DATA) are sequentially transmitted to a plurality of micro-LED driving circuits connected in series, and the enable signal (EN) and the data signal (DATA) are re-timed in each micro-LED driving circuit to have the same delay and the clock signal (CLK) is inverted and transmitted to the next micro-LED driving circuit to avoid signal distortion due to parasitic resistance and capacitance, so that the micro-LED display device of the present invention can operate smoothly at high frequencies and the resolution and size of its display panel are not limited.

Claims

1. A micro light emitting diode display device, characterized in that: include: A display panel including a plurality of pixels; as well as A plurality of micro LED driving circuits, each of which is respectively coupled to at least one pixel of the display panel, the plurality of micro LED driving circuits comprising a first micro LED driving circuit and a second micro LED driving circuit connected in series with each other, the first micro LED driving circuit receiving a zeroth data signal, a zeroth enable signal and a zeroth clock signal and outputting a first data signal, a first enable signal and a first clock signal to the second micro LED driving circuit; The zeroth clock signal and the first clock signal are in anti-phase with each other, and the phase difference between the zeroth data signal and the first data signal is less than one clock signal cycle.

2. The micro light emitting diode display device according to claim 1, characterized in that: Also includes: The data driver is coupled to the first micro LED driving circuit and provides the zeroth data signal, the zeroth enable signal and the zeroth clock signal to the first micro LED driving circuit.

3. The micro-LED display device according to claim 1, characterized in that: The first micro light emitting diode driving circuit comprises: A D-type flip-flop for generating the first data signal according to the zeroth data signal and the zeroth clock signal; and The anti-gate is used to generate the first clock signal according to the zeroth clock signal.

4. The micro-LED display device according to claim 1, characterized in that: The phase difference between the positive edge or the negative edge of the zeroth clock signal and the zeroth data signal is between 0.3 and 0.7 of the clock signal cycle.

5. The micro-LED display device according to claim 1, characterized in that: The phase difference between the zeroth data signal and the first data signal is 0.5 clock signal period.

6. The micro-LED display device according to claim 1, characterized in that: The waveform of the zeroth clock signal changes from a low level to a high level and the waveform of the first clock signal changes from a high level to a low level.

7. The micro-LED display device according to claim 1, characterized in that: The waveform of the zeroth clock signal changes from a high level to a low level and the waveform of the first clock signal changes from a low level to a high level.

8. The micro light emitting diode display device according to claim 1, characterized in that: The start time of the zeroth enable signal corresponds to the start time of the zeroth data cycle of the zeroth data signal, and the start time of the first enable signal corresponds to the start time of the first data cycle of the first data signal.

9. The micro light emitting diode display device according to claim 1, characterized in that: The second micro-LED driving circuit receives the first data signal, the first enable signal and the first clock signal and outputs a second data signal, a second enable signal and a second clock signal, wherein the first clock signal and the second clock signal are inverted to each other and the phase difference between the first data signal and the second data signal is less than one clock signal cycle.

10. The micro light emitting diode display device according to claim 9, characterized in that: The second micro light emitting diode driving circuit comprises: A D-type flip-flop, used for generating the second data signal according to the first data signal and the first clock signal; and The anti-gate is used to generate the second clock signal according to the first clock signal.

11. The micro light emitting diode display device according to claim 9, characterized in that: The phase difference between the positive edge or the negative edge of the first clock signal and the first data signal is between 0.3 and 0.7 of the clock signal cycle.

12. The micro light emitting diode display device according to claim 9, characterized in that: The phase difference between the first data signal and the second data signal is 0.5 clock signal period.

13. The micro light emitting diode display device according to claim 9, characterized in that: The waveform of the first clock signal changes from a low level to a high level and the waveform of the second clock signal changes from a high level to a low level.

14. The micro-LED display device according to claim 9, characterized in that: The waveform of the first clock signal changes from a high level to a low level and the waveform of the second clock signal changes from a low level to a high level.

15. The micro light emitting diode display device according to claim 9, characterized in that: The start time of the second enable signal corresponds to the start time of the second data period of the second data signal.

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