Driving circuit for multi-panel display device and synchronization method thereof

Abstract

The invention provides a driving circuit for a multi-panel display device and a synchronization method thereof. The driving circuit comprises a first driving chip and a second driving chip which share one power supply circuit. Based on the identification control signal, one of the first driving chip and the second driving chip is set as a master driving chip or a slave driving chip. The master drive chip transmits a power enable signal and a control signal to the power supply circuit to trigger the power supply circuit to provide a power voltage to the master drive chip and the slave drive chip. When the main driving chip transmits the time sequence control signal to the subordinate driving chip, the subordinate driving chip executes power supply synchronization operation based on the time sequence control signal, so that the power supply time sequences of the subordinate driving chip and the main driving chip are kept synchronous.

Description

Technical Field

[0001] The present invention relates to a driving circuit, and in particular to a driving circuit for a multi-panel display device and a synchronization method thereof. Background Art

[0002] Organic light emitting diodes (OLED) have been widely used in display devices due to their advantages of low power consumption, wide color gamut, and flexibility. OLED displays can form multiple display panels in a single display device by folding. For example, an OLED smartphone may include a first display panel and a second display panel located at different surfaces of the OLED smartphone. The first display panel of the OLED smartphone may display a calendar or weather information, and the second display panel of the OLED smartphone may display a video.

[0003] Generally, each display panel in a multi-panel display device may have an independent lighting sequence. Therefore, each display panel in the multi-panel display device needs to be equipped with a power supply circuit to meet the power supply requirements of each display panel. However, placing multiple power supply circuits in the multi-panel display device will increase the cost and size of the multi-panel display device.

[0004] Therefore, how to reduce the number of power supply circuits configured in a multi-panel display device has become an important issue. Summary of the invention

[0005] The present invention provides a driving circuit for a multi-panel display device and a synchronization method thereof. The driving circuit can perform a power synchronization operation on each display panel in the multi-panel display device by using a single power supply circuit.

[0006] In an embodiment of the present invention, a driving circuit of a multi-panel display device is provided. The driving circuit of the multi-panel display device includes a first driving chip and a second driving chip. The first driving chip is configured to drive a first display panel of the multi-panel display device. The second driving chip is configured to drive a second display panel of the multi-panel display device. The first driving chip and the second driving chip share a power supply circuit. One of the first driving chip and the second driving chip is set as a main driving chip based on a first identification control signal, and the other of the first driving chip and the second driving chip is set as a slave driving chip based on a second identification control signal. The main driving chip is configured to transmit a power enable signal and a control signal to the power supply circuit, and the power supply circuit is configured to provide a power supply voltage to the main driving chip and the slave driving chip based on the power enable signal and the control signal. In response to the main driving chip transmitting a timing control signal to the slave driving chip, the slave driving chip performs a power synchronization operation based on the timing control signal to synchronize the power timing of the slave driving chip and the main driving chip.

[0007] In another embodiment of the present invention, a driving circuit of a multi-panel display device is provided. The driving circuit of the multi-panel display device includes a first driving chip and a second driving chip. The first driving chip is configured to drive a first display panel of the multi-panel display device. The second driving chip is configured to drive a second display panel of the multi-panel display device. The first driving chip and the second driving chip share a power supply circuit, and the power supply circuit is controlled by a processor. The processor is configured to transmit a power enable signal and a control signal to the power supply circuit, and the power supply circuit is configured to provide a power supply voltage to the first driving chip and the second driving chip based on the power enable signal and the control signal. One of the first driving chip and the second driving chip is set as a main driving chip based on a control signal provided by the processor, and the other of the first driving chip and the second driving chip is set as a slave driving chip based on the control signal. In response to the main driving chip transmitting a timing control signal to the slave driving chip, the slave driving chip performs a power synchronization operation based on the timing control signal to synchronize the power timing of the slave driving chip and the main driving chip.

[0008] In an embodiment of the present invention, a synchronization method of a driving circuit is provided, and the synchronization method is applicable to a multi-panel display device. The driving circuit includes a first driving chip for driving a first display panel of the multi-panel display device and a second driving chip for driving a second display panel of the multi-panel display device. The first driving chip and the second driving chip share a power supply circuit. The synchronization method includes the following steps. One of the first driving chip and the second driving chip is set as a main driving chip based on a control signal, and the other of the first driving chip and the second driving chip is set as a slave driving chip based on the control signal. A power enable signal and a control signal are transmitted to the power supply circuit through the main driving chip. A power supply voltage is provided to the main driving chip and the slave driving chip through the power supply circuit based on the power enable signal and the control signal. In response to the main driving chip transmitting a timing control signal to the slave driving chip, a power synchronization operation is performed by the slave driving chip based on the timing control signal to synchronize the power timing of the slave driving chip and the main driving chip.

[0009] Based on the above, in an embodiment of the present invention, the master driver chip and the slave driver chip in the multi-panel display device share a single power supply circuit. The slave driver chip can perform a power synchronization operation based on a timing control signal provided by the master driver chip and based on a power supply voltage provided by the single power supply circuit, so that the power timing of the slave driver chip and the master driver chip are synchronized. Therefore, the driving circuit and synchronization method of the present invention can reduce the number of power supply circuits in the multi-panel display device.

[0010] In order to make the above features easier to understand, multiple embodiments will be described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The accompanying drawings are included to provide a further understanding of the present invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present invention and together with the description serve to explain the principles of the present invention.

[0012] Figure 1 is a block diagram of a multi-panel display device according to an embodiment of the present invention.

[0013] Figure 2 According to an embodiment of the present invention Figure 1 Detailed connection between the driving circuit 104 and the power supply circuit 103.

[0014] Figure 3A According to an embodiment of the present invention Figure 2 FIG. 4 is a timing diagram of power-on sequence synchronization between the first driver chip DDIC1 and the second driver chip DDIC2.

[0015] Figure 3BAccording to an embodiment of the present invention Figure 2 1 is a timing diagram of the handover operation between the first driver chip DDIC1 and the second driver chip DDIC2.

[0016] Figure 3C According to an embodiment of the present invention Figure 2 1 and 2. FIG. 1 is a timing diagram of power-down sequence synchronization between the first driver chip DDIC1 and the second driver chip DDIC2.

[0017] Figure 4 The communication method between the driving circuit 104 and the power supply circuit 103 is described according to an embodiment of the present invention.

[0018] Figure 5 According to another embodiment of the present invention Figure 1 Detailed connection between the driving circuit 104 and the power supply circuit 103.

[0019] Fig. 6A is a block diagram of a multi-panel display device according to another embodiment of the present invention.

[0020] Figure 6B is a block diagram of a multi-panel display device according to yet another embodiment of the present invention.

[0021] Figure 7 is a block diagram of a multi-panel display device according to yet another embodiment of the present invention.

[0022] Description of Figure Numbers

[0023] 100, 600, 700: multi-panel display device;

[0024] 101, 601, 701: first display panel;

[0025] 102, 602, 702: second display panel;

[0026] 103, 604, 703: power supply circuit;

[0027] 104, 605, 704: driving circuit;

[0028] 201, 202, 605a, 605b, 605c: transmission interface;

[0029] 300, 301, 302, 303, 304, 305, 306, 307, 308, 309, 310, 311, 312, 313, 314: signal;

[0030] 401, 402: I2C interface;

[0031] 501, 1031, 6041: communication interface;

[0032] 603: a third display panel;

[0033] 705: processor;

[0034] 2011, 4011, 5011: first switch;

[0035] 2012, 4012, 5012: second switch;

[0036] 2021, 4021, 5013: the third switch;

[0037] 2022, 4022, 5014: fourth switch;

[0038] 6051a, 6051b, 6051c, 6052a, 6052b, 6052c: switches;

[0039] 7031: The third terminal;

[0040] 7032: fourth terminal;

[0041] 7051: first terminal;

[0042] 7052: Second terminal;

[0043] AVDD: first power supply voltage;

[0044] AVDD_EN: power enable signal;

[0045] DDIC1: first driver chip;

[0046] DDIC2: the second driver chip;

[0047] DDIC3: the third driver chip;

[0048] ELVDD: second power supply voltage;

[0049] ELVSS: third power supply voltage;

[0050] HC: Handover command;

[0051] M / S: Identify control signals;

[0052] SWIRE: control signal;

[0053] PV: power supply voltage;

[0054] RESPWR: reset signal;

[0055] SCL: serial clock signal;

[0056] SDA: serial data signal;

[0057] SLPOUT: wake-up synchronization signal;

[0058] t1: time point;

[0059] t2: time point;

[0060] t3: time point;

[0061] TC, TC1, TC2: timing control signals;

[0062] Td1: first delay time;

[0063] Td2: Second delay time. DETAILED DESCRIPTION

[0064] The term "coupled (or connected)" used throughout this specification (including the claims) may refer to any direct or indirect means of connection. For example, if the text describes a first device coupled (or connected) to a second device, it should be interpreted that the first device can be directly connected to the second device, or the first device can be indirectly connected to the second device through other devices or some means of connection. The terms "first", "second", etc. mentioned in the entire text of this specification (including the claims) are used to name the name of the element, or to distinguish different embodiments or scopes, and are not used to limit the upper or lower limit of the number of elements, nor to limit the order of the elements. In addition, wherever possible, the elements / components / steps with the same number in the drawings and embodiments represent the same or similar parts. Elements / components / steps using the same number or the same terminology in different embodiments can refer to the relevant descriptions of each other.

[0065] Figure 1 is a block diagram of a multi-panel display device according to an embodiment of the present invention. Figure 1, the multi-panel display device 100 includes a first display panel 101, a second display panel 102, a power supply circuit 103 and a driving circuit 104. The driving circuit 104 includes a first driving chip DDIC1 and a second driving chip DDIC2. The first driving chip DDIC1 and the second driving chip DDIC2 share a single power supply circuit 103. The first driving chip DDIC1 and the second driving chip DDIC2 can be display driver integrated circuits, respectively. The power supply circuit 103 can provide power to the first driving chip DDIC1 and the second driving chip DDIC2, so that the first driving chip DDIC1 and the second driving chip DDIC2 can drive the first display panel 101 and the second display panel 102, respectively. According to design requirements, the power supply circuit 103 can be implemented as a power management integrated circuit (PMIC) that manages the power status of the first driving chip DDIC1 and the second driving chip DDIC2.

[0066] For example, Figure 1 The driving circuit 104 in the embodiment can transmit the power enable signal AVDD_EN and the control signal SWIRE to the power supply circuit 103, and the power supply circuit 103 can provide the power supply voltage PV to the driving circuit 104, so that the power supply circuit 103 can manage the power-on sequence (or power-off sequence) of the first driving chip DDIC1 and the second driving chip DDIC2 to meet different scenarios applicable to the multi-panel display device 100. It should be noted that the SWIRE interface protocol is a known interface protocol for power management ICs, and the power enable signal AVDD_EN and the control signal represented by the element symbol SWIRE are both necessary signals for executing the SWIRE interface protocol. In addition, according to the SWIRE interface protocol, the voltage level of the power supply voltage PV output by the power supply circuit 103 to the display driver chip is controlled by the number of pulses of the control signal SWIRE.

[0067] exist Figure 1In an embodiment of the present invention, one of the first driver chip DDIC1 and the second driver chip DDIC2 may be set as a master driver chip, and the other of the first driver chip DDIC1 and the second driver chip DDIC2 may be set as a slave driver chip. The master driver chip and the slave driver chip may be determined based on the identification control signal M / S. For example, the multi-panel display device 100 may include a processor (not shown) to send a command as an identification control signal M / S to each of the first driver chip DDIC1 and the second driver chip DDIC2. The identification control signal M / S may be a first logic value (e.g., M / S=1) defining the master driver chip in the driving circuit 104, and the identification control signal M / S may be a second logic value (e.g., M / S=0) defining the slave driver chip in the driving circuit 104. In another embodiment, the identification control signal M / S may be a first logic value (e.g., M / S=0) defining the master driver chip in the driving circuit 104, and the identification control signal M / S may be a second logic value (e.g., M / S=1) defining the slave driver chip in the driving circuit 104. In another embodiment, each of the first driver chip DDIC1 and the second driver chip DDIC2 may include a hardware pin for indicating a logic value of the identification control signal M / S, so that the master driver chip and the slave driver chip in the driver circuit 104 may be defined by the hardware pin.

[0068] According to the design requirements, Figure 1 The multi-panel display device 100 shown in the figure may be an organic light emitting diode (OLED) display device. When the master driver chip of the driving circuit 104 is determined, the master driver chip of the driving circuit 104 may transmit the power enable signal AVDD_EN and the control signal SWIRE to the power supply circuit 103. When the power supply circuit 103 receives the power enable signal AVDD_EN and the control signal SWIRE, the power supply circuit 103 may provide the power supply voltage PV to both the master driver chip and the slave driver chip of the driving circuit 104. For example, Figure 2 According to an embodiment of the present invention Figure 1 Detailed connection between the driving circuit 104 and the power supply circuit 103.

[0069] Please refer to Figure 2 , the first driver chip DDIC1 of the driver circuit 104 may include a transmission interface 201 for transmitting both the power enable signal AVDD_EN and the control signal SWIRE generated by the first driver chip DDIC1. The second driver chip DDIC2 of the driver circuit 104 may include a transmission interface 202 for transmitting both the power enable signal AVDD_EN and the control signal SWIRE generated by the second driver chip DDIC2. Figure 2 In the embodiment, the transmission interface 201 of the first driver chip DDIC1 includes a first switch 2011 and a second switch 2012, and the transmission interface 202 of the second driver chip DDIC2 includes a third switch 2021 and a fourth switch 2022. The power supply circuit 103 may include a communication interface 1031 for communicating with the first driver chip DDIC1 and the second driver chip DDIC2.

[0070] like Figure 2 As shown in FIG. 1 , the first switch 2011 of the first driver chip DDIC1 and the third switch 2021 of the second driver chip DDIC2 are coupled to the first terminal of the communication interface 1031. In addition, the second switch 2012 and the fourth switch 2022 of the first driver chip DDIC1 are coupled to the second terminal of the communication interface 1031. In another embodiment, the first switch 2011 of the first driver chip DDIC1 and the third switch 2021 of the second driver chip DDIC2 may be coupled to different terminals of the communication interface 1031, respectively. In another embodiment, the second switch 2012 of the first driver chip DDIC1 and the fourth switch 2022 of the second driver chip DDIC2 may be coupled to different terminals of the communication interface 1031, respectively.

[0071] Please refer to Figure 2 , the first driver chip DDIC1 can be set as the master driver chip by receiving an identification control signal M / S with a first logic value (for example, M / S=1), and the second driver chip DDIC2 can be set as the slave driver chip by receiving an identification control signal M / S with a second logic value (for example, M / S=0). Figure 2 The first driver chip DDIC1 in the embodiment is set as the main driver chip, so only the first driver chip DDIC1 is configured to transmit the power enable signal AVDD_EN and the control signal SWIRE to the power supply circuit 103. In detail, in response to receiving a wake-up command from a processor (not shown), the first driver chip DDIC1 can turn on both the first switch 2011 and the second switch 2012, and the second driver chip DDIC2 can turn off both the third switch 2021 and the fourth switch 2022. In addition, in response to receiving a wake-up command from the processor, the first driver chip DDIC1 can transmit the timing control signal TC to the second driver chip DDIC2 so that the second driver chip DDIC2 performs a power-on procedure.

[0072] When the power supply circuit 103 receives the power enable signal AVDD_EN and the control signal SWIRE through the communication interface 1031, the power supply circuit 103 can provide the power supply voltage PV to both the first driver chip DDIC1 and the second driver chip DDIC2. Figure 2 In the embodiment of the present invention, the driving circuit 104 is used to drive the OLED display device (eg Figure 1 100). Therefore, the power supply voltage PV provided by the power supply circuit 103 may include a first power supply voltage AVDD, a second power supply voltage ELVDD, and a third power supply voltage ELVSS. The first driver chip DDIC1 and the second driver chip DDIC2 may use the first power supply voltage AVDD to generate pixel switch control signals, such as scanning signals and light emission signals, for the OLED pixel circuit in the OLED display device. In addition, the first driver chip DDIC1 and the second driver chip DDIC2 may use both the second power supply voltage ELVDD and the third power supply voltage ELVSS to generate a driving current for the OLED pixel circuit in the OLED display device.

[0073] exist Figure 2 In the embodiment of the present invention, the first driver chip DDIC1 (i.e., the main driver chip) can transmit the timing control signal TC to the second driver chip DDIC2, so that the second driver chip DDIC2 can perform a power synchronization operation based on the timing control signal TC, so that the power timing of the second driver chip DDIC2 and the first driver chip DDIC1 are kept synchronized. For example, Figure 3A According to an embodiment of the present invention Figure 2 FIG. 4 is a timing diagram of power-on sequence synchronization between the first driver chip DDIC1 and the second driver chip DDIC2.

[0074] exist Figure 3A In the diagram, the horizontal axis represents the time axis, and the vertical axis represents the signal level (which is the logic level, not the actual value). Figure 3A , signal 300 represents a command from a processor, and signal 301 represents an identification control signal M / S for defining a master driver chip and a slave driver chip. Signal 302 and signal 307 represent internal vertical synchronization signals of the first driver chip DDIC1 and the second driver chip DDIC2, respectively. Signal 303 and signal 308 represent external vertical synchronization signals provided by the first driver chip DDIC1 and the second driver chip DDIC2, respectively. It should be noted that the internal vertical synchronization signal and the external vertical synchronization signal are periodic pulse signals. Signal 304 and signal 309 represent wake-up synchronization signals SLPOUT provided by the first driver chip DDIC1 and the second driver chip DDIC2, respectively. Signal 305 and signal 310 represent enable signals AVDD_EN provided by the first driver chip DDIC1 and the second driver chip DDIC2, respectively. Signal 306 and signal 311 represent control signals SWIRE provided by the first driver chip DDIC1 and the second driver chip DDIC2, respectively. Signals 312 to 314 represent power supply voltages provided by the power supply circuit 103.

[0075] exist Figure 3AIn the embodiment, based on the determination of the identification control signal M / S, the first driver chip DDIC1 can be set as the master driver chip, and the second driver chip DDIC2 can be set as the slave driver chip. Figure 3A In the signal 300, the first driver chip DDIC1 is configured to execute a power-on sequence in response to receiving a wake-up command from the processor, and the second driver chip DDIC2 is configured to perform a power synchronization operation based on the power-on sequence executed by the first driver chip DDIC1. Figure 3A As shown in FIG. 1 , at the beginning of the power-on sequence, the wake-up synchronization signal 304 (SLPOUT) of the first driver chip DDIC1 is pulled to a high logic level, and the power enable signal AVDD_EN of the first driver chip DDIC1 is pulled to a high logic level. Figure 3A The timing control signal TC (e.g., signal 303 (external VS)) and the wake-up synchronization signal 304 (SLPOUT) in the power-on sequence are transmitted to the second driver chip DDIC2 to power on the second driver chip DDIC2. In addition, the control signal SWIRE of the first driver chip DDIC1 starts to carry information at the end of the power-on sequence. Since both the power enable signal AVDD_EN and the control signal SWIRE are only provided by the first driver chip DDIC1 (i.e., the main driver chip) during the power-on sequence, the power enable signal AVDD_EN and the control signal SWIRE (i.e., the second driver chip DDIC2) of the second driver chip DDIC2 are Figure 3A The signals 310 and 311 in FIG. 1 are kept in a high impedance state or a weakly pull-high state.

[0076] After receiving the power enable signal AVDD_EN and the control signal SWIRE through the power supply circuit 103, the power supply circuit 103 can increase the power supply voltage PV (eg, Figure 3A The signals 312 to 314, the signals AVDD, the signals ELVSS, and the signals ELVDD) are transmitted to both the first driver chip DDIC1 and the second driver chip DDIC2. After completing the power synchronization between the first driver chip DDIC1 and the second driver chip DDIC2, the first driver chip DDIC1 and the second driver chip DDIC2 can continue to communicate with each other by using the timing control signal TC, or the first driver chip DDIC1 and the second driver chip DDIC2 can be decoupled from each other.

[0077] Please refer to Figure 1 In order to meet some scenarios of the multi-panel display device 100, the roles of the first driver chip DDIC1 and the second driver chip DDIC2 set as the main driver chip can be swapped. For example, Figure 3B According to an embodiment of the present invention Figure 2The timing diagram of the hand-over operation between the first driver chip DDIC1 and the second driver chip DDIC2 is shown in FIG. Figure 3B In FIG. 1 , the horizontal axis represents the time axis, and the vertical axis represents the signal level (which is a logic level, not an actual value). Assume that the multi-panel display device 100 originally uses the first driver chip DDIC1 as the master driver chip and the second driver chip DDIC2 as the slave driver chip. Please refer to Figure 3B The processor of the multi-panel display device 100 can transmit the handover command HC to both the first driver chip DDIC1 and the second driver chip DDIC2 at time point t1 to exchange the role of the main driver chip between the first driver chip DDIC1 and the second driver chip DDIC2. When the first driver chip DDIC1 (i.e., the main driver chip) receives the handover command HC at time point t1, the first driver chip DDIC1 can slightly adjust Figure 3B The waveforms of the signal 305 and the signal 306 in the circuit are used to determine the appropriate time to disconnect the first switch 2011 and the second switch 2012.

[0078] For example, see Figure 2 and Figure 3B When the first driver chip DDIC1 (i.e., the main driver chip) receives the handover command HC at time point t1, the first driver chip DDIC1 may start from time point t2 and after a first delay time Td1, the power enable signal AVDD_EN and the control signal SWIRE (i.e., Figure 3B The signals 305 and 306 in the figure are both set to change from the active state to the high impedance state (or from the active state to the weak pull-up state). The pulse received by the first driver chip DDIC1 at time point t2 is the pulse of the internal vertical synchronization signal (i.e., signal 302) of the first driver chip DDIC1 that is first received after the first driver chip DDIC1 receives the handover command HC at time point t1. Figure 3B In the embodiment of the present invention, the active state may be a high logic level state, and the high impedance state may be a low logic level state. The length of the first delay time Td1 may be adjusted by the first driving chip DDIC1.

[0079] Please refer to Figure 2 and Figure 3BWhen the second driver chip DDIC2 (i.e., the slave driver chip) receives the handover command HC at time point t1, the second driver chip DDIC2 can determine a suitable time to turn on the third switch 2021 and the fourth switch 2022. For example, the second driver chip DDIC2 can start from time point t3, and after a second delay time Td2, the power enable signal AVDD_EN of the second driver chip DDIC2 and the control signal SWIRE (i.e., Figure 3B The second delay time Td2 can be adjusted by the second driver chip DDIC2.

[0080] Figure 3C According to an embodiment of the present invention Figure 2 The timing diagram of the power-down sequence synchronization between the first driver chip DDIC1 and the second driver chip DDIC2. Figure 3C In , the horizontal axis represents the time axis, and the vertical axis represents the signal level (which is the logic level, not the actual value). Figure 3C In the embodiment, based on the determination of the identification control signal M / S, the second driver chip DDIC2 is set as the master driver chip, and the first driver chip DDIC1 is set as the slave driver chip. Figure 3C In the signal 300, the second driver chip DDIC2 is configured to execute a power-down sequence in response to receiving a sleep command from the processor, and the first driver chip DDIC1 is configured to perform a power synchronization operation based on the power-down sequence executed by the second driver chip DDIC2. Figure 3C As shown in FIG. 1 , in response to receiving a sleep command from the processor, the wake-up synchronization signal 309 (SLPOUT) of the second driver chip DDIC2 is pulled to a low logic level, and the second driver chip DDIC2 can control the timing control signal TC (eg, an external vertical synchronization signal (ie, Figure 3C The signal 308 in the first driving chip DDIC2 is transmitted to the first driving chip DDIC1 to trigger the frequency adjustment operation performed by the first driving chip DDIC1. In detail, the first driving chip DDIC1 can adjust the internal vertical synchronization signal (ie, the internal vertical synchronization signal) during the frequency synchronization period based on the signal 308 provided by the second driving chip DDIC2. Figure 3C The signal 302 in the first driving chip DDIC1 makes the internal vertical synchronization signal (ie, Figure 3CThe signal 302 in the figure can be synchronized with the external vertical synchronization signal (ie, Figure 3C The signal 308 in is synchronized.

[0081] exist Figure 3C In the embodiment, since the main driving chip is the second driving chip DDIC2, the power enable signal AVDD_EN and the control signal SWIRE are only provided by the second driving chip DDIC1 to activate the power-down sequence, and the power enable signal AVDD_EN and the control signal SWIRE of the first driving chip DDIC1 (i.e., Figure 3C Signals 305 and 306 in the circuit remain in a high impedance state or a weakly pulled high state.

[0082] In another embodiment, Figure 1 The driving circuit 104 can communicate with the power supply circuit 103 through an Inter-integrated Circuit (I2C) interface, which is another interface protocol different from the SWIRE protocol. For example, Figure 4 The communication method between the driving circuit 104 and the power supply circuit 103 is described according to an embodiment of the present invention. Figure 4 , the first driver chip DDIC1 of the driver circuit 104 may include an I2C interface 401, and the second driver chip DDIC2 of the driver circuit 104 may include an I2C interface 402. In addition, the I2C interface 401 may include a first switch 4011 for controlling the transmission of a reset signal RESPWR generated by the first driver chip DDIC1, and the I2C interface 401 may include a second switch 4012 for controlling the transmission of both a serial clock signal SCL and a serial data signal SDA generated by the first driver chip DDIC1. Similarly, the I2C interface 402 may include a third switch 4021 for controlling the transmission of a reset signal RESPWR generated by the second driver chip DDIC2, and the I2C interface 402 may include a fourth switch 4022 for controlling the transmission of both a serial clock signal SCL and a serial data signal SDA generated by the second driver chip DDIC2.

[0083] The power supply circuit 103 may include a communication interface 1031 for communicating with the first driver chip DDIC1 and the second driver chip DDIC2. Figure 4In the embodiment of the present invention, the reset signal RESPWR of the I2C interface 401 and the I2C interface 402 is coupled to the first terminal of the communication interface 1031. In addition, the serial clock signals SCL of the I2C interface 401 and the I2C interface 402 are coupled to the second terminal of the communication interface 1031, and the serial data signals SDA of the I2C interface 401 and the I2C interface 402 are coupled to the third terminal of the communication interface 1031. In another embodiment, the reset signal RESPWR, the serial clock signal SCL, and the serial data signal SDA of the I2C interface 401 and the I2C interface 402 may be coupled to different terminals of the communication interface 1031 of the power supply circuit 103, respectively. In another embodiment, the serial clock signal SCL of the I2C interface 401 and the I2C interface 402 may be coupled to different terminals of the communication interface 1031, respectively, and the serial data signal SDA of the I2C interface 401 and the I2C interface 402 may be coupled to different terminals of the communication interface 1031, respectively.

[0084] Please refer to Figure 4 Based on the determination of the identification control signal M / S provided by the processor (not shown), the first driver chip DDIC1 can be set as the master driver chip, and the second driver chip DDIC2 can be set as the slave driver chip. Figure 4 The first driver chip DDIC1 in the embodiment is set as the main driver chip, so only the first driver chip DDIC1 is configured to transmit signals (i.e., the reset signal RESPWR, the serial clock signal SCL, and the serial data signal SDA) to the power supply circuit 103. In detail, in response to receiving a wake-up command from a processor (not shown), the first driver chip DDIC1 may turn on both the first switch 4011 and the second switch 4012, and the second driver chip DDIC2 may turn off both the third switch 4021 and the fourth switch 4022. Therefore, only the first driver chip DDIC1 may output the reset signal RESPWR via the first switch 4011, and output both the serial clock signal SCL and the serial data signal SDA via the second switch 4012.

[0085] When the power supply circuit 103 receives the reset signal RESPWR, the serial clock signal SCL, and the serial data signal SDA through the communication interface 1031, the power supply circuit 103 can provide the power supply voltage PV to both the first driver chip DDIC1 and the second driver chip DDIC2. In addition, for some application scenarios, the processor (not shown) can transmit the handover command HC to both the first driver chip DDIC1 and the second driver chip DDIC2 to exchange the role of the main driver chip between the first driver chip DDIC1 and the second driver chip DDIC2. The details of the above-mentioned power synchronization operation and handover operation can be found in FIG. 3A to FIG. 3C The embodiments of the present invention are analogous to those of the present invention, and thus will not be described in detail.

[0086] Figure 5 According to another embodiment of the present invention Figure 1 Please refer to the detailed connection method between the driving circuit 104 and the power supply circuit 103. Figure 5 , the first driver chip DDIC1 of the driver circuit 104 may include a transmission interface 1041 for transmitting both the power enable signal AVDD_EN and the control signal SWIRE generated by the first driver chip DDIC1. The second driver chip DDIC2 of the driver circuit 104 may include a transmission interface 1042 for transmitting both the power enable signal AVDD_EN and the control signal SWIRE generated by the second driver chip DDIC2. Figure 5 In the embodiment, the power supply circuit 103 may include a communication interface 501 for communicating with the first driver chip DDIC1 and the second driver chip DDIC2. The communication interface 501 includes a first switch 5011, a second switch 5012, a third switch 5013, and a fourth switch 5014. The first switch 5011 and the second switch 5012 are respectively coupled to the first terminal and the second terminal of the transmission interface 1041. The third switch 5013 and the fourth switch 5014 are respectively coupled to the first terminal and the second terminal of the transmission interface 1042.

[0087] Please refer to Figure 5 , based on the determination of the identification control signal M / S provided by the processor (not shown), the first driver chip DDIC1 can be set as the master driver chip, and the second driver chip DDIC2 can be set as the slave driver chip. In addition, the processor (not shown) can transmit the identification control signal M / S to the power supply circuit 103, so as to inform the power supply circuit 103 that the first driver chip DDIC1 is set as the master driver chip. Therefore, the power supply circuit 103 can turn on both the first switch 5011 and the second switch 5012, and can turn off both the third switch 5013 and the fourth switch 5014, so that only the first driver chip DDIC1 can output the power enable signal AVDD_EN and the control signal SWIRE to the power supply circuit 103. In another embodiment, when the second driver chip DDIC2 is set as the main driver chip based on the identification control signal M / S, the power supply circuit 103 can disconnect both the first switch 5011 and the second switch 5012, and can turn on both the third switch 5013 and the fourth switch 5014, so that only the second driver chip DDIC2 can output the power enable signal AVDD_EN and the control signal SWIRE to the power supply circuit 103.

[0088] Please refer to Figure 5When the power supply circuit 103 receives the power enable signal AVDD_EN and the control signal SWIRE through the communication interface 501, the power supply circuit 103 can provide the power supply voltage PV to both the first driver chip DDIC1 and the second driver chip DDIC2. FIG. 3A to FIG. 3C The embodiments of the present invention are analogous to those of the present invention, and thus will not be described in detail.

[0089] Fig. 6A is a block diagram of a multi-panel display device according to another embodiment of the present invention. Fig. 6A , the multi-panel display device 600 includes a first display panel 601, a second display panel 602, a third display panel 603, a power supply circuit 604 and a driving circuit 605. The driving circuit 605 includes a first driving chip DDIC1, a second driving chip DDIC2 and a third driving chip DDIC3. The power supply circuit 604 is shared by the first driving chip DDIC1, the second driving chip DDIC2 and the third driving chip DDIC3. According to the design requirements, the power supply circuit 604 can be implemented as a power management integrated circuit (PMIC), which provides a suitable power supply voltage PV to the first driving chip DDIC1, the second driving chip DDIC2 and the third driving chip DDIC3. The first driving chip DDIC1, the second driving chip DDIC2 and the third driving chip DDIC3 can use the power supply voltage PV to drive the first display panel 601, the second display panel 602 and the third display panel 603 respectively.

[0090] Please refer to Fig. 6A , the first driver chip DDIC1 of the driver circuit 605 may include a transmission interface 605a for transmitting both the power enable signal AVDD_EN and the control signal SWIRE generated by the first driver chip DDIC1. The second driver chip DDIC2 of the driver circuit 605 may include a transmission interface 605b for transmitting both the power enable signal AVDD_EN and the control signal SWIRE generated by the second driver chip DDIC2. The third driver chip DDIC3 of the driver circuit 605 may include a transmission interface 605c for transmitting both the power enable signal AVDD_EN and the control signal SWIRE generated by the third driver chip DDIC3. In addition, the transmission interface 605a of the first driver chip DDIC1 includes a switch 6051a and a switch 6052a. The transmission interface 605b of the second driver chip DDIC2 includes a switch 6051b and a switch 6052b. The transmission interface 605c of the third driver chip DDIC3 includes a switch 6051c and a switch 6052c.

[0091] The power supply circuit 604 may include a communication interface 6041 for communicating with the first driver chip DDIC1, the second driver chip DDIC2, and the third driver chip DDIC3. Fig. 6A As shown in FIG. 6 , switches 6051a, 6051b, and 6051c are coupled to a first terminal of the communication interface 6041, and switches 6052a, 6052b, and 6052c are coupled to a second terminal of the communication interface 6041. In another embodiment, each of switches 6051a, 6051b, 6051c, 6052a, 6052b, and 6052c may be coupled to a different terminal of the communication interface 6041.

[0092] Please refer to Fig. 6A Based on the determination of the identification control signal M / S provided by the processor (not shown), the first driver chip DDIC1 can be set as the master driver chip, and the second driver chip DDIC2 and the third driver chip can be set as slave driver chips. Fig. 6A The first driver chip DDIC1 in the embodiment is set as the main driver chip, so only the first driver chip DDIC1 is configured to transmit the power enable signal AVDD_EN and the control signal SWIRE to the power supply circuit 604. In detail, in response to receiving a wake-up command from a processor (not shown), the first driver chip DDIC1 can turn on both the switch 6051a and the switch 6052a, the second driver chip DDIC2 can turn off both the switch 6051b and the switch 6052b, and the third driver chip DDIC3 can turn off both the switch 6051c and the switch 6052c. It should be noted that the timing control signal TC2 provided by the second driver chip DDIC2 is synchronized with the timing control signal TC1 provided by the first driver chip DDIC1. Therefore, only the first driver chip DDIC1 can output the power enable signal AVDD_EN and the control signal SWIRE to the power supply circuit 604.

[0093] Please refer to Fig. 6A, when the power supply circuit 604 receives the power enable signal AVDD_EN and the control signal SWIRE through the communication interface 6041, the power supply circuit 604 can provide the power supply voltage PV to the first driver chip DDIC1, the second driver chip DDIC2 and the third driver chip DDIC3. Therefore, the first driver chip DDIC1 can perform a power-on sequence (or a power-off sequence), the second driver chip DDIC2 can receive the timing control signal TC1 provided by the first driver chip DDIC1 and perform a power synchronization operation based on the power-on sequence (or power-off sequence) of the first driver chip DDIC1, and the third driver chip DDIC3 can receive the timing control signal TC2 provided by the second driver chip DDIC2 to perform a power synchronization operation based on the power-on sequence (or power-off sequence) of the second driver chip DDIC2. Therefore, the power-on sequences (or power-off sequences) of the first driver chip DDIC1, the second driver chip DDIC2 and the third driver chip DDIC3 are synchronized with each other. Fig. 6A The details of the power synchronization operation can be obtained by Figure 2 and FIG. 3A to FIG. 3C The embodiments of the present invention are analogous to those of the present invention, and thus will not be described in detail.

[0094] Figure 6B FIG. 1 is a block diagram of a multi-panel display device according to another embodiment of the present invention. Figure 6B Based on the determination of the identification control signal M / S provided by the processor (not shown), the second driver chip DDIC2 can be set as the master driver chip, and the first driver chip DDIC1 and the third driver chip can be set as slave driver chips. Figure 6B The second driver chip DDIC2 in the embodiment is set as the main driver chip, so only the second driver chip DDIC2 is configured to transmit the power enable signal AVDD_EN and the control signal SWIRE to the power supply circuit 604. In detail, in response to receiving a wake-up command from a processor (not shown), the first driver chip DDIC1 can turn off both the switch 6051a and the switch 6052a, the second driver chip DDIC2 can turn on both the switch 6051b and the switch 6052b, and the third driver chip DDIC3 can turn off both the switch 6051c and the switch 6052c. Therefore, only the second driver chip DDIC2 can output the power enable signal AVDD_EN and the control signal SWIRE to the power supply circuit 604.

[0095] Please refer to Figure 6B When the power supply circuit 604 receives the power enable signal AVDD_EN and the control signal SWIRE through the communication interface 6041 , the power supply circuit 604 can provide the power supply voltage PV to the first driving chip DDIC1 , the second driving chip DDIC2 , and the third driving chip DDIC3 . Figure 6B The details of the power synchronization operation can be obtained by Figure 2 and FIG. 3A to FIG. 3C The embodiments of the present invention are analogous to those of the present invention, and thus will not be described in detail.

[0096] Figure 7 is a block diagram of a multi-panel display device according to another embodiment of the present invention. Figure 7 , the multi-panel display device 700 includes a first display panel 701, a second display panel 702, a power supply circuit 703, a driving circuit 704, and a processor 705. The driving circuit 704 includes a first driving chip DDIC1 and a second driving chip DDIC2. The first driving chip DDIC1 and the second driving chip DDIC2 share a single power supply circuit 703, and the power supply circuit 703 is controlled by the processor 705. According to design requirements, the power supply circuit 703 can be a power management integrated circuit (PMIC), and the processor 705 can be an application processor. For example, the processor 705 can be an application processor (AP) of a foldable (or curved) OLED mobile phone as the multi-panel display device 700. The power supply circuit 703 can provide the power supply voltage PV (for example, the power supply voltage AVDD, the power supply voltage ELVDD, the power supply voltage ELVSS for driving the OLED pixel circuit) to both the first driver chip DDIC1 and the second driver chip DDIC2 based on the command provided by the processor 705, so that the first driver chip DDIC1 and the second driver chip DDIC2 can drive the first display panel 101 and the second display panel 102 respectively.

[0097] For example, in Figure 7 , the processor 705 includes a first terminal 7051 and a second terminal 7052, and the power supply circuit 703 includes a third terminal 7031 and a fourth terminal 7032. The first terminal 7051 of the processor 705 is coupled to the third terminal 7031 of the power supply circuit 703, and the second terminal 7052 of the processor 705 is coupled to the fourth terminal 7032 of the power supply circuit 703. In an embodiment, the processor 705 and the power supply circuit 703 communicate with each other through an interface of the SWIRE protocol, so that the processor 705 can transmit the power enable signal AVDD_EN to the third terminal 7031 of the power supply circuit 703 through the first terminal 7051, and the processor 705 can transmit the control signal SWIRE to the fourth terminal 7032 of the power supply circuit 703 through the second terminal 7052.

[0098] In addition, the hardware pins of the first driver chip DDIC 1 and the second driver chip DDIC 2 may be used or a command from the processor 705 may be used to define which of the first driver chip DDIC 1 and the second driver chip DDIC 2 is the master driver chip and which is the slave driver chip. Figure 7In the embodiment of FIG. 1 , the first driver chip DDIC1 is set as the master driver chip, and the second driver chip DDIC2 is set as the slave driver chip. Figure 7 The first driving chip DDIC1 is the main driving chip, so the first driving chip DDIC1 is configured to transmit the timing control signal TC to the second driving chip DDIC2.

[0099] When the processor 705 transmits the power enable signal AVDD_EN and the control signal SWIRE to the power supply circuit 703 , the power supply circuit 703 may provide the power voltage PV (eg, AVDD, ELVDD, ELVSS) to the first driver chip DDIC1 and the second driver chip DDIC2 based on the power enable signal AVDD_EN and the control signal SWIRE.

[0100] In summary, according to an embodiment of the present invention, the master driver chip and the slave driver chip in the multi-panel display device share a single power supply circuit. The slave driver chip can perform a power synchronization operation based on a timing control signal provided by the master driver chip and based on a power supply voltage provided by the single power supply circuit, so that the power timing of the slave driver chip and the master driver chip are synchronized. Therefore, the driving circuit and synchronization method of the present invention can reduce the number of power supply circuits in the multi-panel display device.

[0101] Although the present invention has disclosed the embodiments as above, they are not intended to limit the present invention. Any technician in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the definition of the claims.

Claims

1. A driving circuit for a multi-panel display device, comprising: a first driving chip configured to drive a first display panel of the multi-panel display device; as well as A second driver chip is configured to drive a second display panel of the multi-panel display device, wherein the first driver chip and the second driver chip share a power supply circuit, Based on the first identification control signal, one of the first driver chip and the second driver chip is set as the master driver chip, and based on the second identification control signal, the other of the first driver chip and the second driver chip is set as the slave driver chip. The main driver chip is configured to transmit a power enable signal and a control signal to the power supply circuit, and the power supply circuit is configured to provide a plurality of power supply voltages to the main driver chip and the slave driver chip based on the power enable signal and the control signal. In response to the master driver chip transmitting a timing control signal to the slave driver chip, the slave driver chip performs a power synchronization operation based on the timing control signal to synchronize the power timings of the slave driver chip and the master driver chip. 2 . The driving circuit of the multi-panel display device according to claim 1 , wherein the slave driving chip is configured to perform the power synchronization operation based on a power-up sequence or a power-down sequence.

3. The driving circuit of the multi-panel display device according to claim 1, wherein based on a handover command transmitted from a processor to both the first driving chip and the second driving chip, the first driving chip and the second driving chip swap the role of being set as the main driving chip.

4. The driving circuit of a multi-panel display device according to claim 3, wherein in response to the main driving chip receiving the handover command, the main driving chip sets the power enable signal and the control signal to change from an active state to a high impedance state or a weak pull-up state after a first delay time, wherein the first delay time is a delay time calculated from a pulse of an internal vertical synchronization signal of the main driving chip immediately after the handover command.

5. The driving circuit of a multi-panel display device according to claim 3, wherein in response to the slave driver chip receiving the handover command, the slave driver chip sets both the power enable signal and the control signal to change from a high impedance state or a weak pull-up state to an active state after a second delay time, wherein the second delay time is a delay time calculated from a pulse of an internal vertical synchronization signal of the slave driver chip immediately after the handover command. 6 . The driving circuit of the multi-panel display device according to claim 1 , wherein the power enable signal and the control signal are transmitted via an Inter-integrated Circuit (I 2 C) interface.

7. The driving circuit of the multi-panel display device according to claim 1, wherein the first driving chip comprises: A first switch coupled to a first terminal of the power supply circuit; as well as a second switch coupled to a second terminal of the power supply circuit, The second driver chip comprises: a third switch coupled to the first terminal of the power supply circuit; as well as a fourth switch coupled to the second terminal of the power supply circuit, When the first driver chip is set as the main driver chip, the first driver chip turns on the first switch and the second switch, and turns off the third switch and the fourth switch, so that the power enable signal and the control signal are output to the power supply circuit; When the second driver chip is set as the main driver chip, the second driver chip turns on the third switch and the fourth switch, and turns off the first switch and the second switch, so that the power enable signal and the control signal are output to the power supply circuit.

8. The driving circuit of the multi-panel display device according to claim 1, wherein when the first driving chip is set as the main driving chip, the first driving chip outputs the power enable signal and the control signal to the power supply circuit via the first switch and the second switch of the power supply circuit being turned on; When the second driver chip is set as the main driver chip, the second driver chip outputs the power enable signal and the control signal to the power supply circuit via the turned-on third switch and fourth switch of the power supply circuit.

9. The driving circuit of the multi-panel display device according to claim 1, further comprising: A third driver chip is configured to drive a third panel of the multi-panel display device, wherein the first driver chip, the second driver chip and the third driver chip share the power supply circuit, Based on the first identification control signal, one of the first driver chip, the second driver chip and the third driver chip is set as the master driver chip, and based on the second identification control signal, the other two driver chips of the first driver chip, the second driver chip and the third driver chip are set as two slave driver chips. wherein the main driving chip is configured to transmit the power enable signal and the control signal to the power supply circuit, and the power supply circuit is configured to provide the plurality of power supply voltages to the main driving chip and the two slave driving chips based on the power enable signal and the control signal, In response to the master driver chip transmitting the timing control signal to the two slave driver chips, the two slave driver chips perform the power synchronization operation based on the timing control signal to keep the power timing of the two slave driver chips and the master driver chip synchronized.

10. The driving circuit of the multi-panel display device according to claim 1, further comprising: A third driver chip is configured to drive a third panel of the multi-panel display device, wherein the first driver chip, the second driver chip and the third driver chip share the power supply circuit, Based on the first identification control signal, one of the first driver chip, the second driver chip and the third driver chip is set as the master driver chip, and based on the second identification control signal, the other two driver chips of the first driver chip, the second driver chip and the third driver chip are set as the first slave driver chip and the second slave driver chip, wherein the master driver chip is configured to transmit the power enable signal and the control signal to the power supply circuit, and the power supply circuit is configured to provide the plurality of power supply voltages to the master driver chip, the second slave driver chip, and the third slave driver chip based on the power enable signal and the control signal, In response to the master driver chip transmitting a first timing control signal to the first slave driver chip, the first slave driver chip performs the power synchronization operation based on the first timing control signal to synchronize the power timings of the first slave driver chip and the master driver chip. In response to the first slave driver chip transmitting a second timing control signal synchronized with the first timing control signal to the second slave driver chip, the second slave driver chip performs the power synchronization operation based on the second timing control signal to keep the power timing of the second slave driver chip synchronized with the first slave driver chip.

11. A driving circuit for a multi-panel display device, comprising: a first driving chip configured to drive a first display panel of the multi-panel display device; as well as a second driver chip configured to drive a second display panel of the multi-panel display device, wherein the first driver chip and the second driver chip share a power supply circuit, and the power supply circuit is controlled by a processor, wherein the processor is configured to transmit a power enable signal and a control signal to the power supply circuit, and the power supply circuit is configured to provide a plurality of power supply voltages to the first driver chip and the second driver chip based on the power enable signal and the control signal, Based on a first identification control signal provided by the processor, one of the first driver chip and the second driver chip is set as a master driver chip, and based on a second identification control signal, the other of the first driver chip and the second driver chip is set as a slave driver chip. In response to the master driver chip transmitting a timing control signal to the slave driver chip, the slave driver chip performs a power synchronization operation based on the timing control signal to synchronize the power timings of the slave driver chip and the master driver chip. 12 . The driving circuit of the multi-panel display device according to claim 11 , wherein the slave driving chip is configured to perform the power synchronization operation based on a power-up sequence or a power-down sequence. 13 . The driving circuit of the multi-panel display device according to claim 11 , wherein based on a handover command transmitted from the processor to both the first driving chip and the second driving chip, the first driving chip and the second driving chip swap roles set as the main driving chip.

14. A synchronization method of a driving circuit, applicable to a multi-panel display device, wherein the driving circuit comprises a first driving chip for driving a first display panel of the multi-panel display device and a second driving chip for driving a second display panel of the multi-panel display device, wherein the first driving chip and the second driving chip share a power supply circuit, and the synchronization method of the driving circuit comprises: Based on a first identification control signal, one of the first driver chip and the second driver chip is set as a master driver chip, and based on a second identification control signal, the other of the first driver chip and the second driver chip is set as a slave driver chip; Using the main driving chip to transmit a power enabling signal and a control signal to the power supply circuit; Based on the power enable signal and the control signal, using the power supply circuit to provide a plurality of power supply voltages to the master driver chip and the slave driver chip; In response to the master driver chip transmitting a timing control signal to the slave driver chip, the slave driver chip performs a power synchronization operation based on the timing control signal to synchronize power timings of the slave driver chip and the master driver chip. 15 . The synchronization method of a driving circuit according to claim 14 , wherein the slave driving chip performs the power synchronization operation based on a power-on sequence or a power-off sequence.

16. The synchronization method of the driving circuit according to claim 14, further comprising: The processor is used to transmit a handover command to both the first driving chip and the second driving chip, so that the first driving chip and the second driving chip exchange the role of being set as the main driving chip.

17. The synchronization method of the driving circuit according to claim 16, further comprising: In response to the main driver chip receiving the handover command, the main driver chip sets the power enable signal and the control signal to change from the active state to the high impedance state or the weak pull-up state after a first delay time, wherein the first delay time is a delay time calculated from the pulse of the internal vertical synchronization signal of the main driver chip immediately after the handover command.

18. The synchronization method of the driving circuit according to claim 16, further comprising: In response to the slave driver chip receiving the handover command, the slave driver chip sets both the power enable signal and the control signal to change from a high impedance state or a weak pull-up state to an active state after a second delay time, wherein the second delay time is a delay time calculated from a pulse of an internal vertical synchronization signal of the slave driver chip immediately following the handover command.

19. The synchronization method of the driving circuit according to claim 14, wherein the driving circuit further comprises a third driving chip for driving a third display panel of the multi-panel display device, and the first driving chip, the second driving chip and the third driving chip share the power supply circuit, and the synchronization method of the driving circuit further comprises: Based on the first identification control signal, one of the first driver chip, the second driver chip and the third driver chip is set as the master driver chip, and based on the second identification control signal, the other two driver chips among the first driver chip, the second driver chip and the third driver chip are set as two slave driver chips; Using the main driving chip to transmit the power enabling signal and the control signal to the power supply circuit; Based on the power enable signal and the control signal, using the power supply circuit to provide the plurality of power supply voltages to the master driver chip and the two slave driver chips; In response to the master driver chip transmitting the timing control signal to the two slave driver chips, the slave driver chips perform the power synchronization operation based on the timing control signal to synchronize the power timings of the slave driver chips with the master driver chip.

20. The synchronization method of the driving circuit according to claim 14, wherein the driving circuit further comprises a third driving chip for driving a third display panel of the multi-panel display device, and the first driving chip, the second driving chip and the third driving chip share the power supply circuit, and the synchronization method of the driving circuit further comprises: Based on the first identification control signal, one of the first driver chip, the second driver chip and the third driver chip is set as the master driver chip, and based on the second identification control signal, the other two driver chips of the first driver chip, the second driver chip and the third driver chip are set as the first slave driver chip and the second slave driver chip; Using the main driving chip to transmit the power enabling signal and the control signal to the power supply circuit; Based on the power enable signal and the control signal, using the power supply circuit to provide the plurality of power supply voltages to the master driver chip, the first slave driver chip and the second slave driver chip; In response to the master driver chip transmitting a first timing control signal to the first slave driver chip, the first slave driver chip performs the power synchronization operation based on the first timing control signal to synchronize the power timings of the first slave driver chip and the master driver chip; In response to the first slave driver chip transmitting a second timing control signal synchronized with the first timing control signal to the second slave driver chip, the second slave driver chip performs the power synchronization operation based on the second timing control signal to synchronize the power timings of the second slave driver chip and the first slave driver chip.

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