Compensation circuit and display device including same

Abstract

A compensation circuit according to an embodiment and a display device including the same are disclosed. The compensation circuit includes: a gain compensator configured to generate a voltage drop amount using a first pixel driving voltage output from a power supply and a second pixel driving voltage fed back from a wiring of a display panel, in which the generated voltage drop amount is amplified by a predetermined gain value; a first voltage compensator configured to adjust the first reference voltage using the generated voltage drop amount to generate a high potential gamma reference voltage; and a second voltage compensator configured to adjust a second reference voltage using the generated voltage drop amount to generate a low potential gamma reference voltage, the gain value being a value calculated using voltages at two predetermined points within a wiring of the display panel. Accordingly, it is possible to provide a separate compensation circuit optimized according to the position at which the pixel driving voltage is fed back.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0132392, filed on October 5, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a compensation circuit and a display device including the compensation circuit. Background Art

[0004] According to the material of the light-emitting layer, electroluminescent display devices are divided into inorganic light-emitting display devices and organic light-emitting display devices. Active matrix organic light-emitting display devices include self-luminous organic light-emitting diodes (hereinafter referred to as "OLEDs"), and have the advantages of fast response speed, high light-emitting efficiency, brightness and viewing angle.

[0005] In an organic light emitting display device, an organic light emitting diode (called "OLED") is formed in each pixel. These organic light emitting display devices not only have a fast response and excellent luminous efficiency, brightness and viewing angle, but also have excellent contrast and color reproduction rate because these organic light emitting display devices can display black tones as completely black.

[0006] In order to drive the pixel, a pixel driving voltage ELVDD is applied to the pixel. The pixel driving voltage ELVDD has a voltage drop according to the load in the display panel. The compensation circuit compensates the gamma reference voltage using the pixel driving voltage fed back from the input terminal of the display panel, thereby compensating for the voltage drop of the pixel driving voltage.

[0007] In this case, the pixel is a variable resistor, and the resistance of the wiring to which the pixel driving voltage is applied is a fixed resistor. Therefore, when the resistance value of the pixel changes according to the image data, the voltage at the feedback position of the pixel driving voltage also changes, making it difficult to accurately compensate for the voltage drop.

[0008] In addition, if the resistance value of the pixel changes according to the image data, the gain value, which is the resistance ratio of the differential amplifier, should change according to the image data, but the gain value is fixed. Therefore, when the gain value is fixed to match the image data of a specific grayscale level, there will inevitably be over-compensated or uncompensated areas in the image data of other grayscale levels. Summary of the invention

[0009] The present disclosure is intended to address all of the above-mentioned needs and problems.

[0010] The present disclosure provides a compensation circuit and a display device including the compensation circuit.

[0011] It should be noted that the objects of the present disclosure are not limited to the above objects, and other objects of the present disclosure will be apparent to those skilled in the art from the following description.

[0012] A compensation circuit according to an embodiment of the present disclosure may include: a gain compensator, which is configured to generate a voltage drop using a first pixel driving voltage output from a power supply and a second pixel driving voltage fed back from a wiring of a display panel, wherein the generated voltage drop is amplified with a predetermined gain value; a first voltage compensator, which is configured to adjust a first reference voltage using the generated voltage drop to generate a high-potential gamma reference voltage; and a second voltage compensator, which is configured to adjust a second reference voltage using the generated voltage drop to generate a low-potential gamma reference voltage, wherein the gain value is a value calculated using voltages at two predetermined points within the wiring of the display panel.

[0013] A display device according to an embodiment of the present disclosure may include: a display panel in which a plurality of data lines, a plurality of gate lines, and pixels to which a first pixel driving voltage is provided; a data driving unit configured to provide pixel data to the plurality of data lines; and a power supply configured to provide the first pixel driving voltage; and a compensation circuit configured to calculate a voltage drop amount of the first pixel driving voltage, wherein the compensation circuit includes: a gain compensator configured to generate a voltage drop amount using the first pixel driving voltage output from the power supply and a second pixel driving voltage fed back from a wiring of the display panel, wherein the generated voltage drop amount is amplified with a predetermined gain value; a first voltage compensator configured to adjust a first reference voltage using the generated voltage drop amount to generate a high potential gamma reference voltage; and a second voltage compensator configured to adjust a second reference voltage using the generated voltage drop amount to generate a low potential gamma reference voltage, wherein the gain value is a value calculated using voltages at two predetermined points within the wiring of the display panel.

[0014] According to the present disclosure, a mathematical formula for compensating for the voltage drop in the pixel drive voltage can be derived using the voltages of at least two points in the wiring of a display panel to which a pixel drive voltage is applied from a power supply, and a compensation circuit can be implemented based on the derived mathematical formula, so that a separate compensation circuit optimized according to the location where the pixel drive voltage is fed back can be provided.

[0015] Since the present disclosure can provide an optimized separate compensation circuit, the performance of compensating for the voltage drop of the pixel driving voltage can be maximized.

[0016] The present disclosure can reduce power consumption by maximizing the performance of compensating for the voltage drop of the pixel driving voltage.

[0017] The effects of the present application are not limited to the above-mentioned effects, and other effects not mentioned will be clearly understood by those skilled in the art from the following description and the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and other objects, features and advantages of the present disclosure will become more apparent to those skilled in the art by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0019] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present disclosure;

[0020] Figure 2 It is a graphic Figure 1 A diagram showing a cross-sectional structure of a display panel shown in ;

[0021] Figure 3 is a diagram for explaining the operation of a compensation circuit according to an embodiment of the present disclosure;

[0022] 4A to 4F is a diagram for explaining the problems of the conventional compensation circuit;

[0023] Figure 5 is a diagram illustrating a detailed configuration of a compensation circuit according to an embodiment of the present disclosure;

[0024] Figures 6 to 8 is a diagram for explaining a compensation circuit according to a first embodiment;

[0025] Figures 9 to 11 is a diagram for explaining a compensation circuit according to a second embodiment;

[0026] Fig.12 is a diagram for explaining a compensation circuit according to a third embodiment;

[0027] Fig.13 is a diagram for explaining a compensation circuit according to a fourth embodiment;

[0028] Fig.14 and Fig.15 is a diagram for explaining a compensation circuit according to a fifth embodiment;

[0029] Fig.16A and Fig. 16B is a diagram illustrating an arrangement of a compensation circuit according to an embodiment; and

[0030] Fig.17 It is a graphic Figure 5A circuit diagram of an example of a gamma compensation voltage generator is shown in FIG. DETAILED DESCRIPTION

[0031] The advantages and features of the present application and the methods for achieving the advantages and features will become apparent from the exemplary embodiments described in conjunction with the accompanying drawings. However, the present application is not limited to the embodiments to be described below, but can be implemented in different forms, each of which is only provided to complete the disclosure of the present disclosure and fully convey the scope of the present disclosure to those skilled in the art, and the present application is defined by the disclosed claims.

[0032] Since the shapes, sizes, ratios, angles, quantities, etc. illustrated in the drawings for describing the embodiments of the present disclosure are only exemplary, the present disclosure is not limited to the illustrative items. Throughout the application, the same reference numerals represent the same components. In addition, when describing the present disclosure, when it is determined that the detailed description of the related known technology may unnecessarily obscure the subject matter of the present disclosure, its detailed description will be omitted.

[0033] When “including”, “having”, “comprising”, etc. mentioned in the present application are used, other parts may be added unless “only” is used. Unless otherwise clearly stated, the case of expressing a component in the singular includes the plural form.

[0034] In explaining the components, it should be understood that an error range is included even when there is no separate explicit description.

[0035] In the case of describing a positional relationship, for example, when the positional relationship of two components is described as "on," "upper," "lower," "next to," etc., unless "immediately" or "directly" is used, one or more other components may be located between the two components.

[0036] Although the terms "first", "second", etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another component. Therefore, within the technical spirit of the present disclosure, the first component mentioned below can also be the second component.

[0037] Like reference numerals may refer to substantially like elements throughout this application.

[0038] The following embodiments may be combined or combined with each other in part or in whole, and may be linked and operated in various technical ways. These embodiments may be implemented independently or in association with each other.

[0039] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0040] In the display device of the present disclosure, the pixel circuit and the gate driving circuit may include a plurality of transistors. The transistors may be implemented as oxide thin film transistors (oxide TFTs) including oxide semiconductors, low temperature polysilicon (LTPS) TFTs including low temperature polysilicon, and the like.

[0041] A transistor is a three-electrode element including a gate, a source, and a drain. The source is an electrode that provides carriers to the transistor. In a transistor, carriers begin to flow from the source. The drain is the electrode from which carriers leave the transistor. In a transistor, carriers flow from the source to the drain. In the case of an n-channel transistor, since the carriers are electrons, the source voltage is a voltage lower than the drain voltage, so that electrons can flow from the source to the drain. An n-channel transistor has a direction of current flowing from the drain to the source. In the case of a p-channel transistor (P-channel metal oxide semiconductor (PMOS)), since the carriers are holes, the source voltage is higher than the drain voltage, so that holes can flow from the source to the drain. In a p-channel transistor, since holes flow from the source to the drain, current flows from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain may change according to the applied voltage. Therefore, the present disclosure is not limited by the source and drain of a transistor. In the following description, a source and a drain of a transistor will be referred to as a first electrode and a second electrode.

[0042] The gate signal swings between a gate-on voltage and a gate-off voltage. The gate-on voltage is set to a voltage higher than a threshold voltage of the transistor, and the gate-off voltage is set to a voltage lower than the threshold voltage of the transistor.

[0043] The transistor is turned on in response to a gate-on voltage and turned off in response to a gate-off voltage. In the case of an n-channel transistor, the gate-on voltage may be a gate high voltage, and the gate-off voltage may be a gate low voltage. In the case of a p-channel transistor, the gate-on voltage may be a gate low voltage, and the gate-off voltage may be a gate high voltage.

[0044] In an embodiment, a mathematical formula for compensating for a voltage drop in a pixel driving voltage can be derived using voltages at two predetermined points, including points where a pixel driving voltage is fed back in a wiring of a display panel to which a pixel driving voltage is applied from a power supply, and a compensation circuit can be implemented based on the derived mathematical formula.

[0045] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present disclosure, Figure 2 It is a graphic Figure 1 Schematic diagram of a cross-sectional structure of a display panel shown in .

[0046] Reference Figure 1 and Figure 2, a display device according to an embodiment of the present disclosure includes: a display panel 100, a display panel driving unit configured to write pixel data to pixels of the display panel 100, and a power supply unit 600 configured to generate power required to drive the pixels and the display panel driving unit.

[0047] The display panel 100 may be a panel of a rectangular structure having a length in the X-axis direction, a width in the Y-axis direction, and a thickness in the Z-axis direction. The display area AA of the display panel 100 includes a pixel array that displays an input image. The pixel array includes a plurality of data lines 102, a plurality of gate lines 103 intersecting the data lines 102, and pixels arranged in a matrix form. The display panel 100 may further include a power line commonly connected to the pixel. The power line may be commonly connected to the pixel circuit and may supply the voltage required to drive the pixel 101 to the pixel 101.

[0048] Each pixel 101 can be divided into a red sub-pixel, a green sub-pixel and a blue sub-pixel to achieve color. Each pixel can further include a white sub-pixel. Each sub-pixel includes a pixel circuit for driving a light-emitting element. Each pixel circuit is connected to a data line, a gate line and a power line.

[0049] The pixel array includes a plurality of pixel rows L1 to Ln. Each of the pixel rows L1 to Ln includes a row of pixels arranged in a row direction or a length direction (X-axis direction) of the display panel in the pixel array of the display panel 100.

[0050] The display panel 100 may be implemented as a non-transmissive display panel or a transmissive display panel. The transmissive display panel may be applied to a transparent display device in which an image is displayed on a screen and a real background object is visible. The display panel may be manufactured as a flexible display panel.

[0051] The cross-sectional structure of the display panel 100 may include: a circuit layer CIR, a light emitting element layer EMIL, and an encapsulation layer ENC stacked on a substrate SUBS. Figure 2 as shown in .

[0052] The circuit layer CIR may include a thin film transistor (TFT) array including pixel circuits connected to wirings such as data lines, gate lines, power lines, etc., and gate drivers 410 and 420. The circuit layer CIR includes a plurality of metal layers insulated with an insulating layer interposed therebetween, and a semiconductor material layer. All transistors formed in the circuit layer CIR may be implemented as n-channel oxide TFTs.

[0053] The light-emitting element layer EMIL may include a light-emitting element driven by a pixel circuit. The light-emitting element may include a light-emitting element of a red sub-pixel, a light-emitting element of a green sub-pixel, and a light-emitting element of a blue sub-pixel. The light-emitting element layer EMIL may also include a light-emitting element of a white sub-pixel. The light-emitting element layer EMIL corresponding to each sub-pixel may have a structure in which a light-emitting element and a color filter are stacked. The light-emitting element EL in the light-emitting element layer EMIL may be covered by a plurality of protective layers including an organic film and an inorganic film.

[0054] The encapsulation layer ENC covers the light emitting element layer EMIL to seal the circuit layer CIR and the light emitting element layer EMIL. The encapsulation layer ENC may also have a multi-insulating film structure in which organic films and inorganic films are alternately stacked. The inorganic film blocks the penetration of moisture and oxygen. The organic film flattens the surface of the inorganic film. When the organic layer and the inorganic layer are stacked into multiple layers, the movement path of moisture and oxygen becomes longer than that of a single layer, so that the penetration of moisture and oxygen into the light emitting element layer EMIL can be effectively blocked.

[0055] A touch sensor layer (not shown) may be formed on the encapsulation layer ENC, and a polarizing plate or a color filter layer may be disposed thereon. The touch sensor layer may include a capacitive touch sensor that senses a touch input based on a capacitance change before and after the touch input. The touch sensor layer may have a metal wiring pattern and an insulating film that form the capacitance of the touch sensor. The insulating film may insulate the area where the metal wiring pattern intersects and may flatten the surface of the touch sensor layer. The polarizing plate may improve visibility and contrast by converting the polarization of external light reflected by the metal in the touch sensor layer and the circuit layer. The polarizing plate may be implemented as a circular polarizing plate, or a polarizing plate in which a linear polarizing plate and a phase delay film are combined. The cover glass may be adhered to the polarizing plate. The color filter layer may include a red filter, a green filter, and a blue filter. The color filter layer may further include a black matrix pattern. The color filter layer may replace the polarizing plate by absorbing a portion of the wavelength of light reflected from the circuit layer and the touch sensor layer, and increase the color purity of the image reproduced in the pixel array.

[0056] The power supply unit 500 generates direct current (DC) power required to drive the pixel array and the display panel driving unit of the display panel 100 by using a DC-DC converter. The DC-DC converter may include a charge pump, a regulator, a buck converter, a boost converter, etc. The power supply unit 600 may adjust the level of the input DC voltage applied from the host system (not shown) to generate a constant voltage (or DC voltage), such as a gamma reference voltage VGMA, a gate-on voltage VGH and VEH, a gate-off voltage VGL and VEL, a pixel driving voltage ELVDD, a low potential power supply voltage ELVSS, an initialization voltage Vinit, and a reference voltage Vref. The gamma reference voltage VGMA is supplied to the data driving unit 200. The gate-on voltages VGH and VEH and the gate-off voltages VGL and VEL are supplied to the gate driving unit 300. Constant voltages such as the pixel driving voltage ELVDD, the low potential power supply voltage ELVSS, the initialization voltage Vinit, and the reference voltage Vref are commonly supplied to the pixel.

[0057] The display panel driving unit writes pixel data of an input image to pixels of the display panel 100 under the control of a timing controller (T-CON) 400 .

[0058] The display panel driving unit includes a data driving unit 200 and a gate driving unit 300. The display panel driving unit includes a timing controller (T-CON) 400 that controls the data driving unit 200 and the gate driving unit 300.

[0059] The display panel driving unit may further include a touch sensor driving unit for driving the touch sensor. The touch sensor driving unit is omitted in the drawings. The data driving unit 200 and the touch sensor driving unit may be integrated into one integrated circuit (IC).

[0060] The data driving unit 200 generates a data voltage Vdata by converting pixel data of an input image received from the timing controller 400 with a gamma compensation voltage in each frame period using a digital-to-analog converter (DAC). The gamma reference voltage VGMA is divided for each grayscale by a voltage divider circuit. The gamma compensation voltage divided from the gamma reference voltage VGMA is provided to the DAC of the data driving unit 200. The data voltage Vdata is output through an output buffer AMP of each channel of the data driving unit 200.

[0061] In the data driving unit 200, the output buffer AMP included in one channel may be connected to the adjacent data line 102 through the demultiplexer array. The demultiplexer array may be directly formed on the substrate of the display panel 100 or integrated into one driving IC together with the data driving unit 200.

[0062] The gate driving unit 300 may be implemented as a gate in panel (GIP) circuit directly formed on the bezel region of the display panel 100 together with the TFT array of the display area AA. The gate driving unit 300 sequentially outputs gate signals to the gate lines 103 under the control of the timing controller 400. The gate driving unit 300 may sequentially supply the gate signals to the gate lines 103 by shifting the gate signals using a shift register.

[0063] The timing controller 400 receives the digital video data DATA of the input image and the timing signal synchronized with the digital video data from the host system. The timing signal may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a clock CLK, a data enable signal DE, etc. Since the vertical period and the horizontal period can be obtained by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync can be omitted. The data enable signal DE has a period of one horizontal cycle 1H.

[0064] The host system may be one of a TV system, a tablet computer, a laptop computer, a personal computer (PC), a home theater system, and a vehicle system. The host system may scale an image signal from a video source to match the resolution of the display panel 100 and transmit the generated image signal and a timing signal to the timing controller 400.

[0065] The timing controller 400 transmits pixel data of an input image to the data driving unit 200. Based on the timing signals Vsync, Hsync, and DE received from the host system, the timing controller 400 generates a data timing control signal for controlling the operation timing of the data driving unit 200 and a gate timing control signal for controlling the operation timing of the gate driving unit 300. The timing controller 400 synchronizes the data driving unit 200 and the gate driving unit 300 by controlling the operation timing of the display panel driving circuit.

[0066] The gate timing control signal output from the timing controller 400 may be input to the gate driving unit 300 through a level shifter (not shown). The level shifter may receive the gate timing control signal, generate a start signal and a shift clock, and supply them to the gate driving unit 300.

[0067] Figure 3 is a diagram for explaining the operation of the compensation circuit according to an embodiment of the present disclosure.

[0068] Reference Figure 3According to an embodiment of the present disclosure, the compensation circuit 600 may calculate a voltage drop amount using a pixel driving voltage ELVDD_IC applied from a power supply 500 and a pixel driving voltage ELVDD_FB fed back from a display panel 100, and adjust a gamma reference voltage using the calculated voltage drop amount to provide the adjusted gamma reference voltage to a gamma voltage generator 700.

[0069] The gamma voltage generator 700 may generate a gamma voltage for each gray level using the adjusted gamma reference voltages, ie, the high potential gamma reference voltage GMA_REF_H and the low potential gamma reference voltage GMA_REF_L.

[0070] The compensation circuit 600 according to the embodiment may be implemented as a circuit designed based on a mathematical formula for compensating for a voltage drop in a pixel driving voltage using voltages of at least two points in a wiring to which the pixel driving voltage is applied and deriving the mathematical formula.

[0071] FIG. 4A to FIG. 4E 1 is a diagram for explaining problems of a conventional compensation circuit.

[0072] Reference Figure 4A , the two points in the wiring to which the pixel driving voltage is applied may include: a first point P1 to which the pixel driving voltage is fed back, and a second point P2 for calculating the voltage drop amount. For example, the first point P1 may be a location to which the pixel driving voltage is fed back, and the second point P2 may be a location to measure a voltage for compensating the fed-back pixel driving voltage.

[0073] Here, although the first point P1 is disposed closer to the power source 500 than the second point P2, it is not necessarily limited thereto, and the second point P2 may be closer than the first point P1.

[0074] When the pixel is called a variable resistor and the resistance on the wiring is called a fixed resistor, it can be expressed as Figure 4A and 4C An equivalent circuit in which the resistance value shown in FIG. 1 changes according to the gray scale.

[0075] Reference Figure 4B , which shows an equivalent circuit in which the resistance value changes according to the high grayscale, and when the resistance value changes according to the image data, the voltage at the first point P1 and the second point P2 also changes. For example, if the pixel driving voltage is ELVDD=12V, and the resistance values ​​Ra, Rb, and Rc of the wiring and the pixel in the display panel are all 1Ω, the current flowing in the wiring in the display panel is I=4A, so that the voltage at the first point P1 is 8V and the voltage at the second point P2 is 4V.

[0076] Reference Figure 4C, which shows an equivalent circuit in which the resistance value changes according to the low gray level, and when the resistance value changes according to the image data, the voltage at the first point P1 and the second point P2 also changes. For example, if the pixel driving voltage is ELVDD=12V, the resistance values ​​Ra and Rb of the wiring in the display panel are 1Ω, and the resistance value Rc of the pixel is 10Ω, the current flowing in the wiring in the display panel is I=1A, so that the voltage at the point P1 is 11V and the voltage at the point P2 is 10V.

[0077] Reference Figure 4D , it can be seen that when the resistance value of the pixel changes according to the gray level, the voltage at the first point P1 and the second point P2 changes. In order to compensate the voltage at the second point P2, different gain values ​​should be applied to the voltage at the first point P1 according to the gray level.

[0078] Reference Figure 4E In a conventional compensation circuit, the gain value is fixed to the ratio of the resistance values ​​(Ra / Rb). Therefore, with the conventional compensation circuit, different gain values ​​cannot be applied according to the grayscale level.

[0079] Furthermore, since it is not possible to apply different gain values, when the gain value is fixed to a specific gray level, there will inevitably be areas of over-compensation or under-compensation.

[0080] Reference Figure 4F , which shows the result of measuring the brightness change rate according to the gray level. When the same gain value is applied to Figure 4E When the conventional compensation circuit shown in , the brightness at the second point decreases due to the increase in the voltage drop amount in the white pattern, and the brightness at the second point increases due to the decrease in the voltage drop amount in the black pattern.

[0081] Since the voltage drop caused by the resistor at the input terminal of the display panel is compensated by the compensation circuit, it can be seen that the brightness should be constant in the area outside the specific pattern, but the compensation rate is low. The deviation of the brightness change rate tends to increase from high grayscale to low grayscale.

[0082] Therefore, the compensation circuit according to the embodiment can be implemented as a circuit that derives a mathematical expression for compensating for the voltage drop amount in the pixel driving voltage using voltages of at least two points in the wiring to which the pixel driving voltage is applied, and is designed based on the derived mathematical expression.

[0083] Figure 5 is a diagram illustrating a detailed configuration of a compensation circuit according to an embodiment of the present disclosure.

[0084] Reference Figure 5, the compensation circuit 600 according to an embodiment of the present disclosure may include a gain compensator 610 , a first voltage compensator 620 , and a second voltage compensator 630 .

[0085] The gain compensator 610 may generate a voltage drop amount ELVDD_FB′ using a pixel driving voltage ELVDD_IC applied from a power source and a pixel driving voltage ELVDD_FB fed back from a display panel, wherein the voltage drop amount ELVDD_FB′ may be amplified by a predetermined gain value.

[0086] The first voltage compensator 620 may adjust the first reference voltage REF_H using the voltage drop amount ELVDD_FB′ generated by the gain compensator 610 to generate an adjusted high potential gamma reference voltage GMA_REF_H.

[0087] The second voltage compensator 630 may adjust the second reference voltage REF_L using the voltage drop amount ELVDD_FB′ generated by the gain compensator 610 to generate an adjusted low potential gamma reference voltage GMA_REF_L.

[0088] Figures 6 to 8 is a diagram for explaining the compensation circuit according to the first embodiment.

[0089] Reference Figures 6 to 8 , shows an equivalent circuit of a path of a pixel driving voltage when a resistance to a first point P1 is lower than a resistance to a second point P2 in a wiring to which the pixel driving voltage is applied according to the first embodiment.

[0090] Since the resistance value of the input terminal of the display panel at point P1 and the resistance value of the internal wiring at point P2 are fixed values, and the resistance value within the pixel is a variable value according to the pattern of the image data, the gain value is different. However, since the current flowing through the resistance of the input terminal at point P1 and the current flowing through the resistance of the internal wiring at point P2 are always constant, the ratio of the voltage difference between the two ends of each resistor is always the same. Therefore, the voltage at the second point P2 can be calculated using the ratio of the resistance of the input terminal to the resistance of the internal wiring and the voltage at the first point.

[0091] The voltage V3 measured at the second point P2 may be defined as the following Mathematical Expression 1.

[0092] [Formula 1]

[0093]

[0094] Here, V1 is a pixel driving voltage applied from a power source, V2 is a pixel driving voltage fed back from an input terminal of a display panel, a is a resistance value Ra of an input terminal of a display panel, and b is a resistance value Rb of an internal wiring. Here, the resistance value Rc of a pixel is excluded because any value does not affect the above expression 1 which is a voltage relationship between a first point and a second point.

[0095] like Figure 7 As shown in , it can be seen that the voltage actually measured at the second point is the same as the voltage calculated by Formula 1. In other words, it can be seen that the value calculated by Formula 1 is accurate.

[0096] Therefore, in an embodiment, when the resistance to the first point is lower than the resistance to the second point, the gain compensator is designed to compensate the feedback voltage using the above Equation 1.

[0097] like Figure 8 As shown in FIG. 6 , the compensation circuit 600 - 1 according to the first embodiment may include a gain compensator 610 - 1 , a first voltage compensator 620 - 1 , and a second voltage compensator 630 - 1 .

[0098] The gain compensator 610-1 may include a first amplifier circuit implemented by Formula 1. The first amplifier circuit may include: a first operational amplifier OP1-1; a first resistor Ra-1, the first resistor Ra-1 is connected to the inverting input terminal (-) of the first operational amplifier OP1-1 and is applied with a pixel driving voltage V1 output from a power supply; and a second resistor Rb-1, the second resistor Rb-1 is connected between the output terminal OUT and the inverting input terminal (-) of the first operational amplifier OP1-1.

[0099] The pixel driving voltage V2 fed back from the second point P2 is applied to the non-inverting input terminal (+) of the first operational amplifier OP1-1, the pixel driving voltage V1 applied from the power supply is applied to the inverting input terminal (-) of the first operational amplifier OP1-1, and a voltage that compensates the pixel driving voltage by feedback of the gain value is output from the output terminal OUT of the first operational amplifier OP1-1.

[0100] The voltage V3 output from the output terminal OUT of the first operational amplifier OP1 - 1 is expressed by Equation 1.

[0101] The first voltage compensator 620-1 may adjust the first reference voltage REF_H (eg, Figure 8 V4 in ) to generate a high potential gamma reference voltage GMA_REF_H.

[0102] The generated high potential gamma reference voltage GMA_REF_H is expressed by the following equation 2.

[0103] [Formula 2]

[0104]

[0105] The first voltage compensator 620-1 may include a second amplifier circuit. The second amplifier circuit may include: a second operational amplifier OP2-1; a first resistor R2a-1, the first resistor R2a-1 is connected between the inverting input terminal (-) of the second operational amplifier OP2-1 and the ground GND; a second resistor R2b-1, the second resistor R2b-1 is connected between the output terminal OUT and the inverting input terminal (-) of the operational amplifier OP2-1; a third resistor R2c-1, the third resistor R2c-1 is connected to the non-inverting input terminal (+) of the second operational amplifier OP2-1 and is applied with a voltage output from the first operational amplifier OP1-1; and a fourth resistor R2d-1, the fourth resistor R2d-1 is connected to the non-inverting input terminal (+) of the second operational amplifier OP2-1 and is applied with a first reference voltage REF_H.

[0106] For example, the first resistor R2a-1, the second resistor R2b-1, the third resistor R2c-1, and the fourth resistor R2d-1 may have the same resistance value, but are not necessarily limited thereto and may be different.

[0107] The second voltage compensator 630-1 may adjust the second reference voltage REF_L (eg, Figure 8 V5 in ) to generate a low potential gamma reference voltage GMA_REF_L.

[0108] The generated low potential gamma reference voltage GMA_REF_L is expressed by the following equation 3.

[0109] [Formula 3]

[0110]

[0111] The second voltage compensator 630-1 may include a third amplifier circuit. The third amplifier circuit may include: a third operational amplifier OP3-1; a first resistor R3a-1, the first resistor R3a-1 is connected between the inverting input terminal (-) of the third operational amplifier OP3-1 and the ground GND; a second resistor R3b-1, the second resistor R3b-1 is connected between the output terminal OUT and the inverting input terminal (-) of the operational amplifier OP3-1; a third resistor R3c-1, the third resistor R3c-1 is connected to the non-inverting input terminal (+) of the third operational amplifier OP3-1 and is applied with the voltage output from the first operational amplifier OP1-1; and a fourth resistor R3d-1, the fourth resistor R3d-1 is connected to the non-inverting input terminal (+) of the third operational amplifier OP3-1 and is applied with the second reference voltage REF_L.

[0112] For example, the first resistor R3 a - 1 , the second resistor R3 b - 1 , the third resistor R3 c - 1 , and the fourth resistor R3 d - 1 may have the same resistance value, but are not necessarily limited thereto and may be different.

[0113] Figures 9 to 11 2 is a diagram for explaining a compensation circuit according to a second embodiment.

[0114] Reference Figures 9 to 11 , shows an equivalent circuit of a path of a pixel driving voltage when a resistance to a first point is higher than a resistance to a second point in a wiring to which the pixel driving voltage is applied according to the second embodiment.

[0115] The voltage V2 measured at the second point P2 can be defined by the following Equation 4.

[0116] [Formula 4]

[0117]

[0118] Here, the resistance value Rc of the pixel is excluded because any value or position does not affect the above Expression 4 which is the voltage relationship between the first point and the second point.

[0119] like Fig.10 As shown in , it can be seen that the voltage actually measured at the second point P2 is the same as the voltage calculated by equation 4. In other words, it can be seen that the value calculated by equation 4 is accurate.

[0120] Therefore, in an embodiment, when the resistance to the first point is higher than the resistance to the second point, the gain compensator is designed to compensate the feedback voltage using the above Equation 4.

[0121] like Fig.11As shown in FIG. 6 , the compensation circuit 600 - 2 according to the second embodiment may include a gain compensator 610 - 2 , a first voltage compensator 620 - 2 , and a second voltage compensator 630 - 2 .

[0122] The gain compensator 610-2 may include a first amplifier circuit implemented by Formula 4. The first amplifier circuit may include: a first operational amplifier OP1-2; a first resistor Ra-2 connected to a non-inverting input terminal (+) of the first operational amplifier OP1-2 and to which a voltage output from a power supply is applied; and a second resistor Rb-2 connected to a non-inverting input terminal (+) of the first operational amplifier OP1-2 and to which a pixel driving voltage V2 fed back at a second point P2 is applied. The inverting input terminal (-) of the first operational amplifier OP1-2 may be connected to an output terminal OUT.

[0123] The first voltage compensator 620 - 2 may adjust the first reference voltage REF_H using the voltage V3 output from the gain compensator 610 - 2 , thereby generating a high potential gamma reference voltage GMA_REF_H.

[0124] The first voltage compensator 620-2 may include a second amplifier circuit. The second amplifier circuit may include: a second operational amplifier OP2-2; a first resistor R2a-2, the first resistor R2a-2 is connected between the inverting input terminal (-) of the second operational amplifier OP2-2 and the ground GND; a second resistor R2b-2, the second resistor R2b-2 is connected between the output terminal OUT and the inverting input terminal (-) of the operational amplifier OP2-2; a third resistor R2c-2, the third resistor R2c-2 is connected to the non-inverting input terminal (+) of the second operational amplifier OP2-2 and is applied with the voltage output from the first operational amplifier OP1-2; and a fourth resistor R2d-2, the fourth resistor R2d-2 is connected to the non-inverting input terminal (+) of the second operational amplifier OP2-2 and is applied with the first reference voltage REF_H.

[0125] For example, the first resistor R2a-2, the second resistor R2b-2, the third resistor R2c-2, and the fourth resistor R2d-2 may have the same resistance value, but are not necessarily limited thereto and may be different.

[0126] The second voltage compensator 630 - 2 may adjust the second reference voltage REF_L using the voltage V3 output from the gain compensator 610 - 2 , so that the low potential gamma reference voltage GMA_REF_L may be generated.

[0127] The second voltage compensator 630-2 may include a third amplifier circuit. The third amplifier circuit may include: a third operational amplifier OP3-2; a first resistor R3a-2, the first resistor R3a-2 is connected between the inverting input terminal (-) of the third operational amplifier OP3-2 and the ground GND; a second resistor R3b-2, the second resistor R3b-2 is connected between the output terminal OUT and the inverting input terminal (-) of the operational amplifier OP3-2; a third resistor R3c-2, the third resistor R3c-2 is connected to the non-inverting input terminal (+) of the third operational amplifier OP3-2 and is applied with the voltage output from the first operational amplifier OP1-2; and a fourth resistor R3d-2, the fourth resistor R3d-2 is connected to the non-inverting input terminal (+) of the third operational amplifier OP3-2 and is applied with the second reference voltage REF_L.

[0128] For example, the first resistor R3a-2, the second resistor R3b-2, the third resistor R3c-2, and the fourth resistor R3d-2 may have the same resistance value, but are not necessarily limited thereto and may be different.

[0129] Fig.12 is a diagram for explaining a compensation circuit according to a third embodiment.

[0130] Reference Fig.12 , shows an equivalent circuit of a path of a pixel driving voltage when the resistance to a first point in a wiring to which the pixel driving voltage is applied is higher than the resistance to a second point according to the third embodiment.

[0131] The voltage V3 measured at the second point P2 can be defined by the following Equation 5.

[0132] [Formula 5]

[0133]

[0134] Here, b1 and b2 are resistance values ​​Rb1 and Rb2 of the internal wiring, respectively, and when b1+b2 is replaced by b, it becomes the same as the above formula 4. Therefore, the compensation circuit according to the third embodiment is different from the compensation circuit implemented by the above formula 4. Fig.11 Here, the resistance value Rc of the pixel is excluded because any value or position does not affect the above Expression 5 which is the voltage relationship between the first point and the second point.

[0135] Fig.13 2 is a diagram for explaining a compensation circuit according to a fourth embodiment.

[0136] Reference Fig.13, shows an equivalent circuit of a path of a pixel driving voltage when the resistance to a first point in a wiring to which the pixel driving voltage is applied is higher than the resistance to a second point according to the fourth embodiment.

[0137] The voltage V2 measured at the second point P2 can be defined by the following Equation 6.

[0138] [Formula 6]

[0139]

[0140] Here, a1 and a2 are resistance values ​​Ra1 and Ra2 of the input terminal, respectively, and when a1+a2 is replaced by a, it becomes the same as the above formula 4. Therefore, the compensation circuit according to the fourth embodiment is the same as the one implemented by the above formula 4. Fig.11 Here, the resistance value Rc of the pixel is excluded because any value or position does not affect the above Expression 6 which is the voltage relationship between the first point and the second point.

[0141] Fig.14 and Fig.15 is a diagram for explaining a compensation circuit according to a fifth embodiment.

[0142] Reference Figure 14 to Figure 15 , the compensation circuit according to the fifth embodiment may be configured to divide the display panel into the first area S1 and the second area S2, and the compensation circuits of the first and second embodiments are alternately applied to each area.

[0143] For example, the compensation circuit in the first region may operate as the compensation circuit according to the first embodiment, and the compensation circuit in the second region may operate as the compensation circuit according to the second embodiment.

[0144] like Fig.15 As shown in FIG. , the compensation circuit 600 - 5 according to the fifth embodiment may include a first gain compensator 610 - 5 a , a second gain compensator 610 - 5 b , a first voltage compensator 620 - 5 , a second voltage compensator 630 - 5 , a first switching element SW1 , and a second switching element SW2 .

[0145] One frame includes a first section T1 compensating for a voltage drop of a pixel driving voltage in a first region S1 and a second section T2 compensating for a voltage drop of a pixel driving voltage in a second region S2. The first section T1 and the second section T2 may be alternately driven in each frame.

[0146] In the first section T1 , the first switching element SW1 is turned on and the second switching element SW2 is turned off, so that the first gain compensator 610 - 5 a is connected to the first voltage compensator 620 - 5 and the second voltage compensator 630 - 5 .

[0147] In the second section T2, the first switching element SW1 is turned off and the second switching element SW2 is turned on, so that the second gain compensator 610-5b is connected to the first voltage compensator 620-5 and the second voltage compensator 630-5.

[0148] The structure and operation of the compensation circuit are the same as those described in the first and second embodiments.

[0149] Fig.16A and Fig. 16B is a diagram illustrating the arrangement of a compensation circuit according to an embodiment.

[0150] Reference Fig.16A , the compensation circuit 600 and the gamma voltage generator 700 according to the embodiment may be mounted on the source printed circuit board SPCB. The timing controller 400 and the power supply 500 may be mounted on the control printed circuit board CPCB. The control printed circuit board CPCB may be connected to the source printed circuit board SPCB through a flexible circuit film such as a flexible printed circuit FPC.

[0151] Reference Fig. 16B , the compensation circuit 600 , the gamma voltage generator 700 , the timing controller 400 , and the power supply 500 according to the embodiment may be mounted on the control printed circuit board CPCB.

[0152] The pixel driving voltage ELVDD output from the power supply 500 may be provided to the display panel 100 via the flexible printed circuit FPC, the source printed circuit board SPCB and the chip on film COF. The voltage lines on the display panel 100 may be connected to the power supply 500 via the chip on film COF, the source printed circuit board SPCB and the flexible printed circuit FPC.

[0153] Fig.17 It is a graphic Figure 5 A circuit diagram of an example of a gamma compensation voltage generator is shown in FIG.

[0154] Reference Fig.17 , the gamma voltage generator 700 includes a first voltage divider circuit RS01, a first voltage selector, a second voltage divider circuit RS02, a second voltage selector, a third voltage divider circuit RS03, a third voltage selector, a fourth voltage divider circuit RS41 to RS46, a fourth voltage selector, and a fifth voltage divider circuit R51 to R57.

[0155] The first voltage divider circuit RS01 divides the high potential gamma reference voltage GMA_REF_H to output voltages having different voltage levels using resistors connected in series between the high potential gamma reference voltage GMA_REF_H and the low potential gamma reference voltage GMA_REF_L.

[0156] The first voltage selector selects the voltage output from the first voltage divider circuit RS01. The first voltage selector includes a first multiplexer MUX1 to a fourth multiplexer MUX4 connected between the first voltage divider circuit RS01 and the second voltage divider circuit RS02 to provide the voltage selected from the first voltage divider circuit RS01 to the second voltage divider circuit RS02. The first multiplexer MUX1 to the fourth multiplexer MUX4 output voltages lower than the high potential gamma reference voltage GMA_REF_H and having different voltage levels, which are provided to the nodes of the second voltage divider circuit RS02. The voltage output from each of the first multiplexer MUX1 to the fourth multiplexer MUX4 is directly applied to the nodes separated at regular intervals in the second voltage divider circuit RS02 through a buffer. The first multiplexer MUX1 to the fourth multiplexer MUX4 can adjust the voltage setting according to the register settings REG1 to REG4.

[0157] Register settings REG1 to REG4, RGAMA31 to RGAMA33, and RGAMA41 to RGAMA46 may be stored in the first memory 210 before product shipment and then transferred to the second memory 132 when the electroluminescent display device is powered on, or may be stored in the second memory 132 before product shipment. Register settings REG1 to REG4 are register setting values ​​for adjusting brightness during optical compensation or adjusting brightness together with a display brightness value (DBV). The DBV may change in response to an illuminance sensor output signal from a host system or a brightness input value from a user.

[0158] The second voltage divider circuit RS02 includes resistors connected in series between a node to which the high potential gamma reference voltage GMA_REF_H is applied and a node to which the low potential gamma reference voltage GMA_REF_L is applied. The second voltage divider circuit RS02 divides the high potential gamma reference voltage GMA_REF_H and outputs voltages of different voltage levels through nodes between the resistors.

[0159] The second voltage selector may include a multiplexer MUX6 that selects the first reference voltage VREG1 by selecting one of the nodes of the second voltage divider circuit RS02 according to the register setting REG6. The output voltage of the multiplexer MUX6 may be changed according to the register setting REG6. The first reference voltage VREG1 output from the multiplexer MUX6 is provided to the third voltage divider circuit RS03 through a buffer.

[0160] The third voltage divider circuit RS03 divides the first reference voltage VREG1 into output voltages having different voltage levels using resistors connected in series between the first reference voltage VREG1 and the ground GND.

[0161] The third voltage selector includes: a 3-1 multiplexer MUX31, the 3-1 multiplexer MUX31 selects any one of the high potential nodes of the third voltage divider circuit RS03 according to the register setting RGMA31, and outputs a high potential gamma reference voltage from the selected node as the highest gamma compensation voltage V255; a 3-2 multiplexer MUX32, the 3-2 multiplexer MUX32 selects any one of the low potential nodes in the first group in the third voltage divider circuit RS03 according to the register setting RGMA32, and outputs a low potential voltage from the selected node as the seventh gamma tap voltage V1; and a 3-3 multiplexer MUX33, the 3-3 multiplexer MUX33 selects any one of the low potential nodes in the second group in the third voltage divider circuit RS03 according to the register setting RGMA33, and outputs a lowest gamma compensation voltage V0 from the selected node.

[0162] The fourth voltage divider circuits RS41 to RS46 include a 4-1st to 4-6th voltage divider circuit RS41 to RS46 that divide voltage between the highest gamma compensation voltage V255 and the seventh gamma tap voltage V1 to output a gamma compensation voltage for each gray level.

[0163] The fourth voltage selector includes 4-1st to 4-6th voltage selectors that output first to sixth gamma tap voltages V255, V191, ..., V7 using multiplexers MUX41 to MUX46. The first to sixth gamma tap voltages V255, V191, ..., V7 are lower than the highest gamma compensation voltage V255 and higher than the seventh gamma tap voltage V1.

[0164] The 4-1st voltage divider circuit RS41 divides the highest gamma compensation voltage V255 using a resistor connected in series between the highest gamma compensation voltage V255 and the seventh gamma tap voltage V1. The 4-1st voltage selector includes a 4-1st multiplexer MUX41 that selects one of the nodes of the 4-1st voltage divider circuit RS41. The 4-1st multiplexer MUX41 selects one of the nodes of the 4-1st voltage divider circuit RS41 according to the register setting RGMA41 to output a voltage from the selected node.

[0165] The output voltage of the 4-1 th multiplexer MUX41 is output as a first gamma tap voltage V191 via a buffer B41. The first gamma tap voltage V191 is a gamma compensation voltage corresponding to a gray value 191 of the pixel data RGB.

[0166] The 4-2nd voltage divider circuit RS42 divides the first gamma tap voltage V191 using a resistor connected in series between the first gamma tap voltage V191 and the seventh gamma tap voltage V1. The 4-2nd multiplexer MUX42 selects one of the nodes of the 4-2nd voltage divider circuit RS42 according to the register setting RGMA42 to output a voltage from the selected node. The output voltage of the 4-2nd multiplexer MUX42 is output as a second gamma tap voltage V127 via a buffer B42. The second gamma tap voltage V127 is a gamma compensation voltage corresponding to a gray value 127 of the pixel data RGB.

[0167] The 4th-6th voltage divider circuit RS46 divides the fifth gamma tap voltage V15 using a resistor connected in series between the fifth gamma tap voltage V15 and the seventh gamma tap voltage V1. The 4th-6th multiplexer MUX46 selects one of the nodes of the 4th-6th voltage divider circuit RS46 according to the register setting RGMA46 to output a voltage from the selected node. The output voltage of the 4th-6th multiplexer MUX46 is output as the sixth gamma tap voltage V7 via a buffer B46. The sixth gamma tap voltage V7 is a gamma compensation voltage corresponding to the gray value 7 of the pixel data RGB.

[0168] The fifth voltage divider circuits R51 to R57 use resistors connected in series between the highest gamma compensation voltage V255 and the seventh gamma tap voltage V1 to distribute the highest gamma compensation voltage V255, so that the gamma compensation voltages V1 to V255 are output for each grayscale with different voltage levels. The 5-1st voltage divider circuit R51 uses resistors connected in series between the highest gamma compensation voltage V255 and the first gamma tap voltage V191, so that a gamma compensation voltage between the highest gamma compensation voltage V255 and the first gamma tap voltage V191 is output for each grayscale. The 5-2nd voltage divider circuit R52 uses resistors connected in series between the first gamma tap voltage V191 and the second gamma tap voltage V127, so that a gamma compensation voltage between the first gamma tap voltage V191 and the second gamma tap voltage V127 is output for each grayscale. The 5th-6th voltage divider circuit R56 uses a resistor connected in series between the fifth gamma tap voltage V15 and the sixth gamma tap voltage V7, so that a gamma compensation voltage between the fifth gamma tap voltage V15 and the sixth gamma tap voltage V7 is output for each gray level. The 5th-7th voltage divider circuit R57 uses a resistor connected in series between the sixth gamma tap voltage V7 and the seventh gamma tap voltage V1, so that a gamma compensation voltage between the sixth gamma tap voltage V7 and the seventh gamma tap voltage V1 is output for each gray level. The gamma compensation voltages V0 to V255 are provided to the DAC of the data driving unit 200.

[0169] According to the pixel circuit structure, the gamma compensation voltage of the data voltage can be implemented as positive gamma or negative gamma. For example, when the light-emitting device of a pixel such as a transistor driving an OLED is implemented as an n-channel MOSFET and the data voltage is applied to the gate of the transistor, a gamma compensation voltage with positive gamma is generated, and the higher the grayscale (RGB) of the pixel data, the higher the gamma compensation voltage.

[0170] Fig.17 The diagram illustrates a gamma voltage generator set to positive gamma. When the light emitting device of the pixel is implemented as a p-channel MOSFET and the data voltage is applied to the gate of the transistor, a gamma compensation voltage with negative gamma is generated, and the higher the grayscale level (RGB) of the pixel data, the lower the gamma compensation voltage. In this case, Fig.17 , the voltage levels of GMA_REF_H and GMA_REF_L change with each other, and the voltage levels of VREG1 and VREG2 also change with each other.

[0171] Although the embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed in the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above embodiments are exemplary in all aspects and do not limit the present disclosure.

Claims

1. A compensation circuit, comprising: a gain compensator configured to generate a voltage drop amount using a first pixel driving voltage output from a power supply and a second pixel driving voltage fed back from a wiring of the display panel, wherein the generated voltage drop amount is amplified by a predetermined gain value; a first voltage compensator configured to adjust the first reference voltage using the generated voltage drop amount to generate a high potential gamma reference voltage; as well as a second voltage compensator configured to adjust the second reference voltage using the generated voltage drop amount to generate a low potential gamma reference voltage, wherein the gain value is a value calculated using voltages at two predetermined points within a wiring of the display panel.

2. The compensation circuit according to claim 1, wherein the two predetermined points include a first point at which the second pixel driving voltage is fed back, and a second point at which a voltage drop amount of the fed back second pixel driving voltage is calculated. 3 . The compensation circuit according to claim 2 , wherein the gain value changes according to positions of the first point and the second point.

4. The compensation circuit according to claim 3, wherein the first point is disposed closer to the power supply than the second point, and The gain compensator comprises: a first operational amplifier, the first operational amplifier comprising an inverting input terminal to which the first pixel driving voltage output from the power supply is applied, a non-inverting input terminal to which the second pixel driving voltage is applied, and an output terminal; a first resistor connected to the inverting input terminal and to which the first pixel driving voltage is applied; and A second resistor is connected between the output terminal and the inverting input terminal.

5. The compensation circuit according to claim 3, wherein the second point is disposed closer to the power supply than the first point, and The gain compensator comprises: a first operational amplifier, the first operational amplifier comprising an inverting input terminal, a non-inverting input terminal to which the first pixel driving voltage and the second pixel driving voltage are applied, and an output terminal connected to the inverting input terminal; a first resistor connected to the non-inverting input terminal and to which the first pixel driving voltage is applied; and A second resistor is connected to the non-inverting input terminal and is applied with the second pixel driving voltage.

6. The compensation circuit according to claim 4 or 5, wherein the first voltage compensator comprises: a second operational amplifier; a first resistor connected between an inverting input terminal of the second operational amplifier and ground; a second resistor connected between the output terminal of the second operational amplifier and the inverting input terminal; a third resistor connected to the non-inverting input terminal of the second operational amplifier and to which the voltage output from the first operational amplifier is applied; and a fourth resistor connected to the non-inverting input terminal of the second operational amplifier and to which the first reference voltage is applied.

7. The compensation circuit according to claim 6, wherein the second voltage compensator comprises: a third operational amplifier; a first resistor connected between the inverting input terminal of the third operational amplifier and the ground; a second resistor connected between the output terminal of the third operational amplifier and the inverting input terminal; a third resistor connected to a non-inverting input terminal of the third operational amplifier and to which a voltage output from the first operational amplifier is applied; and a fourth resistor connected to the non-inverting input terminal of the third operational amplifier and to which the second reference voltage is applied.

8. The compensation circuit according to claim 1, wherein the display panel comprises a first area and a second area, The gain compensator comprises: a first gain compensator configured to generate a voltage drop amount in the first region by amplifying the voltage drop amount by a first gain value; a first switching element configured to connect the first gain compensator to the first voltage compensator and the second voltage compensator in response to a first control signal; a second gain compensator configured to generate a voltage drop amount in the second region by amplifying the voltage drop amount by a second gain value; and a second switching element configured to connect the second gain compensator to the first voltage compensator and the second voltage compensator in response to a second control signal, and The first switching element and the second switching element are driven alternately. 9 . The compensation circuit of claim 8 , wherein the first control signal and the second control signal are applied from a timing controller.

10. A display device, comprising: a display panel, in which a plurality of data lines, a plurality of gate lines and pixels to which a first pixel driving voltage is provided are arranged; a data driving unit configured to provide pixel data to the plurality of data lines; as well as a power supply configured to provide the first pixel driving voltage; as well as a compensation circuit configured to calculate a voltage drop of the first pixel driving voltage, The compensation circuit comprises: a gain compensator configured to generate a voltage drop amount using the first pixel driving voltage output from the power supply and a second pixel driving voltage fed back from a wiring of the display panel, wherein the generated voltage drop amount is amplified by a predetermined gain value; a first voltage compensator configured to adjust the first reference voltage using the generated voltage drop amount to generate a high potential gamma reference voltage; and a second voltage compensator configured to adjust the second reference voltage using the generated voltage drop amount to generate a low potential gamma reference voltage, and The gain value is a value calculated using voltages at two predetermined points within a wiring of the display panel.

11. The display device according to claim 10, wherein the two predetermined points include a first point at which the second pixel driving voltage is fed back, and a second point at which a voltage drop amount of the fed back second pixel driving voltage is calculated. 12 . The display device according to claim 11 , wherein the gain value changes according to positions of the first point and the second point.

13. The display device according to claim 12, wherein the first point is disposed closer to the power source than the second point, and The gain compensator comprises: a first operational amplifier, the first operational amplifier comprising an inverting input terminal to which the first pixel driving voltage is applied, a non-inverting input terminal to which the second pixel driving voltage is applied, and an output terminal; a first resistor connected to the inverting input terminal and to which the first pixel driving voltage is applied; and A second resistor is connected between the output terminal and the inverting input terminal.

14. The display device according to claim 12, wherein the second point is disposed closer to the power source than the first point, and The gain compensator comprises: a first operational amplifier, the first operational amplifier comprising an inverting input terminal, a non-inverting input terminal to which the first pixel driving voltage and the second pixel driving voltage are applied, and an output terminal connected to the inverting input terminal; a first resistor connected to the non-inverting input terminal and to which the first pixel driving voltage is applied; and A second resistor is connected to the non-inverting input terminal and is applied with the second pixel driving voltage.

15. The display device according to claim 13 or 14, wherein the first voltage compensator comprises: a second operational amplifier; a first resistor connected between an inverting input terminal of the second operational amplifier and ground; a second resistor connected between the output terminal of the second operational amplifier and the inverting input terminal; a third resistor connected to the non-inverting input terminal of the second operational amplifier and to which the voltage output from the first operational amplifier is applied; and a fourth resistor connected to the non-inverting input terminal of the second operational amplifier and to which the first reference voltage is applied.

16. The display device according to claim 15, wherein the second voltage compensator comprises: a third operational amplifier; a first resistor connected between the inverting input terminal of the third operational amplifier and the ground; a second resistor connected between the output terminal of the third operational amplifier and the inverting input terminal; a third resistor connected to a non-inverting input terminal of the third operational amplifier and to which a voltage output from the first operational amplifier is applied; and a fourth resistor connected to the non-inverting input terminal of the third operational amplifier and to which the second reference voltage is applied.

17. The display device according to claim 10, wherein the display panel comprises a first area and a second area, The gain compensator comprises: a first gain compensator configured to generate a voltage drop amount in the first region by amplifying the voltage drop amount by a first gain value; a first switching element configured to connect the first gain compensator to the first voltage compensator and the second voltage compensator in response to a first control signal; a second gain compensator configured to generate a voltage drop amount in the second region by amplifying the voltage drop amount by a second gain value; and a second switching element configured to connect the second gain compensator to the first voltage compensator and the second voltage compensator in response to a second control signal, and The first switching element and the second switching element are driven alternately. 18 . The display device of claim 17 , further comprising a timing controller configured to apply the first control signal and the second control signal.

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