Array substrate, display panel and display device

Abstract

The invention relates to an array substrate, a display panel and a display device. According to the technical scheme, the array substrate comprises a non-display area and a display area, a source driving chip, an integrated gate driving circuit and a gate driving chip are arranged on the non-display area, M rows of thin film transistors are arranged on the display area, and M is a positive integer. The grid electrode driving chip is used for driving continuous P rows of thin film transistors in the M rows of thin film transistors according to the first control signal and the first clock signal output by the source electrode driving chip, and P is a positive integer smaller than M; and the integrated gate driving circuit is used for driving continuous Q rows of thin film transistors in the M rows of thin film transistors according to a second control signal and a second clock signal output by the source driving chip, and Q is the difference between M and P. According to the technical scheme provided by the invention, the special-shaped resolution can be realized in a manner of cascading the GIA and the gate driving chip, and the realization cost is relatively low.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to an array substrate, a display panel and a display device. Background Art

[0002] With the development of amorphous silicon (A-Si) technology, screens have become widely popular, and users' requirements for screen resolution have also increased accordingly. For example, in the process of using car screens, users have put forward the demand for screens with special resolutions (such as 1920*1240, 1280*1280, 2560*1500, etc.).

[0003] However, the current resolution of in-vehicle screens is usually full high definition (FHD) and quad high definition (QHD). FHD resolution is 1920*1200, and QHD resolution can be 2560*1440. Therefore, how to achieve the special resolution of in-vehicle screens has become a technical problem. Summary of the invention

[0004] The present application provides an array substrate, a display panel and a display device.

[0005] In a first aspect, the present application provides an array substrate, which includes a non-display area and a display area, the non-display area is provided with a source driver chip, an integrated gate driver circuit and a gate driver chip, and the display area is provided with M rows of thin film transistors, M is a positive integer; the source driver chip is used to output a first control signal and a first clock signal to the gate driver chip, and to output a second control signal and a second clock signal to the integrated gate driver circuit; the gate driver chip is used to drive P consecutive rows of thin film transistors in the M rows of thin film transistors according to the first control signal and the first clock signal, P is a positive integer less than M; the integrated gate driver circuit is used to drive Q consecutive rows of thin film transistors in the M rows of thin film transistors according to the second control signal and the second clock signal, Q is the difference between M and P.

[0006] In combination with the first aspect, in a possible implementation manner, P is greater than Q.

[0007] In combination with the first aspect, in a possible implementation manner, the second control signal includes a start control signal and a shutdown control signal.

[0008] In combination with the first aspect, in a possible implementation, the second control signal is a shutdown control signal; the integrated gate drive circuit is also used to obtain a start control signal from the gate drive chip; the integrated gate drive circuit is used to drive the continuous Q rows of thin film transistors in the M rows of thin film transistors according to the second control signal, the start control signal and the second clock signal.

[0009] In combination with the first aspect, in a possible implementation manner, a charging time of each row of thin film transistors in the continuous P rows of thin film transistors is greater than or equal to a charging time of each row of thin film transistors in the continuous Q rows of thin film transistors.

[0010] In combination with the first aspect, in a possible implementation manner, the gate driving chip includes a chamfering circuit.

[0011] In combination with the first aspect, in a possible implementation manner, the gate driving chip and the integrated gate driving circuit are distributed on the same side or different sides of the array substrate.

[0012] In combination with the first aspect, in a possible implementation manner, there are multiple integrated gate drive circuits, and the integrated gate drive circuits are distributed on the upper and lower sides of the gate drive chip.

[0013] In a second aspect, the present application provides a display panel, which includes an array substrate as described in the first aspect or any one of the implementations thereof.

[0014] In a third aspect, the present application provides a display device, comprising the display panel as described in the second aspect.

[0015] The technical solution provided by the present application realizes the profiled resolution by integrating the gate driver in array (GIA) and the gate driver chip cascade. Since the GIA is mainly composed of thin-film transistors (TFT) and capacitors, the GIA can be directly set on the array substrate during the production process of the array substrate to improve the production efficiency of the array substrate. In addition, since the implementation cost of the GIA is lower than the purchase cost of the gate driver chip, the implementation cost of the technical solution provided by the present application is lower than that of realizing the profiled resolution by cascading the gate driver chip. Compared with realizing the profiled resolution by all GIA, the power consumption of the technical solution provided by the present application is lower. For the use scenario with a high screen refresh rate, the present application proposes an unequal charging time design scheme, which improves the transmission stability of the GIA signal and improves the display performance of the screen by extending the charging time of each row of TFT driven by the GIA. In addition, the present application reduces the gate high voltage (gate high voltage, VGH) of the off state by adding a chamfering circuit in the gate driver chip, balances the driving ability of the gate driver chip and the GIA to the TFT, improves the problem of the upper and lower split screen, and improves the display performance of the screen. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figures 1 to 4 A schematic diagram of the design architecture of the array substrate provided in this application;

[0017] Figure 5 A schematic diagram of a source driver chip provided in the present application;

[0018] Figure 6 A driving schematic diagram of an array substrate provided in this application;

[0019] Figure 7 A schematic diagram of a design of a driving signal provided in this application;

[0020] Figure 8 A driving schematic diagram of another array substrate provided in the present application;

[0021] Fig. 9 A schematic diagram of another design of a driving signal provided in this application;

[0022] Fig.10 A schematic diagram of another design of a driving signal provided in this application;

[0023] Fig.11 A schematic diagram illustrating the upper and lower split screen provided by this application;

[0024] Fig.12 A schematic diagram of a chamfering circuit provided for this application;

[0025] Fig.13 A schematic diagram illustrating the gate chamfering function provided in this application. DETAILED DESCRIPTION

[0026] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0027] In the description of the present invention, it should be noted that the terms "upper", "lower", "left", "right", etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0028] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the term "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal connection of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances. In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0029] To facilitate the understanding of the present application, the relevant concepts are first explained below.

[0030] 1. Resolution

[0031] Resolution is the number of pixels per unit length. Common screen resolutions include high definition (HD), full high definition (FHD), and quad high definition (QHD). FHD resolution can be 1920*1200 (16:10), and QHD resolution can be 2560*1440 (16:9). Taking FHD resolution as an example, 1920 represents the number of pixels in the horizontal direction of the screen or image, and 1200 represents the number of pixels in the vertical direction of the screen or image. The aspect ratio of the screen is 16:10.

[0032] 2. Thin-film transistor (TFT)

[0033] TFT is a technology used in liquid crystal displays (LCDs). TFT is used to control the arrangement of liquid crystal molecules, thereby controlling the light transmission and light shielding of each pixel to display images.

[0034] 3. Gate driver chip (gate integrated circuit, gate IC)

[0035] The gate driver chip is used to drive the gate of the TFT. For example, the gate driver chip can output a scan signal to the gate of the TFT in a certain timing to turn on or off the gate of the TFT row by row, thereby realizing row-by-row scanning and control of the pixels. The scan signal can be a pulse signal, the high level of the pulse signal is used to turn on the gate of the TFT, and the low level is used to turn off the gate of the TFT. The gate driver chip is a physical IC.

[0036] It should be noted that the gate driver chip is usually designed with 720 / 1080 / 1200 channels (channel, ch), which are used to drive 720 / 1080 / 1200 rows of TFTs in the vertical direction, respectively, and then can realize the control of 720 / 1080 / 1200 rows of pixels in the vertical direction. Among them, each row of TFTs in the vertical direction (that is, each row of pixels) requires a channel for control. For example, for a resolution of 1920*1080, there are 1080 rows of pixels in the vertical direction, so it can be driven by a 1080ch gate driver chip.

[0037] 4. Integrated gate driver in array (GIA)

[0038] GIA can be used to control the gate of TFT. For example, GIA can output a scan signal to the gate of TFT through internal TFT and capacitor components to turn on or off the gate of TFT row by row, thereby realizing row by row scanning and control of pixels. GIA is a circuit arrayed on an array substrate, or a circuit arrayed on TFT glass.

[0039] 5. Source driver chip

[0040] The source driver chip can be used to drive the source of the TFT. For example, the source driver chip can output an analog voltage signal to the source of the TFT to control the brightness and color of the pixel. The source driver chip is a physical IC.

[0041] It should be noted that the source driver chip is usually designed as 1920ch, that is, one source driver chip can realize 1920 columns of TFT in the horizontal direction, thereby realizing the control of 1920 columns of pixels in the horizontal direction. For example, for a resolution of 1920*1080, there are 1920 columns of pixels in the horizontal direction, so it can be driven by one source driver chip.

[0042] In some implementations, the source driver chip may be a timing controller embedded driver IC (TED IC) formed by integrating a timing controller (TCON) and a source driver (Source IC). The TCON module in the source driver chip may convert the data input from the system main control chip through a flexible printed circuit (FPC), and input the converted data to the source driver inside the chip, while outputting a gate control signal to the gate driver chip through a glass wiring. The source driver chip and the gate driver chip may transmit signals to the display area through glass wiring, or the source driver chip and the gate driver chip may transmit signals to the TFT through glass wiring, respectively. The display area may be understood as an area where TFTs are provided.

[0043] In some implementations, the source driver chip may be a touch and display driver integration (TDDI) chip.

[0044] 6. Start vertical signal (STV)

[0045] In the driving circuit of a display device such as a liquid crystal display, the STV signal can be used to indicate the start or stop of the operation of scanning the TFT line by line in the vertical direction. The STV signal can also be used to indicate the starting position of the TFT line by line.

[0046] 7. Clock signal

[0047] The clock signal is mainly used to control the scanning rhythm of the TFT line by line in the vertical direction. For example, in a liquid crystal display device, each pulse of the clock signal corresponds to a time point or step of the scanning operation, so that the image is displayed in the vertical direction in the correct order and rhythm. The clock signal is, for example, a vertical clock pulse (Clock Pulse Vertical, CPV) signal, or a CLK signal.

[0048] The technical problems to be solved by this application are described below.

[0049] With the development of amorphous silicon (a-si) technology, screens have become widely popular, such as in vehicles, home appliances, fitness equipment and other equipment, and users' requirements for screen resolution have also increased accordingly. For example, in the use of vehicle-mounted screens, users have put forward the use requirements of screens with special-shaped resolutions (such as 1920*1240 (3:2), 1280*1280 (1:1), 2560*1500, etc.), but the current resolutions of vehicle-mounted screens are usually FHD resolution and QHD resolution. It should be noted that special-shaped resolution refers to the resolution in which pixels are expanded in the vertical direction compared to the existing resolution standards. For example, the resolution 1920*1240 is expanded by 40 pixels in the vertical direction compared with the FDH resolution; the resolution 2560*1500 is expanded by 60 pixels in the vertical direction compared with the TDH resolution. In some embodiments, the special-shaped resolution can also be understood as a resolution in which the number of pixels in the vertical direction is not an integer multiple of the number of pixel rows that the gate driver chip can drive. For example, the number of pixels in the vertical direction of a resolution of 1280*1280 is 1280, which is 80 pixels more than that of a 1200ch gate driver chip.

[0050] Therefore, how to achieve special-shaped resolution of vehicle-mounted screens becomes a technical problem.

[0051] In a possible implementation, a gate driver chip can be added in cascade to drive the pixels expanded in the vertical direction. However, the implementation cost of this method is high, and the utilization rate of the newly added gate driver chip is low.

[0052] In view of this, the present application proposes an array substrate, a display panel and a display device. In the technical solution provided by the present application, the special-shaped resolution of the vehicle-mounted screen is achieved by cascading GIA and gate drive chips. In the technical solution proposed by the present application, the pixels expanded in the vertical direction are driven by GIA without adding a new gate drive chip. Since GIA is mainly composed of TFT and capacitor, GIA can be directly set on the array substrate during the production process of the array substrate to improve production efficiency. In addition, the implementation cost of GIA is lower than the purchase cost of the gate drive chip, so compared with the implementation method of adding a cascade of a gate drive chip, the implementation cost of the technical solution provided by the present application is lower. It should be noted that the technical solution provided by the present application can be applied to other fields besides vehicle-mounted screens, such as home appliance screens, which is not limited here.

[0053] Figures 1 to 4 A schematic diagram of the design architecture of the array substrate provided in this application. Figures 1 to 4The array substrate 100 shown includes a non-display area and a display area. The non-display area is provided with a GIA 110 and a gate driving chip 120 , and the display area is provided with M rows of TFTs, where M is a positive integer.

[0054] In a possible implementation manner, the GIA 110 and the gate driver chip 120 may be distributed on the same side or different sides of the array substrate 100. Figure 1 and Figure 2 In the figure, the GIA 110 and the gate driving chip 120 are both distributed on the right side of the array substrate 100; Figure 3 and Figure 4 In the embodiment, the GIA 110 is distributed on the left side of the array substrate 100 , and the gate driving chip 120 is distributed on the right side of the array substrate 100 .

[0055] It should be noted that Figures 1 to 4 The number and distribution positions of the GIAs and gate driver chips are for illustration only and are not intended to limit the technical solution of the present application. For example, the gate driver chip may also be located on the left side of the array substrate. For another example, when the number of GIAs is 2 and the number of gate driver chips is 1, the GIAs may be distributed on the upper and lower sides of the gate driver chip.

[0056] Among them, the gate driver chip 120 can be used to drive the continuous P rows of TFTs in the M rows of TFTs, where P is a positive integer less than M; the GIA 110 can be used to drive the continuous Q rows of TFTs in the M rows of TFTs, where Q is the difference between M and P. It should be understood that the GIA 110 and the gate driver chip 120 can be used to drive the gates of the TFTs provided on the display area, and the details can be referred to the above description, which will not be repeated here. The TFTs driven by the GIA 110 and the gate driver chip 120 do not overlap.

[0057] See also Figure 1 and Figure 3 , the GIA 110 can drive the TFTs in the 1st to Qth rows, and the gate driver chip 120 can drive the TFTs in the Q+1th to Mth rows. Figure 2 and Figure 4 The gate driving chip 120 can drive the TFTs in the 1st to Pth rows, and the GIA 110 can drive the TFTs in the P+1th to Mth rows.

[0058] It should be noted that when driving the same number of TFTs, the power consumed by GIA is much greater than the power consumed by the gate driver chip, so P can be made greater than Q, so that the gate driver chip drives a larger number of TFTs and GIA drives a smaller number of TFTs, to further save power consumption.

[0059] In one achievable manner, a source driver chip 130 is further disposed on the non-display area of ​​the array substrate 100 .

[0060] The source driver chip 130 can be used to output control signals and clock signals to the GIA 110 and the gate driver chip 120 to control the GIA 110 and the gate driver chip 120 to drive the TFT; it can also be used to drive the source of the TFT provided on the display area to control the brightness and color of the pixel.

[0061] It should be noted that Figures 1 to 4 The number and position of the source driver chips 130 are only examples, and the present application does not impose any limitation thereto.

[0062] Figure 5 Schematic diagram of the source driver chip provided in this application. Figure 5 As shown, the source driver chip includes 38 pins. Among them, the 2nd to 31st pins are used to output control signals and clock signals to GIA; the 34th pin is used to output an enable (output enable, OE) signal to the gate driver chip, and the 36th pin is used to output a clock signal CPV to the gate driver chip. The gate driver chip can determine the output time and frequency of the scan signal according to the OE and CPV signals. The 37th pin is used to output the start control signal STV-U to the gate driver chip, and the 38th pin is used to receive the shutdown control signal STV-D from the gate driver chip. It should be noted that the number of pins that the source driver chip can output signals to GIA is greater than the number of signals, so the output pins of the signal can be randomly selected, or the output pins of the signal can be predefined, and this application does not limit this.

[0063] The following example takes the car screen resolution of 1920 * 1240 and the screen refresh rate of 60 Hz as an example. Figures 6 to 9 The working principle of the technical solution provided by the present application is described. Among them, 40 rows of TFTs in the vertical direction in the display area are driven by GIA, and 1200 rows of TFTs in the vertical direction in the display area are driven by a 1200ch gate driver chip.

[0064] Figure 6 A driving schematic diagram of an array substrate provided in the present application. Figure 6 The display area shown in FIG. 1 is provided with 1240 rows of TFTs, and the GIA and gate driver chips are distributed on the right side of the array substrate. Two source driver chips (such as Figure 6 The source driver chip 1 and the source driver chip 2 are connected to the GIA, the gate driver chip and the source driver chip 2 respectively.

[0065] In this application, for the convenience of distinction and understanding, the control signal output by the source driver chip to the gate driver chip can be called the first control signal, and the control signal output to the GIA can be called the second control signal; the clock signal output by the source driver chip to the gate driver chip can be called the first clock signal, and the clock signal output to the GIA can be called the second clock signal.

[0066] In this embodiment, the first control signal may include a first start control signal STV-U and an OE signal, the first clock signal may be a CPV signal, the second control signal may include second start control signals STV1 and STV2, and second shutdown control signals STV3 and STV4, and the second clock signal may include CLK1 to CLK4.

[0067] Figure 7 A schematic diagram of a design of a driving signal provided in this application. Figure 7 The driving signals shown include STV1, STV2, CLK1 to CLK4, STV3, STV4, STV-U, STV-D, and scanning signals G41 to G1240 output by the gate driving chip to the TFT. It should be understood that the driving signals may also include other Figure 7 Signals not shown, such as CPV, OE, and scanning signals G1 to G40 output by GIA to TFT.

[0068] See also Figure 7 , the driving signal can be designed as a pulse signal. Among them, the pulse width of STV-U and STV-D signals can be designed to be T, the high level can be designed to be 3.3 volts (V), and the low level can be designed to be 0V; the pulse width of STV1 to STV4 signals can be designed to be 3T, the high level can be designed to be the gate high voltage (gate high voltage, VGH) of the TFT, and the low level can be designed to be the gate low voltage (gatelow voltage, VGL) of the TFT; the high level of CLK1 to CLK4 signals can be designed to be the VGH of the TFT, the pulse width can be designed to be 3T, the low level of CLK1 to CLK4 signals can be designed to be the VGL of the TFT, and the pulse width can be designed to be 5T. Figure 7 The pulse width of the CPV and OE signals not given in the figure can be designed to be T, the high level can be designed to be 3.3V, and the low level can be designed to be 0V. Considering that the scan signal output by the GIA or gate driver chip is used to turn on or off the gate of the TFT, the pulse width of the scan signal can be designed to be T, the high level of the scan signal can be designed to be the VGH of the TFT, and the low level can be designed to be the VGL of the TFT. It should be noted that T can be understood as the charging time of a row of TFTs, or the charging time of 1 line. T can be related to the refresh rate of the screen and the number of TFT rows that need to be charged.

[0069] In a possible implementation, T may satisfy the formula: T=1 / f / M, where f is the refresh rate of the screen or display area, and M is the number of TFT rows that need to be charged, or the number of TFT rows provided on the array substrate.

[0070] In one possible implementation, a buffer (blank) time may be set between the charging time of each row of TFTs to reduce interference between the scanning signals of each row of TFTs. For example, the charging time of 60 rows of TFTs may be set as the buffer time. At this time, T may satisfy the formula: T = 1 / f / (M+60). At this time, if the screen refresh rate is 60 Hz, then T = 1 / 60 / (1240+60) = 12.8 microseconds (us).

[0071] In this embodiment, the source driver chip 1 outputs STV1 and STV2 signals to the GIA to instruct the GIA to start the scanning operation, and outputs clock signals CLK1 to CLK4 to the GIA, and each clock signal includes 10 cycles, so that the GIA can output 40 scanning signals, such as G1 to G40, to the TFTs in the display area in a certain timing, thereby driving the 1st to 40th rows of TFTs in the vertical direction, and then realizing the control of the 1st to 40th rows of pixels in the vertical direction; the source driver chip 1 outputs STV3 and STV4 signals to the GIA to instruct the GIA to stop the scanning operation. Accordingly, to ensure the scanning continuity of the TFT, before the GIA is about to complete the scanning operation, the source driver chip 1 can output the STV-U signal to the gate driver chip to instruct the gate driver chip to start the scanning operation, and output the OE and CPV signals to the GIA. The OE and CPV signals include 1200 cycles, so that the gate driver chip can output 1200 scanning signals, such as G41 to G1240, to the TFTs in the display area in a certain timing sequence, thereby driving the 41st to 1240th rows of TFTs in the vertical direction, and then realizing the control of the 41st to 1240th rows of pixels in the vertical direction; the gate driver chip can output the STV-D signal to the source driver chip 1 to indicate that the scanning is completed. The Gx signal is used to drive the xth row of TFTs in the vertical direction, 1≤x≤1240, and x is an integer. It should be understood that the output time of G41 is later than the output time of G40. In this embodiment, the source driver chip 2 can output a signal to the source of the TFT provided on the display area to control the brightness and color of the pixels in the horizontal direction.

[0072] It should be understood that Figure 7 The driving method shown can be applied to the solution that the GIA drives the TFT in the display area before the gate drive chip, and can also be applied to Figure 3 The array substrate shown.

[0073] Figure 8A driving schematic diagram of another array substrate provided in the present application. Figure 8 The display area shown in FIG. 1 is provided with 1240 rows of TFTs, the GIA is distributed on the left side of the array substrate, the gate driver chip is distributed on the right side of the array substrate, and two source driver chips (such as Figure 8 The source driver chip 1 and the source driver chip 2 are connected to the gate driver chip and the source driver chip 2 respectively, and the GIA is connected to the source driver chip 2.

[0074] In this embodiment, the first control signal may include a first start control signal STV-U and an OE signal, the first clock signal may be a CPV signal, the second control signal may be a second shutdown control signal STV3 and STV4, and the second clock signal may include CLK1 to CLK4.

[0075] In this embodiment, the second start-up control signals STV1 and STV2 can be obtained from the gate driver chip. For example, the last two levels of scanning signals output by the gate driver chip to the display area are used as the start-up control signals of the GIA. It should be noted that since the time of the last two levels of scanning signals G1199 and G1200 output by the gate driver chip is before the start-up scanning operation of the GIA, and the levels of G1199 and G1200 meet the level design conditions of the GIA start-up control signal, the last two levels of scanning signals output by the gate driver chip can be used as the start-up control signals of the GIA.

[0076] Fig. 9 This is a schematic diagram of another design of a driving signal provided in this application. Fig. 9 The driving signals shown include STV-U, STV-D, CLK1 to CLK4, STV3, STV4, and scanning signals G1 to G1200 output by the gate driving chip to the TFT. Among them, STV1 and STV2 can be determined by G1199 and G1200. It should be understood that the driving signals may also include other signals not shown in the figure, such as CPV, OE, and scanning signals G1201 to G1240 output by GIA to the TFT.

[0077] See also Fig. 9 , the driving signal can be designed as a pulse signal. Figure 7 Compared with the design of the driving signal shown in FIG. 1 , in this embodiment, the last two levels of scanning signals output by the gate driving chip are used as the start control signal of the GIA, and the design of the remaining driving signals can refer to FIG. Figure 7 The relevant description in will not be repeated here.

[0078] In this embodiment, the source driver chip 1 outputs STV-U to the gate driver chip to instruct the gate driver chip to start the scanning operation, and outputs OE and CPV signals to the gate driver chip, and OE and CPV include 1200 cycles, so that the gate driver chip can output 1200 scanning signals to the TFTs in the display area according to a certain timing, such as G1 to G1200, thereby driving the 1st to 1200th rows of TFTs in the vertical direction, and then realizing the control of the 1st to 1200th rows of pixels in the vertical direction; the gate driver chip outputs an STV-D signal to the source driver chip to indicate that the scanning is completed. Accordingly, the GIA can start the scanning operation according to STV1 and STV2 obtained from the gate driver chip or the display area, and output the scanning signals G1201 to G1240 to the TFTs in the display area according to a certain timing sequence through the clock signals CLK1 to CLK4 obtained from the source driver chip 2, so as to drive the 1201st to 1240th rows of TFTs in the vertical direction, thereby realizing the control of the 1201st to 1240th rows of pixels in the vertical direction. The source driver chip 2 outputs STV3 and STV4 signals to the GIA to instruct the GIA to stop the scanning operation.

[0079] It should be understood that Fig. 9 The driving method shown can be applied to the scheme that the gate driving chip drives the TFT in the display area before the GIA, and can also be applied to Figure 2 The array substrate shown.

[0080] In the technical solution provided by the present application, the cascaded mode of GIA and gate driver chip is used to achieve the special-shaped resolution. Compared with the implementation mode of gate driver chip cascade, the technical solution provided by the present application can save the number of gate driver chips to save costs; compared with the implementation mode of using GIA in full, the power consumption of the technical solution provided by the present application is lower. According to the actual application situation, the power consumption of 2880-level GIA is 362 milliwatts (mW), the power consumption of 40-level GIA is about 5mW, and the power consumption of 1080-level gate driver chip is 29mW. The power consumption of 2880-level GIA can be understood as the power consumption consumed by GIA driving 2880 rows of TFTs, which can also be called the power consumption of 2880-level GIA. Correspondingly, the power consumption of 1080-level gate driver chip can be understood as the power consumption consumed by the gate driver chip driving 1080 rows of TFTs, which can also be called the power consumption of 1080-level gate driver chip. Compared with the special-shaped resolution of 1920*1240 (3:2), the power consumption of the cascade of GIA and gate driver chips is equivalent to the power consumption of two gate driver chips.

[0081] In the embodiment of the present application, the GIA has a weaker load capacity than the gate driver chip due to its own circuit design and component characteristics. When the screen refresh rate increases, the charging time of each row of TFTs will be reduced accordingly. Due to the limitation of the load capacity, the GIA may not be able to provide sufficient power for each row of TFTs in a shorter charging time, thereby reducing the display performance of the screen. Therefore, the present application provides a design scheme for unequally dividing the charging time. In this design scheme, the charging time of each row of TFTs driven by the gate driver chip can be appropriately reduced, and the time saved in the charging time of the TFTs driven by the gate driver chip can be compensated to the TFTs driven by the GIA, so as to extend the charging time of each row of TFTs driven by the GIA, thereby improving the transmission stability of the GIA signal and improving the display performance of the screen. It should be noted that, since the gate driver chip has a strong load capacity, if the charging time of each row of TFT driven by the gate driver chip is appropriately reduced, the impact on the screen display performance is small. However, since the number of rows of TFT driven by the gate driver chip is large and the number of rows of TFT driven by the GIA is small, if the time saved in the charging time of the TFT driven by the gate driver chip is compensated to the TFT driven by the GIA, the charging time of each row of TFT driven by the GIA will be greatly increased. It should be understood that in this design, the charging time of each row of TFT driven by the GIA is greater than the charging time of each row of TFT driven by the gate driver chip.

[0082] Taking the car screen with a resolution of 1920*1240 (3:2) and a refresh rate of 120Hz as an example, if the unequal charging time is not used, the charging time T of each row of TFT satisfies the formula: T=1 / 120 / (1240+60)=6.4us. This charging time is short, resulting in the GIA being unable to provide sufficient power for each row of TFT in a short charging time. Therefore, the unequal charging time design can be used to extend the charging time of each row of TFT driven by the GIA.

[0083] As an example, the GIA 40-step charging time can be designed or equivalent to the charging time of each row of TFTs when the screen refresh rate is 60Hz, thereby extending the charging time of each row of TFTs driven by the GIA to 12.8us. Accordingly, the charging time of each row of TFTs driven by the gate driver chip can be appropriately reduced. Assuming it is reduced to 6.2us, the gate driver chip 1200-step charging time design can be reversed at this time or equivalent to the charging time of each row of TFTs when the screen refresh rate is 124Hz, such as f=1 / (6.2*(1240+60))=124HZ. The GIA 40-step charging time can be understood as the charging time of each row of TFTs in the 40 rows of TFTs driven by the GIA, and the gate driver chip 1200-step charging time can be understood as the charging time of each row of TFTs in the 1200 rows of TFTs driven by the gate driver chip.

[0084] Fig.10 This is another design schematic diagram of a driving signal provided in this application. Fig.10 As shown, the GIA 40-step charging time is T1, T1 is 12.8us, and the gate driver chip 1200-step charging time is T2, T2 is 6.2us.

[0085] In the embodiment of the present application, due to its own circuit design and component characteristics, the driving capability of GIA to TFT is weaker than that of the gate driving chip to TFT, resulting in the problem of the screen being split up and down, such as Fig.11 To solve this problem, a chamfering circuit can be added to the gate driver chip so that the gate driver chip has a gate chamfering function, thereby reducing the VGH of the shutdown, balancing the driving ability of the gate driver chip and GIA to the TFT, improving the problem of the upper and lower split screen, and improving the display performance of the screen. In the embodiment of the present application, the driving ability of the GIA or the gate driver chip to the TFT can also be referred to as the thrust of the GIA or the gate driver chip.

[0086] Fig.12 Schematic diagram of the chamfering circuit provided for this application. Fig.12 G-1 shown is the gate signal generated by the gate driver chip. Fig.12 As shown, when the CPV signal is at a high level, the PNP (positive-negative-positive) transistor is turned off, and G-1 is directly connected to G1 for output. When the CPV signal is at a low level, the PNP transistor is turned on. At this time, there are the following two situations: Case 1: If the output end of the PNP transistor is connected to the contact 1 of the switch (such as SW in the figure), G-1 will be connected to the external resistor (such as R in the figure) through the turned-on PNP transistor in addition to being connected to G1, so that G-1 is in a slow discharge state, thereby reducing the turned-off VGH until the CPV signal is converted to a high level, the PNP transistor is turned off, and the discharge process of G-1 will end. It should be noted that the discharge speed of G-1 depends on the resistance value of the external resistor. Case 2: If the output end of the PNP transistor is connected to the contact 2 of the switch, G-1 will be connected to VGH through the PNP transistor. In this case, whether the PNP transistor is in the on or off state, the gate chamfering function is in the off state.

[0087] Fig.13 This is a schematic diagram illustrating the gate chamfering function provided in this application. Fig.13As shown, the gate driver chip can turn off the gate of the TFT at T3, that is, the VGH signal starts to switch to a low level at T3. It can be seen that when the chamfer circuit is added, the VGH signal will start to slowly decrease in advance at T4, thereby reducing the VGH that is turned off. In addition, the reduction amplitude of the VGH that is turned off is different for different resistance values ​​of the external resistors in the chamfer circuit. For example, when the resistance value R=R1, the VGH that is turned off is VGH1; when the resistance value R=R2, the VGH that is turned off is VGH2; when the resistance value R=R3, the VGH that is turned off is VGH3. Among them, VGH1>VGH2>VGH3.

[0088] The technical solution of the present application also provides a display panel, which may include the array substrate described in the aforementioned embodiment.

[0089] The technical solution of the present application also provides a display device, such as a display, which may include the display panel described in the aforementioned embodiment.

[0090] It should be emphasized that the above are only preferred embodiments of the present invention and do not limit the present invention in any form. Any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. An array substrate, characterized in that: The array substrate comprises a non-display area and a display area, the non-display area is provided with a source driver chip, an integrated gate driver circuit and a gate driver chip, and the display area is provided with M rows of thin film transistors, where M is a positive integer; The source driver chip is used to output a first control signal and a first clock signal to the gate driver chip, and to output a second control signal and a second clock signal to the integrated gate driver circuit; The gate driving chip is used to drive P consecutive rows of thin film transistors in the M rows of thin film transistors according to the first control signal and the first clock signal, where P is a positive integer less than M; The integrated gate driving circuit is used to drive Q consecutive rows of thin film transistors among the M rows of thin film transistors according to the second control signal and the second clock signal, where Q is the difference between M and P.

2. The array substrate according to claim 1, characterized in that: P is greater than Q.

3. The array substrate according to claim 2, characterized in that: The second control signal includes a start control signal and a stop control signal.

4. The array substrate according to claim 2, characterized in that: The second control signal is a shutdown control signal; The integrated gate drive circuit is further used to obtain a start control signal from the gate drive chip; The integrated gate driving circuit is used to drive consecutive Q rows of thin film transistors in the M rows of thin film transistors according to the second control signal, the start control signal and the second clock signal.

5. The array substrate according to claim 3 or 4, characterized in that: The charging time of each row of thin film transistors in the continuous P rows of thin film transistors is greater than or equal to the charging time of each row of thin film transistors in the continuous Q rows of thin film transistors.

6. The array substrate according to claim 5, characterized in that: The gate driving chip includes a chamfering circuit.

7. The array substrate according to claim 6, characterized in that: The gate driving chip and the integrated gate driving circuit are distributed on the same side or different sides of the array substrate.

8. The array substrate according to claim 7, characterized in that: There are multiple integrated gate driving circuits, and the integrated gate driving circuits are distributed on the upper and lower sides of the gate driving chip.

9. A display panel, characterized in that: The display panel includes the array substrate according to any one of claims 1 to 8.

10. A display device, characterized in that: The display device comprises the display panel as claimed in claim 9.

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