Current latch type sensitive amplifier capable of resisting single event upset

Abstract

The invention relates to a current latch type sense amplifier capable of resisting single event upset. The current latch type sense amplifier comprises a pre-charging circuit, a 4P unit, a 2P2N unit, a bit line input circuit and an enabling tube circuit, the pre-charging circuit is used for stabilizing an output node OUT and an output node OUTN at the same high level through a power supply VDD when a pre-charging signal PRE is at a low level before reading operation of the SRAM; the bit line input circuit and the enabling tube circuit are used for adjusting voltages of output nodes OUT and OUTN according to a voltage difference between a bit line signal BL and an anti-bit line signal BLN when the SRAM performs read operation; and the 4P unit and the 2P2N unit are used for recovering the circuit to the original state according to the redundant nodes S0 and S1 when single event upset occurs. When the pre-charging signal is in a low-level state, the output node is kept at a high level, and in the reading operation process, tiny voltage change is rapidly amplified, and the reliability and the reading precision of the circuit can be ensured.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a current latch-type sensitive amplifier resistant to single-particle upset. Background Art

[0002] Single Event Effect (SEE) refers to the interaction between high-energy particles (such as cosmic rays, solar wind or particles produced by radioactive material decay) and materials in semiconductor devices, causing local instantaneous charge deposition, resulting in transient or permanent abnormalities in electronic devices. Single Event Upset (SEU) refers to the phenomenon that high-energy particles pass through memory or logic circuits and change the state of a storage unit, causing the stored data to flip. This effect is instantaneous, but the data may need to be rewritten to restore normality.

[0003] SRAM and its peripheral circuits built on Fully Depleted Silicon On Insulator (FDSOI) technology have significant advantages in combating single-particle effects. The key is that the buried oxide layer can effectively isolate the charge and reduce the charge injection into the source and drain regions of the device due to high-energy particle impact, thereby significantly reducing the charge collection problem caused by single-particle effects. This directly reduces the probability of single-particle flips and single-event latch-up (SEL).

[0004] The sense amplifier is a key circuit module in the static random access memory (SRAM). Its main function is to transmit a tiny voltage difference through the bit line and the anti-bit line when reading data. This voltage difference is very small and it is very difficult to read directly. The sense amplifier can quickly sense this tiny differential voltage and amplify it, converting it into a standard signal level that can be processed by the logic circuit, thereby ensuring the correctness of the read data. Current latch sense amplifiers are widely used due to their high speed, low power consumption, and ability to adapt to smaller bit line swings. However, the latch structure of the traditional current latch sense amplifier consists of two interlocked inverters. When high-energy particles hit its sensitive node, the transient pulse current generated will cause the latch output to flip, resulting in errors when reading SRAM data. Summary of the invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a current latch-type sensitive amplifier resistant to single-particle upset.

[0006] According to a first aspect of an embodiment of the present invention, there is provided a current latch type sense amplifier resistant to single particle upset, comprising: a precharge circuit, a 4P unit, a 2P2N unit, a bit line input circuit and an enable tube circuit;

[0007] The precharge circuit is used for stabilizing the output node OUT and the output node OUTN to a high level through the power supply VDD when the precharge signal PRE is at a low level before the SRAM performs a read operation, and making the output node OUT and the output node OUTN have the same high level;

[0008] The bit line input circuit and the enable circuit are used to adjust the voltage of the output node OUT and the output node OUTN according to the voltage difference between the bit line signal BL and the inverted bit line signal BLN when the SRAM performs a read operation, so as to amplify the voltage change of the output node OUT and the output node OUTN;

[0009] The 4P unit and the 2P2N unit are used to restore the circuit to its original state according to the redundant node S0 and the redundant node S1 when a single particle upset occurs in a node in the circuit; wherein the redundant node S0 and the redundant node S1 are obtained according to the 4P unit and the 2P2N unit.

[0010] Optionally, the pre-charging circuit includes: a transistor P7, a transistor P8 and a transistor P9; the gates of the transistor P7, the transistor P8 and the transistor P9 are all connected to the pre-charging signal PRE, the source of the transistor P7 is connected to the power supply VDD, the drain of the transistor P7 is connected to the source of the transistor P9 and connected to the output node OUTN; the source of the transistor P8 is connected to the power supply VDD, the drain of the transistor P8 is connected to the drain of the transistor P9 and connected to the output node OUT.

[0011] Optionally, the 4P unit includes: a transistor P1, a transistor P2, a transistor P5 and a transistor P6; the sources of the transistor P1 and the transistor P2 are both connected to the power supply VDD, the drain of the transistor P1 is connected to the source of the transistor P5 and serves as the redundant node S0, the drain of the transistor P2 is connected to the source of the transistor P6 and serves as the redundant node S1, the gate of the transistor P1 is connected to the redundant node S1, and the gate of the transistor P2 is connected to the redundant node S0; the drains of the transistor P5 and the transistor P6 are both grounded, the transistor P5 is connected to the output node OUTN, and the transistor P6 is connected to the output node OUT.

[0012] Optionally, the 2P2N unit includes: a transistor P3, a transistor P4, a transistor N1 and a transistor N2; the sources of the transistor P3 and the transistor P4 are both connected to the power supply VDD, the drain of the transistor P3 is connected to the drain of the transistor N1 and is connected to the output node OUTN, the drain of the transistor P4 is connected to the drain of the transistor N2 and is connected to the output node OUT, the gate of the transistor P3 is connected to the redundant node S1, and the gate of the transistor P4 is connected to the redundant node S0; the sources of the transistor N1 and the transistor N2 are connected to the bit line input circuit, the gate of the transistor N1 is connected to the output node OUT, and the gate of the transistor N2 is connected to the output node OUTN.

[0013] Optionally, the bit line input circuit includes: a transistor N3 and a transistor N4; the drain of the transistor N3 is connected to the source of the transistor N1, the drain of the transistor N4 is connected to the source of the transistor N2, the sources of the transistor N3 and the transistor N4 are both connected to the enable tube circuit, the gate of the transistor N3 is connected to the bit line signal BL, and the gate of the transistor N4 is connected to the inverse bit line signal BLN.

[0014] Optionally, the enabling transistor circuit includes: a transistor N5; a source of the transistor N5 is grounded, a drain of the transistor N5 is connected to sources of the transistor N3 and the transistor N4, and a gate of the transistor N5 is connected to an enabling signal SAE.

[0015] The technical solution provided by the present invention may include the following beneficial effects:

[0016] Through the above technical solution, a circuit composed of a precharge circuit, a 4P unit, a 2P2N unit, a bit line input circuit and an enable tube circuit can maintain output stability during SRAM read operations. The precharge circuit maintains the output node at a high level when the precharge signal is low, and during the read operation, the circuit adjusts the voltage of the output node according to the voltage difference between the bit line signal and the anti-bit line signal to quickly amplify small voltage changes. At the same time, the circuit uses 4P units and 2P2N units to implement a self-recovery mechanism to deal with single-particle flip events. When high-energy particles bombard the circuit, the state of related devices may be affected, and a single-particle flip may occur. However, through the design of redundant nodes in the circuit, it can be effectively restored to the original state, ensuring the reliability and reading accuracy of the circuit.

[0017] Other features and advantages of the present invention will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present invention but do not constitute a limitation of the present invention. In the accompanying drawings:

[0019] Figure 1 The diagram is a schematic structural diagram of a current latch-type sense amplifier resistant to single-particle upset according to an exemplary embodiment.

[0020] Figure 2 A timing diagram is shown according to an exemplary embodiment.

[0021] Figure 3 is another timing diagram shown according to an exemplary embodiment.

[0022] Figure 4 is another timing diagram shown according to an exemplary embodiment.

[0023] Description of Reference Numerals

[0024] 10. Precharge circuit; 2. 4P unit; 3. 2P2N unit; 4. Bit line input circuit; 5. Enable tube circuit. DETAILED DESCRIPTION

[0025] Figure 1 is a schematic diagram of the structure of a current latch type sense amplifier resistant to single-particle upset according to an exemplary embodiment. Figure 1 As shown, it includes: a precharge circuit 10, a 4P unit 20, a 2P2N unit 30, a bit line input circuit 40 and an enable tube circuit 50;

[0026] The precharge circuit 10 is used for stabilizing the output node OUT and the output node OUTN to a high level through the power supply VDD when the precharge signal PRE is at a low level before the SRAM performs a read operation, and making the output node OUT and the output node OUTN have the same high level;

[0027] The bit line input circuit 40 and the enable circuit 50 are used to adjust the voltage of the output node OUT and the output node OUTN according to the voltage difference between the bit line signal BL and the inverted bit line signal BLN when the SRAM performs a read operation, so as to amplify the voltage change of the output node OUT and the output node OUTN;

[0028] The 4P unit 20 and the 2P2N unit 30 are used to restore the circuit to its original state according to the redundant node S0 and the redundant node S1 when a single particle upset occurs in a node in the circuit; wherein the redundant node S0 and the redundant node S1 are obtained according to the 4P unit 20 and the 2P2N unit 30.

[0029] Optionally, the pre-charging circuit 10 includes: a transistor P7, a transistor P8 and a transistor P9; the gates of the transistors P7, P8 and P9 are all connected to a pre-charging signal PRE, the source of the transistor P7 is connected to the power supply VDD, the drain of the transistor P7 is connected to the source of the transistor P9 and is connected to the output node OUTN; the source of the transistor P8 is connected to the power supply VDD, the drain of the transistor P8 is connected to the drain of the transistor P9 and is connected to the output node OUT.

[0030] Specifically, refer to Figure 1 When the pre-charge signal PRE is at a low level (usually logic "0"), transistors P7 and P8 are turned on, and the power supply VDD is directly connected to the output node OUT and the output node OUTN, stabilizing them at a high level (usually logic "1"). Transistor P9 is a balancing tube and is also turned on at this time to ensure that the output node OUT and the output node OUTN have the same high level.

[0031] Optionally, the 4P unit 20 includes: a transistor P1, a transistor P2, a transistor P5 and a transistor P6; the sources of the transistor P1 and the transistor P2 are both connected to the power supply VDD, the drain of the transistor P1 is connected to the source of the transistor P5 and serves as a redundant node S0, the drain of the transistor P2 is connected to the source of the transistor P6 and serves as a redundant node S1, the gate of the transistor P1 is connected to the redundant node S1, and the gate of the transistor P2 is connected to the redundant node S0; the drains of the transistor P5 and the transistor P6 are both grounded, the transistor P5 is connected to the output node OUTN, and the transistor P6 is connected to the output node OUT.

[0032] Optionally, the 2P2N unit 30 includes: a transistor P3, a transistor P4, a transistor N1 and a transistor N2; the sources of the transistor P3 and the transistor P4 are both connected to the power supply VDD, the drain of the transistor P3 is connected to the drain of the transistor N1 and is connected to the output node OUTN, the drain of the transistor P4 is connected to the drain of the transistor N2 and is connected to the output node OUT, the gate of the transistor P3 is connected to the redundant node S1, and the gate of the transistor P4 is connected to the redundant node S0; the sources of the transistor N1 and the transistor N2 are connected to the bit line input circuit 40, the gate of the transistor N1 is connected to the output node OUT, and the gate of the transistor N2 is connected to the output node OUTN.

[0033] Optionally, the bit line input circuit 40 includes: a transistor N3 and a transistor N4; the drain of the transistor N3 is connected to the source of the transistor N1, the drain of the transistor N4 is connected to the source of the transistor N2, the sources of the transistor N3 and the transistor N4 are both connected to the enable circuit 50, the gate of the transistor N3 is connected to the bit line signal BL, and the gate of the transistor N4 is connected to the inverse bit line signal BLN.

[0034] Optionally, the enabling transistor circuit 50 includes: a transistor N5; the source of the transistor N5 is grounded, the drain of the transistor N5 is connected to the sources of the transistor N3 and the transistor N4, and the gate of the transistor N5 is connected to the enabling signal SAE.

[0035] In one embodiment, a sense amplifier is required for the SRAM read operation. The SRAM bit line signal BL and the inverted bit line signal BLN are connected to the differential input terminal of the sense amplifier, and the amplified signal is read out from the output node OUTN and the output node OUT, thus completing the SRAM read operation.

[0036] Figure 2 It is a timing diagram according to an exemplary embodiment. Before the SRAM read operation, when the enable signal SAE is at a low level, the transistor N5 is turned off and the circuit is not enabled. At this time, the pre-charge signal PRE is at a low level, and the three transistors N7, N8 and N9 are turned on, and the output nodes OUT and OUTN are pre-charged to a high level at the same time; when the SRAM performs a read operation, the enable signal SAE and the pre-charge signal PRE rise, the transistor N5 is turned on, the transistor N7, the transistor N8 and the transistor N9 are turned off, the bit line signal BL and the inverse bit line signal BLN are connected to the transistor N3 and the transistor N4 respectively, and when the SRAM reads "1", the voltage of the bit line signal BL is greater than the voltage of the inverse bit line signal BLN. Since the gate voltages of the transistor N3 and the transistor N4 are different, the currents of the two branches are also different, so the voltage drop speeds of the output nodes OUTN and OUT are also different. The branch current corresponding to the transistor N3 with a high gate voltage is relatively large, and the voltage of the corresponding output node OUTN also drops faster, so that the transistor P5 is turned on first, the voltage of the redundant node S0 is reduced, the transistors P2 and P4 are turned on, the output node OUT and the redundant node S1 are connected to the power supply VDD, and the voltage no longer drops, and then remains at a high level. The high-level output node OUT is connected to the gate of the transistor N1, so as to keep the transistor N1 continuously turned on for discharge. The output node OUTN is quickly pulled down to a low level through this feedback process, so as to amplify the tiny voltage difference between the bit line signal BL and the inverted bit line signal BLN to the power supply VDD and GND, and the originally tiny voltage difference between the bit line signal BL and the inverted bit line signal BLN is amplified to the power supply VDD (800 millivolts) to GND (0 millivolts) through the amplifier, which can be referred to Figure 2 12 nanoseconds to 15 nanoseconds.

[0037] When the SRAM reads "0", the bit line signal BL is less than the inverted bit line signal BLN. Since the gate voltages of transistors N3 and N4 are different, the currents of the two branches are also different, so the voltage drop speeds of output nodes OUTN and OUT are also different. The branch current corresponding to transistor N4 with a high gate voltage is larger, and the voltage of its corresponding output node OUT also drops faster, and then transistor P6 is turned on first, the voltage of redundant node S1 decreases, transistors P1 and transistor P3 are turned on, and the output node OUTN and redundant node S0 are connected to the power supply VDD, and the voltage no longer drops, and then remains at a high level. The high-level output node OUTN is connected to the gate of transistor N2, so as to keep transistor N2 continuously turned on for discharge, and the output node OUT is quickly pulled down to a low level through this feedback process.

[0038] In another embodiment, when high-energy particles bombard the device, the transient current generated may cause a single-particle flip at the sensitive node. When a PMOS transistor is bombarded by high-energy particles, only an upward transient current may be formed, thereby forming a flip from "0" to "1" or "1" to "1"; when an NMOS transistor is bombarded by high-energy particles, only a downward transient current may be formed, thereby forming a flip from "1" to "0" or "0" to "0".

[0039] Reference Figure 1 When the SRAM reads "1", if a single-particle flip occurs at the redundant node S0 and changes from "0" to "1", the transistor P2 and the transistor P4 will be temporarily turned off, but the transistor P6 and the transistor N2 will also be turned off at this time, and the states of the redundant node S1 and the output node OUT will not change. With the help of the turned-on transistor P5, the redundant node S0 will be restored; if a single-particle flip occurs at the redundant node S1, since the PMOS transistor can only form an upward transient current, only a "1" to "1" transient pulse can be generated at the redundant node S1, and this will not change the logic value of the redundant node S1, so the redundant node S1 is not a sensitive node at this time.

[0040] Reference Figure 1 and Figure 2When the SRAM reads "1", if a single particle flip occurs at the output node OUT (because the value of the output node OUT is "1" at this time, only transistor N2 needs to be paid attention to), that is, the drain of transistor N2 is bombarded by high-energy particles to generate a downward transient current, and the output node OUT changes from "1" to "0". At this time, transistor N1 will be temporarily closed, and transistor P6 will be turned on, but transistor P2 has always been in the on state, and the size of transistor P2 is larger than transistor P6, so the redundant node S1 will not be pulled down to a low level by transistor P6, but will maintain a high level unchanged, so transistor P3 and transistor P1 will not be turned on, so that the redundant node S0 and the output node OUTN maintain a low level unchanged, and the redundant node OUT is pulled back to a high level by the turned-on transistor P4 and the turned-off transistor N2, realizing the single particle flip self-recovery process of the node, thereby correctly amplifying the voltage difference between the bit line and the anti-bit line to avoid errors in the read operation. You can refer to Figure 2 16 nanoseconds to 18 nanoseconds in the timing diagram.

[0041] Figure 3 is another timing diagram according to an exemplary embodiment, referring to Figure 1 and Figure 3 In the process of SRAM reading "1", if a single particle flip occurs on the output node OUTN (because the value of the output node OUTN is "0" at this time, only transistor P3 needs to be paid attention to), that is, the drain of transistor P3 is bombarded by high-energy particles to generate an upward transient current, and the output node OUTN changes from "0" to "1". At this time, transistor P5 is temporarily closed, and transistor N2 will be temporarily opened, but at the same time, transistor P4 is also in the on state, and transistor P5 is closed. The redundant node S0 node remains unchanged due to the capacitance effect, so that transistor P4 can always remain on. Since the size of transistor P4 is larger than that of transistor N2, the output node OUT node is pulled back to a high level by transistor P4 after a short voltage drop, so that transistor N1 is turned on again, and the output node OUTN is pulled down to a low level by transistor N1, realizing the single particle flip recovery process of the node, thereby correctly amplifying the voltage difference between the bit line and the anti-bit line to avoid errors in the read operation. You can refer to Figure 3 16 nanoseconds to 18 nanoseconds in the timing diagram.

[0042] Figure 4 According to another exemplary timing diagram, refer to Figure 1 and Figure 4, when the SRAM reads "1", if the output node OUT and the output node OUTN have a single particle flip at the same time, as described above, only the transistor N2 needs to be paid attention to at the output node OUT, and only the transistor P3 needs to be paid attention to at the output node OUTN. At this time, the drain of the transistor N2 is bombarded by high-energy particles to generate a downward transient current, and the drain of the transistor P3 is bombarded by high-energy particles to generate an upward transient current. The output node OUT changes from "1" to "0", and the output node OUTN changes from "0" to "1". The transistor N1 and the transistor P5 are temporarily turned off, and the transistor N2 and the transistor P6 are temporarily turned on. The redundant node S1 is because the size of the transistor P2 is larger than that of the transistor P6. Although transistor P2 and transistor P6 are turned on at the same time, under the action of transistor P2 with larger size and stronger driving ability, redundant node S1 maintains high level unchanged, so transistor P1 remains closed and redundant node S0 maintains low level unchanged; transistor P3 also remains closed, so it will not provide a continuous and stable high level to output node OUTN. Under the action of transistor P4 with larger size and stronger driving ability, output node OUT is pulled back to high level, and then transistor N1 is turned on again, and output node OUTN is restored to low level, completing the double-node anti-single particle flip process of output node OUT and output node OUTN, thereby correctly amplifying the voltage difference between the bit line and the anti-bit line to avoid errors in read operation. You can refer to Figure 4 16 nanoseconds to 18 nanoseconds in the timing diagram.

[0043] Refer again Figure 1It should be noted that the circuit structure of this example is completely symmetrical. When the SRAM reads "0", the working principle and anti-single particle upset principle of the sensitive amplifier in this example are similar to the SRAM read "1" operation. When the SRAM reads "0", if the output node OUT and the output node OUTN simultaneously have single particle upsets, as described above, only transistor P4 needs to be paid attention to at the output node OUT, and only transistor N1 needs to be paid attention to at the output node OUTN. At this time, the drain of transistor N1 is bombarded by high-energy particles to generate a downward transient current, and the drain of transistor P4 is bombarded by high-energy particles to generate an upward transient current. The output node OUTN changes from "1" to "0", and the output node OUT changes from "0" to "1". Transistor N2 and transistor P6 are temporarily turned off, and transistors N1 and Transistor P5 is temporarily turned on. Since transistor P1 is larger than transistor P5, redundant node S0 maintains a high level under the action of transistor P1 with a larger size and stronger driving capability, although transistor P1 and transistor P5 are turned on at the same time, transistor P2 remains turned off and redundant node S1 maintains a low level. Transistor P4 also remains turned off, so it will not provide a continuous and stable high level to the output node OUT. Under the action of transistor P3 with a larger size and stronger driving capability, the output node OUTN is pulled back to a high level, and then transistor N2 is turned on again, and the output node OUT returns to a low level, completing the dual-node single-particle flip resistance process of the output node OUT and the output node OUTN, thereby correctly amplifying the voltage difference between the bit line and the anti-bit line to avoid errors in the read operation.

[0044] Through the above technical solution, a current latch-type sensitive amplifier resistant to single-particle upset is provided, and its structure includes multiple PMOS and NMOS transistors to achieve anti-interference ability to transient currents caused by high-energy particles, and can maintain output stability during SRAM read operations. The precharge circuit keeps the output node at a high level in a low-level state, and during the read operation, the circuit adjusts the voltage of the output node according to the voltage difference between the input bit line signal and the inverse bit line signal to quickly amplify small voltage changes. At the same time, the circuit is designed with a self-recovery mechanism to deal with single-particle upset events. When high-energy particles bombard the circuit, the state of the related transistors may be affected, but through the redundant design and feedback mechanism of the circuit, it can be effectively restored to the original state, ensuring the reliability and reading accuracy of the circuit.

[0045] The preferred embodiments of the present invention are described in detail above in conjunction with the accompanying drawings. However, the present invention is not limited to the specific details in the above embodiments. Within the technical concept of the present invention, a variety of simple modifications can be made to the technical solution of the present invention, and these simple modifications all belong to the protection scope of the present invention.

[0046] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present invention will not further describe various possible combinations.

[0047] In addition, various embodiments of the present invention may be arbitrarily combined, and as long as they do not violate the concept of the present invention, they should also be regarded as the contents disclosed by the present invention.

Claims

1. A current latching type sense amplifier resistant to single-event upset, characterized in that: include: A precharge circuit (10), a 4P unit (20), a 2P2N unit (30), a bit line input circuit (40) and an enable tube circuit (50); The precharge circuit (10) is used for stabilizing the output node OUT and the output node OUTN to a high level through the power supply VDD when the precharge signal PRE is at a low level before the SRAM performs a read operation, and making the output node OUT and the output node OUTN have the same high level; The bit line input circuit (40) and the enable tube circuit (50) are used to adjust the voltage of the output node OUT and the output node OUTN according to the voltage difference between the bit line signal BL and the inverse bit line signal BLN when the SRAM performs a read operation, so as to amplify the voltage change of the output node OUT and the output node OUTN; The 4P unit (20) and the 2P2N unit (30) are used to restore the circuit to its original state according to the redundant node S0 and the redundant node S1 when a single particle flip occurs in a node in the circuit; wherein the redundant node S0 and the redundant node S1 are obtained according to the 4P unit (20) and the 2P2N unit (30).

2. The single-event upset-resistant current latched sense amplifier according to claim 1, characterized in that: The pre-charging circuit (10) comprises: a transistor P7, a transistor P8 and a transistor P9; the gates of the transistors P7, P8 and P9 are all connected to the pre-charging signal PRE, the source of the transistor P7 is connected to the power supply VDD, the drain of the transistor P7 is connected to the source of the transistor P9 and connected to the output node OUTN; the source of the transistor P8 is connected to the power supply VDD, the drain of the transistor P8 is connected to the drain of the transistor P9 and connected to the output node OUT.

3. The single-event upset-resistant current latched sense amplifier according to claim 1, characterized in that: The 4P unit (20) comprises: a transistor P1, a transistor P2, a transistor P5 and a transistor P6; the sources of the transistor P1 and the transistor P2 are both connected to the power supply VDD, the drain of the transistor P1 is connected to the source of the transistor P5 and serves as the redundant node S0, the drain of the transistor P2 is connected to the source of the transistor P6 and serves as the redundant node S1, the gate of the transistor P1 is connected to the redundant node S1, and the gate of the transistor P2 is connected to the redundant node S0; the drains of the transistor P5 and the transistor P6 are both grounded, the transistor P5 is connected to the output node OUTN, and the transistor P6 is connected to the output node OUT.

4. The single-event upset-resistant current latched sense amplifier according to claim 1, characterized in that: The 2P2N unit (30) comprises: a transistor P3, a transistor P4, a transistor N1 and a transistor N2; the sources of the transistor P3 and the transistor P4 are both connected to the power supply VDD, the drain of the transistor P3 is connected to the drain of the transistor N1 and is connected to the output node OUTN, the drain of the transistor P4 is connected to the drain of the transistor N2 and is connected to the output node OUT, the gate of the transistor P3 is connected to the redundant node S1, and the gate of the transistor P4 is connected to the redundant node S0; the sources of the transistor N1 and the transistor N2 are connected to the bit line input circuit (40), the gate of the transistor N1 is connected to the output node OUT, and the gate of the transistor N2 is connected to the output node OUTN.

5. The single-event upset-resistant current latched sense amplifier according to claim 4, characterized in that: The bit line input circuit (40) comprises: a transistor N3 and a transistor N4; the drain of the transistor N3 is connected to the source of the transistor N1, the drain of the transistor N4 is connected to the source of the transistor N2, the sources of the transistor N3 and the transistor N4 are both connected to the enabling transistor circuit (50), the gate of the transistor N3 is connected to the bit line signal BL, and the gate of the transistor N4 is connected to the inverse bit line signal BLN.

6. The single-event upset-resistant current latched sense amplifier according to claim 5, characterized in that: The enabling transistor circuit (50) comprises: a transistor N5; the source of the transistor N5 is grounded, the drain of the transistor N5 is connected to the sources of the transistor N3 and the transistor N4, and the gate of the transistor N5 is connected to an enabling signal SAE.

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