Method for thinning semiconductor substrate

Abstract

A method for thinning a semiconductor substrate includes providing a first substrate having a planar front side and a planar back side, creating a device layer on the front side of the first substrate, creating an additional layer on top of the device layer, bonding the first substrate to a second substrate, thinning the first substrate from the back side of the first substrate, creating a cavity in at least one region of the first substrate where the semiconductor device is to be created, the cavity being at least partially filled with a dielectric material, forming a dielectric filled cavity; the device is generated in a region between two adjacent dielectric filled cavities and is covered by an additional dielectric layer; at the end of the thinning step, the first substrate is thinned into a layer of uniform crystalline semiconductor material over the dielectric filled cavity; performing anisotropic etching on the crystalline semiconductor material after the thinning step; an in-plane dimension of a region between two adjacent dielectric filled cavities and a depth of the adjacent cavities are configured such that the anisotropic etch process does not reach the semiconductor device.

Description

Technical Field

[0001] The present invention relates to semiconductor processing and, more particularly, to extreme thinning of substrates from the backside. Background Art

[0002] In semiconductor processing, active devices such as transistors and diodes are manufactured on the front side of a semiconductor substrate (e.g., a silicon processing wafer with a diameter of 300 mm). Above the device, a multilayer interconnect structure is constructed to route signals to or from the device. Traditionally, power transmission to the device is also carried out through the interconnect structure on the front side. However, recent developments have led to the integration of a back power distribution network built on the back side of the substrate. In order to achieve this, the substrate needs to be extremely thinned from the back side, so that the thickness of the substrate portion is less than 500 nm, preferably even to the extent of completely removing the Si substrate and leaving only the active Si devices. Similarly in stacked IC construction, the substrate portion of the IC chip needs to be thinned to a similar extremely low thickness value.

[0003] Traditionally, thinning is performed by applying grinding and polishing techniques to bond the wafer face-down to another processing wafer or a temporary carrier substrate and to remove a large portion of the wafer from its backside.

[0004] However, one problem is that no processed wafer is perfectly flat. Typical thickness for a standard 300 mm diameter processed wafer is 775 μm with a total thickness variation (TTV) of only 1 or a few microns. Relative accuracy is better than 0.2% at full thickness. Both the wafer to be thinned and the receiving (supporting) wafer are subject to this thickness variation after wafer-to-wafer bonding. Therefore, it is practically impossible to thin a wafer from the backside to very low thickness values ​​using only grinding and polishing techniques without negatively affecting the active devices in one or more areas of the wafer. When thinning wafer thicknesses below a few microns, TTV variations of a few microns become a major problem.

[0005] A known solution to this problem is to produce ICs on so-called SOI wafers [silicon-on-insulator], which consist of a thin oxide layer on bulk silicon and a thin epitaxially grown Si layer on top of the oxide. Devices and multilayer interconnect structures are fabricated on this epitaxial Si layer, after which the wafer is bonded face-down to another wafer or a carrier. Thinning from the back by grinding and polishing is then stopped before reaching the oxide layer, and the remaining bulk silicon is removed by wet etching, with the oxide layer acting as an etch stop. Thereafter, the oxide itself is removed by selective etching relative to the epitaxially grown Si. Instead of the oxide layer, an epitaxially grown SiGe layer can be used as an etch stop.

[0006] However, these solutions are technically complex, increasing the cost of the semiconductor manufacturing process. Summary of the invention

[0007] The present invention relates to a method according to the appended claims. According to the method, a first crystalline semiconductor substrate is provided and semiconductor device layers are produced on its front side, in regions separated by dielectric-filled cavities, which regions may include shallow trench isolation regions formed prior to device processing. Additional layers, such as layers of a multilayer interconnect structure, are formed on the device layers. The substrate is then turned over and bonded face-down to a second substrate, followed by thinning the first crystalline substrate from the back side. The thinning process is carried out as far as possible, as long as the entire thickness is not removed anywhere on the surface of the first substrate, i.e. taking into account any inherent thickness variations of the first and second substrates. Thereafter, an anisotropic etch is performed to remove more material from the first substrate. According to the present invention, the in-plane dimensions of the device regions separated by dielectric-filled cavities are configured so that the anisotropic etch is stopped by the crystal planes of the substrate material or the dielectric material in the cavities before reaching the devices on the front side. Depending on the exact dimensions of the device regions and possible depth differences between adjacent dielectric-filled cavities, the anisotropic etch may be stopped when a V-shaped groove is formed in the substrate material. After the anisotropic etch, further dielectric material is deposited and planarized together with the remaining material of the first substrate.

[0008] Therefore, the method can thin the first substrate to a level very close to the device layer, such as the order of tens of nanometers, without the risk of accidentally removing or damaging the device in the device layer. No etching stop layer is required, and the method is applicable to substrates formed integrally of the same material. Therefore, the method can simplify semiconductor process steps and reduce costs.

[0009] The invention relates in particular to a method for producing a thinned semiconductor substrate, said method comprising the following steps, which are performed in succession:

[0010] - providing a first substrate having a planar front side and a planar back side, said first substrate being formed integrally of a crystalline semiconductor material or comprising a layer formed integrally of said crystalline semiconductor material on its front side,

[0011] - producing a device layer on the front side of the first substrate, said device layer comprising a plurality of semiconductor devices,

[0012] - creating additional layers on top of the device layer, ending with a layer with a planar top surface,

[0013] - permanently or temporarily bonding the first substrate to the second substrate by bonding the planar top surface to a bonding surface of the second substrate,

[0014] - thinning the first substrate from the back side of the first substrate,

[0015] Features:

[0016] - before producing the device layer and in at least one or more regions of the first substrate in which the semiconductor device is to be produced, producing a cavity through the front surface of the first substrate and into the crystalline semiconductor material of the first substrate, and at least partially filling the cavity with a dielectric material, thereby forming a dielectric-filled cavity,

[0017] - the device in said one or more regions is produced in a plurality of regions located between two adjacent dielectric-filled cavities and said device is covered by an additional dielectric layer,

[0018] - at the end of the thinning step, the first substrate is reduced to a uniform layer of crystalline semiconductor material remaining above said dielectric-filled cavity,

[0019] - after the thinning step, an anisotropic etching process is performed on the crystalline semiconductor material,

[0020] - the in-plane dimensions of the region between two adjacent dielectric-filled cavities and the depths of the adjacent cavities are configured such that the anisotropic etching process stops at one or more of the following without reaching the semiconductor device:

[0021] oOn the crystal planes of crystalline semiconductor materials,

[0022] oOn the dielectric material in the chamber,

[0023] o on the additional dielectric layer,

[0024] - The method further comprises the following steps after the anisotropic etching process:

[0025] o depositing another dielectric material on the thinned back side of the first substrate,

[0026] o planarizing the other dielectric material and the remaining portion of the crystalline semiconductor material to a common planarized surface.

[0027] According to one embodiment, additional dielectric-filled cavities are also produced in regions of the first substrate where no semiconductor devices are produced.

[0028] According to one embodiment, the space between any pair of adjacent additional dielectric-filled cavities is configured such that the anisotropic etching process does not reach the front side of the first substrate in the space.

[0029] According to one embodiment, at least some of the dielectric-filled cavities located within one or more regions of the first substrate in which the semiconductor device is to be produced are shallow trench isolation regions.

[0030] According to one embodiment, the crystalline semiconductor material is crystalline silicon.

[0031] According to one embodiment, the first substrate is a silicon processing wafer having a planar front side and a planar back side oriented along the crystal planes of silicon.

[0032] According to one embodiment, the in-plane dimensions and the depth of the dielectric-filled cavities are configured such that at least in some of the regions between two adjacent dielectric-filled cavities the etching process ends when a V-shaped groove is formed in the material of the first substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figures 1a to 1c A processed wafer and the layout of multiple dies on the wafer are shown.

[0035] Figures 2 to 13 The key steps of the method according to one embodiment of the present invention are shown.

[0036] Figures 14 to 16 An embodiment of a thinning method according to the invention is shown, in which large areas of bulk material of a processed wafer are removed.

[0037] Figures 17 to 19 One embodiment is shown that includes an additional dielectric filled cavity to prevent bulk wafer material from being removed to the front side of the wafer. DETAILED DESCRIPTION

[0038] Figure 1a A processed wafer 1 is shown, which may be a crystalline silicon wafer as known in the art, such as a standard processed wafer with a diameter of 300 mm and a thickness of 775 μm. The dividing lines 2 divide the wafer surface into a plurality of die regions 3. Four adjacent die regions 3 are located at Figure 1b In these die areas 3, a given layout of active devices such as transistors and diodes will be produced by a series of processing steps. Each die area 3 can be about a few dozen square millimeters and will be filled with nano-sized devices in the finished chip. The separation lines 2 are wide enough to be able to separate the finished chips and can also be used as areas for printing auxiliary features (such as metrology marks).

[0039] like Figure 1c As shown in FIG. 5 (showing an enlarged view of a point 5 in the die area), the method of the present invention is explained based on a nanometer-sized cross section along line AA in one die area 3 . Figure 2 The cross-sectional view of this small area is further enlarged in FIG. Only a thin upper portion of the wafer 1 is shown, which portion has a thickness of about several hundred nanometers. Preferably, the wafer is formed integrally from a crystalline semiconductor material, but a composite wafer with a top layer of crystalline semiconductor material can also be applied to the method of the present invention.

[0040] like Figure 3 As shown, a plurality of trenches 10 are formed through the front surface of the wafer 1 by photolithography and etching, thereby defining semiconductor structures 11 and 12 separated by the trenches 10. Figure 3 In the exemplary case shown, two sets of fins 11 and two larger structures 12 are formed. The fins 11 may have a width of, for example, a few nanometers or tens of nanometers at their tops, and are typically formed for the purpose of processing finFET transistors. The larger areas 12 may be dummy areas, or these areas 12 may be used to process other types of devices thereon, such as planar transistors or diodes. The photolithography steps and etching steps used to produce this type of pattern are well known in the art, so their details are not required to explain the present invention.

[0041] refer to Figure 4 , a dielectric material 13 is selectively deposited and etched back relative to the fins 11 and larger structures 12 to a level between the bottom and top of the fins and structures. This is the creation of so-called shallow trench isolation (STI) 14, another concept well known in the art and applied to electrically isolate adjacent devices. The dielectric material 13 can be silicon oxide or any suitable material known for this purpose.

[0042] The dielectric-filled trench 14 is an embodiment of the broader term "dielectric-filled cavity" used in the attached claim 1. A trench is an elongated cavity whose length is much greater than its width. The STI regions used to isolate devices are usually produced in the form of such elongated cavities (i.e., trenches). However, other areas on the chip may include dielectric-filled cavities of other shapes, particularly square or rectangular, where the difference between the length and width of the rectangle is smaller. As will be explained later in this specification, the presence of the dielectric-filled cavity 14 plays a major role in the present invention. According to embodiments of the present invention, dielectric-filled trenches or other cavities can be formed in areas where such trenches or cavities are not found in prior art designs, such as in the dividing line 2 between adjacent die areas 3. The reasons for this will also be further explained herein. However, at present, attention should be focused again on the small cross-section AA as shown in Figures 1 to 4.

[0043] After the dielectric-filled trench 14 has been created, the actual processing of the semiconductor device takes place. This involves a number of process steps which are not described in detail here, since these steps are known per se and do not constitute a specific feature of the present invention. The result is presented in simplified form in Figure 5 . Device regions 15 are formed on the two sets of fins. These may be gate regions of finFETs, for example. One of the larger regions 12a may be a dummy region, while the other region 12b receives a planar device 16 on its upper surface.

[0044] Other known steps are Figure 6 and Figure 7 . Another dielectric material 17 is deposited and planarized. This is a material suitable for use as a pre-metal dielectric (PMD), such as SiO2 or a low-K material. Interconnect vias 18 and conductors 19 are produced in the PMD layer 17 by known techniques (such as a single damascene process or a dual damascene process). The planarized PMD layer 17 in which the device is embedded is referred to as a "device layer" 20 in the present invention. The device layer may correspond to the front end of the line portion of the chip, and also includes a first metallization layer sometimes referred to as an M0 layer or the middle end of the line.

[0045] On the device layer 20, additional interconnect vias and conductor layers are processed (see Figure 7 ), which may correspond to the back side of the end line portion of the integrated circuit. In the illustrated embodiment, the BEOL portion schematically shows a layer 21 having a planar top surface 22.

[0046] Subsequently, the wafer is flipped over and bonded face-down to another substrate. For this purpose, the planar top surface 22 of the BEOL portion 21 may be the surface of a dielectric bonding layer (formed of, for example, SiO2 or SiCN), or a hybrid bonding layer comprising a dielectric material and a coplanar metal contact pad. Such a bonding layer is suitable for a well-known wafer to wafer direct bonding process, which may involve a heating step for forming a strong bond.

[0047] Alternatively, the planar top surface 22 of the BEOL portion 21 may be suitable for temporarily bonding the wafer face-down to a temporary carrier wafer. Figure 8 A temporary carrier 23 and a removable adhesive layer 24 are shown, to which the BEOL portion 21 is bonded, such that the main body of the processed wafer 1 faces upwards. Suitable types of carrier wafers and adhesives for this purpose are also well known to those skilled in the art.

[0048] refer to Fig. 9 , and then the wafer 1 is thinned from the back. This can be done by any thinning method known in the art, for example by first using a grinding technique in order to remove most of the bulk material of the wafer in a short time. It is possible to use an etching process instead of the grinding technique. Preferably, polishing is performed after the grinding or etching process, for example in the form of chemical mechanical polishing (CMP) to further reduce the thickness at a slower rate, ultimately resulting in a smooth rear surface 25 of the thinned wafer 1. Alternatively, an additional etching process can be applied to obtain the rear surface 25.

[0049] At this time, due to the inherent thickness variations of both the wafer 1 and the carrier 23 and possibly due to a certain degree of non-uniformity in the applied thinning technology, Fig. 9The thickness A of the remaining silicon bulk substrate shown is not constant over the entire surface of the wafer 1, but varies in the micrometer range. Fig. 9 In the case shown in , the initial thinning is configured so that the wafer 1 is reduced to a uniform layer 1' of wafer material remaining above the dielectric-filled trenches 14, i.e., no dielectric-filled trenches 14 are exposed by the thinning process. Taking into account common values ​​of thickness variation on processed wafers, an average thickness A of, for example, 500 nm to 1 μm is usually sufficient for this condition. However, if the thickness variation of the applied substrate is lower than the values ​​usually encountered, the actual average value of the thickness A can be lower.

[0050] According to the present invention, the remaining wafer material is then further thinned by an anisotropic etching process, such as Fig.10 As shown, wafer material is selectively removed relative to the dielectric-filled trench 14. The process is anisotropic in the sense that the bulk semiconductor material of the wafer 1 is removed along specific crystal planes of the wafer material. Processes of this type are known per se and are used, for example, to produce pyramidal indentations in the surface of semiconductor wafers. For example, when the wafer 1 is a Si wafer whose planar surface is oriented along the (100) crystal plane, the KOH or TMAH etching process will remove Si along the (111) crystal plane, which is oriented at about 54° relative to the (100) crystal plane.

[0051] Due to the anisotropic nature of the etching process and due to the selectivity of the etching process with respect to the dielectric material in the trench 14, when Fig.10 In the case shown, the etching process stops automatically. The bottom of the (reverse) trench is exposed, and a V-groove 26 is formed in the semiconductor region between two adjacent trenches. If the wafer is actually a (100) Si wafer, the angle α in each V-groove 26 is about 54°.

[0052] It can be seen that the wafer has now been thinned without the need for an etch stop layer adjacent to the device layer 20. However, in order to achieve this result, additional conditions must be met. The position of the bottom of the V-groove where the etching process stops depends on the depth of the groove and the spacing between the STI grooves, that is, the width of the semiconductor region between two adjacent grooves. The latter parameter in particular determines whether the etching process reaches the front side of the wafer before automatically stopping. Therefore, in the area of ​​the wafer where active devices are produced on the front side of the wafer, the spacing between adjacent dielectric-filled cavities (such as STI grooves) needs to be configured so that anisotropic etching does not reach the active devices located on the front side of the wafer. In other words, anisotropic etching cannot allow the removal of semiconductor materials that contribute to the operation of active devices.

[0053] This situation must be taken into account during the design phase to ensure that the distance between adjacent STI trenches is not greater than a given maximum value.

[0054] Fig.10 It is also shown that the depth difference between two adjacent STI trenches 14 will cause the tip of the V-groove 26 to deviate from the center of the spacing between the two trenches. When the depth difference is further increased, the trench is no longer a V-groove, but the anisotropic etch will still stop due to its selectivity with respect to the dielectric material of the STI trench. This Fig.11 In the case shown, the depth difference between the plurality of adjacent STI trenches is higher than Fig.10 The depth difference in the embodiment shown is such that the anisotropic etch stops when it reaches the material of the STI region at position 27. This is also an allowable embodiment of the present invention. However, in most chip designs, the STI depth is targeted to be relatively uniform across the wafer, so it is more likely to occur. Fig.10 The situation shown.

[0055] Therefore, we will use Fig.10 to explain the subsequent processing steps. Fig.12 As shown, a layer of dielectric material 30 is deposited to fill the V-grooves 26 and form a uniform layer. Preferably, the thickness of this layer is at least twice the depth of the deepest trench (measured from the bottom of the deepest trench). Fig.13 As shown, this layer 30 is thinned, preferably by grinding and / or polishing, to a level 31, wherein most of the bulk wafer material is removed. On this planarized surface 31, further processing steps may be performed, for example for producing a backside power distribution network.

[0056] As described above, the conditions that need to be met are that the spacing between the dielectric-filled cavities 14 and the devices formed within the spacing on the front side of the wafer are large enough to avoid the negative impact of the anisotropic etching process on the devices. As also described above, the STI regions known in the chip design can exhibit the function of the dielectric-filled cavities required in the method described in the present invention. However, this does not mean that the method is applicable to any existing chip design. In order to make the existing design compatible with the present invention, it may be necessary to add STI regions or adjust the spacing between existing STI regions.

[0057] In areas of the wafer where no active devices are present, the spacing between adjacent dielectric-filled cavities can be larger, to the extent that wafer material is removed to the wafer front side within said spacing. An example of such a spacing is Fig.14 The region between the dielectric-filled trenches 32 and 33 may be located, for example, in a separation line between two adjacent die regions on a wafer.

[0058] like Fig.14As shown in , the anisotropic etching process removes the wafer material between the grooves 32 and 33 to the front side of the wafer 1, thereby creating a wide gap 35 between the grooves 32 and 33. This is not prohibited within the scope of the present invention, as long as the etching process stops on the PMD material 17 at the bottom of the gap 35 (i.e., an etching process that is selective with respect to the PMD material is required). Thereafter, the gap 35 is filled with the dielectric material 30 used to fill the V-groove 26, as shown in FIG. Fig.15 As shown, then Fig.16 According to another embodiment, the anisotropic etch may be timed so that it stops before reaching the front side of the wafer 1 in the gap region 35 .

[0059] However, planarizing the large dielectric-filled gap 35 may be difficult, especially when the surface area of ​​the gap becomes too large, which may lead to a recessed effect. Therefore, preferably, additional dielectric-filled trenches are intentionally provided in areas of the wafer where no active devices are formed. This is particularly useful in Figure 17-19 The spacing between the additional trenches 40 also allows the anisotropic etch to stop before reaching the front side of the wafer by forming a V-groove 26 in areas where no devices are present. Fig.19 This results in smaller gaps between adjacent trenches and a flatter backside after the final thinning step shown.

[0060] Although the invention has been illustrated and described in detail in the drawings and the foregoing description, such illustration and description should be considered illustrative or exemplary rather than restrictive. Other changes to the disclosed embodiments can be understood and implemented by those skilled in the art in practicing the claimed invention by studying the drawings, the disclosure and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality. The fact that certain measures are set forth in mutually different dependent claims does not mean that a combination of these measures cannot be utilized. Any reference signs in the claims should not be interpreted as limiting the scope.

Claims

1. A method for producing a thinned semiconductor substrate, the method comprising the following steps which are performed in succession: - providing a first substrate (1) having a planar front side and a planar back side, said first substrate being formed integrally of a crystalline semiconductor material or comprising a layer formed integrally of said crystalline semiconductor material on its front side, - producing a device layer (20) on the front side of the first substrate (1), said device layer comprising a plurality of semiconductor devices, - creating an additional layer (21) on top of the device layer (20), ending with a layer having a planar top surface (22), - permanently or temporarily bonding the first substrate (1) to the second substrate (23) by bonding the planar top surface (22) to a bonding surface of the second substrate (23), - thinning the first substrate (1) from the back side of the first substrate, Features: - before producing the device layer (20) and in at least one or more regions of the first substrate (1) in which the semiconductor device is to be produced, producing a cavity (10) through the front surface of the first substrate and into the crystalline semiconductor material of the first substrate, and at least partially filling the cavity with a dielectric material, thereby forming a dielectric-filled cavity (14), - the device in the one or more regions is produced in a plurality of regions located between two adjacent dielectric-filled cavities (14) and the device is covered by an additional dielectric layer (17), - at the end of the thinning step, the first substrate is thinned to a uniform layer (1') of crystalline semiconductor material remaining above said dielectric-filled cavity (14), - after the thinning step, an anisotropic etching process is performed on the crystalline semiconductor material, - configuring the in-plane dimensions of the region between two adjacent dielectric-filled cavities (14), and the depths of the adjacent cavities (14), so that the anisotropic etching process stops at one or more of the following locations without reaching the semiconductor device: oOn the crystal planes of crystalline semiconductor materials, o on a dielectric material in the chamber (14), o on the additional dielectric layer (17), The method further comprises the following steps after the anisotropic etching process: o depositing another dielectric material (30) on the thinned back side of the first substrate (1), o planarizing the further dielectric material (30) and the remaining portion of the crystalline semiconductor material to a common planarized surface (31).

2. The method of claim 1, wherein: An additional dielectric-filled cavity (40) is also created in the area of ​​the first substrate (1) where no semiconductor device is produced.

3. The method of claim 2, wherein: The space between any pair of adjacent additional dielectric filling cavities (40) is configured so that the anisotropic etching process does not reach the front surface of the first substrate (1) in the space.

4. A method as claimed in any one of the preceding claims, wherein: At least some of the dielectric-filled cavities (14) are shallow trench isolation regions, the dielectric-filled cavities being located within one or more regions of the first substrate in which the semiconductor device is to be produced.

5. A method as claimed in any one of the preceding claims, wherein: The crystalline semiconductor material is crystalline silicon.

6. The method of claim 5, wherein: The first substrate is a silicon fabricated wafer having a planar front side and a planar back side along the (100) crystal orientation of silicon.

7. A method as claimed in any of the preceding claims, wherein the in-plane dimensions and the depth of the dielectric-filled cavities (14) are configured so that, at least in some of the areas between two adjacent dielectric-filled cavities, the etching process ends when a V-shaped groove (26) is formed in the material of the first substrate (1).

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