Scheduling method and related device

Abstract

The embodiment of the invention provides a scheduling method, which comprises the following steps of: determining a wafer priority sequence by taking a plurality of wafers to be scheduled in a target material set as objects, and adding a next wafer to be scheduled into a schedule and outputting the wafer based on the priority sequence of the wafers to be scheduled so as to ensure continuous wafer outputting. The probability of idle equipment modules in the semiconductor process equipment is reduced, and the scheduling efficiency of the semiconductor process equipment is improved.

Description

Technical Field

[0001] The present specification relates to the field of semiconductor technology, specifically, to automatic control technology under the field of semiconductor technology, and more specifically, to a scheduling method and related devices. Background Art

[0002] Semiconductor process equipment is a type of equipment used for semiconductor wafer manufacturing. Semiconductor process equipment may include modules such as an alignment module (Aligner), a robot, a vacuum lock (LoadLock), a wafer loading and unloading position (LoadPort) and multiple process chambers (Process Chamber). Semiconductor process equipment can be used to achieve automatic processing and circulation of wafers.

[0003] In order to improve the working efficiency of semiconductor process equipment, semiconductor process equipment can be used to process multiple wafers in parallel. Currently, there is a problem of low equipment utilization in the wafer scheduling technology in semiconductor process equipment. Summary of the invention

[0004] The embodiments of this specification provide a scheduling method and related devices to achieve the purpose of improving equipment utilization.

[0005] To achieve the above technical objectives, the embodiments of this specification provide the following technical solutions:

[0006] In a first aspect, an embodiment of the present specification provides a scheduling method, which is applied to a controller of a semiconductor process equipment, wherein the semiconductor process equipment further includes a wafer loading and unloading position, and the scheduling method includes:

[0007] Acquire a target material set, wherein the target material set includes a plurality of wafers to be scheduled;

[0008] Based on the priority parameters of the wafers to be scheduled, determining the priority order of the plurality of wafers to be scheduled;

[0009] Based on the priority order of the wafers to be scheduled, the wafers to be scheduled are scheduled from the corresponding wafer loading and unloading positions in sequence, and the wafer delivery time of the wafers to be scheduled with a high priority is earlier than the wafer delivery time of the wafers with a low priority.

[0010] In a second aspect, an embodiment of the present specification provides a semiconductor process scheduling device, comprising: a processor and a memory; a computer program is stored in the memory, and when the processor executes the computer program, it implements any of the scheduling methods described above.

[0011] In a third aspect, an embodiment of the present specification provides a semiconductor process equipment, including a semiconductor process scheduling device and a plurality of device modules;

[0012] The semiconductor process scheduling device is configured to schedule the wafers to be scheduled to be output according to any of the scheduling methods described above.

[0013] In a fourth aspect, an embodiment of the present specification further provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the scheduling method as described above is implemented.

[0014] It can be seen from the above technical scheme that the scheduling method provided in the embodiment of this specification takes multiple wafers to be scheduled in the target material set as the object, determines the priority order of the wafers, and based on the priority order of the wafers to be scheduled, adds the next wafer to be scheduled to the schedule and outputs the wafer to ensure continuous output. Because the wafer is no longer bound to the semiconductor process equipment during the scheduling process, the probability of idle equipment modules appearing in the semiconductor process equipment is reduced, thereby improving the scheduling efficiency of the semiconductor process equipment. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the embodiments of this specification or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this specification. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0016] Figure 1 A schematic diagram of the structure of a semiconductor process equipment provided for one embodiment of the present specification;

[0017] Figure 2 A schematic diagram of the structure of another semiconductor process equipment provided for one embodiment of the present specification;

[0018] Figure 3 A flowchart of a scheduling method provided for one embodiment of this specification;

[0019] Figure 4 A schematic diagram of a process for determining wafer priority provided for one embodiment of this specification;

[0020] Figure 5 A schematic diagram of a process for determining the priority of a process task provided for one embodiment of this specification;

[0021] Figure 6 A schematic diagram of a process for determining a control task priority is provided for one embodiment of this specification;

[0022] Figure 7A schematic diagram of the structure of a computing device provided for one embodiment of the present specification. DETAILED DESCRIPTION

[0023] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of this specification shall have the common meanings understood by persons with ordinary skills in the field to which this specification belongs. The words "first", "second" and similar words used in the embodiments of this specification do not indicate any order, quantity or importance, but are only used to avoid confusion of constituent elements.

[0024] Unless the context requires otherwise, throughout the specification, "plurality" means "at least two", and "including" is interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "examples", "specific examples" or "some examples" are intended to indicate that a particular feature, structure, material or characteristic associated with the embodiment or example is included in at least one embodiment or example of the specification. The schematic representation of the above terms does not necessarily refer to the same embodiment or example.

[0025] The following will be combined with the drawings in the embodiments of this specification to clearly and completely describe the technical solutions in the embodiments of this specification. Obviously, the described embodiments are only part of the embodiments of this specification, not all of the embodiments. Based on the embodiments in this specification, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this specification.

[0026] Overview

[0027] refer to Figure 1 , Figure 1 The structure diagram of a semiconductor process equipment is shown, and the semiconductor process equipment may include a first robot 10, a second robot 20, a wafer loading and unloading position 21, a calibration module 22, a cooling module 23, a buffer module 24, a vacuum lock 25 and a plurality of process chambers 11; wherein,

[0028] Each wafer loading and unloading position 21 can hold a wafer box, and each wafer box can hold multiple wafers.

[0029] The calibration module 22 may include a slot, and the calibration module 22 may calibrate the wafer placed in the slot.

[0030] Processing chamber 11 (Processing Module), each process chamber 11 may have a slot to place a wafer for processing.

[0031] The cooling module 23 (Cooler) is used to cool the wafer after processing.

[0032] The first robot 10 (or vacuum transfer robot, Vacuum Transfer Robot, abbreviated as VTR) can be a double-arm robot. The two arms of the double-arm robot can be 180° and fixed. Each arm has a slot, and each slot can hold a wafer. Generally, the two arms cannot perform wafer picking and placing operations at the same time; the first robot 10 is responsible for transporting wafers between the vacuum lock 25 and multiple process chambers 11.

[0033] There can be two slots on the vacuum lock (LoadLock) 25, each slot can hold a wafer, and the vacuum lock 25 can switch between atmospheric state and vacuum state. When the vacuum lock state is converted to atmospheric state, the wafer located on the side of the second robot 20 can be sent into the vacuum lock 25; when the vacuum lock 25 is converted to vacuum state, the wafer located on the side of the first robot 10 can be sent into the vacuum lock 25.

[0034] The second robot 20 (or atmospheric robot, Air Transfer Robot, referred to as ATR) can be a single-arm robot. The second robot 20 can have a slot for placing a wafer. The second robot 20 can be responsible for transporting wafers between the wafer loading and unloading position 21, the calibration module 22 and the vacuum lock 25.

[0035] The buffer module 24 , also called a material buffer, can load multiple wafers to prevent the wafer loading and unloading position 21 from storing both processed wafers and unprocessed wafers.

[0036] Understandably, Figure 1 The following is only used to exemplify the feasible structure of the semiconductor process equipment. In other embodiments, the semiconductor process equipment may include more or fewer types of equipment modules. For example, some semiconductor process equipment may include a first robot 10, a second robot 20, a wafer loading and unloading position 21, a calibration module 22, a cooling module 23, a buffer module 24, a vacuum lock 25 and at least some equipment modules in multiple process chambers 11; the number of equipment modules of the same type included in the semiconductor process equipment may also be different, for example, Figure 1In the semiconductor process equipment shown, the number of wafer loading and unloading positions 21 is 3, the number of buffer modules 24 is 4, the number of vacuum locks 25 is 2, and the number of process chambers 11 is 4. However, in other embodiments, the number of wafer loading and unloading positions 21 of the semiconductor process equipment can be 2 or 4, etc., the number of buffer modules 24 can be 6 or 8, etc., the number of vacuum locks 25 can be 3 or 4, etc., and the number of process chambers 11 can be 6 or 8, etc., for example, Figure 2 The semiconductor process equipment shown in the figure has four wafer loading and unloading positions (LP1 to LP4), four process chambers (PM1 to PM4), two vacuum locks (LLA and LLB), and Figure 2 The semiconductor process equipment shown does not include a buffer module, and this specification does not limit the feasible topological structure of the semiconductor process equipment, which depends on the actual situation.

[0037] In the semiconductor process equipment, the first manipulator and the second manipulator can be called the transmission module, and the modules other than the first manipulator and the second manipulator can be called the equipment module. Figure 2 Taking the semiconductor process equipment shown as an example, the process path of the wafer can be expressed as: LoadPort->Aligner->LoadLock->PM->LoadLock->Cooler->LoadPort. The PM module can be freely combined in parallel by PM1-PM4. For example, path 1: LoadPort->Aligner->LoadLock->PM1 / PM2->LoadLock->Cooler->LoadPort; path 2: LoadPort->Aligner->LoadLock->PM3 / PM4->LoadLock->Cooler->LoadPort. The controller of the semiconductor process equipment is usually scheduled in units of a wafer box (Foup). Before the wafers in the wafer box participate in the scheduling, the wafer box will be loaded on the wafer loading and unloading position. During the scheduling process, scheduling can be performed in units of a wafer box, that is, a control task is established for all wafers in a wafer box. The control task can be called a Cjob (Control job), and the wafers in different control tasks can be triggered from different wafer loading and unloading positions.

[0038] A control task may include at least one process task, which may be called a Pjob (Process job). The process paths of wafers in different process tasks are different, and the process paths of wafers in the same process task are the same. Each process task includes at least one wafer.

[0039] When creating a control task, you can set the type for the control task. The types of control tasks can include manual tasks (ManuJobs), highest tasks (HighestJobs), higher tasks (HigherJobs) and normal tasks (NormalJobs).

[0040] A manual task is a separate control task inserted manually. The manual task includes at least one process task. The process task includes at least one wafer. The manual task can be used to realize the process of moving the wafer from one position to another position of the semiconductor process equipment.

[0041] The highest task is an emergency order, which has the authority to interrupt all other control tasks in execution except manual tasks. It can stop a control task that has already started producing wafers, but wafers that have already been produced from the wafer loading and unloading position can continue to complete the remaining process path.

[0042] A higher task is also a type of urgent order, with a lower priority than the highest task, but higher than the normal task. It cannot interrupt the control task of the normal task being executed, but can be queued up to execute before other control tasks of the normal task that are not executed. For example, suppose there are two control tasks of the normal task type: Task 1 and Task 2 are queued for execution. When Task 1 is executed, the upper computer issues a control task of the higher task type. Then the newly issued control task can be queued up to execute before Task 2, but cannot interrupt the executing Task 1.

[0043] Normal tasks are the task types used when semiconductor process equipment is operating normally, and have the lowest priority among all control tasks.

[0044] When creating a control task, the process tasks in the control task are also assigned configuration priorities to define the scheduling order between different process tasks in the same control task. In the same process task, different wafers have different priorities, and the scheduling order of wafers can be determined according to their identity (such as wafer ID).

[0045] In order to strictly control the scheduling scale, in some scheduling methods, the host will allocate idle process chambers to wafers based on the occupancy of process chambers in semiconductor process equipment and task priority information. That is, by binding wafers to idle process chambers, when the remaining process time of the wafer in the process chamber is a predetermined time, the process chamber is released, and the scheduling algorithm will allocate the process chamber to the next wafer and schedule the next wafer, thus ensuring that all scheduled wafers are processed in the process chamber strictly according to the priority order.

[0046] However, the inventors have found that this scheduling method may cause the scheduling results to deviate from the global optimal choice. In some cases, some equipment modules of the semiconductor process equipment become idle, thereby reducing the overall scheduling and production efficiency.

[0047] For example, suppose a control task Cjob is configured with a process task Pjob, and the Pjob contains scheduling tasks for 25 wafers, and the identity of each wafer is 1 to 25, and the priority of the wafer decreases from 1 to 25. Assume that the process path of the wafer in the Pjob includes: LoadPort->Aligner->LoadLock->PM1 / PM2->LoadLock->Cooler->LoadPort; the process time of the wafer in the process chamber is 100s. According to the scheduling method described above, during the scheduling process, the process chamber PM1 will be bound to the wafer with priority 1, and the process chamber PM2 will be bound to the wafer with priority 2. When the wafer with priority 1 enters PM1 to start the process, and the predetermined time (for example, 50s) is left before the end of the process, PM1 is released, and the scheduling algorithm binds PM1 to the next wafer with priority 3; similarly, when the wafer with priority 2 enters PM2 to start the process, and the predetermined time (for example, 50s) is left before the end of the process, PM2 is released, and the scheduling algorithm binds PM2 to the next wafer with priority 4. At this time, set the release time of PM1 (or the time when the scheduling algorithm binds the next wafer to the process chamber) to 50 seconds before the end of the wafer process. Then, for any process path and process time configuration, PM1 will be released at this time. This release time is not determined by the scheduling algorithm, and is not a property that changes with the process path, but an empirical value manually configured during the scheduling process. This release time may be appropriate for some process paths and process times, but when the process path and process time change, it may cause some equipment modules to be idle.

[0048] Assume that when the release timing of PM1 is set to 50 seconds before the end of the wafer process, for the Pjob of process path A and process time A, it can ensure that the various equipment modules in the semiconductor process equipment are not idle and ensure that the equipment operates at a higher efficiency. However, for the Pjob of process path B and process time B, PM1 may need to be released 70 seconds before the end of the process to ensure that the various equipment modules in the semiconductor process equipment are not idle. However, since the above scheduling algorithm does not sense all wafers that need to be scheduled, it will only sense and schedule the next wafer 50 seconds before the end of the wafer process in PM1, which will cause the next wafer to be delayed by 20 seconds. In this case, even if the equipment modules Aligner and LoadLock before PM1 are idle due to no wafer occupancy, the scheduling algorithm will not schedule the next wafer from the wafer loading and unloading position, resulting in reduced scheduling and production efficiency of the entire equipment.

[0049] In order to solve this problem, the inventors have discovered that the priority order of wafers can be determined based on multiple wafers to be scheduled in the target material set. Based on the priority order of the wafers to be scheduled, the next wafer to be scheduled can be added to the schedule and shipped out to ensure continuous shipping, thereby reducing the probability of idle equipment modules in the semiconductor process equipment and improving the scheduling efficiency of the semiconductor process equipment. In addition, the timing for adding the next wafer to be scheduled to be added to the schedule and shipped out can be when the target module (for example, the first equipment module that the wafer arrives at after being shipped from the wafer loading and unloading position) is idle.

[0050] Based on the above concept, an implementation manner of this specification provides a scheduling method. The scheduling method provided in the implementation manner of this specification will be exemplarily described below in conjunction with the accompanying drawings.

[0051] Exemplary Methods

[0052] To be applied to Figure 3 Taking the controller of the semiconductor process equipment shown in as an example, the present specification provides a scheduling method, wherein the semiconductor process equipment further includes a wafer loading and unloading position. In some embodiments, the semiconductor process equipment may further include a target module, and the target module is the first equipment module that the wafer arrives at after being unloaded from the wafer loading and unloading position. The scheduling method includes:

[0053] S301: Acquire a target material set, where the target material set includes a plurality of wafers to be scheduled;

[0054] S302: Determine the priority order of the plurality of wafers to be scheduled based on the priority parameters of the wafers to be scheduled;

[0055] S303: The wafers to be scheduled are scheduled to be discharged from the corresponding wafer loading and unloading positions in sequence, and the discharge time of the wafers to be scheduled with a high priority is earlier than the discharge time of the wafers with a low priority.

[0056] The controller of the semiconductor process equipment includes but is not limited to the host computer of the semiconductor process equipment. During the scheduling process, the controller can receive scheduling information, which may include relevant information of the wafer to be scheduled, relevant information of the control tasks to be generated and the process tasks. After receiving the scheduling information, the controller uses the scheduling information as the input of the scheduling algorithm, so that the scheduling algorithm can schedule the wafer to be scheduled based on the scheduling information. The scheduling method provided in the implementation mode of this specification may be part of the scheduling algorithm in the controller, which is used to determine the priority order of the wafers to be scheduled and schedule the wafer output based on the priority order. The complete scheduling algorithm can also be used to plan the scheduling sequence of the wafer based on the process path and the current state of the equipment module. The scheduling sequence records the scheduling action of the wafer to be scheduled to complete the process according to the process path and return to the wafer loading and unloading position, the start execution time and end time of each scheduling action, and other information.

[0057] The target material set may refer to a set of all wafers to be scheduled that are currently located at the wafer loading and unloading position, and the target material set may include wafers waiting to execute control tasks and process tasks. That is, in this embodiment, instead of scheduling each wafer by binding wafers to idle process chambers based on process chambers, the priority order of each wafer to be scheduled is determined based on multiple wafers to be scheduled that participate in the scheduling, and then the wafers to be scheduled are scheduled based on their priority order, which reduces the probability of long-term idleness of equipment modules in semiconductor process equipment and improves scheduling and production efficiency.

[0058] The priority parameters of the wafers to be scheduled may include parameters that affect the order of wafers to be scheduled, and these parameters include but are not limited to: the configuration priority of the wafer to be scheduled (such as an identity), the configuration priority of the process task to which the wafer to be scheduled belongs, the configuration priority of the control task to which the wafer to be scheduled belongs, the creation time of the process task to which the wafer to be scheduled belongs, the creation time of the control task to which the wafer to be scheduled belongs, the wafer-out time of the control task to which the wafer to be scheduled belongs, the wafer-out time of the process task to which the wafer to be scheduled belongs, etc., any one or any combination thereof. This specification does not limit this, and it depends on the actual situation. Among them, the wafer-out time of a control task or process task refers to the time when the first wafer in the task leaves the wafer loading and unloading position after being planned by the scheduling algorithm. When the scheduling algorithm receives relevant information of a control task or a process task for the first time, the wafer delivery time defaults to infinity. The scheduling algorithm can make preliminary plans based on the identity of the wafer to be scheduled, the configuration priority of the process task to which the wafer to be scheduled belongs, and the configuration priority of the control task to which the wafer to be scheduled belongs. The wafer delivery time of each control task or process task can be obtained. The wafer delivery time represents the scheduling priority of different tasks (control tasks / process tasks) to a certain extent, and can be used as a reference parameter for determining the priority of the wafer to be scheduled.

[0059] In a feasible implementation, the target module may refer to the first equipment module to which the wafer arrives after being unloaded from the wafer loading and unloading position, for example, Figure 1 In the example, the target module may include a buffer module or a calibration module. Figure 2 In the embodiment, the target module may include a calibration module (Aligner), and the target module may be different depending on the structure of the semiconductor process equipment. This specification does not limit this, and the specific configuration depends on the actual situation.

[0060] The step of sequentially scheduling the wafers to be scheduled from corresponding wafer loading and unloading positions based on the priority order of the wafers to be scheduled specifically includes:

[0061] When the target module is idle, the wafers to be scheduled are scheduled to be discharged from corresponding wafer loading and unloading positions in sequence based on the priority order of the wafers to be scheduled.

[0062] In this embodiment, a timing for scheduling the wafer to be scheduled out of the wafer loading and unloading position is given. The timing may be when the target module is idle, and the target module refers to the first equipment module that the wafer arrives at after being taken out of the wafer loading and unloading position. In this way, the idle time of the target module can be minimized, thereby improving the processing efficiency of the semiconductor process equipment on the wafer.

[0063] In a feasible embodiment, a feasible method for determining the priority of wafers to be scheduled is provided. Specifically, the priority parameters include: the configuration priority of the wafers to be scheduled; the control task includes at least one process task, and the process task includes at least one scheduling task of the wafers to be scheduled, and the process paths of the wafers to be scheduled in the same process task are the same.

[0064] The step of determining the priority order of the plurality of wafers to be scheduled based on the priority parameters of the wafers to be scheduled comprises:

[0065] For the multiple wafers to be scheduled that belong to the same process task, the priority of the wafers to be scheduled is determined according to their configuration priorities, and the priority of the wafers to be scheduled with a higher configuration priority is higher than the priority of the wafers to be scheduled with a lower configuration priority.

[0066] In one embodiment, the configuration priority of the wafer to be scheduled can be determined based on the identity of the wafer to be scheduled. In this embodiment, for multiple scheduled wafers belonging to the same process task, determining their respective priorities based on the configuration priority can ensure orderly scheduling of the scheduled wafers in the same process task.

[0067] In an optional implementation manner, the priority parameter further includes: the wafer delivery time of the wafer to be scheduled and the creation time of the control task to which the wafer to be scheduled belongs;

[0068] The step of determining the priority order of the plurality of wafers to be scheduled based on the priority parameters of the wafers to be scheduled comprises:

[0069] For each wafer to be scheduled that belongs to different process tasks, compare the wafer delivery time of the wafer to be scheduled with the creation time of the control tasks to which other wafers to be scheduled belong, and determine that the priority of the wafer to be scheduled with an earlier wafer delivery time is higher than the priority of the wafer to be scheduled with a later creation time of the control tasks to which it belongs.

[0070] In an optional implementation, the priority parameter further includes: the priority of the process task to which the wafer to be scheduled belongs; and determining the priority order of the plurality of wafers to be scheduled based on the priority parameter of the wafer to be scheduled includes:

[0071] For the multiple wafers to be scheduled that belong to different process tasks, and the wafer delivery time of each wafer to be scheduled is no earlier than the creation time of the control task to which other wafers to be scheduled belong, the priorities of the multiple wafers to be scheduled are determined according to the priorities of the process tasks to which they each belong, and the priority of the wafer to be scheduled that belongs to a process task with a higher priority is higher than the priority of the wafer to be scheduled that belongs to a process task with a lower priority.

[0072] Specifically, in one embodiment, if the two wafers to be scheduled belong to the same process task, the priority of the wafer to be scheduled is determined according to the configuration priority of the wafer to be scheduled;

[0073] If the two wafers to be scheduled belong to different process tasks, the priority of the first wafer of the two wafers to be scheduled is set higher than the priority of the second wafer, wherein the wafer delivery time of the first wafer is earlier than the creation time of the control task to which the second wafer belongs;

[0074] If the two wafers to be scheduled belong to different process tasks, and the delivery time of any one of the two wafers to be scheduled is not earlier than the creation time of the control task to which the other wafer belongs, then the priority of the two wafers to be scheduled is determined according to the priority of the process tasks to which the two wafers to be scheduled belong.

[0075] refer to Figure 4 , Figure 4 A feasible process for comparing the priorities of two wafers to be scheduled (i.e., wafer 1 and wafer 2) is shown. When the priority parameters of wafer 1 and wafer 2 are input, it is first determined whether wafer 1 and wafer 2 belong to the same process task (Pjob). If so, the priority can be determined directly according to the configuration priority of wafer 1 and wafer 2. In the wafer box, in order to distinguish different wafers, corresponding identity tags are usually assigned to the wafers. In one embodiment, the configuration priority of the wafers decreases in order from small to large identity tags.

[0076] If wafer 1 and wafer 2 do not belong to the same process task, determine whether there is a wafer whose delivery time is less than the creation time of the control task to which the other wafer belongs. If so, it means that in the preliminary planning of the scheduling algorithm, the wafer with an earlier delivery time has a higher priority scheduling. The wafer with an earlier delivery time can be used as the first wafer, and the other wafer can be used as the second wafer, and the priority of the first wafer is determined to be higher than that of the second wafer.

[0077] If there is no wafer whose wafer-out time is less than the creation time of the control task to which another wafer belongs, the priority of the process tasks to which the two wafers belong respectively is determined as the priority of the corresponding wafer.

[0078] In this embodiment, a feasible method for determining wafer priority through several priority parameters is provided, which is simple and easy to implement and does not require complicated calculations.

[0079] In a feasible implementation, a feasible process for determining the priority of a process task is given, referring to Figure 5 , the process includes:

[0080] For process tasks belonging to the same type of control tasks, the film release time of each process task, the priority of the control task to which each process task belongs and the configuration priority are compared in turn, and the priority of each process task is determined according to the comparison result; among which, the process task with an earlier film release time has a higher priority; the process task with a higher priority of the control task to which it belongs has a higher priority; and the process task with a higher configuration priority has a higher priority.

[0081] In an optional implementation, the process of determining the priority of the process task includes:

[0082] For process tasks belonging to different control tasks, the priority of the corresponding process task is determined according to the priority of the control task to which it belongs. The higher the priority of the control task to which it belongs, the higher the priority of the process task.

[0083] Specifically, if the two process tasks belong to the same type of control tasks, the wafer delivery time of the two process tasks, the priority of the control tasks to which the two process tasks belong and the configuration priority of the two process tasks are compared in turn, and the priority of the two process tasks is determined according to the comparison result; the configuration priority of the process task is allocated when the process task is created, and the configuration priority of the process task is used to characterize the scheduling order of process tasks of the same type;

[0084] If the two process tasks belong to a first control task and a second control task of different types, respectively, the priorities of the process tasks are determined according to the types of the first control task and the second control task.

[0085] Figure 5 A feasible process for comparing the priorities of two process tasks (i.e., Pjob1 and Pjob2) is shown. When Pjob1 and Pjob2 are taken as input, it is first determined whether Pjob1 and Pjob2 belong to the same type of control tasks (Cjob). If so, the output times of the two process tasks, the priorities of the control tasks to which the two process tasks belong, and the configuration priorities of the two process tasks are compared in turn. According to the comparison results, the priorities of the two process tasks are determined; if not, the priorities are determined according to the types of control tasks to which Pjob1 and Pjob2 belong respectively.

[0086] In a feasible implementation, a feasible process is provided for determining the priorities of the two process tasks by sequentially comparing the wafer delivery times of the two process tasks, the priorities of the control tasks to which the two process tasks belong, and the configuration priorities of the two process tasks, according to the comparison results. The process includes:

[0087] If the two process tasks have different film delivery times, the process task with an earlier film delivery time has a higher priority;

[0088] If the wafer output time of the two process tasks is the same, the priorities of the control tasks to which the two process tasks belong are compared, and the process task to which the control task has a higher priority has a higher priority;

[0089] If the control tasks to which the two process tasks belong have the same priority level, the configuration priorities of the two process tasks are compared, and the process task with a higher configuration priority level has a higher priority level.

[0090] In this embodiment, when determining the priority of a process task, the importance of the production time of the process task, the priority of the control task to which the process task belongs, and the configuration priority of the process task are reduced in turn. This is because the scheduling algorithm has made advance planning with reference to many parameters when initially planning and determining the production time of the process task. The production time can more accurately represent the scheduling priority of the process task. Therefore, first comparing the production time of the process task can more accurately determine the priority between the process tasks. In addition, in this embodiment, the method of determining the priority of the process task is simple and easy, and does not require complex calculations.

[0091] In an optional implementation, a feasible determination process of the priority of a control task is provided, such as Figure 6 As shown, the process may include:

[0092] For control tasks of the same type, the production time, creation time and configuration priority of each control task are compared in turn, and the priority of each control task is determined based on the comparison result; among them, the control task with an earlier production time has a higher priority; the control task with an earlier creation time has a higher priority; the process task with a higher configuration priority has a higher priority.

[0093] Optionally, the process of determining the priority of the control task includes:

[0094] For control tasks of different types, the priorities of the control tasks are determined according to the types of the control tasks.

[0095] Specifically, if the types of the two control tasks are the same, the production time, creation time and configuration priority of the two control tasks are compared in turn, and the priority of the control task is determined according to the comparison result; the configuration priority of the control task is allocated when the control task is created, and the configuration priority of the control task is used to characterize the scheduling order of control tasks of the same type;

[0096] If the types of the two control tasks are different, the priorities of the control tasks are determined according to the types of the control tasks.

[0097] Similarly, in this embodiment, when determining the priority of a control task, the importance of the control task's release time, creation time, and configuration priority are reduced in sequence. This is because the scheduling algorithm has made plans with reference to many parameters when preliminarily planning to determine the release time of the control task. The release time can more accurately represent the scheduling priority of the control task. Therefore, first comparing the release time of the control tasks can more accurately determine the priority between the control tasks.

[0098] Optionally, in one embodiment, as described above, the types of control tasks may include: manual tasks and top tasks;

[0099] Thus, determining the priority of the control task according to the type of the control task specifically includes:

[0100] The priority of a control task of type manual task is higher than that of other types of control tasks;

[0101] The priority of a control task of the highest task type is higher than the priority of a control task of a type that is not a manual task and the highest task;

[0102] For each control task that is not a manual task or the highest task, compare the release time of the control task with the creation time of other control tasks to determine that the priority of the control task with an earlier release time is higher than the priority of the control task with a later creation time.

[0103] Optionally, in one embodiment, the types of control tasks further include: higher tasks and ordinary tasks;

[0104] The determining the priority of the control task according to the type of the control task further includes:

[0105] For each control task that is not a manual task or a top task, if the release time of each control task is not earlier than the creation time of other control tasks, the priority of the control task of the higher task type is higher than the priority of the control task of the ordinary task type.

[0106] Specifically, in one embodiment, the priority determination process of the control task can also be described as: sequentially comparing the production time, creation time and configuration priority of the two control tasks, and determining the priority of the control task according to the comparison result, specifically including:

[0107] If the two control tasks have different wafer delivery times, the process task with an earlier wafer delivery time among the two control tasks has a higher priority;

[0108] If the release time of the two control tasks is the same, compare the creation time of the control tasks, and the control task with the earlier creation time has a higher priority;

[0109] If the creation time of the two control tasks is the same, the configuration priorities of the two control tasks are compared, and the control task with a higher configuration priority has a higher priority.

[0110] In order to accurately determine the priority of control tasks, still refer to Figure 6 In one embodiment, if the types of the two control tasks are different, determining the priority of the control task according to the type of the control task specifically includes:

[0111] If there is a manual task in the types of the two control tasks, it is determined that the priority of the control task of the manual task type is higher than the priority of the other control task;

[0112] If the manual task does not exist in the types of the two control tasks, then when there is a highest task, determining that the priority of the control task of the highest task type is higher than the priority of the other control task;

[0113] If the manual task and the highest task do not exist in the two control tasks, then when there is a first control task whose production time is earlier than the creation time of the second control task, determining that the priority of the first control task is higher than the priority of the second control task;

[0114] If there is no situation where the output time of the first control task is earlier than the creation time of the second control task, the priority of the control task of the higher type among the two control tasks is greater than the priority of the control task of the common type.

[0115] The manual task includes a control task inserted by a user, the highest task includes a control task that interrupts other types of tasks except the manual task, and the higher task includes a control task that is inserted and executed before an unexecuted ordinary task.

[0116] Assuming that the control tasks to be compared are Cjob1 and Cjob2, first determine whether the types of the two control tasks are consistent. If they are consistent, then compare the production time, creation time and configuration priority of the control tasks of Cjob1 and Cjob2 in turn, and determine the priority of Cjob1 and Cjob2 based on the comparison result; if they are inconsistent, when there is a manual task, determine that the control task of type manual task in Cjob1 and Cjob2 has a higher priority;

[0117] If there is no manual task, then when there is a top task, it is determined that the control task of the top task type in Cjob1 and Cjob2 has a higher priority;

[0118] If there are no manual tasks and top tasks, different from the traditional priority determination method, it is determined whether there is a first control task whose release time is earlier than the creation time of the second control task between the two control tasks. If so, it is determined that the priority of the first control task is higher than the priority of the second control task. If not, it is determined that the priority of the control task with the higher type among the two control tasks is higher than the priority of the control task with the ordinary type.

[0119] In this embodiment, if the types of the two control tasks are respectively a higher task and a normal task, if the normal task has been executed, the higher task cannot interrupt the normal task that is already being executed, that is, the priority of the normal task that has been released should be higher than the priority of the higher task that has just been created. Therefore, by comparing the release time and creation time of the two control tasks, if the release time of one control task is earlier than the creation time of the other control task, the priority execution of the control task with the earlier release time is guaranteed, thereby ensuring the normal execution of the normal task that has been released. In this embodiment, the correct determination of the priority of the higher task and the normal task being executed is guaranteed through the above comparison method.

[0120] Exemplary Devices

[0121] In an exemplary embodiment of the present specification, a semiconductor process scheduling device is also provided, including: a processor and a memory; a computer program is stored in the memory, and when the processor executes the computer program, the scheduling method described in any of the above embodiments is implemented.

[0122] Accordingly, the embodiments of the present specification also provide a semiconductor process equipment, including: a semiconductor process scheduling device and a plurality of device modules;

[0123] The semiconductor process scheduling device is configured to schedule wafers to be scheduled according to the scheduling method described in any of the above embodiments.

[0124] Another embodiment of the present application further provides a computing device, see Figure 7 As shown, an exemplary embodiment of the present specification also provides a computing device, including: a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the steps of the scheduling method according to various embodiments of the present specification described in the above embodiments of the present specification are executed.

[0125] The internal structure of the computing device can be as follows Figure 7As shown, the computing device includes a processor, a memory, a network interface and an input device connected through a system bus. Among them, the processor of the computing device is used to provide computing and control capabilities. The memory of the computing device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The network interface of the computing device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, the steps of the scheduling method according to various embodiments of the present specification described in the above embodiments of the present specification are performed.

[0126] The processor may include a main processor and may also include a baseband chip, a modem, etc.

[0127] The memory stores a program for executing the technical solution of the present invention, and may also store an operating system and other key services. Specifically, the program may include a program code, and the program code includes computer operation instructions. More specifically, the memory may include a read-only memory (ROM), other types of static storage devices that can store static information and instructions, a random access memory (RAM), other types of dynamic storage devices that can store information and instructions, a disk storage, a flash, and the like.

[0128] The processor may be a general-purpose processor, such as a general-purpose central processing unit (CPU), a microprocessor, etc., or an application-specific integrated circuit (ASIC), or one or more integrated circuits for controlling the execution of the program of the scheme of the present invention. It may also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component.

[0129] The input device may include a device for receiving data and information input by a user, such as a keyboard, a mouse, a camera, a scanner, a light pen, a voice input device, a touch screen, a pedometer, or a gravity sensor.

[0130] Output devices may include means that allow information to be output to a user, such as display screens, printers, speakers, etc.

[0131] The communication interface may include using any transceiver or the like to communicate with other devices or communication networks, such as Ethernet, Radio Access Network (RAN), Wireless Local Area Network (WLAN), etc.

[0132] The processor executes the program stored in the memory and calls other devices, which can be used to implement each step of any scheduling method provided in the above embodiments of the present application.

[0133] The computing device may also include a display component and a voice component. The display component may be a liquid crystal display or an electronic ink display. The input device of the computing device may be a touch layer covered on the display component, or a button, trackball or touchpad provided on the housing of the computing device, or an external keyboard, touchpad or mouse.

[0134] Those skilled in the art will understand that Figure 7 The structure shown in the figure is only a block diagram of a part of the structure related to the scheme of this specification, and does not constitute a limitation on the computing device to which the scheme of this specification is applied. The specific computing device may include more or fewer components than shown in the figure, or combine certain components, or have a different arrangement of components.

[0135] Exemplary computer program products and storage media

[0136] In addition to the above-mentioned methods and devices, the scheduling method provided in the embodiments of this specification may also be a computer program product, which includes computer program instructions, which, when executed by a processor, enable the processor to execute the steps of the scheduling method according to various embodiments of this specification described in the above "Exemplary Method" section of this specification.

[0137] The computer program product may be written in any combination of one or more programming languages ​​to write program code for performing the operations of the embodiments of the present specification, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0138] In addition, an embodiment of the present specification also provides a computer-readable storage medium on which a computer program is stored, and the computer program is executed by a processor to execute the steps of the scheduling method according to various embodiments of the present specification described in the above "Exemplary Method" section of the present specification.

[0139] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this specification can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0140] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0141] The above-mentioned embodiments only express several implementation methods of this specification, and the descriptions are relatively specific and detailed, but they cannot be understood as limiting the scope of the solutions provided by the embodiments of this specification. It should be pointed out that for ordinary technicians in this field, several modifications and improvements can be made without departing from the concept of this specification, which all belong to the protection scope of this specification. Therefore, the protection scope of the patent of this specification shall be based on the attached claims.

Claims

1. A scheduling method, characterized in that: A controller applied to a semiconductor process equipment, wherein the semiconductor process equipment further comprises a wafer loading and unloading position, and the scheduling method comprises: Acquire a target material set, wherein the target material set includes a plurality of wafers to be scheduled; Based on the priority parameters of the wafers to be scheduled, determining the priority order of the plurality of wafers to be scheduled; Based on the priority order of the wafers to be scheduled, the wafers to be scheduled are scheduled from the corresponding wafer loading and unloading positions in sequence, and the wafer delivery time of the wafers to be scheduled with a high priority is earlier than the wafer delivery time of the wafers with a low priority.

2. The method according to claim 1, characterized in that The semiconductor process equipment further includes a target module, which is the first equipment module to which the wafer to be scheduled arrives after it is unloaded from the wafer loading and unloading position; The step of sequentially scheduling the wafers to be scheduled from corresponding wafer loading and unloading positions based on the priority order of the wafers to be scheduled specifically includes: When the target module is idle, the wafers to be scheduled are scheduled to be discharged from corresponding wafer loading and unloading positions in sequence based on the priority order of the wafers to be scheduled.

3. The method according to claim 2, characterized in that The target material set includes all wafers to be scheduled that are currently located at the wafer loading and unloading positions.

4. The method according to claim 2, characterized in that: The priority parameters include: the configuration priority of the wafer to be scheduled; The step of determining the priority order of the plurality of wafers to be scheduled based on the priority parameters of the wafers to be scheduled comprises: For the multiple wafers to be scheduled that belong to the same process task, the priority of the wafers to be scheduled is determined according to their configuration priorities, and the priority of the wafers to be scheduled with a higher configuration priority is higher than the priority of the wafers to be scheduled with a lower configuration priority.

5. The method according to claim 4, characterized in that The priority parameters also include: the wafer delivery time of the wafer to be scheduled and the creation time of the control task to which the wafer to be scheduled belongs; The step of determining the priority order of the plurality of wafers to be scheduled based on the priority parameters of the wafers to be scheduled comprises: For each wafer to be scheduled that belongs to different process tasks, compare the wafer delivery time of the wafer to be scheduled with the creation time of the control tasks to which other wafers to be scheduled belong, and determine that the priority of the wafer to be scheduled with an earlier wafer delivery time is higher than the priority of the wafer to be scheduled with a later creation time of the control tasks to which it belongs.

6. The method according to claim 5, characterized in that The priority parameter also includes: the priority of the process task to which the wafer to be scheduled belongs; and determining the priority order of the plurality of wafers to be scheduled based on the priority parameter of the wafer to be scheduled includes: For the multiple wafers to be scheduled that belong to different process tasks, and the wafer delivery time of each wafer to be scheduled is no earlier than the creation time of the control task to which other wafers to be scheduled belong, the priorities of the multiple wafers to be scheduled are determined according to the priorities of the process tasks to which they each belong, and the priority of the wafer to be scheduled that belongs to a process task with a higher priority is higher than the priority of the wafer to be scheduled that belongs to a process task with a lower priority.

7. The method according to claim 6, characterized in that The process of determining the priority of the process task includes: For process tasks belonging to the same type of control tasks, the film release time of each process task, the priority of the control task to which each process task belongs and the configuration priority are compared in turn, and the priority of each process task is determined according to the comparison result; among which, the process task with an earlier film release time has a higher priority; the process task with a higher priority of the control task to which it belongs has a higher priority; and the process task with a higher configuration priority has a higher priority.

8. The method according to claim 6 or 7, characterized in that: The process of determining the priority of the process task includes: For process tasks belonging to different control tasks, the priority of the corresponding process task is determined according to the priority of the control task to which it belongs. The higher the priority of the control task to which it belongs, the higher the priority of the process task.

9. The method according to claim 8, characterized in that The process of determining the priority of the control task includes: For control tasks of the same type, the production time, creation time and configuration priority of each control task are compared in turn, and the priority of each control task is determined based on the comparison result; among them, the control task with an earlier production time has a higher priority; the control task with an earlier creation time has a higher priority; the process task with a higher configuration priority has a higher priority.

10. The method according to claim 9, characterized in that The process of determining the priority of the control task includes: For control tasks of different types, the priorities of the control tasks are determined according to the types of the control tasks.

11. The method according to claim 10, characterized in that The types of control tasks include: manual tasks and top tasks; The determining the priority of the control task according to the type of the control task specifically includes: The priority of a control task of type manual task is higher than that of other types of control tasks; The priority of a control task of the highest task type is higher than the priority of a control task of a type that is not a manual task and the highest task; For each control task that is not a manual task or the highest task, compare the release time of the control task with the creation time of other control tasks to determine that the priority of the control task with an earlier release time is higher than the priority of the control task with a later creation time.

12. The method according to claim 11, characterized in that The types of control tasks also include: higher tasks and ordinary tasks; The determining the priority of the control task according to the type of the control task further includes: For each control task that is not a manual task or a top task, if the release time of each control task is not earlier than the creation time of other control tasks, the priority of the control task of the higher task type is higher than the priority of the control task of the ordinary task type.

13. A semiconductor process scheduling device, characterized in that: include: Processor and memory; The memory stores a computer program, and when the processor executes the computer program, the scheduling method according to any one of claims 1 to 12 is implemented.

14. A semiconductor process equipment, characterized in that: Includes semiconductor process scheduling equipment and multiple equipment modules; The semiconductor process scheduling device is configured to schedule wafers to be scheduled according to the scheduling method according to any one of claims 1 to 12.

15. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the scheduling method according to any one of claims 1 to 12 is implemented.

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