Preparation method of interconnection structure, semiconductor structure and chemical mechanical polishing equipment

Abstract

The invention provides a preparation method of an interconnection structure, a semiconductor structure and chemical mechanical polishing equipment. According to the preparation method, after a chemical mechanical polishing process is executed, a protective layer is formed on the surface of an exposed metal layer by adopting an evaporation process within a preset first time, so that oxygen isolation is realized by utilizing the protective layer. Even if waiting is overtime due to reasons in the technological process, the metal layer is protected by the protective layer, the oxidation reaction does not occur, and the performance of the device can be guaranteed. And before the diffusion barrier layer is formed, the protective layer is removed by adopting a cleaning process, so that the subsequent deposition of a thin film is not influenced, the structural characteristics of the device are not changed, and other impurities are not introduced and additional device film layer damage is not generated in the process of removing the protective layer. Moreover, the chemical mechanical polishing equipment provided by the invention is additionally provided with the evaporation chamber and the first cleaning chamber, so that not only can the preparation requirements of the preparation method of the interconnection structure be met, but also each process link is convenient to manage and control.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor preparation, and in particular to a method for preparing an interconnection structure, a semiconductor structure and chemical mechanical polishing equipment. Background Art

[0002] The back end of line (BEOL) of chip manufacturing mainly involves the preparation of multi-layer wiring and interconnection. Among them, the Damascus copper interconnection structure has become the mainstream interconnection structure due to its excellent electrical performance and compatibility with manufacturing processes. The existing preparation process of the Damascus copper interconnection structure is mainly as follows: Figure 1 As shown, a dielectric layer 101 is deposited on a substrate 100, and interconnection grooves are formed in the dielectric layer 101. Then, a copper layer 102 is electroplated on the surface of the dielectric layer 101 and in the interconnection grooves. Figure 2 As shown, a chemical mechanical polishing process (CMP) is used to remove the excess copper plating on the surface of the dielectric layer 101, and the copper layer 102 located in the interconnection groove is exposed. Since there is a long process waiting time (QTIME) after CMP is performed and before the next diffusion barrier layer is deposited, if the exposed copper layer 102 is in the air for a long time, it will be oxidized to form substances such as copper oxide 103. Therefore, the process integration engineer (PIE) needs to strictly control QTIME.

[0003] However, in the actual process, due to reasons such as stacking and machine downtime, it is easy to cause the wafer waiting time to exceed the set QTIME, which will inevitably cause the exposed copper layer 102 to undergo oxidation reaction. This will not only cause copper surface defects, but also cause changes in the resistance of the copper wire, causing the electrical parameters to shift, seriously affecting the performance of the device. In this regard, the existing technology can only solve this problem by polishing again. However, repeated polishing is not only cumbersome, but also has limited effect on the removal of substances such as copper oxide 103, which will still have an adverse effect on device performance.

[0004] Therefore, a new preparation method is urgently needed to solve the above technical problems. Summary of the invention

[0005] The object of the present invention is to provide a method for preparing an interconnect structure, a semiconductor structure and a chemical mechanical polishing device to solve the problem of how to avoid oxidation of a metal layer during the preparation of the interconnect structure.

[0006] In order to solve the above technical problems, the present invention provides a method for preparing an interconnect structure, comprising:

[0007] A substrate is provided; at least one dielectric layer is formed on the substrate, and the dielectric layer has a plurality of interconnected grooves;

[0008] forming a metal layer on the dielectric layer, wherein the metal layer fills the plurality of interconnection grooves;

[0009] Grinding the metal layer by a chemical mechanical polishing process until the surface of the dielectric layer is exposed and the surface of the remaining metal layer in the interconnection groove is exposed;

[0010] forming a protective layer on the surface of the remaining metal layer by using an evaporation process within a preset first time;

[0011] After a preset second time, removing the protective layer by a cleaning process;

[0012] A diffusion barrier layer is formed on the surfaces of the dielectric layer and the remaining metal layer.

[0013] Optionally, in the method for preparing the interconnect structure, after grinding the metal layer and before forming the protective layer, the method for preparing the interconnect structure further comprises:

[0014] The surfaces of the dielectric layer and the remaining metal layer are cleaned with a cleaning liquid to remove the grinding liquid; wherein the cleaning liquid is pre-treated by nitrogen filling.

[0015] Optionally, in the method for preparing the interconnect structure, the evaporation material used in the evaporation process includes organic matter containing benzene rings.

[0016] Optionally, in the method for preparing the interconnect structure, the evaporation process is performed in a nitrogen environment, and the process temperature of the evaporation process is less than or equal to 80°C.

[0017] Optionally, in the method for preparing the interconnect structure, the cleaning agent used in the cleaning process includes an organic composition; and,

[0018] The cleaning process is performed in an inert gas environment; and during the cleaning process, the temperature of the inert gas is lower than the evaporation temperature of the organic composition; when the cleaning process is completed, the temperature of the inert gas rises to the evaporation temperature of the organic composition or higher than the evaporation temperature within a preset third time.

[0019] Optionally, in the method for preparing the interconnect structure, the organic composition includes: acetone, ethanol and isopropanol; and acetone:ethanol:isopropanol=3:1:1; and the inert gas includes argon.

[0020] Optionally, in the method for preparing the interconnect structure, the material of the metal layer includes copper, and the metal layer is formed by an electroplating process.

[0021] Based on the same inventive concept, the present invention further provides a semiconductor structure, including an interconnect structure prepared by the interconnect structure preparation method.

[0022] Based on the same inventive concept, the present invention also provides a chemical mechanical polishing device, comprising at least a polishing chamber, a vapor deposition chamber and a first cleaning chamber;

[0023] The grinding chamber is used to perform a chemical mechanical grinding process to grind the metal layer until the surface of the dielectric layer is exposed, and the surface of the remaining metal layer located in the interconnection groove is exposed; wherein the dielectric layer has a plurality of the interconnection grooves, and the metal layer before grinding covers the surface of the dielectric layer and fills the plurality of interconnection grooves in the dielectric layer;

[0024] The evaporation chamber is used to perform an evaporation process to form a protective layer by evaporation on the surface of the metal layer remaining after grinding;

[0025] The first cleaning chamber is used to perform a cleaning process to remove the protection layer.

[0026] Optionally, in the chemical mechanical polishing equipment, the chemical mechanical polishing equipment further comprises a second cleaning chamber; the second cleaning chamber is used to clean the surface of the ground dielectric layer and the remaining metal layer after grinding the metal layer and before forming the protective layer to remove the grinding liquid; and

[0027] The first cleaning chamber and the second cleaning chamber both have a temperature control module and an inert gas supply module, which are used to adjust the chamber temperature and supply inert gas, respectively.

[0028] In summary, the present invention provides a method for preparing an interconnect structure, a semiconductor structure and a chemical mechanical polishing device. Compared with the prior art, the method for preparing the interconnect structure uses a vapor deposition process to form a protective layer on the surface of the exposed metal layer within a preset first time after performing the chemical mechanical polishing process, so as to use the protective layer to isolate oxygen in the air. Even if the waiting timeout occurs due to some reason during the process, the metal layer will not undergo an oxidation reaction under the protection of the protective layer, which is conducive to ensuring the better electrical performance of the device. And after the preset second time, the protective layer can be removed by a cleaning process to form the diffusion barrier layer, which not only does not affect the subsequent deposition of the thin film, but also does not change the device structure characteristics, and in the process of removing the protective layer, no other impurities are introduced, and no additional device film layer damage is generated. And, the chemical mechanical polishing device provided by the present invention is provided with an evaporation chamber and a first cleaning chamber, which can not only meet the preparation requirements of the method for preparing the interconnect structure, but also facilitate the control of each process link. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Those skilled in the art will appreciate that the drawings are provided for a better understanding of the present invention, but do not constitute any limitation on the scope of the present invention.

[0030] Figure 1 It is a schematic diagram of the structure of forming a copper layer in an interconnection trench in the prior art.

[0031] Figure 2 It is a schematic diagram of the structure in which the surface of a copper layer is oxidized to form copper oxide in the prior art.

[0032] Figure 3 Detailed description of the invention The figure is a flow chart of a method for preparing an interconnection structure in an embodiment of the present invention.

[0033] Figure 4 It is a schematic diagram of a semiconductor structure in which interconnection trenches are formed in a dielectric layer according to an embodiment of the present invention.

[0034] Figure 5 It is a schematic diagram of a semiconductor structure in which a metal layer fills and covers an interconnection trench in an embodiment of the present invention.

[0035] Figure 6 It is a schematic diagram of a semiconductor structure in which a portion of a metal layer is ground away in an embodiment of the present invention.

[0036] Figure 7 It is a schematic diagram of a semiconductor structure in which a protective layer is formed on the surface of a metal layer in an embodiment of the present invention.

[0037] Figure 8 Schematic diagram of a semiconductor structure in which a diffusion barrier layer is formed in an embodiment of the present invention.

[0038] Fig. 9It is a schematic diagram of a metal interconnect structure forming multiple metal layers in an embodiment of the present invention.

[0039] Fig.10 Schematic diagram of the structure of the chemical mechanical polishing equipment in an embodiment of the present invention.

[0040] And, in the attached drawings:

[0041] 100-substrate; 101-deposited dielectric layer; 102-copper layer; 103-copper oxide;

[0042] 200-substrate; 201-interlayer dielectric layer; 202-dielectric layer; 203-barrier layer; 204-metal layer; 205-protective layer; 206-diffusion barrier layer;

[0043] 300-grinding chamber; 301-second cleaning chamber; 302-evaporation chamber; 303-first cleaning chamber;

[0044] C-metal contact hole; T-interconnect trench. DETAILED DESCRIPTION

[0045] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different proportions are used. It should also be understood that, unless otherwise specified or indicated, the terms "first", "second", "third", etc. in the specification are only used to distinguish between the various components, elements, steps, etc. in the specification, and are not used to represent the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0046] See also Figure 3 This embodiment provides a method for preparing an interconnect structure, comprising:

[0047] Step 1 S10: providing a substrate; at least one dielectric layer is formed on the substrate, and the dielectric layer has a plurality of interconnected grooves;

[0048] Step 2 S20: forming a metal layer on the dielectric layer, and the metal layer fills the plurality of interconnection grooves;

[0049] Step three S30: grinding the metal layer using a chemical mechanical polishing process until the surface of the dielectric layer is exposed and the surface of the remaining metal layer in the interconnection groove is exposed;

[0050] Step 4 S40: forming a protective layer on the surface of the remaining metal layer by using an evaporation process within a preset first time;

[0051] Step 5 S50: removing the protective layer by a cleaning process after a preset second time;

[0052] Step six S60: forming a diffusion barrier layer on the surfaces of the dielectric layer and the remaining metal layer.

[0053] Based on this, the preparation method of the interconnect structure provided in this embodiment, after performing the chemical mechanical polishing process, uses an evaporation process to form a protective layer on the surface of the exposed metal layer within a preset first time, so as to use the protective layer to isolate oxygen in the air. The preset first time can be the necessary time for the wafer to be transported between various devices, so as to form a protective layer on the surface of the wafer as quickly as possible. Even if the waiting timeout occurs for some reason during the process, that is, after the preset second time, the metal layer will not undergo an oxidation reaction under the protection of the protective layer, which is beneficial to ensure better electrical performance of the device. And before forming the diffusion barrier layer, the preparation method uses a cleaning process to remove the protective layer, which does not affect the subsequent deposition of the thin film and does not change the structural characteristics of the device.

[0054] The following is combined with Figures 3 to 10 The preparation method of the interconnection structure provided in this embodiment is specifically described.

[0055] Step 1 S10: Please refer to Figure 4 , a substrate 200 is provided; at least one dielectric layer 202 is formed on the substrate 200; and the dielectric layer 202 has a plurality of interconnection trenches T.

[0056] It should be noted that the interconnection structure is generally prepared in BEOL, and the interconnection structure will be prepared above the device layer. Therefore, before executing step 1 S10, a substrate 200 needs to be provided, and the substrate 200 includes a stacked substrate and a device layer. The substrate can be selected according to the actual needs of the device, for example: a silicon substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, an SOI (Silicon-on-insulator) substrate or a GOI (Germanium-on-Insulator) substrate, etc. The device layer includes various functional devices, such as CMOS transistors, etc. And, to achieve electrical connection between the interconnection structure and the device layer. An interlayer dielectric layer 201 is also formed between the interconnection structure and the device layer, and a plurality of metal contact holes C are provided in the interlayer dielectric layer 201, which are generally filled with metal tungsten to be able to connect with the metal layer in the interconnection structure.

[0057] Based on this, the dielectric layer 202 can be formed on the interlayer dielectric layer 201, and a plurality of interconnection trenches T are formed in the dielectric layer 202 through an etching process. The interconnection trenches T penetrate the dielectric layer 202 and can be connected to the metal contact holes C. The material of the dielectric layer 202 is generally a low dielectric material, and can be silicon oxide doped with boron or carbon. In addition, the dielectric layer 202 can be a single-layer film structure or a multi-layer superimposed film structure, and the materials of each film structure can be the same or different.

[0058] Preferably, a barrier layer 203 is formed on the sidewall of the interconnection trench T and the surface of the dielectric layer 202 to prevent the metal from migrating or diffusing into the dielectric layer 202. The material of the barrier layer 203 includes but is not limited to: Ta, TaN or a stack of Ta and TaN, and may also include other metals and metal nitrides.

[0059] Step 2 S20: Please refer to Figure 5 , a metal layer 204 is formed on the dielectric layer 202 , and the metal layer 204 fills the plurality of interconnection trenches T.

[0060] Preferably, the metal layer 204 is formed by electrochemical plating (ECP). When the barrier layer 203 is formed on the dielectric layer 202, the metal layer 204 is located on the surface of the barrier layer 203 and fills and covers each of the interconnection trenches T. The material of the metal layer 204 includes but is not limited to copper.

[0061] Step 3 S30: Please refer to Figure 6 The metal layer 204 is polished by a chemical mechanical polishing process until the surface of the dielectric layer 202 and the remaining surface of the metal layer 204 in the interconnection trench T are exposed.

[0062] Since the metal wires in the interconnect structure are composed of metal materials located in each of the interconnect trenches T, it is necessary to grind away the excess copper plating on the surface of the dielectric layer 202, leaving only a portion of the metal layer 204 located in each of the interconnect trenches T. Figure 5 As shown, in the semiconductor structure after grinding, the remaining metal layer 204 is located in each of the interconnection trenches T, and its surface is flush with the barrier layer 203 .

[0063] Preferably, after grinding away the redundant portion of the metal layer 204 and before performing the step 4 (S40), the method for preparing the interconnect structure further includes: using a cleaning liquid to clean the surface of the dielectric layer 202 and the remaining metal layer 204 to remove the grinding liquid. In other words, the surface of the ground semiconductor structure is cleaned with a cleaning liquid to remove residues such as the grinding liquid.

[0064] Preferably, the cleaning liquid is pure water, and the pure water is pre-treated by nitrogen filling. It should be noted that the cleaning liquid contains a large amount of dissolved oxygen, which is easy to react with the exposed surface of the metal layer 204 to cause an oxidation reaction, affecting the electrical properties of the metal layer 204. Therefore, nitrogen is introduced into the cleaning liquid in advance to replace the dissolved oxygen in the water with nitrogen, which can effectively reduce the dissolved oxygen content in the cleaning liquid, thereby avoiding oxidation reaction on the surface of the metal layer 204 exposed during the cleaning process, and ensuring that the device has better performance.

[0065] Step 4 S40: Please refer to Figure 7 , a protective layer 205 is formed on the surface of the remaining metal layer 204 by using an evaporation process within a preset first time.

[0066] Since there is a certain process waiting time after CMP is performed and before the diffusion barrier layer is deposited, in order to avoid oxidation due to the surface of the metal layer 204 being exposed to the air for too long, the preparation method provided in this embodiment will place the semiconductor structure in the evaporation chamber within a preset first time after the grinding is completed, and use the evaporation process to quickly form a protective layer 205 on the exposed surface of the metal layer, so as to reduce the exposure time of the surface of the metal layer 204 as much as possible, thereby avoiding oxidation reaction. Among them, the preset first time can be the necessary time for the wafer to be transported between various devices, so as to form the protective layer 205 on the surface of the metal layer 204 as quickly as possible.

[0067] It is understandable that the evaporation process has the advantage of high film forming efficiency, can quickly form the dense protection layer 205, and use the protection layer 205 to effectively block the metal layer 204 from contacting oxygen in the air, thereby avoiding the occurrence of oxidation reaction and protecting the electrical properties of the metal layer 204. Therefore, no matter how long the waiting timeout is caused by some reason in the process, the metal layer 204 will not undergo oxidation reaction under the protection of the protection layer 205, which is conducive to ensuring better electrical performance of the device.

[0068] Preferably, the evaporation process is performed at a process temperature of less than or equal to 80° C., and the evaporation material used in the evaporation process includes an organic substance containing a benzene ring, which spontaneously forms a protective layer 205 on the surface of the metal layer 204. Furthermore, in order to prevent the metal from undergoing an oxidation reaction with oxygen in the air at high temperature, nitrogen needs to be introduced into the vacuum evaporation chamber during the evaporation process to prevent oxidation of the metal layer 204.

[0069] Step 5 S50: Please refer to Figure 7 After a preset second time, a cleaning process is used to remove the protective layer 205.

[0070] In this embodiment, the preset second time refers to the time when the wafer is placed outside waiting for the next process. And under the protection of the protective layer 205, even if the preset second time is exceeded for some reason, the metal layer 204 will be oxidized, effectively ensuring its electrical properties. When it is necessary to form a diffusion barrier layer on the surface of the metal layer 204, that is, after the preset second time, a cleaning process can be used to clean and remove the protective layer 205. Preferably, the cleaning agent used in the cleaning process includes an organic composition. For example, the organic composition includes: acetone, ethanol and isopropanol; preferably, the combination ratio of organic matter is acetone: ethanol: isopropanol = 3:1:1, to form a non-polar solvent, which has the advantages of efficient cleaning, environmental protection and non-corrosive to metals.

[0071] Furthermore, in order to avoid oxidation reaction between air and the exposed metal layer 204 during the cleaning process, an inert gas is introduced into the chamber during the cleaning process, and the cleaning process is performed in an inert gas atmosphere. Optionally, the inert gas is argon. Also, during the cleaning process, the temperature of the inert gas is lower than the evaporation temperature of the organic composition; when the cleaning process is completed, the temperature of the inert gas rises to the evaporation temperature of the organic composition or is higher than the evaporation temperature within a preset third time. Among them, the preset third time referred to in this embodiment is a relatively short period of time, which is not specifically limited in this embodiment, and is used to control the organic composition to evaporate quickly in a short time to avoid residue.

[0072] It is understandable that during the cleaning process, if the atmosphere temperature is lower than the evaporation temperature of the organic composition, the organic composition can be fully dissolved and remove the protective layer 205. After the cleaning is completed, if there are still organic composition residues on the surface of the semiconductor structure, the atmosphere temperature is immediately raised to the evaporation temperature of the organic composition or higher than the evaporation temperature, and the organic composition remaining on the surface of the metal layer 204 and the barrier layer 203 can be quickly removed by high-temperature volatilization without introducing other cleaning processes, thereby ensuring that the surface of the semiconductor structure is clean, streamlining the process flow, improving process efficiency, and not causing additional damage to the wafer surface.

[0073] Exemplarily, the organic composition includes acetone, ethanol and isopropanol, and since alcohols and ethers have low boiling points and are volatile, the boiling point of acetone is 56.1°C and the boiling point of ethanol is 78.3°C; therefore, after cleaning is completed, the temperature of the inert gas is raised to 110°C to evaporate the acetone and ethanol on the surface of the semiconductor structure.

[0074] Step 6 S60: Please refer to Figure 8 A diffusion barrier layer 206 is formed on the surfaces of the dielectric layer 202 and the remaining metal layer 204 .

[0075] Preferably, a plasma enhanced chemical vapor deposition process is used to form a diffusion barrier layer 206 on the surface of the dielectric layer 202 and the remaining metal layer 204. The material of the diffusion barrier layer 206 includes but is not limited to silicon carbide (Nitride Doped Silicon Carbide, NDC), and its function is to prevent the metal material in the metal layer 204 from diffusing into the dielectric layer 202, thereby improving the reliability of the interconnection structure.

[0076] Further, such as Fig. 9 As shown, in order to meet the interconnection requirements of different types of devices, the process of step 1 S10 to step 6 S60 may be repeated on the diffusion barrier layer 206 to form a more complex interconnection structure.

[0077] Based on the same concept, this embodiment also provides a semiconductor structure, including an interconnect structure prepared by the above-mentioned method for preparing the interconnect structure.

[0078] Based on the same concept, this embodiment also provides a chemical mechanical polishing device for performing the polishing process, cleaning process and evaporation process in the above-mentioned method for preparing the interconnect structure.

[0079] See also Figures 4 to 10The chemical mechanical polishing equipment at least includes a polishing chamber 300, an evaporation chamber 302 and a first cleaning chamber 303. The polishing chamber 300 is used to perform the chemical mechanical polishing process to polish the metal layer 204 until the surface of the dielectric layer 202 is exposed, and the surface of the remaining metal layer 204 in the interconnection groove T is exposed. The dielectric layer 202 has a plurality of interconnection grooves T, and the metal layer 204 before polishing covers the surface of the dielectric layer 202 and fills the plurality of interconnection grooves T in the dielectric layer 202. The evaporation chamber 302 is used to perform the evaporation process to form a protective layer 205 by evaporation on the surface of the remaining metal layer 204 after polishing. The first cleaning chamber 303 is used to perform the cleaning process to remove the protective layer 205. And, the chemical mechanical polishing equipment also includes a second cleaning chamber 301. The second cleaning chamber 301 is used to clean the surfaces of the ground dielectric layer 202 and the remaining metal layer 204 to remove the grinding liquid after grinding the metal layer 204 and before forming the protective layer 205. Preferably, the cleaning liquid is pre-treated by nitrogen filling.

[0080] Furthermore, because the evaporation chamber 302 requires a specific temperature during use, and in order to ensure the smooth progress of the evaporation process, some inert gas needs to be added, so a temperature control module and an inert gas supply module are provided in the first cleaning chamber 303, which are used to adjust the temperature of the chamber and supply inert gas, respectively. Among them, the temperature control module can adjust the temperature in the chamber when cleaning and removing the protective layer 205, for example, adjusting the temperature in the chamber to be lower than the evaporation temperature of the organic composition to ensure that the organic composition can be fully dissolved and remove the protective layer 205. And after the cleaning is completed, the temperature control module continues to provide temperature control, and includes controlling the time node and the speed of temperature rise. For example, the temperature is controlled to rise to the evaporation temperature of the organic composition or greater than the evaporation temperature within a preset third time, and then high temperature volatilization is used to quickly remove the organic composition remaining on the surface of the metal layer 204 and the barrier layer 203, eliminating other cleaning steps. And, the temperature control module and the inert gas supply module are also provided in the second cleaning chamber 301 to optimize the cleaning effect.

[0081] In summary, the present embodiment provides a method for preparing an interconnect structure, a semiconductor structure and a chemical mechanical polishing device. Among them, after performing the chemical mechanical polishing process, the preparation method of the interconnect structure uses a cleaning liquid to remove residues such as the polishing liquid, and the cleaning liquid is pre-treated with nitrogen gas, which can effectively prevent the dissolved oxygen in the cleaning liquid from reacting with the metal layer 204. In addition, after cleaning, a protective layer 205 is formed on the surface of the exposed metal layer 204 by an evaporation process within a preset first time, so as to utilize the protective layer 205 to isolate oxygen in the air. Even if the waiting timeout occurs due to some reason during the process, the metal layer 204 will not undergo an oxidation reaction under the protection of the protective layer 205, which is beneficial to ensure better electrical performance of the device. And after the preset second time, in order to form the diffusion barrier layer 206, a cleaning process can be used to clean and remove the protective layer 205, and by increasing the atmosphere temperature to the evaporation temperature of the cleaning agent or greater than the evaporation temperature when the cleaning is completed, the cleaning agent attached to the surface of the semiconductor structure can be volatilized simultaneously, without introducing other cleaning links, which is conducive to streamlining the process flow and improving process efficiency, and does not introduce other impurities, and does not cause additional device film layer damage. Based on the same concept, the chemical mechanical polishing equipment provided in this embodiment is additionally provided with an evaporation chamber 302 and a first cleaning chamber 303, which can not only meet the preparation requirements of the preparation method of the interconnect structure, but also facilitate the control of each process link.

[0082] In addition, it should be recognized that although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiment according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still belongs to the scope of protection of the technical solution of the present invention.

Claims

1. A method for preparing an interconnect structure, characterized in that: include: providing a substrate; At least one dielectric layer is formed on the substrate, and the dielectric layer has a plurality of interconnected grooves; forming a metal layer on the dielectric layer, wherein the metal layer fills the plurality of interconnection grooves; Grinding the metal layer by a chemical mechanical polishing process until the surface of the dielectric layer is exposed and the surface of the remaining metal layer in the interconnection groove is exposed; forming a protective layer on the surface of the remaining metal layer by using an evaporation process within a preset first time; After a preset second time, removing the protective layer by a cleaning process; A diffusion barrier layer is formed on the surfaces of the dielectric layer and the remaining metal layer.

2. The method for preparing an interconnection structure according to claim 1, characterized in that: After grinding the metal layer and before forming the protective layer, the method for preparing the interconnect structure further includes: The surfaces of the dielectric layer and the remaining metal layer are cleaned with a cleaning liquid to remove the grinding liquid; wherein the cleaning liquid is pre-treated by nitrogen filling.

3. The method for preparing an interconnection structure according to claim 1, characterized in that: The evaporation material used in the evaporation process includes organic matter containing benzene rings.

4. The method for preparing an interconnection structure according to claim 3, characterized in that: The evaporation process is performed in a nitrogen environment, and a process temperature of the evaporation process is less than or equal to 80° C.

5. The method for preparing an interconnection structure according to claim 1 or 3, characterized in that: The cleaning agent used in the cleaning process includes an organic composition; and, The cleaning process is performed in an inert gas environment; and during the cleaning process, the temperature of the inert gas is lower than the evaporation temperature of the organic composition; when the cleaning process is completed, the temperature of the inert gas rises to the evaporation temperature of the organic composition or higher than the evaporation temperature within a preset third time.

6. The method for preparing an interconnection structure according to claim 5, characterized in that: The organic composition includes: acetone, ethanol and isopropanol; and the ratio of acetone:ethanol:isopropanol=3:1:1; and the inert gas includes argon.

7. The method for preparing an interconnection structure according to claim 1, characterized in that: The material of the metal layer includes copper, and the metal layer is formed by an electroplating process.

8. A semiconductor structure, characterized in that: The invention comprises an interconnection structure prepared by the method for preparing an interconnection structure as claimed in any one of claims 1 to 7.

9. A chemical mechanical polishing device, characterized in that: At least comprising a grinding chamber, an evaporation chamber and a first cleaning chamber; The grinding chamber is used to perform a chemical mechanical grinding process to grind the metal layer until the surface of the dielectric layer is exposed, and the surface of the remaining metal layer located in the interconnection groove is exposed; wherein the dielectric layer has a plurality of the interconnection grooves, and the metal layer before grinding covers the surface of the dielectric layer and fills the plurality of interconnection grooves in the dielectric layer; The evaporation chamber is used to perform an evaporation process to form a protective layer by evaporation on the surface of the metal layer remaining after grinding; The first cleaning chamber is used to perform a cleaning process to remove the protection layer.

10. The chemical mechanical polishing equipment according to claim 9, characterized in that: The chemical mechanical polishing equipment further includes a second cleaning chamber; the second cleaning chamber is used to clean the surfaces of the polished dielectric layer and the remaining metal layer after polishing the metal layer and before forming the protective layer to remove the polishing liquid; as well as, The first cleaning chamber and the second cleaning chamber both have a temperature control module and an inert gas supply module, which are used to adjust the chamber temperature and supply inert gas, respectively.

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