Microelectronic assembly including interconnects employing different solder materials

Abstract

Microelectronic assemblies, related devices and methods are disclosed herein. In some embodiments, a microelectronic component may include: a first die in a first layer having a first surface and an opposing second surface; a redistribution layer (RDL) on the first layer, where the RDL includes a conductive via having a larger width toward a first surface of the RDL and a smaller width toward an opposite second surface of the RDL; wherein the first surface of the RDL is electrically coupled to the second surface of the first die through a first solder interconnect having a first solder; and a second die in a second layer on the RDL, where the second die is electrically coupled to the RDL by a second solder interconnect having a second solder, where the second solder is different from the first solder.

Description

[0001] This application is a divisional application. The original application is a patent application submitted to the China Patent Office on November 21, 2022, with application number 202211545075.9, and the name of the invention is "Microelectronic components including interconnections using different solder materials." Background Art

[0002] Integrated circuit (IC) devices (e.g., dies) are often coupled together in a multi-die IC package to integrate features or functions and facilitate connections to other components (e.g., a package substrate). In conventional packages, the dies can be coupled together by solder. Such packages are limited in the density of interconnections that can be achieved by solder interconnections between dies. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Each embodiment can be easily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, similar reference numerals represent similar structural elements. The embodiments are shown in the drawings by way of example and not by way of limitation.

[0004] Figure 1 is a side cross-sectional view of an exemplary microelectronic assembly according to various embodiments.

[0005] Figure 2A-2N According to various embodiments, Figure 1 Side cross-sectional views of various stages in an exemplary process of microelectronic assembly.

[0006] Figure 3 is a flow chart of an exemplary method of making an exemplary microelectronic assembly according to various embodiments.

[0007] Figure 4 is a top view of a wafer and die that may be incorporated into a microelectronic assembly according to any of the embodiments disclosed herein.

[0008] Figure 5 is a side cross-sectional view of an IC device that can be incorporated into a microelectronic assembly according to any of the embodiments disclosed herein.

[0009] Figure 6 is a side cross-sectional view of an IC device assembly that may include a microelectronic assembly according to any of the embodiments disclosed herein.

[0010] Figure 7 is a block diagram of an exemplary electrical device that may include a microelectronic assembly according to any of the embodiments disclosed herein. DETAILED DESCRIPTION

[0011] Microelectronic assemblies, related devices, and methods are disclosed herein. For example, in some embodiments, a microelectronic assembly may include: a first die in a first layer having a first surface and an opposite second surface; a redistribution layer (RDL) on the first layer, wherein the RDL includes a conductive via having a larger width toward the first surface of the RDL and a smaller width toward the opposite second surface of the RDL; wherein the first surface of the RDL is electrically coupled to the second surface of the first die through a first solder interconnect having a first solder; and a second die in a second layer on the RDL, wherein the second die is electrically coupled to the RDL through a second solder interconnect having a second solder, wherein the second solder is different from the first solder.

[0012] Transmitting a large number of signals between two or more dies in a multi-die IC package is challenging due to the decreasing size of such dies and the increasing use of stacked die arrangements. Conventional solutions for achieving small form factor, high performance and high density interconnection in multi-die IC packages include die partitioning and / or the use of small silicon dies without the use of through silicon vias (TSVs) for die-to-die interconnection. Some of these conventional solutions require additional assembly operations and dedicated manufacturing equipment, which increases cost and manufacturing complexity and reduces die yield. Another current solution includes embedding bridge dies with TSVs or active functional dies for fine interconnection (e.g., die tiling) between multiple dies, however, this solution suffers from highly cumulative bump thickness variation (BTV), which increases with the number of bridges to be embedded and results in increased manufacturing costs and decreased yield. The microelectronic structures and assemblies disclosed herein can achieve interconnect densities as high or higher than conventional solutions without the overhead of conventional high-cost manufacturing operations and with improved yields, for example, by reducing the risk of die shifting during reconfiguration to prevent significant actual position errors, patterning interconnects directly on low total thickness variation (TTV) glass carriers and achieving lower BTV, incorporating sacrificial films with low elastic modulus to maintain low BTV, and eliminating the need for top-side passivation that requires strict design rules. In addition, the microelectronic structures and assemblies disclosed herein provide new flexibility for electronic device designers and manufacturers, allowing them to achieve their device goals without having to face excessive cost or manufacturing complexity.

[0013] In the detailed description below, reference will be made to the accompanying drawings which form part thereof, in which similar parts are always indicated by similar reference numerals, and in which embodiments that can be practiced are shown by way of example. It should be understood that other embodiments may be employed and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the detailed description below should not be understood in a limiting sense.

[0014] Various operations may be described as multiple discrete actions or operations in sequence in a manner that is most helpful in understanding the claimed subject matter. However, the description order should not be inferred to imply that these operations are necessarily sequence-dependent. Specifically, these operations may not be performed in the order of introduction. The described operations may be performed in an order different from the described embodiments. In other embodiments, various additional operations may be performed and / or the described operations may be omitted.

[0015] For purposes of this disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For purposes of this disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C). The figures are not necessarily drawn to scale. Although many of the figures show rectilinear structures with straight walls and right-angle corners, this is only for simplicity of illustration, and actual devices made using these techniques may exhibit rounded corners, surface roughness, and other features.

[0016] The description uses the phrases "in an embodiment" or "in various embodiments," each of which may refer to one or more of the same embodiment or different embodiments. In addition, the words "including," "comprising," "having," and the like used in connection with the embodiments of the present disclosure are synonymous. As used herein, "package" and "IC package" are synonymous, as are "die" and "IC die." The words "top" and "bottom" may be used herein to explain various features of the accompanying drawings, but these words are intended for ease of discussion only and do not imply an intended or desired orientation. As used herein, the word "insulation" means "electrical insulation" unless otherwise specified. Throughout the specification and claims, the word "coupled" means a direct or indirect connection, for example, a direct electrical, mechanical, or magnetic connection between the things being connected or an indirect connection through one or more passive or active intermediate devices. The meaning of the singular article includes the plural referenced objects. The meaning of "in..." includes "in..." and "on...". Unless otherwise indicated, the use of ordinal adjectives such as "first", "second", "third", etc. to describe common objects simply indicates that different instances of similar objects are being referenced, and does not imply that the objects described must be in a certain temporal or spatial order in an arranged manner or in any other way.

[0017] When used to describe a range of dimensions, the phrase "between X and Y" means a range that includes X and Y. For convenience, the term "Figure 2" may be used to indicate Figure 2A-2N Although certain elements may be referred to in the singular herein, such elements may include multiple sub-elements. For example, "insulating material" may include one or more insulating materials.

[0018] Figure 1 is a side cross-sectional view of an exemplary microelectronic assembly according to various embodiments. The microelectronic assembly 100 may include a multi-layer die subassembly 104 having a first layer die 114-1 coupled via a first solder interconnect 130 having a first solder material 132 and a second layer die 114-2 electrically coupled via a second solder interconnect 140 having a second solder material 136. As used herein, the term "multi-layer die subassembly" 104 may refer to a composite die having two or more stacked dielectric layers together with one or more die within each layer, and conductive interconnects and / or conductive paths connecting the one or more die (including die in non-adjacent layers). As used herein, the terms "multi-layer die subassembly" and "composite die" may be used interchangeably. Figure 1As shown in , the multi-layer die subassembly 104 may include a first redistribution layer (RDL) 148-1, a passivation layer 149, a first layer 104-1 including a die 114-1 having a TSV 117 and a conductive pillar 152, a second layer 104-2 having a die 114-2 and a die 114-3, and a second RDL 148-2 located between the first layer 104-1 and the second layer 104-2, wherein the die 114-1 is electrically coupled to the second RDL 148-2 through a first solder interconnect 130, and the dies 114-2, 114-3 are electrically coupled to the second RDL 148-2 through a second solder interconnect 140. As used herein, the terms "second solder interconnect 140" and "first level interconnect (FLI)" may be used interchangeably. The multi-layer die subassembly 104 may include a first surface 170-1 and an opposite second surface 170-2. Specifically, the die 114-1 may include a bottom surface (e.g., a surface facing the first surface 170-1) having a first conductive contact 122 and an opposite top surface (e.g., a surface facing the second surface 170-2) having a second conductive contact 124. In some embodiments, the first conductive contact 122 and the second conductive contact 124 may be surrounded by (e.g., embedded in) a molding material 123. The die 114-2, 114-3 may include a conductive contact 122 located on the bottom surface of the die (e.g., a surface facing the first surface 170-1). The first RDL 148-1 and the second RDL 148-2 may include conductive paths (e.g., conductive vias 194 and conductive lines 196) passing through a dielectric material. The vias 194 in the first RDL 148-1 and the second RDL 148-2 may have an inverted tapered shape because the vias 194 are formed to have a larger width (e.g., y-direction or y-axis) at the bottom surface (e.g., a surface closer to the first surface 170-1) and a smaller width at the top surface (e.g., a surface closer to the second surface 170-2). The first RDL 148-1 and the second RDL 148-2 may include a first conductive contact 172 on the bottom surface and a second conductive contact 174 on the top surface.

[0019] As used herein, "conductive contact" may refer to a portion of a conductive material (e.g., metal) that acts as an electrical interface between different components (e.g., portions of a conductive interconnect); the conductive contact may be recessed into the surface of a component, flush with the surface of a component, or extend from the surface of a component, and may take any appropriate form (e.g., portions of a conductive pad or slot or conductive line or via). In a general sense, "interconnect" refers to any element that provides a physical connection between two other elements. For example, an electrical interconnect provides an electrical connection between two electrical components, thereby facilitating the communication of electrical signals between them; an optical interconnect provides an optical connection between two optical components, thereby facilitating the communication of optical signals between them. As used herein, both electrical interconnects and optical interconnects are included in the term "interconnect". The nature of the interconnect described herein should be understood with reference to the signal medium associated with the interconnect. Thus, when used with reference to an electronic device (e.g., an IC that operates with electrical signals), the term "interconnect" describes any element formed of a conductive material for providing an electrical connection to one or more components associated with the IC or / and between various such components. In such cases, the word "interconnect" can refer to both conductive traces (sometimes referred to as "metal traces", "wires", "metal wires", "conductors", "metal conductors", "trench" or "metal trenches") and conductive vias (sometimes referred to as "vias" or "metal vias"). Sometimes, conductive traces and vias may be referred to as "conductive traces" and "conductive vias", respectively, thereby emphasizing the fact that these elements include conductive materials (e.g., metals). Similarly, when used with reference to devices that also operate optical signals (e.g., photonic ICs (PICs)), "interconnect" can also describe any element formed of optically conductive materials for providing optical connections to one or more elements associated with the PIC. In such cases, the word "interconnect" can refer to optical waveguides (e.g., structures that guide and confine light waves), including optical fibers, splitters, optical combiners, optical couplers, and optical vias.

[0020] For example, any of the conductive contacts disclosed herein (e.g., conductive contacts 122, 124, 146, 172, and / or 174) may include, for example, a bonding pad, a solder bump, a conductive post, or any other suitable conductive contact. Figure 1As shown in , die 114-1 is shown as having conductive contacts 124 extending from the surface of the die, and may be more preferably referred to herein as a "bumped die" or "micro-bumped die". Dies 114-2 and 114-3 are shown as having conductive contacts 122 flush with the die, and may be referred to herein as "bumpless dies". Die 114-1 further includes a molding material 123 surrounding the first conductive contact 122 and the second conductive contact 124. In some embodiments, die 114-1 may include a passivation layer (not shown) located at the top and / or bottom surface of die 114-1 between die 114-1 and molding material 123, for example, a material including silicon and nitrogen (e.g., in the form of silicon nitride). Die 114 may include other conductive pathways (e.g., including lines and vias) and / or other circuit systems (not shown) coupled to corresponding conductive contacts (e.g., conductive contacts 122, 124) on the surface of die 114.

[0021] The first solder interconnect 130 may include the conductive contact 124 on the top surface of the die 114-1, solder 132, and the conductive contact 172 on the bottom surface of the second RDL 148-1. The first solder interconnect 130 disclosed herein may take any suitable form.

[0022] The first solder interconnect 130 may have a finer pitch than or the same pitch as the second solder interconnect 140 in the microelectronic assembly. The solder interconnect 130 may have a finer pitch than the die-to-package substrate (DTPS) interconnect 150 in the microelectronic assembly. As used herein, the pitch is measured from center to center (e.g., from the center of the conductive contact to the center of the adjacent conductive contact, or from the center of the conductive column to the center of the adjacent conductive column). In some embodiments, the solder interconnect 130 may include a small conductive bump (e.g., a copper bump) attached to the conductive contact 124 by solder 132. In some embodiments, the solder interconnect 130 disclosed herein may have a pitch between 1 micron and 100 microns. In some embodiments, the diameter of the solder 132 is equal to about half of the minimum pitch. The solder interconnect 130 may have a pitch that is too fine to be directly coupled to the package substrate 102 (e.g., too fine to act as a DTPS interconnect 150). In some embodiments, the solder interconnect 130 may be used as a data transmission channel, while the DTPS interconnect 150 may be used for power and ground lines and others. In some embodiments, the first solder interconnect 130 in the microelectronic assembly 100 may include a solder 132 that is a no remelt solder, a low temperature solder, or a conventional solder. As used herein, a "no remelt solder" includes a solder having a melting point of more than 400 degrees Celsius. For example, the no remelt solder may include a copper and tin alloy solder paste, wherein during reflow, the tin alloy particles melt and react with the copper alloy particles to form an intermetallic compound (IMC), for example, a Cu-Cu-Mg ... 3 Sn in the form of IMC. The non-remelting solder interconnect can be formed at a lower temperature (e.g., a temperature of 241 degrees Celsius to melt the tin alloy particles), and once the non-remelting solder interconnect with IMC is formed, the melting point temperature of the non-remelting solder is raised to above 400 degrees Celsius. As used herein, a "lower temperature" solder includes a solder having a melting point below 241 degrees Celsius. In some embodiments, the lower temperature solder may include tin and bismuth (eutectic tin-bismuth) or tin, silver and bismuth. In some embodiments, the lower temperature solder may include indium, indium and tin, or gallium. "Conventional solder" includes a solder having a melting point equal to 241 degrees Celsius and may include tin.

[0023] The second solder interconnect 140 may include a conductive contact 174, solder 136, and a conductive contact 122 on the bottom surface of the tube core 114-2 or the tube core 114-3 located on the top surface of the second RDL 148-2. The second solder interconnect 140 disclosed herein may take any suitable form. The second solder interconnect 140 may have a rougher pitch than the first solder interconnect 130 in the microelectronic assembly or the same pitch. The second solder interconnect 140 may have a finer pitch than the DTPS interconnect 150 in the microelectronic assembly. In some embodiments, the second solder interconnect 140 disclosed herein may have a pitch between 50 microns and 150 microns. In some embodiments, the second solder interconnect 140 in the microelectronic assembly 100 may include a solder 136 as a higher temperature solder. The higher temperature solder includes a solder having a melting point higher than 241 degrees Celsius. In some embodiments, the higher temperature solder material may include a metal alloy, including a tin alloy, such as tin and copper; tin and gold; tin and silver; or tin, silver and copper (e.g., 96.5% tin, 3% silver and 0.5% copper). In some embodiments, the second solder interconnect 140 may include a solder 136 that is a non-reflow solder (e.g., a solder having a melting point greater than 400 degrees Celsius).

[0024] The DTPS interconnects 150 disclosed herein may take any suitable form. In some embodiments, a set of DTPS interconnects 150 may include solder 134 (e.g., solder bumps or solder balls that are subjected to thermal reflow to form the DTPS interconnects 150). For example, the DTPS interconnects 150 may include solder 134 that is a non-reflow solder, a lower temperature solder, or a conventional solder. In some embodiments, the second solder interconnects 140 in the microelectronic assembly 100 may be formed before the DTPS interconnects 150 are formed, so that the second solder interconnects 140 may use a higher temperature solder (e.g., a solder having a melting point greater than 241 degrees Celsius), while the DTPS interconnects 150 may use a non-reflow solder (e.g., a solder having a melting point greater than 400 degrees Celsius). In such a case, the second solder interconnects 140 may be surrounded by an underfill 127-2 to contain any reflow of the higher temperature solder when forming the DTPS interconnects 150. In some embodiments, the second solder interconnect 140 in the microelectronic assembly 100 can be formed after forming the DTPS interconnect 150, so that the second solder interconnect 140 can use a higher temperature solder (e.g., a solder having a melting point greater than 241 degrees Celsius), while the DTPS interconnect 150 can use a lower temperature solder (e.g., a solder having a melting point less than 241 degrees Celsius). In such a case, the DTPS interconnect 150 can be surrounded by the underfill material 127-3 to contain any remelting of the low temperature solder when the second solder interconnect 140 is formed at a higher temperature. The chemical composition of the solders 132, 134, 136 can be determined using any suitable technique (e.g., energy dispersive x-ray (EDX)).

[0025] In some embodiments, a group of DTPS interconnects 150 may include an anisotropic conductive material, such as an anisotropic conductive film or an anisotropic conductive paste. Anisotropic conductive materials may include conductive materials dispersed in non-conductive materials. In the microelectronic assembly 100 disclosed herein, some or all of the DTPS interconnects 150 may have a larger spacing than some or all of the first solder interconnects 130. The first solder interconnects 130 and the second solder interconnects 140 may have a smaller spacing than the DTPS interconnects 150, which is attributed to the higher material similarity between the die 114 and the first RDL 148-1 than between the first RDL 148-1 and the package substrate 102 on both sides of a group of DTPS interconnects 150. Specifically, the material composition difference between the first RDL 148-1 and the package substrate 102 may cause the first RDL 148-1 and the package substrate 102 to expand and contract differently due to the heat generated during operation (and the heat applied during various manufacturing operations). To mitigate damage caused by such differential expansion and contraction (e.g., cracking, solder bridging, etc.), the DTPS interconnect 150 may be formed larger and further apart than the first solder interconnect 130 and the second solder interconnect 140, which may be subject to less thermal stress due to the higher material similarity of the die 114 and the RDL 148. In some embodiments, the DTPS interconnect 150 disclosed herein may have a pitch between 100 microns and 350 microns.

[0026] The die 114-1 in the first layer 104-1 may be coupled to the package substrate 102 by the DTPS interconnect 150 through the conductive paths in the first RDL 148-1 and the passivation layer 149, and may be coupled to the die 114-2, 114-3 in the second layer 104-2 by the first solder interconnect 130 and the second solder interconnect 140 through the conductive paths in the second RDL 148-2. The die 114-2, 114-3 in the second layer 104-2 may be coupled to the package substrate 102 by the second solder interconnect 140 and the DTPS interconnect 150 through the conductive paths in the first RDL 148-1, the second RDL 148-2 and the passivation layer 149 and the conductive pillars 152 to form multi-level (ML) interconnects. The ML interconnects may be power delivery interconnects or high-speed signal interconnects. As used herein, the term "ML interconnect" may refer to an interconnection including a conductive pillar between a first component and a second component, wherein the first component and the second component are not located in adjacent layers, or may refer to an interconnection across one or more layers (e.g., an interconnection between a first die in a first layer and a second die in a third layer, or an interconnection between a package substrate and a die in a second layer). Figure 1As shown in FIG. , the DTPS interconnect 150 may include conductive contacts 146 on the top surface of the package substrate 102 , solder 134 , and conductive contacts 172 on the bottom surface of the first RDL 148 - 1 (eg, at the bottom surface 170 - 1 of the multilayer die subassembly 104 ).

[0027] The microelectronic assembly 100 may include one or more RDLs 148 (eg, a first RDL 148-1 and a second RDL 148-2, such as Figure 1 ). The RDL 148 may include an insulating material (e.g., a dielectric material formed in multiple layers, as is known in the art) and one or more conductive paths (e.g., including conductive vias 194 and / or conductive traces 196) through the dielectric material. The conductive paths may electrically couple a first conductive contact 172 and a second conductive contact 174 on the RDL 148. In some embodiments, the insulating material of the RDL 148 may be composed of a dielectric material, a bismaleimide triazine (BT) resin, a polyimide material, an epoxy material (e.g., a glass-reinforced epoxy matrix material or an epoxy build film, etc.), a molding material, an oxide-based material (e.g., silicon dioxide or spin-on oxide), or a low-k or ultra-low-k dielectric (e.g., a carbon-doped dielectric, a fluorine-doped dielectric, a porous dielectric, and an organic polymer dielectric). Although Figure 1 Two RDLs 148-1, 148-2 are shown, but the multilayer die subassembly 104 can include any suitable number of RDLs 148, including one RDL 148 or more than two RDLs 148. The microelectronic assembly 100 can further include one or more passivation layers 149. The material of the passivation layer 149 can include any suitable material, such as silicon and nitrogen (e.g., in the form of silicon nitride); silicon, oxygen, and nitrogen (e.g., in the form of silicon oxynitride); silicon and oxygen (e.g., in the form of silicon oxide); tantalum and nitrogen (e.g., in the form of tantalum nitride); aluminum and oxygen (e.g., in the form of aluminum oxide); yttrium and oxygen (e.g., in the form of yttrium oxide); titanium and oxygen (e.g., in the form of titanium oxide); and hafnium and oxygen (e.g., in the form of hafnium oxide). In some embodiments, the passivation layer 149 can be omitted.

[0028] For example, the conductive pillars 152 can be formed of any suitable conductive material, such as copper, silver, nickel, gold, aluminum, or other metals or alloys. The conductive pillars 152 can be formed using any suitable process, for example, including a photolithography process or an additive process such as cold spray or 3D printing. In some embodiments, the conductive pillars 152 disclosed herein can have a spacing between 75 microns and 200 microns. As used herein, the spacing is measured from center to center (from the center of one conductive pillar to the center of an adjacent conductive pillar). The conductive pillars 152 can have any suitable size and shape. In some embodiments, the conductive pillars 152 can have a circular, rectangular, or other shaped cross-section. The conductive pillars 152 can be electrically connected to the first and / or second RDLs 148-1, 148-2 via non-solder interconnects, for example, metal-to-metal interconnects, such as Figure 1 as shown in .

[0029] The tube core 114 disclosed herein may include an insulating material (e.g., a dielectric material formed in multiple layers, as is known in the art) and multiple conductive paths formed through the insulating material. In some embodiments, the insulating material of the tube core 114 may include a dielectric material such as silicon dioxide, silicon nitride, oxynitride, a polyimide material, a glass-reinforced epoxy resin matrix material, or a low-k or ultra-low-k dielectric (e.g., a carbon-doped dielectric, a fluorine-doped dielectric, a porous dielectric, an organic polymer dielectric, an optically imageable dielectric, and / or a benzocyclobutene-based polymer). In some embodiments, the insulating material of the tube core 114 may include a semiconductor material such as silicon, germanium, or a III-V group material (e.g., gallium nitride) and one or more additional materials. For example, the insulating material may include silicon oxide or silicon nitride. The conductive paths in the tube core 114 may include conductive traces and / or conductive vias, and may connect any conductive contacts in the tube core 114 in any suitable manner (e.g., connecting multiple conductive contacts located on the same surface or different surfaces of the tube core 114). Reference will be made to the following. Figure 5 Exemplary structures that may be included in die 114 disclosed herein are discussed. Conductive pathways within die 114 may be appropriately bordered with liner materials (such as adhesive liners and / or barrier liners). In some embodiments, die 114 is a wafer. In some embodiments, die 114 is a monolithic silicon, a fan-out or fan-in packaged die, or a die stack (e.g., a stacked wafer, a stacked die, or a stacked multilayer die).

[0030] In some embodiments, die 114 may include conductive pathways for routing power, ground, and / or signals to / from other die 114 included in microelectronic assembly 100. For example, die 114-1 may include TSVs (not shown) including conductive material vias (e.g., metal vias) isolated from surrounding silicon or other semiconductor material by a barrier oxide, or may include other conductive pathways by which the package substrate 102 may be connected to one or more die 114 located “on top” of die 114-1 (e.g., on top of die 114-1). Figure 1 In some embodiments, die 114-1 may not route power and / or ground to die 114-2, 114-3; instead, die 114-2, 114-3 may be directly coupled to power lines and / or ground lines in package substrate 102 via ML interconnects (e.g., via conductive pillars 152). In some embodiments, die 114-1 in first layer 104-1 (also referred to herein as "base die," "interposer die," or "bridge die") may be thicker than die 114-2, 114-3 in second layer 104-2. In some embodiments, die 114 may span multiple layers of multi-layer die subassembly 104. In some embodiments, die 114-1 may be a memory device (e.g., as described below with reference to Figure 4 In some embodiments, die 114-1 may be a processor die, a radio frequency chip, a power converter, a network processor, a workload accelerator, a security encryptor, or a passive / active bridge die providing high bandwidth die-to-die interconnection between die 114-2 and 114-3 at low power. In some embodiments, die 114-2 and / or die 114-3 may be a processor die.

[0031] The multi-layer die subassembly 104 may include an insulating material 133 (e.g., a dielectric material formed in multiple layers, as is known in the art) to form multiple layers and embed one or more dies within the layers. Specifically, the die 114-1 and the conductive pillar 152 may be embedded in the insulating material 133-1 in the first layer 104-1, and the second die 114-2 and the third die 114-3 may be embedded in the insulating material 133-2 in the second layer 104-2. In some embodiments, the insulating material 133 of the multi-layer die subassembly 104 may be a dielectric material, such as an organic dielectric material, a flame retardant grade 4 material (FR-4), a bismaleimide triazine (BT) resin, a polyimide material, a glass-reinforced epoxy matrix material, or a low-k or ultra-low-k dielectric (e.g., a carbon-doped dielectric, a fluorine-doped dielectric, a porous dielectric, and an organic polymer dielectric). In some embodiments, the die 114 may be embedded in a non-homogeneous dielectric, such as dielectric layers arranged in a stack (e.g., alternating layers of different inorganic dielectrics). In some embodiments, the insulating material 133 of the multi-layer die subassembly 104 may be a molding material, such as an organic polymer with inorganic silica gel particles. In some embodiments, the insulating materials 133-1 and 133-2 are the same insulating material. In some embodiments, the insulating material 133-1 is different from the insulating material 133-2. The multi-layer die subassembly 104 may include one or more ML interconnects (e.g., including conductive vias and / or conductive pillars, as shown) passing through the dielectric material. The multi-layer die subassembly 104 may have any suitable external dimensions. For example, in some embodiments, the thickness of the multi-layer die subassembly 104 may be between 100um and 2000um. In some embodiments, the multi-layer die subassembly 104 may include a composite die, such as a stacked die. The multi-layer die subassembly 104 may have any suitable number of layers, any suitable number of dies, and any suitable die arrangement. For example, in some embodiments, the multi-layer die subassembly 104 may have between 3 and 20 layers of dies. In some embodiments, the multi-layer die subassembly 104 may include layers having between 2 and 50 dies.

[0032] The package substrate 102 may include an insulating material (e.g., a dielectric material formed in multiple layers, as known in the art) and one or more conductive paths (e.g., including conductive traces and / or conductive vias, as shown) through which power, ground, and signals are routed. In some embodiments, the insulating material of the package substrate 102 may be a dielectric material, such as an organic dielectric material, a flame retardant grade 4 material (FR-4), a BT resin, a polyimide material, a glass-reinforced epoxy matrix material, an organic dielectric with an inorganic filler, or a low-k or ultra-low-k dielectric (e.g., a carbon-doped dielectric, a fluorine-doped dielectric, a porous dielectric, and an organic polymer dielectric). Specifically, when the package substrate 102 is formed using a standard printed circuit board (PCB) process, the package substrate 102 may include FR-4, and the conductive paths in the package substrate 102 may be formed by patterned copper sheets separated by FR-4 build layers. The conductive paths in the package substrate 102 may be appropriately bordered with a liner material (such as an adhesive liner and / or a barrier liner). In some embodiments, the packaging substrate 102 may be formed using a photolithographically defined via packaging process. In some embodiments, the packaging substrate 102 may be manufactured using a standard organic packaging manufacturing process, and thus the packaging substrate 102 may take the form of an organic package. In some embodiments, the packaging substrate 102 may be a set of redistribution layers formed on a flat carrier, which is formed by laminating or spin-coating dielectric materials and establishing conductive vias and conductive lines by laser drilling and electroplating. In some embodiments, the packaging substrate 102 may be formed onto a removable carrier using any suitable technique, such as a redistribution layer technique. Any method known in the art for making the packaging substrate 102 may be used, and for the sake of brevity, such methods will not be further discussed here.

[0033] In some embodiments, package substrate 102 may be a lower density medium, and die 114 may be a higher density medium or include an area with a higher density medium. As used herein, the terms "lower density" and "higher density" are relative terms indicating that the conductive paths (e.g., including conductive interconnects, conductive lines, and conductive vias) in the lower density medium are larger and / or have larger spacing than the conductive paths in the higher density medium. In some embodiments, the higher density medium may be manufactured using a modified semi-additive process or semi-additive build process with the aid of advanced photolithography (with small vertical interconnect features formed by advanced laser or photolithography), while the lower density medium may be a PCB manufactured using a standard PCB process (e.g., a standard subtractive process using etching chemicals to remove unwanted copper areas, which forms extensive vertical interconnect features by standard laser processes). In other embodiments, the higher density medium may be manufactured using a semiconductor manufacturing process such as a single heavy metal damascene process or a dual metal damascene process. In some embodiments, additional die may be disposed on the top surface of die 114-2, 114-3. In some embodiments, additional components may be disposed on the top surface of the dies 114 - 2 , 114 - 3 .Additional passive components such as surface mount resistors, capacitors, and / or inductors may be disposed on the top or bottom surface of the package substrate 102 or embedded in the package substrate 102 .

[0034] Figure 1The microelectronic assembly 100 may also include an underfill material 127. For example, the microelectronic assembly 100 may include an underfill material 127-1 extending around the first solder interconnect 130, may include an underfill material 127-2 extending around the second solder interconnect 140, and may include an underfill material 127-3 extending around the associated DTPS interconnect 150 between the multilayer die subassembly 104 and the package substrate 102. The underfill material 127 may be an insulating material, such as a suitable epoxy material. In some embodiments, the underfill material 127 may include a capillary underfill, a non-conductive film (NCF), or a molded underfill. In some embodiments, the underfill material 127-1 may include an epoxy flux that facilitates soldering the die 114-1 to the second RDL 148-2 when forming the first solder interconnect 130, and then polymerizes and encapsulates the first solder interconnect 130. In some embodiments, the underfill material 127-2 may include an epoxy flux that facilitates soldering of the die 114-2 and / or 114-3 to the second RDL 148-2 when forming the second solder interconnect 140, and then polymerizes and encapsulates the second solder interconnect 140. In some embodiments, the underfill material 127-3 may include an epoxy flux that facilitates soldering of the multilayer die subassembly 104 to the package substrate 102 when forming the DTPS interconnect 150, and then polymerizes and encapsulates the DTPS interconnect 150. The underfill material 127-1 and / or 127-2 may be selected to have a coefficient of thermal expansion (CTE) that can relieve or minimize stress between the die 114 and the RDL 148 caused by uneven thermal expansion in the microelectronic assembly 100. The underfill material 127-3 can be selected to have a coefficient of thermal expansion (CTE) that can relieve or minimize stress between the RDL 148 and the package substrate 102 caused by uneven thermal expansion in the microelectronic assembly 100. In some embodiments, the CTE of the underfill material 127 can have a value between the CTE of the package substrate 102 (e.g., the CTE of the dielectric material of the package substrate 102) and the CTE of the insulating material 133 of the die 114 and / or the multi-layer die subassembly 104.

[0035] Figure 1The microelectronic assembly 100 may also include a circuit board (not shown). The package substrate 102 may be coupled to the circuit board via a second level interconnect located at the bottom surface of the package substrate 102. The second level interconnect may be any suitable second level interconnect, including solder balls for a ball grid array arrangement, pins in a pin grid array arrangement, or lands in a land grid array arrangement. For example, the circuit board may be a motherboard and may have other components attached thereto. As is known in the art, the circuit board may include conductive pathways and other conductive contacts for transmitting power, ground, and signals through the circuit board wiring. In some embodiments, the second level interconnect may not couple the package substrate 102 to the circuit board, but may couple the package substrate 102 to another IC package, an interposer, or any other suitable component. In some embodiments, the multilayer die subassembly 104 may not be coupled to the package substrate 102, but may be coupled to a circuit board, for example, a PCB.

[0036] although Figure 1 The multi-layer die subassembly 104 is depicted with a particular number of dies 114 coupled to the package substrate 102 and other dies 114, but this number and arrangement is merely illustrative and the multi-layer die subassembly 104 may include any desired number and arrangement of dies 114 coupled to the package substrate 102. Although Figure 1 Die 114-1 is shown as a double-sided die, and dies 114-2, 114-3 are shown as single-sided dies, but die 114 can be a single-sided or double-sided die, and can be a single-pitch die or a mixed-pitch die. In some embodiments, additional components can be disposed on the top surface of die 114-2 and / or 114-3. In this context, a double-sided die refers to a die that has connections on both surfaces. In some embodiments, a double-sided die can include TSVs (e.g., TSV 117 in die 114-1) to form connections on both surfaces. The active surface of the double-sided die, i.e., the surface containing one or more active devices and the majority of the interconnections, can face in either direction, depending on the design requirements and electrical requirements.

[0037] Figure 1 Many elements of the microelectronic assembly 100 are included in other figures; the discussion of these elements will not be repeated when discussing these figures, and any of these elements can take any form disclosed herein. Figure 1A number of elements are illustrated as being included in the microelectronic assembly 100, but several of these elements may not be present in the microelectronic assembly 100. For example, in various embodiments, the bottom fill material 127-2 and / or 127-3 and the package substrate 102 may not be included. In some embodiments, each of the microelectronic assemblies 100 disclosed herein may function as a system-in-package (SiP) having a plurality of dies 114 having different functions included therein. In such embodiments, the microelectronic assembly 100 may be referred to as a SiP.

[0038] The microelectronic assembly 100 disclosed herein may be manufactured using any suitable technique. For example, Figure 2A-2N According to various embodiments, Figure 1 1 is a side cross-sectional view of various stages in an exemplary process of microelectronic assembly 100. Figure 2A-2N An exemplary process is depicted in which the second solder interconnect 140 and the second RDL 148-2 are formed first, and then the die 114-1 is coupled to form the first solder interconnect 130, which can achieve more precise solder bump formation. Figure 2A-2N The operations discussed in the present disclosure (and other figures showing the manufacturing process) are shown in a particular order, but these operations can be performed in any suitable order. In addition, additional operations not shown can be performed without departing from the scope of the present disclosure. Moreover, the present disclosure can be modified according to the present disclosure. Figure 2A-2N Various of the operations discussed may be performed to fabricate other of the microelectronic assemblies 100 disclosed herein.

[0039] Figure 2A The assembly is shown after patterning solder 136 and a second conductive contact 174 for a second solder interconnect 140 (e.g., a first level interconnect) on a first carrier 105-1. The carrier 105 may include any suitable material to provide stability during manufacturing operations, thereby achieving the strict relative solder bump variation (e.g., small rBTV) required for top die (e.g., die 114-2, 114-3) attachment. As the bump pitch decreases, the rBTV requirement becomes more stringent. In an example where the second solder interconnect 140 has a bump pitch of 18 microns, the solder bump coplanarity value may be equal to 1.5 microns. In some embodiments, the carrier 105 may include glass (e.g., a glass panel) or other low TTV material. In some embodiments, the carrier 105 may be sized to form a quarter panel. The solder 136 may include any suitable higher temperature solder material, as described above with reference to Figure 1 The second conductive contact 174 may include any suitable conductive material, such as nickel and / or copper, and may be formed using any suitable technique, including semi-additive plating.

[0040] Figure 2B The assembly is shown after a removable protective material 142 is provided around the solder 136 and the second conductive contact 174. The removable protective material 142 may include any suitable material, such as a dry film resist, a thermally decomposable polymer, or an easily etched dielectric material. The removable protective material 142 may be formed using any suitable process including lamination or spraying or slit coating and curing. In some embodiments, the removable protective material 142 may be initially deposited on and above the top surface of the conductive contact 174 and then polished back to expose the top surface of the conductive contact 174 and planarize the surface to reduce TTV. The removable protective material 142 may be removed using any suitable technique, including grinding or etching, such as wet etching, dry etching (e.g., plasma etching), wet spraying, or laser ablation (e.g., using an excimer laser). In some embodiments, the thickness of the removable protective material 142 may be minimized to reduce the required etching time. In some embodiments, the top surface of the removable protective material 142 may be planarized using any suitable technique, such as chemical mechanical polishing (CMP).

[0041] Figure 2C Shown in Figure 2B The second RDL 148-2 may be patterned in reverse order because the component will be inverted so that the second RDL 148-2 will be toward the top surface (eg, closer to the second surface 170-2, such as Figure 1 ). The second RDL 148-2 may include a conductive path (e.g., a conductive line 196 and a via 194) between the first conductive contact 172 and the second conductive contact 174. The second RDL 148-2 may be manufactured using any suitable technology, such as a PCB technology or a redistribution layer technology. The conductive via 194 may be formed to have a tapered shape so that the conductive via 194 has a smaller width at the bottom (e.g., toward the first surface 270-1) and a larger width at the top (e.g., toward the second surface 270-2). In some embodiments, the conductive via 194 in the second RDL 148-2 may be formed using a photolithography process (e.g., by patterning the via, laminating a dielectric and planarizing), a photoimageable dielectric (PID) process (e.g., by laminating the PID, exposing the PID to form a via opening and providing a conductive material in the opening to form a conductive via), or a laser drilling process (e.g., by forming a via opening in a dielectric material and providing a conductive material in the opening to form a conductive via).

[0042] Figure 2DThe assembly is shown after depositing solder 132 (eg, to form first solder interconnect 130) on first conductive contact 172. Solder 132 may include materials that are non-reflow solder, lower temperature solder, or conventional solder, as described above with reference to Figure 1 described.

[0043] Figure 2E shows that when die 114-1 is placed Figure 2D The assembly after forming a first solder interconnect 130 between the first conductive contact 172 on the die 114-1 and the second RDL 148-2 and dispensing the underfill 127-1 around the first solder interconnect 130. The die 114-1 may be placed using any suitable method, such as automated pick and place. The die 114-1 may include a first conductive contact 122 and a second conductive contact 124 surrounded by a molding material 123 that may be formed on the die 114-1 before the die 114-1 is placed on the assembly. The die 114-1 may further include a TSV 117. Figure 2E The assembly may be subjected to a solder reflow process during which the solder 132 of the first solder interconnect 130 melts and bonds, thereby mechanically and electrically coupling the die 114-1 to the second RDL 148-2. The underfill material 127-1 may be formed of any suitable material and may be dispensed using any suitable technique, as described above with reference to Figure 1 As stated. Figure 2E As shown in FIG. 1 , a die attach film (DAF) between the die 114 - 1 and the second RDL 148 - 2 is omitted because the die 114 - 1 is soldered to the second RDL 148 - 2 via the solder 132 .

[0044] Figure 2F Shown in Figure 2EThe component after depositing a conductive material (e.g., copper) on the top surface of the component to generate the conductive pillar 152. The conductive pillar 152 can be formed on the first conductive contact 172 on the second RDL 148-2 and electrically coupled thereto. The conductive pillar 152 can be formed using any suitable technology, for example, a photolithography process or an additive process such as cold spray or three-dimensional printing. The conductive pillar 152 can have any suitable external dimensions. In some embodiments, the conductive pillar 152 can span one or more layers. For example, in some embodiments, the individual conductive pillar 152 can have an aspect ratio (height: diameter) between 1:1 and 4:1 (e.g., between 1:1 and 3:1). In some embodiments, the individual conductive pillar 152 can have a diameter (e.g., cross-section) between 10 microns and 150 microns. For example, the individual conductive pillar 152 can have a diameter between 50 microns and 100 microns. In some embodiments, the individual conductive pillar 152 can have a height (e.g., z height or thickness) between 50 microns and 150 microns. The conductive pillars 152 may have any suitable cross-sectional shape, such as square, triangle, oval, or others.

[0045] Figure 2GThe assembly is shown after depositing insulating material 133-1 on and around the tube core 114-1 and the conductive pillar 152 and planarizing the top surface of the assembly to form the first layer 104-1. The insulating material 133-1 can be a molding material, such as an organic polymer with inorganic silica gel particles, an epoxy resin material, or a silicon and nitrogen material (for example, in the form of silicon nitride). In some embodiments, the insulating material 133-1 is a dielectric material. In some embodiments, the dielectric material can include an organic dielectric material, a flame retardant 4-level material (FR-4), a BT resin, a polyimide material, a glass-reinforced epoxy resin matrix material, or a low-k or ultra-low-k dielectric (for example, a carbon-doped dielectric, a fluorine-doped dielectric, a porous dielectric, and an organic polymer dielectric). The insulating material 133-1 can be formed using any suitable process, including lamination or slit coating and curing. In some embodiments, the insulating material 133-1 in liquid form may be dispensed, flowed and conformed around various shaped components and metallizations, and may then be subjected to a process that renders the insulating material 133-1 solid, such as curing. In some embodiments, the insulating material 133-1 may be initially deposited on and above the top surface of the die 114-1, and then polished back to expose the top surface of the conductive contacts 122 on the die 114-1. The insulating material 133-1 may be removed using any suitable technique, including grinding or etching, such as wet etching, dry etching (e.g., plasma etching), wet spraying, or laser ablation (e.g., using an excimer laser). In some embodiments, the thickness of the insulating material 133-1 may be minimized, thereby reducing the required etching time. In some embodiments, the top surface of the insulating material 133-1 may be planarized using any suitable technique (e.g., chemical mechanical polishing (CMP)).

[0046] Figure 2H Shown in Figure 2G A passivation layer 149 and an RDL 148 (eg, a first RDL 148-1, such as a first RDL 148-2) are formed on the top surface of the component. Figure 1 ). The passivation layer 149 may include a conductive path (e.g., a conductive line 196 and a conductive via 194). The first RDL 148-1 may include a conductive path (e.g., a conductive line 196 and a conductive via 194) between the first conductive contact 172 and the second conductive contact 174 on the first RDL 148-1. The passivation layer 149 may be manufactured using any suitable technology, such as plasma chemical vapor deposition (PCVD) or electron beam evaporation or sputtering. The first RDL 148-1 may be manufactured using any suitable technology, such as PCB technology or redistribution layer technology, as described above with reference to Figure 2CThe conductive via 194 may be formed to have a tapered shape such that the conductive via 194 has a smaller width at the bottom (eg, toward the first surface 270-1) and a larger width at the top (eg, toward the second surface 270-2). In some embodiments, the passivation layer 149 and / or the first RDL 148-1 may be omitted.

[0047] Fig.2I The assembly is shown after depositing solder 134 (eg, for forming DTPS solder interconnect 150) on the first conductive contact 172 of the first RDL 148-1. The solder 134 may include a solder material that is a non-reflow solder, a lower temperature solder, or a conventional solder, as described above with reference to Figure 1 In embodiments where the first RDL 148 - 1 and / or the passivation layer 149 are omitted, the solder 134 may be deposited on the conductive contacts (not shown) on the top surface (eg, toward the second surface 270 - 2 ) of the insulating material 133 - 1 of the first layer 104 - 1 .

[0048] Figure 2J-1 The assembly of forming the second solder interconnect 140 prior to the DTPS interconnect 150 is shown. Figure 2J-1 The assembly is shown after providing a sacrificial material 143 around the solder 134 and the first conductive contact 172 on the first RDL 148-1 and attaching the second carrier 105-2 to the top surface 270-2 of the assembly. The sacrificial material 143 may include any suitable material, such as titanium (e.g., as an etch stop layer) and copper, laser release materials, negative coefficient of thermal expansion (CTE) materials, dry film resists, thermally decomposable polymers, easily etched dielectric materials, or combinations thereof. The removable protective material 142 may be formed using any suitable process including lamination or slit coating and curing. The second carrier 105-2 may include any suitable carrier 105, as described above with reference to Figure 2A As described, and may include a carrier 105 having a greater thickness than the first carrier 105 - 1 or other such carriers, thereby reducing warpage when the first carrier 105 - 1 is removed.

[0049] Figure 2J-2 The DTPS interconnect 150 is formed before the second solder interconnect 140. Figure 2J-1 Optional components. Figure 2J-2 The package substrate 102 is shown attached to Fig.2I The assembly after forming the DTPS solder interconnect 150 and dispensing the underfill 127-3 around the DTPS interconnect 150 is formed on the top surface 270-2 of the assembly. The DTPS interconnect 150 may include the conductive contact 146 on the package substrate 102, the solder 134, and the first conductive contact 172 on the first RDL 148-1. Figure 2J-2 The assembly may be subjected to a solder reflow process during which the solder 134 of the DTPS interconnect 150 melts and bonds, thereby mechanically and electrically coupling the package substrate 102 to the Fig.2I The bottom fill material 127-3 may be formed of any suitable material and may be dispensed using any suitable technique, as described above with reference to Figure 1 As mentioned above. Figure 2J-2 The components are implemented as follows Figure 2K-2M In the other operations described above, the package substrate 102 may function as the second carrier 105 - 2 .

[0050] Figure 2K Shows an inverted Figure 2J-1 The components of the first carrier 105 - 1 and the components after the first carrier 105 - 1 is removed. If multiple components are manufactured together, the components can be singulated (eg, singulated into four quarter panels) after the first carrier 105 - 1 is removed.

[0051] Figure 2L The assembly is shown after the removable protective material 142 is removed. The removable protective material 142 can be removed using any suitable technique. For example, in some embodiments, the removable protective material 142 can be removed using dimethyl sulfoxide in an acid copper etch process, an ammoniated copper etch process, or a wet strip process.

[0052] Figure 2M The die 114-2, 114-3 are shown placed Figure 2K On the top surface of the assembly, a second solder interconnect 140 is formed between the die 114-2, 114-3 and the second conductive contact 174 on the second RDL 148-2 and an insulating material 133-2 is deposited on and around the die 114-2, 114-3 to form the assembly after the second layer 104-2. The die 114-2, 114-3 can be placed by any suitable method, such as automated pick and place. The die 114-2, 114-3 can include a first conductive contact 122 located on the bottom surface. Figure 2M The assembly can be subjected to a solder reflow process during which the solder 136 of the solder interconnect 140 melts and bonds, thereby mechanically and electrically coupling the die 114-2, 114-3 to the second RDL 148-2. The solder 136 can include any suitable material, including a higher temperature solder material, as described above with reference to Figure 1 The insulating material 133-2 may include any suitable material and may be formed and removed using any suitable process, including the process described above with reference to Figure 2G In some embodiments, the insulating material 133-1 (eg, Figure 2G) is different from the insulating material 133-2 in the second layer 104-2 (eg, Figure 2M In some embodiments, the insulating material 133-1 (eg, Figure 2G ) is deposited in the second layer 104-2 and is in contact with the insulating material 133-2 (eg, Figure 2M 140). In some embodiments, the bottom filler 127-2 may be dispensed around the second solder interconnect 140 before depositing the insulating material 133-2. In some embodiments, the bottom filler 127-2 around the second solder interconnect 140 may be omitted. In some embodiments, the insulating material 133-2 may be initially deposited onto and above the top surface of the tube core 114-2, 114-3, and then polished back to expose the top surface of the tube core 114-2, 114-3. If the insulating material 133-2 is formed to completely cover the tube core 114-2, 114-3, then the insulating material 133-2 may be removed using any suitable technique, including grinding or etching, such as wet etching, dry etching (e.g., plasma etching), wet spraying, or laser ablation (e.g., using an excimer laser). In some embodiments, the thickness of the insulating material 133-2 can be minimized, thereby reducing the required etching time. In some embodiments, the top surface of the insulating material 133-2 may be planarized using any suitable process (e.g., CMP).

[0053] Figure 2N The assembly is shown after removing the second carrier 105-2 and removing the sacrificial material 143. The sacrificial material 143 may be removed using any suitable technique. For example, in some embodiments, the sacrificial material 143 may be removed using dimethyl sulfoxide in an alkaline copper etch process or a wet strip process. In some embodiments, when an etch stop is used, a dry etch process may be used to remove the sacrificial material 143. In some embodiments, when a thermally decomposable polymer material is used, heat may be used to remove the sacrificial material 143. In some embodiments, when a laser release material is used, light may be used to remove the sacrificial material 143. Figure 2N The component itself can be a microelectronic component 100, as shown. Figure 2N The microelectronic assembly 100 is further fabricated to form other microelectronic assemblies 100; for example, solder 134 may be used to interconnect the microelectronic assembly 100 with the DTPS interconnect 150. Figure 2N The microelectronic assembly 100 is coupled to a packaging substrate 102, which is Figure 1 The microelectronic assembly 100 is similar.

[0054] Figure 31 is a flow chart of an exemplary method of making an exemplary microelectronic assembly according to various embodiments. In 302, a higher temperature solder 136 and a conductive contact (e.g., a conductive contact 174 located on a second RDL 148-2) for a second solder interconnect 140 are patterned on a first carrier 105-1. The higher temperature solder 136 and the conductive contact 174 are encapsulated with a removable protective material 142, and the top surface of the removable protective material 142 is planarized.

[0055] At 304 , an RDL 148 (eg, Figure 1 The second RDL 148-2 is formed and electrically coupled to the conductive contact 174 and the higher temperature solder 136. The RDL 148 can be formed in a reverse order (e.g., formed upside down) because the assembly is then inverted (e.g., so that it has an orientation with the higher temperature solder 136 located at the top surface of the microelectronic assembly 100, as shown in FIG. Figure 1 ).

[0056] At 306, solder 132 is deposited on the conductive contacts 172 at the top surface of the RDL 148, thereby forming a first solder interconnect 130. The solder 132 may include a non-reflow solder, a lower temperature solder, or a conventional solder.

[0057] In 308, the first layer die 114-1 is attached to the top surface of the RDL 148 and electrically coupled to the RDL 148 through the first solder interconnect 130. An underfill material 127-1 may be deposited around the first solder interconnect 130. The underfill process may include dispensing the underfill material in liquid form, allowing the material to flow and fill the interstitial gap around the first solder interconnect 130, and subjecting the assembly to a curing process (e.g., baking) to make the material solid. The first layer die 114-1 may be placed and electrically coupled to the RDL 148 through the first solder interconnect 130 without using DAF or other adhesive materials.

[0058] In 310, a conductive pillar 152 is formed on the top surface of the RDL 148 and electrically coupled to the conductive contact 172 on the RDL 148. After the conductive pillar 152 is formed, an insulating material 133-1 is disposed on and around the first layer die 114-1 and the conductive pillar 152 using any suitable method so that the insulating material 133-1 encapsulates the first layer die 114-1 and the conductive pillar 152. The top surface of the insulating material 133-1 may be planarized using CMP or any other suitable process. A grinding (also known as back grinding) process may substantially planarize and / or smooth the top surface of the assembly.

[0059] At 312, another RDL 148 (eg, Figure 1 The first RDL 148-1 is formed and electrically coupled to the first layer die 114-1 and the conductive pillar 152. The other RDL 148 can be formed in a reverse order (e.g., formed upside down) because the assembly is then inverted (e.g., so that it has an orientation with the higher temperature solder 136 located at the top surface of the microelectronic assembly 100, such as Figure 1 ).

[0060] In 314, solder 134 is deposited on the conductive contact 172 at the top surface of the other RDL 148, thereby forming a DTPS interconnect 150. The solder 134 may include a non-reflow solder, a lower temperature solder, or a conventional solder. In an embodiment in which the second solder interconnect 140 is formed before the DTPS interconnect 150, the solder 134 is encapsulated with a sacrificial material 143, the second carrier 105-2 is attached to the top surface of the sacrificial material 143, the assembly is inverted, and the first carrier 105-1 is removed. In an embodiment in which the DTPS interconnect 150 is formed before the second solder interconnect 140, the package substrate 102 may be attached, and the DTPS interconnect 150 may be formed. An underfill material 127-3 may be deposited around the DTPS interconnect 150. The underfill process may include dispensing an underfill material in liquid form, allowing the material to flow and fill the gap space around the DTPS interconnect 150, and subjecting the assembly to a curing process (e.g., baking) to make the material solid.

[0061] In 316, the removable protective material 142 is removed, and the second layer of tube cores 114-2 and / or 114-3 are attached and electrically coupled to the solder 136 (e.g., located at the top surface of the assembly after inversion) to form a second solder interconnect 140. An underfill material 127-2 may be deposited around the second solder interconnect 140. The underfill process may include dispensing the underfill material in liquid form, allowing the material to flow and fill the gap space around the second solder interconnect 140, and subjecting the assembly to a curing process (e.g., baking) to make the material solid. The second layer of tube cores 114-2, 114-3 may be encapsulated with an insulating material 133-2, and the material may be planarized using CMP or any other suitable process.

[0062] In 318, the second carrier 105-2 and sacrificial material 143 (if used) are removed to expose the solder 134. Other operations may be performed, such as attaching the package substrate 102 and electrically coupling it to the solder 134 to form the DTPS interconnect 150.

[0063] The microelectronic assembly 100 disclosed herein can be used for any suitable application. For example, in some embodiments, the microelectronic assembly 100 can be used to implement extremely small form factor voltage regulation, especially for field programmable gate arrays (FPGAs) or processing units (e.g., central processing units, graphics processing units, FPGAs, modems, application processors, etc.) in mobile devices and small form factor devices. In another example, the die 114 in the microelectronic assembly 100 can be a processing device (e.g., central processing unit, graphics processing unit, FPGA, modem, application processor, server processor, etc.).

[0064] The microelectronic assembly 100 disclosed herein may be incorporated into any suitable electronic component. Figure 4-7 Various examples of devices that can include or be contained in any microelectronic assembly 100 disclosed herein are shown.

[0065] Figure 4 1 is a top view of a wafer 1500 and die 1502 (e.g., any suitable die 114 as die 114) that may be included in any microelectronic assembly 100 disclosed herein. Wafer 1500 may be composed of semiconductor material and may include one or more die 1502 having IC structures formed on a surface of wafer 1500. Each of die 1502 may be a repeating unit of a semiconductor product including any suitable IC. After fabrication of the semiconductor product is complete, wafer 1500 may undergo a singulation process in which the dies 1502 are separated from one another to provide discrete "chips" of the semiconductor product. Die 1502 may be any die 114 disclosed herein. Die 1502 may include one or more transistors (e.g., transistors discussed below). Figure 5 Some of the transistors 1640 of the transistors 1640), supporting circuitry that routes electrical signals to the transistors, passive components (e.g., signal traces, transistors, capacitors, or inductors), and / or any other IC components. In some embodiments, wafer 1500 or die 1502 may include memory devices (e.g., random access memory (RAM) devices, such as static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM) devices, conductive bridge RAM (CBRAM) devices, etc.), logic devices (e.g., AND, OR, NAND, or NOR gates), or any other suitable circuit elements. Multiple of these devices may be combined on a single die 1502. For example, a memory array formed by multiple memory devices may be coupled to a processing device (e.g., Figure 7The processing device 1802 of the memory device or other logic configured to store information in the memory device or execute instructions stored in the memory array is formed on the same die 1502. In some embodiments, the die 1502 (e.g., die 114) can be a central processing unit, a radio frequency chip, a power converter, or a network processor. Various microelectronic assemblies 100 disclosed herein can be manufactured using die-to-wafer assembly technology, in which some dies 114 are attached to a wafer 1500 including other dies 114, and then the wafer 1500 is singulated.

[0066] Figure 5 1 is a side cross-sectional view of an IC device 1600 that can be incorporated into any microelectronic assembly 100 disclosed herein (e.g., can be incorporated into any die 114). One or more of the IC devices 1600 can be incorporated into one or more die 1502 ( Figure 4 ) among. IC device 1600 can be formed into a die substrate 1602 (e.g., Figure 4 1500) and may be included in a die (e.g., Figure 4 The die substrate 1602 may be a semiconductor substrate composed of a semiconductor material system, for example, the semiconductor material system includes an n-type or p-type material system (or a combination of the two). For example, the die substrate 1602 may include a crystalline substrate formed using bulk silicon or a silicon-on-insulator (SOI) infrastructure. In some embodiments, the die substrate 1602 may be formed using alternative materials (which may or may not be combined with silicon), including but not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Other materials classified as II-VI, III-V, or IV may also be used to form the die substrate 1602. Although several examples of materials that may form the die substrate 1602 are described herein, any material that may serve as the basis for the IC device 1600 may be used. The die substrate 1602 may be a singulated die (for example, Figure 4 of a die 1502) or a wafer (e.g., Figure 4 portion of wafer 1500).

[0067] The IC device 1600 may include one or more device layers 1604 disposed on a die substrate 1602. The device layer 1604 may include features of one or more transistors 1640 (e.g., metal oxide semiconductor field effect transistors (MOSFETs)) formed on the die substrate 1602. The device layer 1604 may include, for example, one or more source and / or drain (S / D) regions 1620, a gate 1622 that controls current flow between the S / D regions 1620 within the transistor 1640, and one or more S / D contacts 1624 that conduct routing of electrical signals to and from the S / D regions 1620. The transistor 1640 may include additional features not shown for clarity, such as device isolation regions, gate contacts, etc. The transistor 1640 is not limited to Figure 5 The types and configurations depicted in the drawings and may include a wide variety of other types and configurations, such as planar transistors, non-planar transistors, or a combination of both. Non-planar transistors may include FinFET transistors such as dual-gate transistors or tri-gate transistors and gate-wrap-around or all-around transistors such as nanoribbon transistors and nanowire transistors.

[0068] Each transistor 1640 may include a gate 1622 formed by at least two layers (i.e., a gate dielectric and a gate electrode). The gate dielectric may include a layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide, silicon carbide and / or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium and zinc. Examples of high-k materials that can be used in the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium oxide silicon, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, scandium tantalum lead oxide and lead zinc niobate. In some embodiments, when a high-k material is used, an annealing process may be performed on the gate dielectric to improve its quality.

[0069] The gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor 1640 will be a PMOS transistor or an NMOS transistor. In some embodiments, the gate electrode may be composed of a stack of two or more metal layers, wherein one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Other metal layers may be included for other purposes, such as barrier layers. For PMOS transistors, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any metal discussed below with reference to the NMOS transistor (e.g., for work function adjustment). For NMOS transistors, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any metal discussed above with reference to the PMOS transistor (e.g., for work function adjustment).

[0070] In some embodiments, when viewed from a cross-sectional view of transistor 1640 along the source-channel-drain direction, the gate electrode may be composed of a U-shaped structure including a bottom portion substantially parallel to the surface of die substrate 1602 and two sidewall portions substantially perpendicular to the top surface of die substrate 1602. In other embodiments, at least one of the metal layers forming the gate electrode may simply be a planar layer substantially parallel to the top surface of die substrate 1602 and does not include a sidewall portion substantially perpendicular to the top surface of die substrate 1602. In other embodiments, the gate electrode may be composed of a combination of a U-shaped structure and a planar non-U-shaped structure. For example, the gate electrode may be composed of one or more U-shaped metal layers formed on top of one or more planar non-U-shaped layers.

[0071] In some embodiments, a pair of sidewall spacers may be formed to opposite sides of the gate stack to bracket the gate stack. The sidewall spacers may be formed of materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. Processes for forming sidewall spacers are known in the art and generally include deposition and etching process steps. In some embodiments, multiple pairs of spacers may be used, for example, two, three, or four pairs of sidewall spacers may be formed on opposite sides of the gate stack.

[0072] The S / D regions 1620 may be formed into the die substrate 1602 and adjacent to the gate 1622 of each transistor 1640. For example, the S / D regions 1620 may be formed using either an implantation / diffusion process or a deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorus, or arsenic may be ion implanted into the die substrate 1602 to form the S / D regions 1620. The ion implantation process may be followed by an annealing process that activates the dopants and further diffuses them into the die substrate 1602. In the latter process, the die substrate 1602 may first be etched to form a recess at the location of the S / D regions 1620. Thereafter, an epitaxial deposition process may be performed to fill the recess with the material used to make the S / D regions 1620. In some embodiments, the S / D regions 1620 may be made of a silicon alloy, such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be in-situ doped with dopants such as boron, arsenic, or phosphorus. In some embodiments, one or more alternative semiconductor materials, such as germanium or III-V materials or alloys, may be used to form S / D region 1620. In other embodiments, S / D region 1620 may be formed using one or more layers of metal and / or metal alloys.

[0073] The device layer 1604 may be provided with one or more interconnect layers (in Figure 5 1600) may be arranged to route electrical signals (e.g., power signals and / or input / output (I / O) signals) to / from devices (e.g., transistors 1640) of device layer 1604. For example, conductive features (e.g., gates 1622 and S / D contacts 1624) of device layer 1604 may be electrically coupled to interconnect structures 1628 of interconnect layers 1606-1610. The one or more interconnect layers 1606-1610 may form a metallization stack (also referred to as an "ILD stack") 1619 of IC device 1600.

[0074] The interconnect structure 1628 can be arranged within the interconnect layers 1606-1610 to route electrical signals according to a wide variety of designs; specifically, the arrangement is not limited to Figure 5 The specific configuration of interconnect structure 1628 is depicted. Figure 5 A specific number of interconnect layers 1606 - 1610 are shown in FIG. 1 , but embodiments of the present disclosure include IC devices having more or fewer interconnect layers than depicted.

[0075] In some embodiments, the interconnect structure 1628 may include wires 1628a and / or vias 1628b filled with a conductive material such as metal. The wires 1628a may be arranged to route electrical signals in a direction substantially parallel to a surface of the die substrate 1602 on which the device layer 1604 is formed. For example, the wires 1628a may be arranged to route electrical signals in a direction substantially parallel to a surface of the die substrate 1602 on which the device layer 1604 is formed. Figure 5 The vias 1628b may be arranged to route electrical signals in a direction that is substantially perpendicular to the surface of the die substrate 1602 on which the device layer 1604 is formed. In some embodiments, the vias 1628b may electrically couple together the lines 1628a of different interconnect layers 1606-1610.

[0076] The interconnect layers 1606-1610 may include a dielectric material 1626 disposed between interconnect structures 1628, such as Figure 5 In some embodiments, the dielectric material 1626 disposed between the interconnect structures 1628 in different layers of the interconnect layers 1606 - 1610 may have different compositions; in other embodiments, the composition of the dielectric material 1626 may be the same between different interconnect layers 1606 - 1610 .

[0077] A first interconnect layer 1606 (referred to as Metal 1 or "M1") can be formed directly on the device layer 1604. In some embodiments, the first interconnect layer 1606 can include wires 1628a and / or vias 1628b, as shown. The wires 1628a of the first interconnect layer 1606 can be coupled to contacts of the device layer 1604 (e.g., S / D contacts 1624).

[0078] A second interconnect layer 1608 (referred to as Metal 2 or "M2") may be formed directly on the first interconnect layer 1606. In some embodiments, the second interconnect layer 1608 may include vias 1628b, thereby coupling lines 1628a of the second interconnect layer 1608 with lines 1628a of the first interconnect layer 1606. Although the lines 1628a and vias 1628b are structurally outlined with lines within each interconnect layer (e.g., within the second interconnect layer 1608) for clarity, in some embodiments, the lines 1628a and vias 1628b may have structural and / or material continuity (e.g., filled simultaneously in a dual damascene process).

[0079] A third interconnect layer 1610 (referred to as Metal 3 or "M3") (and additional interconnect layers as needed) may be formed successively on the second interconnect layer 1608 according to similar techniques and configurations described in connection with the second interconnect layer 1608 or the first interconnect layer 1606. In some embodiments, the interconnect layers may be thicker the "higher" they are in the metallization stack 1619 in the IC device 1600 (i.e., the farther from the device layer 1604).

[0080] IC device 1600 may include a solder resist material 1634 (eg, polyimide or similar material) formed on interconnect layers 1606-1610 and one or more conductive contacts 1636. Figure 5 , the conductive contact 1636 is shown as taking the form of a bonding pad. The conductive contact 1636 can be electrically coupled to the interconnect structure 1628 and configured to route electrical signals of the (multiple) transistors 1640 to other external devices. For example, a solder joint can be formed on the one or more conductive contacts 1636 to mechanically and / or electrically couple the chip including the IC device 1600 to another component (e.g., a circuit board). The IC device 1600 may include additional or alternative structures to route electrical signals from the interconnect layers 1606-1610; for example, the conductive contact 1636 may include other similar features (e.g., pillars) that route electrical signals to external components.

[0081] In some embodiments where IC device 1600 is a double-sided die (e.g., similar to die 114-1), IC device 1600 may include another metallization stack (not shown) located on an opposite side of device layer(s) 1604. This metallization stack may include a plurality of interconnect layers as discussed above with reference to interconnect layers 1606-1610, thereby providing conductive pathways (e.g., including conductive lines and vias) between device layer(s) 1604 and additional conductive contacts (not shown) located on an opposite side of IC device 1600 from conductive contacts 1636.

[0082] In other embodiments where the IC device 1600 is a double-sided die (e.g., similar to die 114-1), the IC device 1600 may include one or more TSVs extending through the die substrate 1602; these TSVs may make contact with the device layer(s) 1604 and may provide a conductive path between the device layer(s) 1604 and additional conductive contacts (not shown) located on a side of the IC device 1600 opposite the conductive contact 1636.

[0083] Figure 61700 is a side cross-sectional view of an IC device assembly 1700 that may include any microelectronic assembly 100 disclosed herein. In some embodiments, the IC device assembly 1700 may be the microelectronic assembly 100. The IC device assembly 1700 includes a number of components disposed on a circuit board 1702 (e.g., which may be a motherboard). The IC device assembly 1700 includes components disposed on a first side 1740 of the circuit board 1702 and an opposite second side 1742 of the circuit board 1702; in general, the components may be disposed on one or both of the sides 1740 and 1742. Any of the IC packages discussed below with reference to the IC device assembly 1700 may take the form of any suitable embodiment of the embodiments of the microelectronic assembly 100 disclosed herein.

[0084] In some embodiments, circuit board 1702 may be a PCB that includes multiple metal layers separated from each other by layers of dielectric material and interconnected by conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals between components coupled to circuit board 1702 (optionally in conjunction with other metal layers). In other embodiments, circuit board 1702 may be a non-PCB substrate. In some embodiments, circuit board 1702 may be, for example, a circuit board.

[0085] Figure 6 The IC device assembly 1700 shown in FIG. 1 includes a package-on-interposer structure 1736 coupled to a first side 1740 of a circuit board 1702 via a coupling component 1716. The coupling component 1716 can electrically and mechanically couple the package-on-interposer structure 1736 to the circuit board 1702 and can include solder balls (e.g., Figure 6 as shown), male and female portions of the socket, adhesive, bottom fill material and / or any other suitable electrical and / or mechanical coupling structure.

[0086] Package-on-interposer structure 1736 may include IC package 1720 coupled to interposer 1704 via coupling component 1718. Coupling component 1718 may take any suitable form for the application, such as the forms discussed above with reference to coupling component 1716. Figure 6 A single IC package 1720 is shown, but multiple IC packages may be coupled to interposer 1704; in fact, additional interposers may be coupled to interposer 1704. Interposer 1704 may provide an intermediate substrate for bridging circuit board 1702 and IC package 1720. IC package 1720 may be or may include, for example, a die ( Figure 4 1502), IC devices (e.g., Figure 51600) or any other suitable component. In general, interposer 1704 can extend connections to a wider spacing or reroute connections to different connections. For example, interposer 1704 can couple IC package 1720 (e.g., die) to a set of ball grid array (BGA) conductive contacts of coupling component 1716 for coupling to circuit board 1702. Figure 6 In the illustrated embodiment, IC package 1720 and circuit board 1702 are attached to opposite sides of interposer 1704; in other embodiments, IC package 1720 and circuit board 1702 may be attached to the same side of interposer 1704. In some embodiments, three or more components may be interconnected via interposer 1704.

[0087] In some embodiments, the interposer 1704 may be formed as a PCB including a plurality of metal layers separated from each other by dielectric material layers and interconnected by conductive vias. In some embodiments, the interposer 1704 may be formed of epoxy, glass fiber reinforced epoxy, epoxy with inorganic fillers, ceramic material, or polymer material such as polyimide. In some embodiments, the interposer 1704 may be formed of alternative rigid or flexible materials, which may include materials identical to those used in semiconductor substrates described above, such as silicon, germanium, and other III-V and IV materials. The interposer 1704 may include metal interconnects 1708 and vias 1710, which include but are not limited to TSV 1706. The interposer 1704 may further include an embedded device 1714, which includes both passive devices and active devices. Such devices may include but are not limited to capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and micro-electromechanical systems (MEMS) devices may also be formed on interposer 1704. Package-on-interposer structure 1736 may take the form of any package-on-interposer structure known in the art.

[0088] IC device assembly 1700 may include an IC package 1724 coupled to first side 1740 of circuit board 1702 via coupling component 1722. Coupling component 1722 may take the form of any of the embodiments discussed above with reference to coupling component 1716, and IC package 1724 may take the form of any of the embodiments discussed above with reference to IC package 1720.

[0089] Figure 61700 includes a package-on-package structure 1734 coupled to a second side 1742 of a circuit board 1702 via a coupling component 1728. The package-on-package structure 1734 may include an IC package 1726 and an IC package 1732 coupled together via a coupling component 1730 such that the IC package 1726 is disposed between the circuit board 1702 and the IC package 1732. The coupling components 1728 and 1730 may take the form of any of the embodiments of the coupling component 1716 discussed above, and the IC packages 1726 and 1732 may take the form of any of the embodiments of the IC package 1720 discussed above. The package-on-package structure 1734 may be configured according to any package-on-package structure known in the art.

[0090] Figure 7 1 is a block diagram of an exemplary electrical device 1800 that may include one or more of the microelectronic assemblies 100 disclosed herein. For example, any suitable component of the components of the electrical device 1800 may include one or more of the IC device assembly 1700, IC device 1600, or die 1502 disclosed herein, and may be arranged into any of the microelectronic assemblies 100 disclosed herein. Figure 7 A certain number of components are shown as being included in the electrical device 1800, but any one or more of these components may be omitted or doubled, depending on the application. In some embodiments, some or all of the components included in the electrical device 1800 may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated onto a single system-on-chip (SoC) die.

[0091] Furthermore, in various embodiments, the electrical device 1800 may not include Figure 7 The electronic device 1800 may include one or more of the components shown, but the electronic device 1800 may include an interface circuit system for coupling to the one or more components. For example, the electronic device 1800 may not include the display device 1806, but may include a display device interface circuit system (e.g., a connector and a driver circuit system), and the display device 1806 may be coupled to the interface circuit system. In another set of examples, the electronic device 1800 may not include the audio input device 1824 or the audio output device 1808, but may include an audio input or output device interface circuit system (e.g., a connector and a support circuit system), and the audio input device 1824 and the audio output device 1808 may be coupled to the interface circuit system.

[0092] The electrical device 1800 may include a processing device 1802 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or part of a device that processes electronic data from registers and / or memory to transform the electronic data into other electronic data that can be stored in registers and / or memory. The processing device 1802 may include one or more digital signal processors (DSPs), application specific ICs (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptographic processors (dedicated processors that execute cryptographic algorithms in hardware), server processors, or any other appropriate processing devices. Generally, the electrical device 1800 may include a memory 1804, which itself may include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or a hard drive. In some embodiments, the memory 1804 may include a memory that shares a die with the processing device 1802. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).

[0093] In some embodiments, the electrical device 1800 may include a communication chip 1812 (e.g., one or more communication chips). For example, the communication chip 1812 may be configured to manage wireless communications for implementing data transfers to and from the electrical device 1800. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that can transmit data through a non-solid medium using modulated electromagnetic radiation. The term does not imply that the associated devices do not contain any wiring, although in some embodiments they may not.

[0094] The communication chip 1812 can implement any of a wide variety of wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards (including WiFi (IEEE 802.11 series), IEEE 802.16 standards (e.g., IEEE 802.16-2005 amendments)), Long Term Evolution (LTE) projects together with any amendments, updates and / or revisions (e.g., Advanced LTE projects, Ultra Mobile Broadband (UMB) projects (also known as "3GPP2"), etc.). IEEE 802.16-compatible broadband wireless access (BWA) networks are generally referred to as WiMAX networks, which is an acronym for Worldwide Interoperability for Microwave Access, which is a certification mark for products that have passed compliance and interoperability testing of the IEEE 802.16 standard. The communication chip 1812 can operate according to a Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 1812 can work according to Enhanced Data Rates for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 1812 can work according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution Data Optimized (EV-DO), their derivatives, and any other wireless protocols designated as 3G, 4G, 5G and higher generations. In other embodiments, the communication chip 1812 can work according to other wireless protocols. The electrical device 1800 may include an antenna 1822 to facilitate wireless communication and / or receive other wireless communications (such as AM or FM radio transmissions).

[0095] In some embodiments, the communication chip 1812 can manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., Ethernet). As described above, the communication chip 1812 may include multiple communication chips. For example, the first communication chip 1812 may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and the second communication chip 1812 may be dedicated to longer-range wireless communications such as global positioning systems (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, or others. In some embodiments, the first communication chip 1812 may be dedicated to wireless communications, and the second communication chip 1812 may be dedicated to wired communications.

[0096] The electrical device 1800 may include a battery / power circuit system 1814. The battery / power circuit system 1814 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuit systems for coupling components of the electrical device 1800 to an energy source separate from the electrical device 1800 (e.g., AC line power).

[0097] The electrical device 1800 may include a display device 1806 (or corresponding interface circuitry, as discussed above). The display device 1806 may include any visual indicator, such as a heads-up display, a computer monitor, a projector, a touch screen display, a liquid crystal display (LCD), a light emitting diode display, or a flat panel display.

[0098] The electrical device 1800 may include an audio output device 1808 (or corresponding interface circuitry, as discussed above). The audio output device 1808 may include any device that generates an audible indication, such as a speaker, headphones, or earbuds.

[0099] The electronic device 1800 may include an audio input device 1824 (or corresponding interface circuitry, as discussed above). The audio input device 1824 may include any device that generates a signal representing sound, such as a microphone, a microphone array, or a digital instrument (e.g., an instrument with a Musical Instrument Digital Interface (MIDI) output).

[0100] The electrical device 1800 may include a GPS device 1818 (or corresponding interface circuitry, as discussed above). The GPS device 1818 may communicate with a satellite-based system and may receive the location of the electrical device 1800, as is known in the art.

[0101] The electrical device 1800 may include other output devices 1810 (or corresponding interface circuitry, as discussed above). Examples of other output devices 1810 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or additional storage.

[0102] The electrical device 1800 may include other input devices 1820 (or corresponding interface circuitry, as discussed above). Examples of other input devices 1820 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a trackpad, a barcode reader, a quick response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0103] The electrical device 1800 may have any desired form factor, such as a computing device or a handheld, portable or mobile computing device (e.g., a cellular phone, a smart phone, a mobile Internet device, a music player, a tablet computer, a laptop, a notebook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, etc.), a desktop electrical device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device. In some embodiments, the electrical device 1800 may be any other electronic device that processes data.

[0104] The following paragraphs provide various examples of the embodiments disclosed herein.

[0105] Example 1 is a microelectronic assembly comprising: a first die in a first layer having a first surface and an opposite second surface; a redistribution layer (RDL) on the first layer, wherein the RDL comprises conductive vias having a larger width toward the first surface of the RDL and a smaller width toward the opposite second surface of the RDL, wherein the first surface of the RDL is electrically coupled to the second surface of the first die via a first solder interconnect having a first solder; and a second die in a second layer on the RDL, wherein the second die is electrically coupled to the RDL via a second solder interconnect having a second solder, wherein the second solder is different from the first solder.

[0106] Example 2 may include the subject matter of Example 1, and may further provide that the second solder comprises a higher temperature solder.

[0107] Example 3 may include the subject matter of Example 1 or 2, and may further provide that the second solder includes tin and copper; tin and gold; tin and silver; or tin, silver, and copper.

[0108] Example 4 may include the subject matter of any of Examples 1-3, and may further provide that the first solder includes a non-reflow solder, a lower temperature solder, or a conventional solder.

[0109] Example 5 may include the subject matter of Example 4, and may further provide that the first solder interconnect comprises a lower temperature solder or a conventional solder, and the microelectronic assembly may further comprise an underfill material surrounding the first solder interconnect.

[0110] Example 6 may include the subject matter of any of Examples 1-3, and may further specify that the first solder interconnect includes tin and bismuth; tin, silver, and bismuth; indium; indium and tin; or gallium.

[0111] Example 7 may include the subject matter of any of Examples 1-6, and may further provide that the pitch of the first solder interconnect is between 1 micrometer and 100 micrometers.

[0112] Example 8 may include the subject matter of any of Examples 1-7, and may further provide that the pitch of the second solder interconnects is between 50 microns and 150 microns.

[0113] Example 9 may include the subject matter of any of Examples 1-8, and may further provide that the first die is electrically coupled to the second die via a first solder interconnect, a conductive via in the RDL, and a second solder interconnect.

[0114] Example 10 may include the subject matter of any of Examples 1-9, and may further include: a package substrate electrically coupled to the first surface of the first die via a third solder interconnect having a third solder, wherein the third solder is different from the second solder.

[0115] Example 11 may include the subject matter of Example 10, and may further provide that the third solder includes a non-reflow solder, a lower temperature solder, or a conventional solder.

[0116] Example 12 may include the subject matter of any of Examples 1-11, and may further include: a conductive pillar in the first layer, wherein the conductive pillar is coupled to the RDL via a non-solder interconnect.

[0117] Example 13 may include the subject matter of any of Examples 1-12, and may further specify that the RDL is a first RDL, and may further include a second RDL located at the first surface of the first die.

[0118] Example 14 may include the subject matter of Example 13, and may further include: a passivation layer between the second RDL and the first surface of the first die.

[0119] Example 15 may include the subject matter of any of Examples 1-14, and may further provide that the first layer and the second layer include one or more insulating materials.

[0120] Example 16 is a microelectronic assembly comprising: a first die in a first layer having a first surface and an opposite second surface; a redistribution layer (RDL) on the first layer, wherein the RDL comprises conductive vias having a larger width toward the first surface of the RDL and a smaller width toward the opposite second surface of the RDL, wherein the first surface of the RDL is electrically coupled to the second surface of the first die via a first solder interconnect; and a second die in a second layer on the RDL, wherein the second die is electrically coupled to the RDL via a second solder interconnect, wherein the second solder interconnect comprises a higher temperature solder.

[0121] Example 17 may include the subject matter of Example 16, and may further provide that the first solder interconnect comprises a non-reflow solder, a lower temperature solder, or a conventional solder.

[0122] Example 18 may include the subject matter of Example 17, and may further provide that the first solder interconnect comprises a lower temperature solder or a conventional solder, and the microelectronic assembly may further comprise an underfill material surrounding the first solder interconnect.

[0123] Example 19 may include the subject matter of Example 16, and may further provide that the first solder interconnect includes tin and bismuth; tin, silver, and bismuth; indium; indium and tin; or gallium.

[0124] Example 20 may include the subject matter of Example 16, and may further provide that the second solder interconnect includes tin and copper; tin and gold; tin and silver; or tin, silver, and copper.

[0125] Example 21 may include the subject matter of any of Examples 16-20, and may further provide that the pitch of the first solder interconnect is between 1 micrometer and 100 micrometers.

[0126] Example 22 may include the subject matter of any of Examples 16-21, and may further provide that the pitch of the second solder interconnect is between 50 microns and 150 microns.

[0127] Example 23 may include the subject matter of any of Examples 16-22, and may further provide that the first die is electrically coupled to the second die via a first solder interconnect, a conductive via in the RDL, and a second solder interconnect.

[0128] Example 24 may include the subject matter of any of Examples 16-23, and may further include: a package substrate electrically coupled to the first surface of the first die via a third solder interconnect, wherein the third solder interconnect comprises a non-reflow solder, a lower temperature solder, or a conventional solder.

[0129] Example 25 may include the subject matter of any of Examples 16-24, and may further include: a conductive pillar in the first layer, wherein the conductive pillar is coupled to the RDL via a non-solder interconnect.

[0130] Example 26 may include the subject matter of any of Examples 16-25, and may further specify that the RDL is a first RDL, and may further include a second RDL located at the first surface of the first die.

[0131] Example 27 may include the subject matter of Example 26, and may further include: a passivation layer between the second RDL and the first surface of the first die.

[0132] Example 28 may include the subject matter of any of Examples 16-27, and may further provide that the first layer and the second layer include one or more insulating materials.

[0133] Example 29 is a microelectronic component comprising: a first tube core located in a first layer including a first surface having a first conductive contact portion and an opposite second surface having a second conductive contact portion; a redistribution layer (RDL) located on the first layer including a first surface having a third conductive contact portion and an opposite second surface having a fourth conductive contact portion, wherein the third conductive contact portion on the RDL is electrically coupled to the second conductive contact portion on the first tube core through a first solder interconnect, and wherein the first solder interconnect comprises a non-remelting solder, a lower temperature solder, or a conventional solder; and a second tube core located in a second layer on the second surface of the RDL including a surface having a fifth conductive contact portion, wherein the fifth conductive contact portion on the second tube core is electrically coupled to the fourth conductive contact portion on the RDL through a second solder interconnect, and wherein the second solder interconnect comprises a higher temperature solder.

[0134] Example 30 may include the subject matter of Example 29, and may further provide that the first die is electrically coupled to the second die via the first solder interconnect, the conductive via in the RDL, and a second solder interconnect.

[0135] Example 31 may include the subject matter of Example 29 or 30, and may further provide that the RDL further includes a conductive via having a larger width toward the first surface of the RDL and a smaller width toward the second surface of the RDL.

[0136] Example 32 may include the subject matter of any of Examples 29-31, and may further provide that the pitch of the first solder interconnect is between 1 micrometer and 100 micrometers.

[0137] Example 33 may include the subject matter of any of Examples 29-32, and may further provide that the pitch of the second solder interconnect is between 50 microns and 150 microns.

[0138] Example 34 may include the subject matter of any of Examples 29-33, and may further provide that the second solder interconnect includes tin and copper; tin and gold; tin and silver; or tin, silver, and copper.

[0139] Example 35 may include the subject matter of any of Examples 29-34, and may further provide that the first solder interconnect includes tin and bismuth; tin, silver, and bismuth; indium; indium and tin; or gallium.

[0140] Example 36 may include the subject matter of any of Examples 29-34, and may further provide that the first solder interconnect includes a non-reflow solder, and wherein the non-reflow solder includes copper and tin.

[0141] Example 37 may include the subject matter of any of Examples 29-34, and may further provide that the first solder interconnect includes a lower temperature solder or a conventional solder, and the microelectronic assembly may further include an underfill material surrounding the first solder interconnect.

[0142] Example 38 may include the subject matter of any of Examples 29-37, and may further include: a package substrate electrically coupled to the first conductive contact of the first die by a third solder interconnect, wherein the third solder interconnect comprises a non-reflow solder, a lower temperature solder, or a conventional solder.

[0143] Example 39 may include the subject matter of Example 38, and may further provide that the third solder interconnect includes tin and bismuth; tin, silver, and bismuth; indium; indium and tin; or gallium.

[0144] Example 40 may include the subject matter of Example 38, and may further provide that the third solder interconnect comprises a lower temperature solder or a conventional solder, and the microelectronic assembly may further comprise an underfill material surrounding the third solder interconnect.

[0145] Example 41 is a method of manufacturing a microelectronic assembly, comprising: patterning a higher temperature solder on a first carrier and encapsulating the higher temperature solder with a removable protective material; forming a redistribution layer (RDL) on the removable protective material and electrically coupling the RDL to the higher temperature solder; depositing a non-reflow solder, a lower temperature solder, or a conventional solder on a conductive contact on a top surface of the RDL; attaching a first die to the non-reflow solder, the lower temperature solder, or the conventional solder on the conductive contact on the top surface of the RDL and forming a first solder interconnect; forming a conductive pillar on one or more of the components; encapsulating the first die and the conductive pillar with an insulating material and planarizing; depositing a die-to-package substrate (DTPS) solder on the conductive contacts on the top surface of the insulating material, encapsulating with a sacrificial material, and attaching a second carrier to the top surface of the sacrificial material, wherein the DTPS solder comprises a non-reflow solder, a lower temperature solder, or a conventional solder; inverting the assembly, separating the first carrier, and removing the removable protective material; attaching a second die to the higher temperature solder and forming a second solder interconnect; and separating the second carrier and removing the sacrificial material.

[0146] Example 42 may include the subject matter of Example 41, and may further provide that the first solder interconnect includes tin and bismuth; tin, silver, and bismuth; indium; indium and tin; or gallium.

[0147] Example 43 may include the subject matter of Example 41 or 42, and may further provide that the second solder interconnect includes tin and copper; tin and gold; or tin, silver, and copper.

[0148] Example 44 may include the subject matter of any of Examples 41-43, and may further include depositing an underfill material around the first solder interconnect.

[0149] Example 45 may include the subject matter of any of Examples 41-44, and may further provide that the RDL is a first RDL, and the method may further include forming a second RDL on the insulating material, and depositing DTPS solder on the conductive contacts on the top surface of the second RDL.

[0150] Example 46 may include the subject matter of any of Examples 41-44, and may further include attaching a package substrate to the DTPS solder and forming a third solder interconnect.

[0151] Example 47 may include the subject matter of Example 46, and may further provide that the third solder interconnect is formed before forming the second solder interconnect.

[0152] Example 48 may include the subject matter of Example 47, and may further include depositing an underfill material around the third solder interconnect prior to forming the second solder interconnect.

Claims

1. A microelectronic assembly comprising: A redistribution layer (RDL), the redistribution layer (RDL) comprising: upper surface; a lower surface opposite to the upper surface; and a plurality of conductive vias, wherein one of the conductive vias has a smaller width toward the upper surface and a larger width toward the lower surface; a first plurality of interconnects electrically coupled to a lower surface of the RDL, and comprising a first solder having a first material composition; a second plurality of interconnects coupled to an upper surface of the RDL, the second plurality of interconnects comprising a second solder having a second material composition different from the first material composition; and A die is above an upper surface of the RDL, and the die is coupled to the RDL through the second plurality of interconnects.

2. The microelectronic assembly according to claim 1, wherein: Each of the plurality of conductive vias has a smaller width toward the upper surface and a larger width toward the lower surface.

3. The microelectronic assembly according to claim 1, wherein: Each of the plurality of conductive vias tapers toward the upper surface. 4 . The microelectronic assembly of claim 1 , further comprising an electronic component coupled to the RDL through the first plurality of interconnects.

5. The microelectronic assembly of claim 1 , further comprising: A second die is coupled to the RDL through the first plurality of interconnects.

6. The microelectronic assembly according to claim 1, wherein: A first adjacent pair of the first plurality of interconnects are arranged at a first distance, a second adjacent pair of the second plurality of interconnects are arranged at a second distance, and the first distance is greater than the second distance.

7. The microelectronic assembly according to claim 1, wherein: The first plurality of interconnects has a different size than the second plurality of interconnects.

8. The microelectronic assembly of claim 1, wherein: The RDL includes at least three metal layers.

9. The microelectronic assembly of claim 1, wherein: The first solder includes copper.

10. The microelectronic assembly of claim 9, wherein: The second solder does not include copper.

11. The microelectronic assembly of claim 1 , wherein: The first solder includes tin and silver.

12. A microelectronic package comprising: Package substrate; a redistribution layer (RDL), the redistribution layer (RDL) being above the package substrate, and the RDL comprising: a first surface; a second surface opposite to the first surface, wherein the first surface is between the second surface and the packaging substrate; and a plurality of via holes, the plurality of via holes gradually becoming thinner in a direction of the second surface; a first plurality of interconnects electrically coupled to a first surface of the RDL, and comprising a first solder of a first material; a second plurality of interconnects coupled to a second surface of the RDL, the second plurality of interconnects comprising a second solder of a second material different from the first material; and A die is coupled to the RDL via the second plurality of interconnects.

13. The microelectronic package of claim 12, wherein: The first plurality of interconnects is between a first surface of the RDL and the packaging substrate.

14. The microelectronic package of claim 12, wherein: The package substrate is a printed circuit board (PCB).

15. The microelectronic package of claim 12, wherein: The RDL includes a first metal layer and a second metal layer, and the plurality of vias couple the first metal layer to the second metal layer.

16. The microelectronic package of claim 15, wherein: The first metal layer is in contact with the first plurality of interconnects, and the microelectronic package also includes a third metal layer in contact with the second plurality of interconnects.

17. A microelectronic assembly comprising: A redistribution layer (RDL), the redistribution layer (RDL) comprising: a first surface; a second surface opposite to the first surface; a plurality of metal layers, wherein a first metal layer of the plurality of metal layers is along the first surface and a second metal layer of the plurality of metal layers is along the second surface; and a plurality of via holes, the plurality of via holes gradually becoming thinner in a direction of the second surface; a first plurality of interconnects electrically coupled to a first surface of the RDL, the first plurality of interconnects comprising a first solder having a first material composition, and the first solder in contact with the first metal layer; a second plurality of interconnects coupled to a second surface of the RDL, the second plurality of interconnects comprising a second solder having a second material composition different from the first material composition, and the second solder is in contact with the second metal layer; and A die is coupled to the RDL via the second plurality of interconnects.

18. The microelectronic assembly of claim 17, further comprising an electronic component coupled to the RDL through the first plurality of interconnects.

19. The microelectronic assembly of claim 18, wherein: The electronic component is a second die.

20. The microelectronic assembly of claim 17, wherein: Each of the second plurality of interconnects also includes a conductive post coupled to the second solder.

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