Chip packaging structure

Abstract

The invention discloses a chip packaging structure, which comprises a plurality of stacked chips, a plurality of conductive pieces extending along the stacking direction, a packaging sleeve assembly for packaging the plurality of chips and the plurality of conductive pieces therein, and a substrate positioned on the outer side of the packaging sleeve assembly, and is characterized in that the chips comprise a first chip and a second chip which are arranged along the stacking direction; the packaging sleeve comprises a first packaging sleeve for packaging the first chip inside and a second packaging sleeve for packaging the second chip and the plurality of conductive pieces inside, the substrate is located at one side, far away from the first packaging sleeve, of the second packaging sleeve, the substrate comprises a connecting part, and the first chip and the second chip are electrically connected with the connecting part respectively; a part of the first chip protrudes out of the outer edge of the second chip to form a protruding part, the multiple conductive parts are located at the positions, corresponding to the protruding part, in the second packaging sleeve and located on the same side of the second chip, and the first chip is electrically connected with the connecting part through the conductive parts.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a chip packaging structure. Background Art

[0002] With the continuous development of microelectronics technology, users have higher and higher requirements for system miniaturization, multi-function, low power consumption, etc., especially the blowout of market demand for portable handheld terminals in recent years, such as smart phones, tablet computers and various wearable devices, which require higher integration and interconnection capabilities. Three-dimensional stacking packaging is a very effective technical approach to meet the above requirements.

[0003] The existing three-dimensional stacked packaging structure, especially the three-dimensional fan-out packaging structure, often needs to use two or more plastic encapsulation processes to achieve wafer reconstruction and plastic encapsulation protection. However, in the currently known three-dimensional stacked packaging structure, the multiple stacked chip structures that are plastic-encapsulated need to lead out the pins of each chip one by one, so that the pins of the chip extend out of the packaging structure in order to connect with external chips or circuit boards and other components, resulting in an increase in the overall volume of the packaging structure, which is not conducive to achieving product miniaturization. Summary of the invention

[0004] In view of this, the present invention provides a chip packaging structure to solve the problem that the existing packaging structure has a large overall volume and is not conducive to miniaturization.

[0005] On the one hand, the present application provides a chip packaging structure, comprising a plurality of chips arranged in a stacked manner, a plurality of conductive members extending in a stacking direction, a packaging sleeve component encapsulating the plurality of chips and the plurality of conductive members inside, and a substrate located outside the packaging sleeve component, wherein the chips comprise a first chip and a second chip arranged in the stacking direction, the packaging sleeve comprises a first packaging sleeve encapsulating the first chip inside and a second packaging sleeve encapsulating the second chip and the plurality of conductive members inside, the substrate is located on a side of the second packaging sleeve away from the first packaging sleeve, the substrate comprises a connecting portion, and the first chip and the second chip are electrically connected to the connecting portion respectively;

[0006] Part of the first chip protrudes beyond the outer edge of the second chip to form a protrusion, and the plurality of conductive members are located in the second packaging sleeve at positions corresponding to the protrusion and on the same side of the second chip, and the first chip is electrically connected to the connection portion through the conductive members.

[0007] In some embodiments, a first interconnect pin and a first external connection pin are provided on a side of the first chip close to the second chip, a second interconnect pin and a second external connection pin are provided on the second chip, the first interconnect pin and the second interconnect pin are electrically connected, the second external connection pin is located on a side of the second chip away from the first chip and is electrically connected to the connection portion, and the first external connection pin is electrically connected to the connection portion through the conductive member.

[0008] In some embodiments, the connecting portion includes a first connecting portion connected to the first chip and a second connecting portion electrically connected to the second chip. In a direction perpendicular to the stacking direction, the first connecting portion is located at an end of the substrate close to the conductive member, and the second connecting portion is located at an end of the substrate away from the conductive member.

[0009] In some embodiments, the number of the second external connection pins on the side of the second chip close to the conductive element is less than the number of the second external connection pins on the side of the second chip away from the conductive element.

[0010] In some embodiments, the second external connection pin includes a plurality of RF pins, the plurality of RF pins are located on a side of the second chip away from the conductive member, and the connection portion electrically connected to the RF pins is located on a side of the substrate away from the conductive member.

[0011] In some embodiments, the second external connection pins on the side of the second chip away from the conductive member are all the RF pins.

[0012] In some embodiments, the second interconnection pin is located on a side of the second chip close to the first chip, the second interconnection pin is arranged opposite to the corresponding first interconnection pin, and the first external connection pin is closer to the conductive member than the first interconnection pin.

[0013] In some embodiments, the second interconnection pin is located at a side of the second chip away from the first chip and is disposed close to the conductive member, and the second interconnection pin is electrically connected to the first interconnection pin through the corresponding conductive member.

[0014] In some embodiments, the second external connection pin includes a radio frequency pin and a power pin, the radio frequency pin is located on a side of the second chip away from the conductive member, and the power pin is located on a side of the second chip close to the conductive member.

[0015] In some embodiments, the first chip is a control chip, and the second chip is a radio frequency chip.

[0016] In some embodiments, along a first direction perpendicular to the stacking direction, one side of the first chip protrudes beyond an outer edge of the second chip, and the other opposite side is flush with an outer edge of the second chip.

[0017] The chip packaging structure provided by the present invention forms a protruding portion by making a portion of the first chip protrude beyond the outer edge of the second chip, and multiple conductive parts are located in the second packaging sleeve at positions corresponding to the protruding portions. Therefore, when the first chip is electrically connected to the connecting part, it is not necessary to lead the pins to the circumferential outside of the first chip, and they can be connected to the conductive parts at the protruding portions, which is beneficial to reducing the overall volume of the chip packaging structure so as to achieve miniaturization of the product. Moreover, since multiple conductive parts are located on the same side of the second chip, the pins on the side of the second chip away from the conductive parts will not be affected by the conductive parts during routing, making its routing design more flexible. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A schematic cross-sectional view of a chip packaging structure provided by an embodiment of the present invention;

[0019] Figure 2 for Figure 1 A top view of a substrate, a first chip and a second chip of the chip packaging structure shown in FIG. 1 in an exploded state;

[0020] Figure 3 for Figure 2 An assembly diagram of the substrate, the first chip and the second chip shown in ;

[0021] Figure 4 A schematic cross-sectional view of a chip packaging structure provided by another embodiment of the present invention.

[0022] In the figure: 10, chip packaging structure; 12, conductive member; 14, packaging sleeve assembly; 15, substrate; 16, connection portion; 161, first connection portion; 162, second connection portion; 18, first chip; 20, second chip; 22, first packaging sleeve; 24, second packaging sleeve; 26, dielectric layer; 181, protrusion; 281, first interconnection pin; 282, first external connection pin; 301, second interconnection pin; 302, second external connection pin; 303, RF pin; 304, power pin. DETAILED DESCRIPTION

[0023] The present invention is further described below in conjunction with the accompanying drawings and specific implementation methods. It should be noted that, under the premise of no conflict, the various embodiments or technical features described below can be arbitrarily combined to form a new embodiment.

[0024] It should be noted that all directional indications in the embodiments of the present invention (such as up, down, left, right, front, back, inside, outside, top, bottom...) are only used to explain the relative position relationship between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0025] It should also be noted that when an element is referred to as being "fixed on" or "disposed on" another element, the element may be directly on the other element or there may be an intermediate element at the same time. When an element is referred to as being "connected to" another element, it may be directly connected to the other element or there may be an intermediate element at the same time.

[0026] See also Figure 1 and Figure 2 A chip packaging structure 10 provided by an embodiment of the present invention includes a plurality of chips arranged in a stacked manner, a conductive member 12 extending in a stacking direction, a packaging sleeve assembly 14 that encapsulates the plurality of chips and the plurality of conductive members 12 therein, and a substrate 15 located outside the packaging sleeve assembly 14. The plurality of chips include a first chip 18 and a second chip 20 arranged in the stacking direction. The first chip 18 and the second chip 20 are arranged at intervals and are electrically connected to each other. The packaging sleeve assembly 14 wraps the first chip 18 and the second chip 20 therein, thereby protecting the first chip 18 and the second chip 20. The substrate 15 includes a connecting portion 16, and the first chip 18 and the second chip 20 are electrically connected to the connecting portion 16, respectively. Optionally, the first chip 18 is electrically connected to the connecting portion 16 through the conductive member 12, and the second chip 20 is electrically connected to the connecting portion 16 without passing through the conductive member 12. External elements such as a circuit board or other chips are electrically connected to the connecting portion 16 to achieve electrical connection with the first chip 18 and the second chip 20.

[0027] The specific number of chips is not limited, for example, two, three or more than three, and the multiple chips can be chips of the same type or chips of different types. In this embodiment, the number of chips is two, and for the convenience of distinguishing descriptions, the two chips are respectively referred to as a first chip 18 and a second chip 20.

[0028] In an optional embodiment, the first chip 18 is a control chip, such as a COMS (Complementary Metal Oxide Semiconductor) control chip, which can be used as a controller. The second chip 20 is an analog chip, such as a radio frequency chip. The first chip 18 is electrically connected to the second chip 20 for controlling the second chip 20.

[0029] The packaging sleeve assembly 14 includes a first packaging sleeve 22 and a second packaging sleeve 24. The first packaging sleeve 22 is arranged corresponding to the first chip 18 to encapsulate the first chip 18 inside and protect the first chip 18. The second packaging sleeve 24 is arranged corresponding to the second chip 20 to encapsulate the second chip 20 and the conductive member 12 inside and protect the second chip 20 and the conductive member 12. The connecting portion 16 is located on a side of the second packaging sleeve 24 away from the first packaging sleeve 22. It can be understood that the first packaging sleeve 22 and the second packaging sleeve 24 can be made of the same or different packaging materials, and are usually made in different steps in the manufacturing process of the chip packaging structure 10.

[0030] Optionally, the projection of the first packaging sleeve 22 at right angles to the stacking direction coincides with the projection of the second packaging sleeve 24 at right angles to the stacking direction. Both the first packaging sleeve 22 and the second packaging sleeve 24 are made of EMC (Electromagnetic Compatibility) plastic packaging materials. The first packaging sleeve 22 and the second packaging sleeve 24 respectively have a certain electromagnetic shielding effect on the first chip 18 and the second chip 20 located therein, thereby reducing the interference of external components on the first chip 18 and the second chip 20, and improving the reliability of the first chip 18 and the second chip 20.

[0031] Preferably, a shielding member is provided in the second packaging sleeve 24 , and the shielding member surrounds the outer circumference of the second chip 20 , thereby forming an electromagnetic shielding effect for the second chip 20 , so as to reduce electromagnetic interference to the second chip 20 and improve the reliability of the second chip 20 .

[0032] The specific shape of the shielding member is not limited, for example, it can be a metal shielding ring surrounding the outer periphery of the second chip 20, or it can be a plurality of metal shielding columns spaced around the outer periphery of the second chip 20, as long as it can provide electromagnetic shielding effect for the second chip 20.

[0033] The chip package structure 10 further includes a dielectric layer 26 attached and fixed to the side of the second package sleeve 24 away from the first package sleeve 22, the substrate 15 is located on the side of the dielectric layer 26 away from the second package sleeve 24, a first redistribution layer 27 is provided in the dielectric layer 26, and the first chip 18 and the second chip 20 are respectively electrically connected to the connection part 16 through the first redistribution layer 27. The connection part 16 can be regarded as an exposed pin patch of the chip package structure 10, so as to support electrical connection with external components through direct attachment or welding of the connection part 16.

[0034] Please refer again Figure 1In one embodiment, the first chip 18 is provided with a plurality of first interconnect pins 281 and a plurality of first external pins 282, and the first interconnect pins 281 and the first external pins 282 are both located on the side of the first chip 18 close to the second chip 20. The second chip 20 is provided with a plurality of second interconnect pins 301 and a plurality of second external pins 302, and the plurality of second interconnect pins 301 are located on the side of the second chip 20 close to or away from the first chip 18, and the plurality of second external pins 302 are located on the side of the second chip 20 away from the first chip 18. The connecting portion 16 includes a plurality of first connecting portions 161 and a plurality of second connecting portions 162 arranged at intervals, the first connecting portion 161 is electrically connected to the first chip 18, and the second connecting portion 162 is electrically connected to the second chip 20. Among them, the first interconnection pin 281 and the second interconnection pin 301 are electrically connected to realize the electrical connection between the first chip 18 and the second chip 20, the first external connection pin 282 is electrically connected to the first connection part 161 through the conductive member 12 to realize the electrical connection between the first chip 18 and the first connection part 161, and the second external connection pin 302 is electrically connected to the second connection part 162 to realize the electrical connection between the second chip 20 and the second connection part 162. When the external element is connected to the first connection part 161 and the second connection part 162, the effect of electrically connecting the external element to the first chip 18 and the second chip 20 is formed.

[0035] It should be noted that when the second interconnection pin 301 is located on the side of the second chip 20 away from the first chip 18, the first interconnection pin 281 can be electrically connected to the second interconnection pin 301 through the conductive member 12; when the second interconnection pin 301 is located on the side of the second chip 20 close to the first chip 18, the second interconnection pin 301 and the first interconnection pin 281 are located between the first chip 18 and the second chip 20, and at this time, the second interconnection pin 301 and the first interconnection pin 281 do not need to be electrically connected with the aid of the conductive member 12.

[0036] In an optional example, a first redistribution layer 27 is provided in the dielectric layer 26, and the first redistribution layer 27 is located between the connecting portion 16 and the second chip 20. A second redistribution layer 29 is provided in the first package sleeve 22, and the second redistribution layer 29 is located between the first chip 18 and the second chip 20. The second redistribution layer 29 is electrically connected to the first interconnect pin 281 and the first external pin 282, and the first redistribution layer 27 is electrically connected to the first connecting portion 161 and the second connecting portion 162. The first external connecting pin 281 is electrically connected to the conductive member 12 through the second redistribution layer 29, and is electrically connected to the first redistribution layer 27 through the conductive member 12, and finally realizes electrical connection with the first connecting portion 161, and the second external connecting pin 302 is directly electrically connected to the second connecting portion 162 through the first redistribution layer 27. When the second interconnection pin 301 is located on a side of the second chip 20 close to the first chip 18, the first interconnection pin 281 is directly electrically connected to the second interconnection pin 301 through the second redistribution layer 29; when the second interconnection pin 301 is located on a side of the second chip 20 away from the first chip 18, the second interconnection pin 301 is electrically connected to the first redistribution layer 27; the first interconnection pin 281 is electrically connected to the conductive member 12 through the second redistribution layer 29, and is electrically connected to the first redistribution layer 27 through the conductive member 12, thereby realizing electrical connection between the first interconnection pin 281 and the second interconnection pin 301.

[0037] Please refer again Figure 1 In one embodiment, part of the first chip 18 protrudes beyond the outer edge of the second chip 20 to form a protrusion 181, and multiple conductive members 12 are located in the second packaging sleeve 24 at positions corresponding to the protrusion 181. In an optional example, the conductive member 12 is located below the protrusion 181, and multiple conductive members 12 are located on the same side of the second chip 20. The first chip 18 is electrically connected to the connecting portion 16 through the conductive member 12. By making the first chip 18 protrude beyond the outer edge of the second chip 20 to form a protrusion 181, a conductive member 12 is arranged below the protrusion 181, and the conductive member 12 can extend in a straight line along the stacking direction without being blocked by the second chip 20, so that the pins of the first chip 18 are electrically connected to the conductive member 12 at the protrusion 181, and there is no need to lead the pins of the first chip 18 to the circumferential outer side of the first chip 18, which is conducive to reducing the circumferential size of the chip packaging structure 10, so as to achieve miniaturization of the product, and because multiple conductive members 12 are located on the same side of the second chip 20, the pins on the side of the second chip 20 away from the conductive member 12 will not be affected by the conductive member 12 during routing, making its routing design more flexible, reducing the impact of routing on chip performance, and achieving the characteristics of taking into account the overall volume and routing flexibility. In this embodiment, the first external connection pin 282 of the first chip 18 is electrically connected to the conductive member 12 at the protrusion 181.

[0038] Optionally, the conductive member 12 is columnar and made of metal material to achieve a conductive effect, that is, the conductive member 12 is a metal conductive column.

[0039] Taking the first chip 18 as a control chip and the second chip 20 as a radio frequency chip to form a chip packaging structure 10 as an example, the control chip can be connected to the first connection part 161 through the first external connection pin 282 and the conductive member 12, and connected to the external signal input terminal through the first connection part 161 to obtain an input signal, and generate a control signal according to the input signal; the control chip is electrically connected to the second interconnection pin 301 of the radio frequency chip through the first interconnection pin 281, and transmits the control signal to the radio frequency chip to control the operation of the radio frequency chip. The radio frequency chip can be electrically connected to the second connection part 162 through the second external connection pin 302, and connected to the external signal input terminal through the second connection part 162 to obtain an input radio frequency signal from the outside, or it can be connected to the external signal output terminal through the second connection part 162 to output a radio frequency signal.

[0040] The first external connection pins 282 are closer to the conductive member 12 than the first interconnection pins 281 . Optionally, at least part of the first external connection pins 282 are disposed on the protruding portion 181 of the first chip 18 so that the first external connection pins 282 are electrically connected to the conductive member 12 .

[0041] In the direction perpendicular to the stacking direction, the first connection portion 161 is located at one end of the substrate 15 close to the conductive member 12, and the second connection portion 162 is located at one end of the substrate 15 away from the conductive member 12, thereby reducing the distance between the first connection portion 161 and the conductive member 12 and between the second connection portion 162 and the second external connection pin 302, facilitating the electrical connection between the first connection portion 161 and the conductive member 12 and between the second connection portion 162 and the second external connection pin 302, and reducing the difficulty of wiring.

[0042] In one embodiment, the number of second external connection pins 302 on the side of the second chip 20 close to the conductive member 12 is less than the number of second external connection pins 302 on the side of the second chip 20 away from the conductive member 12. Since the pins on the side of the second chip 20 away from the conductive member 12 will not be affected by the conductive member 12 when routing, the routing design is more flexible. By arranging more second external connection pins 302 on the side of the second chip 20 away from the conductive member 12, more second external connection pins 302 on the second chip 20 will not be affected by the conductive member 12 when routing, thereby reducing the difficulty of routing.

[0043] In one embodiment, the second chip 20 is a radio frequency chip. Since the routing of the radio frequency chip has a relatively large impact on its performance, in the present application, by arranging multiple conductive members 12 on the same side of the second chip 20, the routing of the second external pin 302 on the side of the second chip 20 away from the conductive member 12 will not be affected by the conductive member 12, and the routing design is more flexible, which helps to reduce the impact of the routing on the performance of the second chip 20 and improve the reliability of the second chip 20.

[0044] See also Figure 1 and Figure 4 The second external connection pin 302 includes a plurality of RF pins 303 for being electrically connected to the second connection portion 162. The plurality of RF pins 303 are all located on the side of the second chip 20 away from the conductive member 12, and the second connection portion 162 electrically connected to the RF pin 303 is located on the side of the substrate 15 away from the conductive member 12. Since the RF pin 303 and the corresponding second connection portion 162 are both located on the side away from the conductive member 12, this can shorten the distance between the RF pin 303 and the corresponding second connection portion 162, making the connection convenient, and also can make the RF pin 303 not be affected by the conductive member 12 when being electrically connected to the second connection portion 162, making the routing of the RF pin 303 more flexible, and reducing the influence of the routing of the RF pin 303 on the RF function of the second chip 20.

[0045] Preferably, the second external connection pins 302 on the side of the second chip 20 away from the conductive member 12 are all RF pins 303, to prevent the presence of other types of pins on the side of the second chip 20 away from the conductive member 12 and to avoid the routing of other types of pins affecting the routing of the RF pins 303.

[0046] The second external connection pin 302 also includes a power pin 304. The RF pin 303 is used for inputting and outputting RF signals. The power pin 304 is used for inputting and outputting power signals. The RF pin 303 is located on the side of the second chip 20 away from the conductive member 12. The power pin 304 is located on the side of the second chip 20 close to the conductive member 12 to avoid interference between the routing of the power pin 304 and the routing of the RF pin 303.

[0047] exist Figure 1In the illustrated embodiment, the second interconnect pin 301 is located on a side of the second chip 20 close to the first chip 18 , the second interconnect pin 301 is arranged opposite to the corresponding first interconnect pin 281 , and the second interconnect pin 301 is directly connected to the first interconnect pin 281 through the second redistribution layer 29 . By arranging the second interconnection pin 301 and the second external connection pin 302 on opposite sides of the second chip 20 respectively, the first redistribution layer 27 and the second redistribution layer 29 are respectively located on opposite sides of the second chip 20, so that the pins used for interconnection of the first chip 18 and the second chip 20 and the pins used for external connection are respectively routed on different sides of the second chip 20, which can reduce the risk of routing crossing and reduce the difficulty of routing, thereby reducing the space required for routing, which is beneficial to reducing the overall volume of the chip packaging structure 10, and the second interconnection pin 301 is arranged relative to the first interconnection pin 281, so that there is no risk of crossing between the multiple second interconnection pins 301 and the first interconnection pin 281 during the routing process, which is beneficial to reducing the difficulty of routing, and the first external connection pin 282 is closer to the conductive member 12 than the first interconnection pin 281, which facilitates the electrical connection between the first external connection pin 282 and the conductive member 12.

[0048] The second interconnect pin 301 is arranged opposite to the corresponding first interconnect pin 281, which means that the second redistribution layer 29 will not cross when connecting the second interconnect pin 301 and the corresponding first interconnect pin 281. At this time, the first interconnect pin 281 and the corresponding second interconnect pin 301 can be directly opposite to each other, or there can be a certain distance in the horizontal direction. For example, multiple first interconnect pins 281 and corresponding second interconnect pins 301 are arranged in rows and columns.

[0049] The first redistribution layer 27 is a multi-layer structure, the second redistribution layer 29 is a single-layer structure, and the thickness of the second redistribution layer 29 is smaller than that of the first redistribution layer 27 .

[0050] Figure 2 for Figure 1 The top view of the first chip 18, the second chip 20 and the substrate 15 of the chip packaging structure in the illustrated embodiment in the exploded state, wherein the substrate 15 is provided with a plurality of first connection parts 161 and a plurality of second connection parts 162, and the plurality of first connection parts 161 and the plurality of second connection parts 162 are arranged at intervals. The first chip 18 is provided with a plurality of first interconnection pins 281 and a plurality of first external connection pins 282, and the plurality of first interconnection pins 281 and the plurality of first external connection pins 282 are located on the same side of the first chip 18 and are arranged at intervals. The second chip 20 is provided with a plurality of second interconnection pins 301 and a plurality of RF pins 303, and the plurality of second interconnection pins 301 and the plurality of second external connection pins 302 are arranged at intervals and are respectively located on the front side (i.e., the surface close to the first chip 18) and the back side (i.e., the surface away from the first chip 18) of the second chip 20.

[0051] Figure 3 for Figure 2 1 is an assembly diagram of the first chip 18, the second chip 20 and the substrate 15. It can be seen from the figure that the RF pin 303 and the second connection part 162 are located on the same side, and the RF pin 303 is directly connected to the corresponding second connection part 162 through the first redistribution layer 27 to achieve electrical connection between the second chip 20 and the external element. The second interconnection pin 301 and the first interconnection pin 281 are located between the first connection part 161 and the second connection part 162, and the second interconnection pin 301 is arranged opposite to and connected to the first interconnection pin 281 to achieve electrical connection between the first chip 18 and the second chip 20. The first external connection pin 282, the conductive member 12 and the first connection part 161 are located on the same side and below the protruding part 181 of the first chip 18. The first external connection pin 282 is electrically connected to the conductive member 12 through the second redistribution layer 29, and the conductive member 12 is electrically connected to the first connection part 161 through the first redistribution layer 27 to achieve electrical connection between the first chip 18 and the external element.

[0052] exist Figure 4 In another embodiment shown, the second interconnect pin 301 is located on a side of the second chip 20 away from the first chip 18, the second interconnect pin 301 is provided on the side of the second chip 20 close to the conductive member 12 and is electrically connected to the first interconnect pin 281 through the corresponding conductive member 12. Specifically, the first interconnect pin 281 is electrically connected to the conductive member 12 through the second redistribution layer 29, the conductive member 12 is electrically connected to the first redistribution layer 27, the second interconnect pin 301 is located on a side of the second chip 20 close to the first redistribution layer 27 and is electrically connected to the first redistribution layer 27, thereby realizing the electrical connection between the first interconnect pin 281 and the second interconnect pin 301. By providing the second interconnect pin 301 on the side of the second chip 20 close to the conductive member 12, the spacing between the second interconnect pin 301 and the conductive member 12 can be reduced, and the electrical connection between the second interconnect pin 301 and the first interconnect pin 281 is facilitated.

[0053] In one embodiment, along a first direction perpendicular to the stacking direction, one side of the first chip 18 protrudes beyond the outer edge of the second chip 20, and the other opposite side is flush with the outer edge of the second chip 20, thereby forming a relatively large area below the protrusion 181 to set the conductive member 12, so as to make full use of the space in the area and set a larger number of conductive members 12 below the protrusion 181.

[0054] Along the second direction perpendicular to the stacking direction and the first direction, that is, the first direction and the second direction are two vertical directions in a plane perpendicular to the stacking direction, the relative two sides of the second chip 20 can respectively protrude beyond the outer edges of the relative two sides of the first chip 18, or can be flush with the relative two sides of the first chip 18, or can be located on the inner side of the outer edge of the first chip 18.

[0055] The above-mentioned embodiments are only preferred embodiments of the present invention and cannot be used to limit the scope of protection of the present invention. Any non-substantial changes and substitutions made by technicians in this field on the basis of the present invention shall fall within the scope of protection required by the present invention.

Claims

1. A chip packaging structure, characterized in that: The invention comprises a plurality of chips arranged in a stacked manner, a plurality of conductive members (12) extending in a stacking direction, a packaging sleeve assembly (14) for packaging the plurality of chips and the plurality of conductive members (12) therein, and a substrate (15) located outside the packaging sleeve assembly (14); the chips comprise a first chip (18) and a second chip (20) arranged in the stacking direction; the packaging sleeve assembly (14) comprises a first packaging sleeve (22) for packaging the first chip (18) therein, and a second packaging sleeve (24) for packaging the second chip (20) and the plurality of conductive members (12) therein; the substrate (15) is located on a side of the second packaging sleeve (24) away from the first packaging sleeve (22); the substrate (15) comprises a connecting portion (16); the first chip (18) and the second chip (20) are electrically connected to the connecting portion (16) respectively; A portion of the first chip (18) protrudes beyond the outer edge of the second chip (20) to form a protruding portion (181); a plurality of the conductive members (12) are located in the second packaging sleeve (24) at positions corresponding to the protruding portions (181) and are located on the same side of the second chip (20); and the first chip (18) is electrically connected to the connecting portion (16) via the conductive members (12).

2. The chip packaging structure according to claim 1, characterized in that: A first interconnection pin (281) and a first external connection pin (282) are provided on a side of the first chip (18) close to the second chip (20); the second chip (20) is provided with a second interconnection pin (301) and a second external connection pin (302); the first interconnection pin (281) and the second interconnection pin (301) are electrically connected; the second external connection pin (302) is located on a side of the second chip (20) away from the first chip (18) and is electrically connected to the connection portion (16); and the first external connection pin (282) is electrically connected to the connection portion (16) via the conductive member (12).

3. The chip packaging structure according to claim 1, characterized in that: The connecting portion (16) comprises a first connecting portion (161) connected to the first chip (18) and a second connecting portion (162) electrically connected to the second chip (20); along a direction perpendicular to the stacking direction, the first connecting portion (161) is located at one end of the substrate (15) close to the conductive member (12), and the second connecting portion (162) is located at one end of the substrate (15) away from the conductive member (12).

4. The chip packaging structure according to claim 2, characterized in that: The number of the second external connection pins (302) on the side of the second chip (20) close to the conductive member (12) is less than the number of the second external connection pins (302) on the side of the second chip (20) away from the conductive member (12).

5. The chip packaging structure according to claim 2, characterized in that: The second external connection pin (302) includes a plurality of radio frequency pins (303), and the plurality of radio frequency pins (303) are all located on a side of the second chip (20) away from the conductive member (12), and the connection portion (16) electrically connected to the radio frequency pins (303) is located on a side of the substrate (15) away from the conductive member (12).

6. The chip packaging structure according to claim 5, characterized in that: The second external connection pins (302) on the side of the second chip (20) away from the conductive member (12) are all the radio frequency pins (303).

7. The chip packaging structure according to claim 2, characterized in that: The second interconnect pin (301) is located on a side of the second chip (20) close to the first chip (18), the second interconnect pin (301) is arranged opposite to the corresponding first interconnect pin (281), and the first external connection pin (282) is closer to the conductive member (12) than the first interconnect pin (281).

8. The chip packaging structure according to claim 2, characterized in that: The second interconnection pin (301) is located on a side of the second chip (20) away from the first chip (18) and is arranged close to the conductive member (12); the second interconnection pin (301) is electrically connected to the first interconnection pin (281) via the corresponding conductive member (12).

9. The chip packaging structure according to claim 2, characterized in that: The second external connection pin (302) comprises a radio frequency pin (303) and a power pin (304); the radio frequency pin (303) is located on a side of the second chip (20) away from the conductive member (12); and the power pin (304) is located on a side of the second chip (20) close to the conductive member (12).

10. The chip packaging structure according to any one of claims 1 to 9, characterized in that: The first chip (18) is a control chip, and the second chip (20) is a radio frequency chip; and / or, Along a first direction perpendicular to the stacking direction, one side of the first chip (18) protrudes beyond the outer edge of the second chip (20), and the other opposite side is flush with the outer edge of the second chip (20).

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