Chip packaging structure and packaging method

Abstract

The invention provides a chip packaging structure and a packaging method, and relates to the technical field of semiconductor packaging. In the chip packaging structure, a first flip chip is mounted on a substrate and is electrically connected with the substrate. The second flip chip is at least partially mounted to the first flip chip. The second flip chip is provided with a first electric connecting column which is electrically connected with the substrate; the second flip chip is provided with a first cylinder. The third flip chip is at least partially attached to the second flip chip; the third flip chip is provided with a second electric connecting column which is electrically connected with the substrate; the third flip chip is provided with a second cylinder. The first column body is located between the first electric connection column and the first flip chip, and a gap is formed between the first column body and the substrate. The second column body is located between the second electric connection column and the second flip chip, and a gap is formed between the second column body and the substrate. The packaging structure is beneficial to improving the flowability and the filling property of the bottom colloid, and prevents the colloid from cracking or generating a cavity.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and in particular to a chip packaging structure and a packaging method. Background Art

[0002] With the rapid development of the semiconductor industry, most of the flip-chip stacking hybrid packaging structures are used to meet the needs of multifunctional and miniaturized electronic packaging products. As the stacking density continues to increase, the size of the flip chip solder joints is getting smaller and smaller, and the height of the flip chip copper pillars is getting higher and higher. The current density and solder joint operating temperature of the copper pillars and solder joints are rising sharply, resulting in electromigration inside the copper pillars and solder joints. The electromigration phenomenon is an atomic migration phenomenon caused by the continuous inelastic collision of high-density electron flow with atoms in the solder joints. The electromigration phenomenon will cause bumps (Hillocks) and voids in the interconnected solder joints, and the interface layer of the bottom filling glue layer will be affected by the electromigration phenomenon. When the current and temperature gradient are larger, it will not only trigger the electromigration effect, but also easily lead to defects such as dissolution of the glue layer interface layer compound and glue layer fracture, thereby causing the integrity of the glue layer welding structure to be damaged and the mechanical properties to degrade, resulting in device failure. Summary of the invention

[0003] The object of the present invention is to provide a chip packaging structure and packaging method, which can alleviate the defects of dissolution and fracture of bottom filling glue caused by electromigration and improve the reliability of the packaging structure.

[0004] In a first aspect, the present invention provides a chip packaging structure, comprising: substrate; A first flip chip; the first flip chip is attached to the substrate and electrically connected to the substrate; a second flip chip, the second flip chip being at least partially mounted to the first flip chip; the second flip chip being provided with a first electrical connection column, the first electrical connection column being electrically connected to the substrate; the second flip chip being provided with a first column; a third flip chip, the third flip chip being at least partially mounted to the second flip chip; the third flip chip being provided with a second electrical connection column, the second electrical connection column being electrically connected to the substrate; the third flip chip being provided with a second column; The first pillar is located between the first electrical connection pillar and the first flip chip, and there is a distance between the first pillar and the substrate; The second pillar is located between the second electrical connection pillar and the second flip chip, and there is a distance between the second pillar and the substrate.

[0005] In an optional embodiment, one end of the first column away from the second flip chip is lower than or flush with a side surface of the first flip chip close to the substrate; And / or, one end of the second pillar away from the third flip chip is lower than a side surface of the second flip chip close to the substrate.

[0006] In an optional embodiment, a distance of the second column below a surface of a side of the second flip chip close to the substrate is greater than or equal to half a height of the first column.

[0007] In an optional embodiment, a third column is further provided on the side of the second flip chip provided with the first column; the third column is mounted on a side of the first flip chip away from the substrate; A fourth column is also provided on the side of the third flip chip where the second column is provided; the fourth column is mounted on a side of the second flip chip away from the substrate.

[0008] In an optional embodiment, the second flip chip is provided with a first passivation layer, and the first pillar and the third pillar are connected to the first passivation layer; The third flip chip is provided with a second passivation layer, and the second column and the fourth column are connected to the second passivation layer.

[0009] In an optional embodiment, a first upright chip is mounted on a side of the first flip chip away from the substrate; and the second flip chip is at least partially mounted on the first upright chip; The first front-mounted chip is provided with a first grounding pad, the substrate is provided with a second grounding pad, and the first grounding pad and the second grounding pad are connected by wire bonding; A gap is provided between the third pillar and the first front-mounted chip to form an electrostatic channel.

[0010] In an optional embodiment, a second front-mounted chip is mounted on a side of the second flip chip away from the substrate; and the third flip chip is at least partially mounted on the second front-mounted chip; The second front-mounted chip is provided with a third ground pad, and the third ground pad is wire-bonded to the first ground pad; A gap is provided between the fourth pillar and the second front-mounted chip to form an electrostatic channel.

[0011] In an optional embodiment, a bridge chip is further included, the second flip chips include at least two, each of the second flip chips is provided with the second front-mounted chip; and the bridge chip is electrically connected to the two second front-mounted chips respectively.

[0012] In an optional embodiment, it also includes a fourth electrical connection column and a surface chip; the third flip chip is provided with a wiring layer on the side away from the substrate, and the surface chip is mounted on the wiring layer; one end of the fourth electrical connection column is electrically connected to the wiring layer, and the other end is electrically connected to the second face-up chip.

[0013] In an optional embodiment, a first metal layer is provided between the first flip chip and the first face-up chip; The chip packaging structure also includes a plastic package, a shielding layer and a third electrical connection column; the plastic package covers the first flip chip, the second flip chip, the third flip chip and the first face-up chip; the shielding layer is grounded; one end of the third electrical connection column is connected to the first metal layer, and the other end is connected to the shielding layer.

[0014] In an optional embodiment, a side of the first metal layer away from the substrate is covered with a glue layer; and the third electrical connection column passes through the glue layer and is electrically connected to the first metal layer.

[0015] In a second aspect, the present invention provides a packaging method for preparing a chip packaging structure as described in any one of the aforementioned embodiments.

[0016] The chip packaging structure and packaging method provided by the embodiments of the present invention have the following beneficial effects: In the chip packaging structure provided by the embodiment of the present invention, a plurality of flip chips are stacked on a substrate, and each flip chip is electrically connected to the substrate. Each flip chip is provided with a column and an electrical connection column for connecting to the substrate. There is a spacing between the column and the substrate. In this way, the column can be used to enhance the capillary action of the bottom filling glue, which is conducive to the flow of the colloid and improves the filling property of the colloid, reduces the risk of voids or cracks in the bottom filling glue under the electromigration phenomenon, and improves the reliability of the packaging structure.

[0017] The packaging method provided in the embodiment of the present invention is used to prepare the above-mentioned chip packaging structure and improve the reliability of the packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 A schematic diagram of a first structure of a chip packaging structure provided by an embodiment of the present invention; Figure 2A second structural schematic diagram of a chip packaging structure provided by an embodiment of the present invention; Figure 3 A third structural schematic diagram of a chip packaging structure provided by an embodiment of the present invention; Figure 4 A fourth structural schematic diagram of a chip packaging structure provided by an embodiment of the present invention; Figure 5 A fifth structural schematic diagram of a chip packaging structure provided by an embodiment of the present invention; Figure 6 A schematic diagram of a process for manufacturing a chip packaging structure provided by an embodiment of the present invention; Figure 7 The embodiment of the present invention provides Figure 5 One of the process schematic diagrams of the chip packaging structure shown; Figure 8 The embodiment of the present invention provides Figure 5 The second process schematic diagram of the chip packaging structure shown; Fig. 9 The embodiment of the present invention provides Figure 4 Schematic diagram of the process of chip packaging structure shown.

[0020] Icons: 100-chip packaging structure; 110-substrate; 111-second ground pad; 120-first flip chip; 130-second flip chip; 131-first electrical connection column; 132-first column; 133-third column; 134-first passivation layer; 140-third flip chip; 141-second electrical connection column; 142-second column; 143-fourth column; 144-second passivation layer; 151- Bottom filling glue; 152-plastic package; 161-first upright chip; 162-first ground pad; 163-electrostatic channel; 165-second upright chip; 166-third ground pad; 171-bridge chip; 172-fourth electrical connection column; 173-wiring layer; 174-surface chip; 181-third electrical connection column; 182-shielding layer; 183-first metal layer; 184-glue layer; 190-solder ball. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0022] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0023] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0024] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inside", "outside", etc. indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, or the positions or positional relationships in which the product of the invention is usually placed when in use. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific position, be constructed and operated in a specific position, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", "third", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0025] In addition, the terms "horizontal", "vertical", "overhanging" and the like do not mean that the components are required to be absolutely horizontal or overhanging, but can be slightly tilted. For example, "horizontal" only means that its direction is more horizontal than "vertical", and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0026] In the description of the present invention, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "set", "install", "connect", and "connect" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0027] Some embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0028] In the stacked packaging structure in the semiconductor field, when the current density and solder joint operating temperature of the copper pillar solder joint increase sharply, it is easy to cause electromigration inside the copper pillar solder joint. Electron migration not only destroys the structure of the copper pillar solder joint, but also causes defects such as dissolution of the interface compound of the bottom filler glue layer and fracture of the glue layer, thereby causing the integrity of the welding structure protected by the bottom filler to be damaged and the mechanical properties to be degraded. In addition, in the stacked packaging structure, as the height of the chip copper pillar increases, the contact area between the bottom filler and the copper pillar increases, and the electron migration phenomenon becomes more obvious. The fluidity of the bottom filler layer deteriorates due to the thermoelectric effect, resulting in voids in the bottom filler. And when affected by electron migration, the glue layer of the bottom filler is prone to problems such as glue layer fracture at the void, affecting the reliability of the package.

[0029] A chip packaging structure and packaging method proposed in an embodiment of the present invention can improve the flow of bottom filling glue and the filling property of the colloid, reduce the risk of dissolution, voids or cracks of the bottom filling glue under the phenomenon of electromigration, and improve the reliability of the packaging structure.

[0030] Combination Figure 1 An embodiment of the present invention provides a chip packaging structure 100 , including a substrate 110 , a first flip chip 120 , a second flip chip 130 , a third flip chip 140 and a bottom filling glue 151 .

[0031] The first flip chip 120 is mounted on the substrate 110 and electrically connected to the substrate 110. The bumps at the bottom of the first flip chip 120 are welded to the pads on the substrate 110 to achieve electrical connection.

[0032] The second flip chip 130 is at least partially mounted to the first flip chip 120. The second flip chip 130 is provided with a first electrical connection column 131, and the first electrical connection column 131 is electrically connected to the substrate 110. The first flip chip 120 and the second flip chip 130 are partially stacked, and a portion of the second flip chip 130 is stacked on the first flip chip 120, and the other portion extends outside the first flip chip 120. The portion extending outside the first flip chip 120 is provided with a first electrical connection column 131, and the first electrical connection column 131 is directly welded to the pad on the substrate 110. A first column 132 is also provided on one side of the second flip chip 130 provided with the first electrical connection column 131. The first column 132 is connected to the portion of the second flip chip 130 extending outside the first flip chip 120. The first column 132 is located between the first electrical connection column 131 and the first flip chip 120, and there is a gap between the first column 132 and the substrate 110.

[0033] The third flip chip 140 is at least partially mounted to the second flip chip 130; the third flip chip 140 is provided with a second electrical connection column 141, and the second electrical connection column 141 is electrically connected to the substrate 110. The third flip chip 140 and the second flip chip 130 are partially stacked, that is, a part of the third flip chip 140 is stacked on the second flip chip 130, and the other part extends outside the second flip chip 130. The part extending outside the second flip chip 130 is provided with a second electrical connection column 141, and the second electrical connection column 141 is directly welded to the pad on the substrate 110. It should be understood that in the stacking height direction, the length of the second electrical connection column 141 is greater than the length of the first electrical connection column 131.

[0034] A second column 142 is also provided on one side of the third flip chip 140 where the second electrical connection column 141 is provided. The second column 142 is located between the second electrical connection column 141 and the second flip chip 130 , and there is a gap between the second column 142 and the substrate 110 .

[0035] The bottom filling glue 151 protects the pads on the substrate 110, the first electrical connection column 131, the second electrical connection column 141, the bumps at the bottom of the first flip chip 120, and the welding structure. By setting the first column 132 and the second column 142, it is helpful to improve the fluidity and filling performance of the bottom filling glue 151, and the filling is more complete. In this way, even when electromigration occurs, the bottom filling glue 151 is not easy to dissolve, crack or have voids. In addition, it is also helpful to improve the heat dissipation performance.

[0036] It is easy to understand that the stacking structure in this embodiment adopts a horizontally extended stacking, that is, a part of each layer of flip chips is stacked on the lower chip, and the other part extends outside the lower chip, and the part extending outside is provided with an electrical connection column and a column, and the electrical connection column is used to directly weld with the substrate 110, that is, each flip chip is directly welded with the substrate 110. In this way, the higher the height of the stack, the longer the length of the corresponding electrical connection column. For the same flip chip, the length of the column is less than the length of the electrical connection column, that is, the end of the column away from the flip chip is suspended, and there is a gap between the substrate 110. This arrangement is conducive to improving the fluidity of the bottom filling glue 151, and the colloid filling is more complete and uniform, and it is not easy to have the phenomenon of colloid dissolution, cracking or voids. Of course, the setting of the first column 132 and the second column 142 can also play a role in improving the heat dissipation performance.

[0037] In this embodiment, the length of the first column 132 is smaller than the length of the first electrical connection post 131 . The length of the second column 142 is smaller than the length of the second electrical connection post 141 .

[0038] Optionally, one end of the first pillar 132 away from the second flip chip 130 is lower than or flush with a side surface of the first flip chip 120 close to the substrate 110. In this embodiment, one end of the first pillar 132 close to the substrate 110 is flush with the lower surface of the first flip chip 120. The lower surface here refers to a side surface of the first flip chip 120 where the bottom bump is set.

[0039] Optionally, one end of the second column 142 away from the third flip chip 140 is lower than the side surface of the second flip chip 130 close to the substrate 110. That is, the end of the second column 142 close to the substrate 110 is lower than the lower surface of the second flip chip 130. Optionally, the distance that the second column 142 is lower than the side surface of the second flip chip 130 close to the substrate 110 is half the height of the first column 132. In other words, the distance that the end of the second column 142 close to the substrate 110 exceeds the lower surface of the second flip chip 130 is H2, and the length of the first column 132 is H1, and H2 is greater than or equal to half of H1. With this arrangement, there is a certain height difference between the lower ends of the first column 132 and the second column 142, which is conducive to enhancing the capillary action of the colloid, improving the fluidity and filling properties of the colloid, and facilitating heat dissipation.

[0040] Optionally, the second flip chip 130 is provided with a third column 133 on one side where the first column 132 is provided. The third column 133 is mounted on the side of the first flip chip 120 away from the substrate 110. The third flip chip 140 is provided with a fourth column 143 on one side where the second column 142 is provided; the fourth column 143 is mounted on the side of the second flip chip 130 away from the substrate 110. In other words, the portion of the second flip chip 130 stacked on the first flip chip 120 is provided with the third column 133, and the portion of the third flip chip 140 stacked on the second flip chip 130 is provided with the fourth column 143. The provision of the third column 133 and the fourth column 143 can play a role in heat dissipation and buffering. At the same time, it can also enhance the capillary action of the colloid, improve the fluidity and filling properties of the colloid, and thereby reduce the risk of cracking, voids and other problems in the colloid.

[0041] Optionally, a first passivation layer 134 is provided on the side of the second flip chip 130 close to the substrate 110, and the first column 132 and the third column 133 are connected to the first passivation layer 134. An opening is provided on the first passivation layer 134 to expose the pad at the bottom of the second flip chip 130, so as to facilitate the electrical connection between the first electrical connection column 131 and the chip pad, thereby ensuring that the first electrical connection column 131 can realize the electrical connection function. In other words, the first column 132 and the third column 133 do not require electrical connection and do not need to participate in the electrical connection. Similarly, the third flip chip 140 is provided with a second passivation layer 144, and the second column 142 and the fourth column 143 are connected to the second passivation layer 144. An opening is provided on the second passivation layer 144 to expose the pad at the bottom of the third flip chip 140, so as to facilitate the connection between the second electrical connection column 141 and the chip pad, thereby ensuring that the second electrical connection column 141 can realize the electrical connection function. The first passivation layer 134 and the second passivation layer 144 are used as insulating layers to prevent electromigration caused by thermoelectric effect of the pillars. The first passivation layer 134 and the second passivation layer 144 can be made of any one or more of silicon dioxide, silicon nitride, silicon oxynitride, polyimide and benzocyclobutene.

[0042] It should be noted that the first column 132, the second column 142, the third column 133 and the fourth column 143 can be made of metal or other materials; they can be conductive materials or insulating materials, which are not specifically limited here. In this embodiment, the first column 132, the second column 142, the third column 133 and the fourth column 143 are made of metal materials. The number of the first column 132, the second column 142, the third column 133 and the fourth column 143 can be flexibly set according to actual conditions.

[0043] In some embodiments, only one type of the first column 132 and the second column 142 may be provided. Only one type of the third column 133 and the fourth column 143 may also be provided, or both may be omitted.

[0044] In the chip packaging structure 100, the number of flip chips and the number of stacked layers can be flexibly set according to actual conditions. For example, two, three, four, five or more layers can be stacked. The number of chips in each layer can be flexibly designed, such as one, two, three, four or more, which is not specifically limited here.

[0045] Optionally, the chip packaging structure 100 further includes a plastic package 152, which is disposed on the substrate 110 and is used to cover all chips, bottom filler 151, etc. on the substrate 110 to protect it. It is also beneficial to enhance the strength of the packaging structure. Solder balls 190 are disposed at the bottom of the substrate 110 for electrical connection with other external modules.

[0046] Combination Figure 2Optionally, a first front-mounted chip 161 is mounted on a side of the first flip chip 120 away from the substrate 110; the second flip chip 130 is at least partially mounted on the first front-mounted chip 161. The first front-mounted chip 161 is provided with a first grounding pad 162, and the substrate 110 is provided with a second grounding pad 111, and the first grounding pad 162 and the second grounding pad 111 are wired and connected. The number of the first front-mounted chips 161 can be flexibly designed and is not specifically limited.

[0047] Optionally, there is a gap between the third column 133 and the first upright chip 161 to form an electrostatic channel 163. It can be understood that the first upright chip 161 is provided with a plurality of electrostatic pads, and the plurality of electrostatic pads and the plurality of third columns 133 are arranged one by one, and there is a gap between the third column 133 and the electrostatic pad. In this way, the electrostatic ions between the chips can be guided to the electrostatic channel 163 by the first column 132, and guided to the first ground pad 162 along the electrostatic channel 163, and released after wire bonding, so as to achieve the purpose of static dissipation. Of course, all electrostatic pads can be evenly spaced by the third column 133 to form an electrostatic channel 163. It is also possible that a part of the electrostatic pads are spaced from the third column 133 to form an electrostatic channel 163, and the rest of the electrostatic pads are in contact with the third column 133. The electrostatic channel 163 is conducive to improving the mobility of electrostatic ions, guiding the electrostatic ions to the grounding wire for release, or guiding them to the third column 133 in contact with the electrostatic pad for release. It can be understood that the electrostatic pad in contact with the third column 133 has a grounding characteristic and can complete the electrostatic discharge. In this embodiment, a portion of the third column 133 is in contact with the electrostatic pad, which can increase the grounding reliability, ensure that the static electricity is released, avoid the chip from being disturbed or damaged by static electricity, and also reduce the influence of the thermoelectric effect on the reliability of the packaging structure.

[0048] Since it is necessary to guide the release of static electricity ions, metal columns are used for the first column 132 and the third column 133. Of course, other conductive materials, such as conductive colloids, can also be used as long as they can absorb and guide static electricity.

[0049] Combination Figure 3Optionally, a second upright chip 165 is mounted on the side of the second flip chip 130 away from the substrate 110. The third flip chip 140 is at least partially mounted on the second upright chip 165. The second upright chip 165 is provided with a third grounding pad 166, and the third grounding pad 166 is wired to the first grounding pad 162, which can shorten the wire bonding path. There is a gap between the fourth column 143 and the second upright chip 165 to form an electrostatic channel 163. In this way, the electrostatic channel 163 is conducive to improving the fluidity of electrostatic ions. The first column 132 and the second column 142 respectively guide the electrostatic ions between the chips to the electrostatic channel 163, and flow along the electrostatic channel 163 to the wire bonding arc. Due to the grounding property of the wire bonding arc, the effect of electrostatic release is achieved. The design of the electrostatic channel 163 between the second upright chip 165 and the third flip chip 140 is similar to the design of the electrostatic channel 163 between the first upright chip 161 and the second flip chip 130, which will not be repeated here.

[0050] Since it is necessary to guide the release of static electricity ions, metal columns are used for the second column 142 and the fourth column 143. Of course, other conductive materials, such as conductive colloids, can also be used as long as they can absorb and guide static electricity.

[0051] Combination Figure 4 Optionally, the chip packaging structure 100 also includes a bridge chip 171, a fourth electrical connection column 172 and a surface chip 174. The second flip chip 130 includes at least two, and each second flip chip 130 is provided with a second upright chip 165. That is, at least two second upright chips 165 are included. The bridge chip 171 is electrically connected to the two second upright chips 165, respectively. The two second upright chips 165 are arranged at intervals, and one end of the bridge chip 171 is electrically connected to one of the second upright chips 165, and the other end is electrically connected to the other second upright chip 165. In this embodiment, the bridge chip 171 adopts a flip chip. With this arrangement, the structure is compact and the chip integration is high.

[0052] Optionally, a wiring layer 173 is provided on the side of the third flip chip 140 away from the substrate 110, and a surface chip 174 is mounted on the wiring layer 173. The surface chip 174 can be a normal chip or a flip chip, and the number of the surface chips 174 can be one or more, which is not specifically limited here. It can be understood that a dielectric layer is coated on the surface of the plastic package 152, and the wiring layer 173 is formed by exposure, development, etc.

[0053] One end of the fourth electrical connection column 172 is electrically connected to the wiring layer 173, and the other end is electrically connected to the second front-mounted chip 165. In this way, the upper wiring layer 173, the surface chip 174 and the lower substrate 110 can be indirectly electrically connected. Compared with the structure in which the upper wiring layer 173 is directly connected to the substrate 110 through the electrical connection column, the length of the fourth electrical connection column 172 is shorter, the transmission path is shorter, the transmission efficiency is higher, and the transmission loss is lower.

[0054] It can be understood that there are multiple fourth electrical connection pillars 172. Some of the fourth electrical connection pillars 172 are used to realize the functional electrical connection between the second front chip 165 and the wiring layer 173, and the other fourth electrical connection pillars 172 are used as static electricity guiding pillars, which are connected to the ground line on the second front chip 165, and can absorb and guide the static electricity in the wiring layer 173 and the static electricity between the surface chips 174, so as to complete the static electricity release of the wiring layer 173 and the surface chip 174.

[0055] Combination Figure 5 Optionally, one or more first upright chips 161 are stacked on the first flip chip 120. A first metal layer 183 is provided between the first flip chip 120 and the first upright chip 161. The chip packaging structure 100 also includes a shielding layer 182 and a third electrical connection column 181. The shielding layer 182 is grounded. In this embodiment, the shielding layer 182 is a metal layer arranged on the surface of the plastic package 152, and can be formed by sputtering metal on the upper surface and the surrounding side of the plastic package 152. A grounding wiring is provided in the substrate 110 and extends to the side wall to connect with the shielding layer 182.

[0056] The third electrical connection pillar 181 is arranged in a direction perpendicular to the substrate 110. One end of the third electrical connection pillar 181 is connected to the first metal layer 183, and the other end is connected to the shielding layer 182. In this way, the first metal layer 183 can be used as an electrostatic release layer to guide the electrostatic ions to the shielding layer 182 for release. In addition, this structure can also achieve electromagnetic shielding of the entire packaging structure, and can also achieve partitioned electromagnetic shielding of the chips on both sides of the third electrical connection pillar 181. It is also beneficial to improve the heat dissipation performance of the overall structure.

[0057] Optionally, the side of the first metal layer 183 away from the substrate 110 is covered with a glue layer 184. The glue layer 184 can realize the mounting and fixing of the first front-mounted chip 161, and the third electrical connection column 181 passes through the glue layer 184 to be electrically connected to the first metal layer 183. That is, the first metal layer 183 is arranged below the glue layer 184, so as to avoid the fracture or void of the glue layer 184 caused by electromigration.

[0058] In this embodiment, the plastic package 152 covers the first flip chip 120, the second flip chip 130, the third flip chip 140 and the first front-mounted chip 161. It should be noted that the ground pad on the first front-mounted chip 161 is wire-bonded to the substrate 110, and the first front-mounted chip 161 is also provided with an electrostatic pad. An electrostatic channel 163 is formed between the first front-mounted chip 161 and the second flip chip 130. The electrostatic ions are led out along the electrostatic channel 163 to the ground pad or the first metal layer 183 to achieve the effect of electrostatic release.

[0059] Combination Figure 6 The embodiment of the present invention further provides a packaging method for preparing the aforementioned chip packaging structure 100. The packaging method is generally as follows: A substrate 110 is provided. The substrate 110 may be a base plate or a lead frame, or a substrate 110 made of an organic wiring layer, a silicon base or a germanium base. Functional pads and ground pads are designed on the substrate 110. A first flip chip 120, a second flip chip 130, and a third flip chip 140 are sequentially mounted on the substrate 110. Each flip chip is reflow soldered with a functional pad on the substrate 110 through a bottom bump or an electrical connection column. A bottom filling glue 151 is formed by a dispensing process, and the bottom filling glue 151 is used to protect the welding structure at the bottom of the chip. A plastic encapsulation body 152 is formed by a plastic encapsulation process, and the plastic encapsulation body 152 is used to protect the entire stacking structure. A ball planting process is used again to form solder balls 190 on the back of the substrate 110. Finally, a cutting process is used to cut and separate the package structure into single products to complete the process.

[0060] Optional, Figure 5 The packaging method of the structure shown is roughly as follows: Combination Figure 7 and Figure 8 A substrate 110 is provided, and a first flip chip 120 is mounted on the substrate 110. A first metal layer 183 is formed on a side of the first flip chip 120 away from the substrate 110.

[0061] A vertical metal pillar, ie, a third electrical connection pillar 181 , is formed on the first metal layer 183 .

[0062] A glue layer 184 is applied to the side of the first flip chip 120 away from the substrate 110, and the first face-up chip 161 is mounted. The first face-up chip 161 and the substrate 110 are connected by wire bonding.

[0063] The second flip chip 130 and the third flip chip 140 are stacked and mounted in sequence. Optionally, after mounting the second flip chip 130, the second front-mounted chip 165 may be mounted according to actual conditions. In some embodiments, the second front-mounted chip 165 may also be omitted.

[0064] Fill the bottom filling glue 151, and then perform plastic packaging. After plastic packaging, grind the upper surface of the plastic packaging body 152 to expose the third electrical connection column 181. Plant the ball, and then cut and separate into single products.

[0065] The surface of a single product is metal sputtered to form a shielding layer 182. The shielding layer 182 is electrically connected to the third electrical connection column 181 exposed on the surface of the plastic package body 152. The packaging process is completed.

[0066] Optional, Figure 4 The packaging method of the structure shown is roughly as follows: Combination Fig. 9 , a substrate 110 is provided, and a first flip chip 120 is mounted on the substrate 110 .

[0067] A glue layer 184 is applied to the side of the first flip chip 120 away from the substrate 110, and the first face-up chip 161 is mounted. The first face-up chip 161 and the substrate 110 are connected by wire bonding.

[0068] The second flip chip 130 is stacked and mounted on the first front-mounted chip 161, and an electrostatic channel 163 is formed between the second flip chip 130 and the first front-mounted chip 161. The second flip chip 130 is connected to the substrate 110 through the first electrical connection column 131.

[0069] The second flip chip 130 is mounted with the second face-up chip 165. The third flip chip 140 is mounted with the second face-up chip 165. An electrostatic channel 163 is formed between the third flip chip 140 and the second face-up chip 165.

[0070] The bridge chip 171 is mounted on two adjacent second front-mounted chips 165 .

[0071] The bottom filling glue 151 is formed by dispensing. The plastic packaging body 152 is formed by plastic packaging. The ball is planted on the back side of the substrate 110.

[0072] An opening is formed on the plastic package 152, and metal is electroplated to form a fourth electrical connection column 172. A wiring layer 173 is formed on the surface of the plastic package 152, and the wiring layer 173 is electrically connected to the fourth electrical connection column 172. A surface chip 174 is mounted on the wiring layer 173.

[0073] Cut and separate into individual products. Complete the process.

[0074] In this embodiment, the first electrical connection pillar 131 , the second electrical connection pillar 141 , the third electrical connection pillar 181 and the fourth electrical connection pillar 172 are respectively made of metal pillars, such as copper pillars, etc., which are not specifically limited here.

[0075] In summary, the chip packaging structure 100 and packaging method provided by the embodiment of the present invention have the following beneficial effects: In the chip packaging structure 100 provided by the embodiment of the present invention, a plurality of flip chips are stacked on a substrate 110, and each flip chip is electrically connected to the substrate 110. Each flip chip is provided with a column and an electrical connection column for connecting to the substrate 110. There is a gap between the column and the substrate 110. In this way, the column can be used to enhance the capillary action of the bottom filling glue 151, which is beneficial to the flow of the colloid and improves the filling property of the colloid, reduces the risk of voids or cracks in the bottom filling glue 151 under the electromigration phenomenon, improves the reliability of the packaging structure, and is also beneficial to improve the heat dissipation performance.

[0076] The first flip chip 120 is mounted with the first front chip 161, and the second flip chip 130 is stacked on the first front chip 161. An electrostatic channel 163 can be formed between the second flip chip 130 and the first front chip 161 to discharge static electricity. By providing the shielding layer 182 and the third electrical connection column 181, the technical effects of electromagnetic shielding and partition shielding can be achieved.

[0077] The packaging method provided in the embodiment of the present invention is used to prepare the above-mentioned chip packaging structure 100 to improve the reliability of the packaging structure.

[0078] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or make equivalent replacements for some or all of the technical features therein. Any modifications, equivalent replacements, improvements, etc. made should be included in the protection scope of the present invention.

Claims

1. A chip packaging structure, characterized in that: include: substrate; A first flip chip; the first flip chip is attached to the substrate and electrically connected to the substrate; a second flip chip, the second flip chip being at least partially mounted to the first flip chip; the second flip chip being provided with a first electrical connection column, the first electrical connection column being electrically connected to the substrate; the second flip chip being provided with a first column; a third flip chip, the third flip chip being at least partially mounted to the second flip chip; the third flip chip being provided with a second electrical connection column, the second electrical connection column being electrically connected to the substrate; the third flip chip being provided with a second column; The first pillar is located between the first electrical connection pillar and the first flip chip, and there is a distance between the first pillar and the substrate; The second pillar is located between the second electrical connection pillar and the second flip chip, and there is a distance between the second pillar and the substrate.

2. The chip packaging structure according to claim 1, characterized in that: One end of the first column away from the second flip chip is lower than or flush with a side surface of the first flip chip close to the substrate; And / or, one end of the second pillar away from the third flip chip is lower than a side surface of the second flip chip close to the substrate.

3. The chip packaging structure according to claim 2, characterized in that: The distance of the second pillar below a surface of the second flip chip close to the substrate is greater than or equal to half the height of the first pillar.

4. The chip packaging structure according to claim 1, characterized in that: A third column is also provided on the side of the second flip chip provided with the first column; the third column is mounted on the side of the first flip chip away from the substrate; A fourth column is also provided on the side of the third flip chip where the second column is provided; the fourth column is mounted on a side of the second flip chip away from the substrate.

5. The chip packaging structure according to claim 4, characterized in that: The second flip chip is provided with a first passivation layer, and the first pillar and the third pillar are connected to the first passivation layer; The third flip chip is provided with a second passivation layer, and the second column and the fourth column are connected to the second passivation layer.

6. The chip packaging structure according to claim 4, characterized in that: A first upright chip is mounted on a side of the first flip chip away from the substrate; the second flip chip is at least partially mounted on the first upright chip; The first front-mounted chip is provided with a first grounding pad, the substrate is provided with a second grounding pad, and the first grounding pad and the second grounding pad are connected by wire bonding; A gap is provided between the third pillar and the first front-mounted chip to form an electrostatic channel.

7. The chip packaging structure according to claim 6, characterized in that: A second front-mounted chip is mounted on a side of the second flip chip away from the substrate; the third flip chip is at least partially mounted on the second front-mounted chip; The second front-mounted chip is provided with a third ground pad, and the third ground pad is wire-bonded to the first ground pad; A gap is provided between the fourth pillar and the second front-mounted chip to form an electrostatic channel.

8. The chip packaging structure according to claim 7, characterized in that: It also includes a bridge chip, the second flip chips include at least two, each of the second flip chips is provided with the second front-mounted chip; the bridge chip is electrically connected to the two second front-mounted chips respectively.

9. The chip packaging structure according to claim 8, characterized in that: It also includes a fourth electrical connection column and a surface chip; the third flip chip is provided with a wiring layer on the side away from the substrate, and the surface chip is mounted on the wiring layer; one end of the fourth electrical connection column is electrically connected to the wiring layer, and the other end is electrically connected to the second face-up chip.

10. The chip packaging structure according to claim 6, characterized in that: A first metal layer is provided between the first flip chip and the first face-up chip; The chip packaging structure also includes a plastic package, a shielding layer and a third electrical connection column; the plastic package covers the first flip chip, the second flip chip, the third flip chip and the first face-up chip; the shielding layer is grounded; one end of the third electrical connection column is connected to the first metal layer, and the other end is connected to the shielding layer.

11. The chip packaging structure according to claim 10, characterized in that: A side of the first metal layer away from the substrate is covered with a glue layer; the third electrical connection column passes through the glue layer and is electrically connected to the first metal layer.

12. A packaging method, characterized in that: Used to prepare a chip packaging structure as claimed in any one of claims 1 to 11.

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