Chip Packaging Structure and Packaging Method

Abstract

A chip packaging structure and a packaging method provided by the present application relate to the field of semiconductor packaging technology. In this chip packaging structure, a first flip chip is mounted on a substrate and electrically connected to the substrate. A second flip chip is at least partially mounted on the first flip chip. The second flip chip is provided with a first electrical connection post, and the first electrical connection post is electrically connected to the substrate; the second flip chip is provided with a first column. A third flip chip is at least partially mounted on the second flip chip; the third flip chip is provided with a second electrical connection post, and the second electrical connection post is electrically connected to the substrate; the third flip chip is provided with a second column. The first column is located between the first electrical connection post and the first flip chip, and there is a spacing between the first column and the substrate. The second column is located between the second electrical connection post and the second flip chip, and there is a spacing between the second column and the substrate. This packaging structure is beneficial to improving the fluidity and filling property of the bottom colloid, and preventing the colloid from cracking or having voids.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and particularly to a chip packaging structure and a packaging method. Background Art

[0002] With the rapid development of the semiconductor industry, most use a flip-chip stacked hybrid packaging structure to meet the requirements of multi-functionality and miniaturization of electronic packaging products. As the stacking density continues to increase, the size of the solder joints of flip chips becomes smaller and the height of the copper pillars of flip chips becomes higher. The current density borne by the copper pillars and solder joints and the working temperature of the solder joints increase sharply, resulting in electromigration phenomena inside the copper pillars and solder joints. The electromigration phenomenon is an atomic migration phenomenon caused by the continuous inelastic collision of high-density electron flow with atoms in the solder joints. The electromigration phenomenon will cause the formation of hillocks and voids in the interconnect solder joints, and the interface layer of the underfill layer is affected by the electromigration phenomenon. When the current and temperature gradient are larger, it not only triggers the electromigration effect but also easily leads to defects such as dissolution of the compound in the interface layer of the adhesive layer and fracture of the adhesive layer, thereby causing damage to the integrity of the adhesive layer welding structure and degradation of mechanical properties, resulting in device failure. Summary of the Invention

[0003] The purpose of the present invention is to provide a chip packaging structure and a packaging method to alleviate defects such as dissolution and fracture of the underfill caused by the electromigration phenomenon and improve the reliability of the packaging structure.

[0004] In a first aspect, the present invention provides a chip packaging structure, including:

[0005] A substrate;

[0006] A first flip chip; the first flip chip is mounted on the substrate and electrically connected to the substrate;

[0007] A second flip chip, at least part of the second flip chip is mounted on the first flip chip; the second flip chip is provided with a first electrical connection column, and the first electrical connection column is electrically connected to the substrate; the second flip chip is provided with a first column;

[0008] A third flip chip, at least part of the third flip chip is mounted on the second flip chip; the third flip chip is provided with a second electrical connection column, and the second electrical connection column is electrically connected to the substrate; the third flip chip is provided with a second column;

[0009] The first column is located between the first electrical connection column and the first flip chip, and there is a spacing between the first column and the substrate;

[0010] The second column is located between the second electrical connection column and the second flip chip, and there is a spacing between the second column and the substrate.

[0011] In an alternative embodiment, one end of the first column away from the second flip chip is lower than or flush with a side surface of the first flip chip close to the substrate;

[0012] and / or, one end of the second column away from the third flip chip is lower than a side surface of the second flip chip close to the substrate.

[0013] In an alternative embodiment, the distance by which the second column is lower than a side surface of the second flip chip close to the substrate is greater than or equal to half of the height of the first column.

[0014] In an alternative embodiment, a third column is further provided on a side of the second flip chip where the first column is provided; the third column is mounted on a side of the first flip chip away from the substrate;

[0015] A fourth column is further provided on a side of the third flip chip where the second column is provided; the fourth column is mounted on a side of the second flip chip away from the substrate.

[0016] In an alternative embodiment, the second flip chip is provided with a first passivation layer, and the first column and the third column are connected to the first passivation layer;

[0017] The third flip chip is provided with a second passivation layer, and the second column and the fourth column are connected to the second passivation layer.

[0018] In an alternative embodiment, a first front-mounted chip is mounted on a side of the first flip chip away from the substrate; at least a part of the second flip chip is mounted on the first front-mounted chip;

[0019] The first front-mounted chip is provided with a first ground pad, the substrate is provided with a second ground pad, and the first ground pad and the second ground pad are wire-bonded;

[0020] A gap is provided between the third column and the first front-mounted chip to form an electrostatic channel.

[0021] In an alternative embodiment, a second front-mounted chip is mounted on a side of the second flip chip away from the substrate; at least a part of the third flip chip is mounted on the second front-mounted chip;

[0022] The second front-mounted chip is provided with a third ground pad, and the third ground pad and the first ground pad are wire-bonded;

[0023] A gap is provided between the fourth cylinder and the second front-mounted chip to form an electrostatic channel.

[0024] In an alternative embodiment, a bridging chip is further included. There are at least two second flip chips, and each second flip chip is provided with a second front-mounted chip; the bridging chip is electrically connected to the two second front-mounted chips respectively.

[0025] In an alternative embodiment, a fourth electrical connection column and a surface layer chip are further included; a wiring layer is provided on a side of the third flip chip away from the substrate, and the surface layer chip is mounted on the wiring layer; one end of the fourth electrical connection column is electrically connected to the wiring layer, and the other end is electrically connected to the second front-mounted chip.

[0026] In an alternative embodiment, a first metal layer is provided between the first flip chip and the first front-mounted chip;

[0027] The chip packaging structure further includes a plastic package, a shielding layer, and a third electrical connection column; the plastic package covers the first flip chip, the second flip chip, the third flip chip, and the first front-mounted chip; the shielding layer is grounded; one end of the third electrical connection column is connected to the first metal layer, and the other end is connected to the shielding layer.

[0028] In an alternative embodiment, an adhesive layer is covered on a side of the first metal layer away from the substrate; the third electrical connection column passes through the adhesive layer and is electrically connected to the first metal layer.

[0029] In a second aspect, the present invention provides a packaging method for preparing the chip packaging structure according to any one of the foregoing embodiments.

[0030] The chip packaging structure and the packaging method provided by the embodiments of the present invention have the following beneficial effects:

[0031] For the chip packaging structure provided by the embodiments of the present invention, a plurality of flip chips are stacked on the substrate, and each flip chip is electrically connected to the substrate. Each flip chip is provided with a cylinder and an electrical connection column for connecting to the substrate. There is a spacing between the cylinder and the substrate. In this way, the capillary action of the underfill can be enhanced by using the cylinder, which is beneficial to the flow of the colloid and improves the filling property of the colloid, reduces the risk of voids or cracks in the underfill under the phenomenon of electromigration, and improves the reliability of the packaging structure.

[0032] The packaging method provided by the embodiments of the present invention is used to prepare the above chip packaging structure, which improves the reliability of the packaging structure. Description of the Drawings

[0033] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0034] Figure 1 The first structural schematic diagram of the chip packaging structure provided by the embodiment of the present invention;

[0035] Figure 2 The second structural schematic diagram of the chip packaging structure provided by the embodiment of the present invention;

[0036] Figure 3 The third structural schematic diagram of the chip packaging structure provided by the embodiment of the present invention;

[0037] Figure 4 The fourth structural schematic diagram of the chip packaging structure provided by the embodiment of the present invention;

[0038] Figure 5 The fifth structural schematic diagram of the chip packaging structure provided by the embodiment of the present invention;

[0039] Figure 6 The process schematic diagram of the chip packaging structure provided by the embodiment of the present invention;

[0040] Figure 7 Provided by the embodiment of the present invention Figure 5 One of the process schematic diagrams of the chip packaging structure shown;

[0041] Figure 8 Provided by the embodiment of the present invention Figure 5 Two of the process schematic diagrams of the chip packaging structure shown;

[0042] Figure 9 Provided by the embodiment of the present invention Figure 4 The process schematic diagram of the chip packaging structure shown.

[0043] Icons: 100 - Chip packaging structure; 110 - Substrate; 111 - Second ground pad; 120 - First flip chip; 130 - Second flip chip; 131 - First electrical connection post; 132 - First pillar; 133 - Third pillar; 134 - First passivation layer; 140 - Third flip chip; 141 - Second electrical connection post; 142 - Second pillar; 143 - Fourth pillar; 144 - Second passivation layer; 151 - Underfill; 152 - Encapsulant; 161 - First front-mounted chip; 162 - First ground pad; 163 - Electrostatic channel; 165 - Second front-mounted chip; 166 - Third ground pad; 171 - Bridging chip; 172 - Fourth electrical connection post; 173 - Wiring layer; 174 - Surface chip; 181 - Third electrical connection post; 182 - Shielding layer; 183 - First metal layer; 184 - Adhesive layer; 190 - Solder ball. Detailed implementation manners

[0044] To make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Apparently, the described embodiments are some but not all of the embodiments of the present invention. The components of the embodiments of the present invention usually described and illustrated in the accompanying drawings here can be arranged and designed in various different configurations.

[0045] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed present invention, but merely represents selected embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the scope of protection of the present invention.

[0046] It should be noted that: Similar reference numerals and letters denote similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0047] In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of the present invention is usually placed during use. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be construed as a limitation of the present invention. In addition, the terms "first", "second", "third", etc. are only used for descriptive distinction and cannot be construed as indicating or implying relative importance.

[0048] In addition, terms such as "horizontal", "vertical", "overhanging", etc. do not require the components to be absolutely horizontal or overhanging, but can be slightly inclined. For example, "horizontal" only means that its direction is more horizontal relative to "vertical", and does not mean that the structure must be completely horizontal, but can be slightly inclined.

[0049] In the description of the present invention, it should also be noted that, unless otherwise clearly specified and limited, the terms "arranged", "installed", "connected", and "coupled" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and can be the communication inside two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

[0050] The following will describe in detail some embodiments of the present invention with reference to the accompanying drawings. Without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0051] In a stacked package structure in the semiconductor field, when the current density and the solder joint working temperature borne by the copper pillar solder joints increase sharply, it is easy to cause electromigration phenomena inside the copper pillar solder joints. Electromigration not only damages the structure of the copper pillar solder joints, but also can trigger defects such as dissolution of the interfacial layer compound of the underfill layer and fracture of the underfill layer, thereby resulting in damage to the integrity of the solder joint structure protected by the underfill and degradation of the mechanical properties. And in the stacked package structure, as the height of the chip copper pillars increases, the contact area between the underfill and the copper pillars increases, and the electromigration phenomenon becomes more obvious. The fluidity of the underfill layer becomes poor due to the thermoelectric effect, resulting in voids in the underfill. And when affected by electromigration, problems such as fracture of the underfill layer are likely to occur at the voids of the underfill layer, affecting the packaging reliability.

[0052] A chip package structure and a packaging method proposed by an embodiment of the present invention can improve the flow of the underfill and the filling property of the colloid, reduce the risk of dissolution, voids or cracking of the underfill under the electromigration phenomenon, and improve the reliability of the package structure.

[0053] Combined Figure 1 , an embodiment of the present invention provides a chip package structure 100, including a substrate 110, a first flip chip 120, a second flip chip 130, a third flip chip 140, and an underfill 151.

[0054] The first flip chip 120 is mounted on the substrate 110 and is electrically connected to the substrate 110. The bumps at the bottom of the first flip chip 120 are soldered to the pads on the substrate 110 to achieve electrical connection.

[0055] The second flip chip 130 is at least partially mounted to the first flip chip 120. The second flip chip 130 is provided with a first electrical connection post 131, and the first electrical connection post 131 is electrically connected to the substrate 110. The first flip chip 120 and the second flip chip 130 are partially stacked, with a part of the second flip chip 130 stacked on the first flip chip 120 and another part extending outside the first flip chip 120. The part extending outside the first flip chip 120 is provided with the first electrical connection post 131, and the first electrical connection post 131 is directly welded to the pad on the substrate 110. On the side of the second flip chip 130 where the first electrical connection post 131 is provided, a first column 132 is further provided. The first column 132 is connected to the part of the second flip chip 130 that extends outside the first flip chip 120. The first column 132 is located between the first electrical connection post 131 and the first flip chip 120, and there is a spacing between the first column 132 and the substrate 110.

[0056] The third flip chip 140 is at least partially mounted to the second flip chip 130; the third flip chip 140 is provided with a second electrical connection post 141, and the second electrical connection post 141 is electrically connected to the substrate 110. The third flip chip 140 and the second flip chip 130 are partially stacked, that is, a part of the third flip chip 140 is stacked on the second flip chip 130 and another part extends outside the second flip chip 130. The part extending outside the second flip chip 130 is provided with the second electrical connection post 141, and the second electrical connection post 141 is directly welded to the pad on the substrate 110. It should be understood that in the stacking height direction, the length of the second electrical connection post 141 is greater than the length of the first electrical connection post 131.

[0057] On the side of the third flip chip 140 where the second electrical connection post 141 is provided, a second column 142 is further provided. The second column 142 is located between the second electrical connection post 141 and the second flip chip 130, and there is a spacing between the second column 142 and the substrate 110.

[0058] The underfill 151 protects the pads on the substrate 110, the first electrical connection post 131, the second electrical connection post 141, the bumps at the bottom of the first flip chip 120, and the welding structure, etc. By providing the first column 132 and the second column 142, it is beneficial to improve the fluidity and filling performance of the underfill 151, and the filling is more complete. In this way, even when electromigration occurs, the underfill 151 is not easily dissolved, cracked or have voids. In addition, it is also beneficial to improve the heat dissipation performance.

[0059] It is easy to understand that the stacking structure in this embodiment adopts horizontal expansion stacking, that is, a part of each layer of flip chip is stacked on the lower chip, and the other part extends outside the lower chip, and electrical connection posts and columns are provided on the extended part. The electrical connection posts are used to directly weld to the substrate 110, that is, each flip chip is directly welded to the substrate 110. In this way, the higher the stacking height, the longer the corresponding length of the electrical connection posts. For the same flip chip, the length of the column is less than the length of the electrical connection post, that is, one end of the column far from the flip chip is suspended, and there is a gap between it and the substrate 110. Such a setting is beneficial to improving the fluidity of the underfill 151, the colloid is filled more completely and evenly, and it is not easy to appear phenomena such as colloid dissolution, cracking or voids. Of course, the setting of the first column 132 and the second column 142 can also play a role in improving the heat dissipation performance.

[0060] In this embodiment, the length of the first column 132 is less than the length of the first electrical connection post 131. The length of the second column 142 is less than the length of the second electrical connection post 141.

[0061] Optionally, one end of the first column 132 far from the second flip chip 130 is lower than or flush with the side surface of the first flip chip 120 close to the substrate 110. In this embodiment, one end of the first column 132 close to the substrate 110 is flush with the lower surface of the first flip chip 120. Here, the lower surface refers to the side surface of the first flip chip 120 where the bottom bumps are provided.

[0062] Optionally, one end of the second column 142 far from the third flip chip 140 is lower than the side surface of the second flip chip 130 close to the substrate 110. That is, one end of the second column 142 close to the substrate 110 is lower than the lower surface of the second flip chip 130. Optionally, the distance that the second column 142 is lower than the side surface of the second flip chip 130 close to the substrate 110 is half of the height of the first column 132. In other words, the distance that one end of the second column 142 close to the substrate 110 extends beyond the lower surface of the second flip chip 130 is H2, the length of the first column 132 is H1, and H2 is greater than or equal to half of H1. Such a setting makes there be a certain height difference at the lower ends of the first column 132 and the second column 142, which is beneficial to enhancing the capillary action of the colloid, improving the fluidity and filling property of the colloid, and is beneficial to heat dissipation.

[0063] Optionally, on the side of the second flip chip 130 where the first pillar 132 is provided, a third pillar 133 is further provided. The third pillar 133 is mounted on the side of the first flip chip 120 away from the substrate 110. On the side of the third flip chip 140 where the second pillar 142 is provided, a fourth pillar 143 is further provided; the fourth pillar 143 is mounted on the side of the second flip chip 130 away from the substrate 110. In other words, the third pillar 133 is provided on the part of the second flip chip 130 stacked on the first flip chip 120, and the fourth pillar 143 is provided on the part of the third flip chip 140 stacked on the second flip chip 130. The provision of the third pillar 133 and the fourth pillar 143 can play a role in heat dissipation and buffering. At the same time, it can also enhance the capillary action of the colloid, improve the fluidity and filling property of the colloid, and further reduce the risk of problems such as cracking and voids in the colloid.

[0064] Optionally, on the side of the second flip chip 130 close to the substrate 110, a first passivation layer 134 is provided, and the first pillar 132 and the third pillar 133 are connected to the first passivation layer 134. There are openings on the first passivation layer 134 to expose the pads at the bottom of the second flip chip 130, so as to facilitate the electrical connection between the first electrical connection pillar 131 and the chip pads and ensure that the first electrical connection pillar 131 can achieve the electrical connection function. In other words, the first pillar 132 and the third pillar 133 do not have electrical connection requirements and do not need to participate in the electrical connection. Similarly, the third flip chip 140 is provided with a second passivation layer 144, and the second pillar 142 and the fourth pillar 143 are connected to the second passivation layer 144. There are openings on the second passivation layer 144 to expose the pads at the bottom of the third flip chip 140, so as to facilitate the connection between the second electrical connection pillar 141 and the chip pads and ensure that the second electrical connection pillar 141 can achieve the electrical connection function. The first passivation layer 134 and the second passivation layer 144 serve as insulating layers to avoid the electromigration phenomenon caused by the thermoelectric effect of the pillars. The first passivation layer 134 and the second passivation layer 144 can be any one or more of silicon dioxide, silicon nitride, silicon oxynitride, polyimide, benzocyclobutene, etc.

[0065] It should be noted that the first pillar 132, the second pillar 142, the third pillar 133, and the fourth pillar 143 can be made of metal or other materials; they can be conductive materials or insulating materials, and no specific limitation is made here. In this embodiment, the first pillar 132, the second pillar 142, the third pillar 133, and the fourth pillar 143 are respectively made of metal. The number of the first pillar 132, the second pillar 142, the third pillar 133, and the fourth pillar 143 can be flexibly set according to the actual situation.

[0066] In some embodiments, only one of the first pillar 132 and the second pillar 142 can be provided. Only one of the third pillar 133 and the fourth pillar 143 can also be provided, or all can be omitted.

[0067] In the chip packaging structure 100, the number of flip chips and the number of stacked layers can be flexibly set according to actual situations. For example, two, three, four, five or more layers can be stacked. The number of chips in each layer can be flexibly designed, such as one, two, three, four or more, which is not specifically limited here.

[0068] Optionally, the chip packaging structure 100 further includes a plastic package 152. The plastic package 152 is disposed on the substrate 110 and is used to cover all the chips, underfill 151, etc. on the substrate 110, playing a protective role. At the same time, it is beneficial to enhance the strength of the packaging structure. Solder balls 190 are provided at the bottom of the substrate 110 for electrical connection with other external modules.

[0069] Combined Figure 2 , optionally, a first front-mounted chip 161 is mounted on the side of the first flip chip 120 away from the substrate 110; at least a part of the second flip chip 130 is mounted on the first front-mounted chip 161. The first front-mounted chip 161 is provided with a first ground pad 162, and the substrate 110 is provided with a second ground pad 111. The first ground pad 162 and the second ground pad 111 are wire-bonded. The number of the first front-mounted chips 161 can be flexibly designed and is not specifically limited.

[0070] Optionally, there is a gap between the third pillar 133 and the first front-mounted chip 161 to form an electrostatic channel 163. It can be understood that a plurality of electrostatic pads are provided on the first front-mounted chip 161, and the plurality of electrostatic pads and the plurality of third pillars 133 are arranged in one-to-one correspondence, and there is a gap between the third pillar 133 and the electrostatic pads. In this way, the electrostatic ions between the chips can be guided by the first pillar 132 to the electrostatic channel 163 and guided along the electrostatic channel 163 to the first ground pad 162, and are released through wire bonding, achieving the purpose of electrostatic dissipation. Of course, all the electrostatic pads can be evenly spaced from the third pillar 133 to form the electrostatic channel 163. Or a part of the electrostatic pads are spaced from the third pillar 133 to form the electrostatic channel 163, and the remaining electrostatic pads are in contact with the third pillar 133. The electrostatic channel 163 is beneficial to improving the mobility of electrostatic ions, guiding the electrostatic ions to the grounding wire bonding for release, or guiding them to the third pillar 133 in contact with the electrostatic pads for release. It can be understood that the electrostatic pads in contact with the third pillar 133 have grounding characteristics and can complete electrostatic release. In this embodiment, a part of the third pillars 133 are in contact with the electrostatic pads, which can increase the grounding reliability, ensure that the static electricity is released, avoid the chips, etc. from being interfered or damaged by static electricity, and can also mitigate the influence of the thermoelectric effect on the reliability of the packaging structure.

[0071] Since it is necessary to guide the release of static ions, the first column 132 and the third column 133 are respectively made of metal columns. Of course, other conductive materials such as conductive colloids can also be used as long as they can adsorb and guide static electricity.

[0072] Combined Figure 3 , optionally, on the side of the second flip chip 130 away from the substrate 110, a second front-mounted chip 165 is mounted. At least part of the third flip chip 140 is mounted on the second front-mounted chip 165. The second front-mounted chip 165 is provided with a third ground pad 166, and the third ground pad 166 is wire-bonded to the first ground pad 162, which can shorten the wire-bonding path. There is a gap between the fourth column 143 and the second front-mounted chip 165 to form an electrostatic channel 163. In this way, the electrostatic channel 163 is beneficial to improving the mobility of static ions. The first column 132 and the second column 142 respectively guide the static ions between the chips to the electrostatic channel 163 and flow along the electrostatic channel 163 to the wire-bonding arc. Due to the grounding property of the wire-bonding arc, the function of static electricity release is achieved. The design of the electrostatic channel 163 between the second front-mounted chip 165 and the third flip chip 140 is similar to the design of the electrostatic channel 163 between the first front-mounted chip 161 and the second flip chip 130, which will not be elaborated here.

[0073] Since it is necessary to guide the release of static ions, the second column 142 and the fourth column 143 are respectively made of metal columns. Of course, other conductive materials such as conductive colloids can also be used as long as they can adsorb and guide static electricity.

[0074] Combined Figure 4 , optionally, the chip packaging structure 100 further includes a bridging chip 171, a fourth electrical connection column 172, and a surface layer chip 174. There are at least two second flip chips 130, and each second flip chip 130 is provided with a second front-mounted chip 165. That is, there are at least two second front-mounted chips 165. The bridging chip 171 is electrically connected to the two second front-mounted chips 165 respectively. The two second front-mounted chips 165 are arranged at intervals, one end of the bridging chip 171 is electrically connected to one of the second front-mounted chips 165, and the other end is electrically connected to the other second front-mounted chip 165. In this embodiment, the bridging chip 171 is a flip chip. Such a setting makes the structure compact and the chip integration degree high.

[0075] Optionally, on the side of the third flip chip 140 away from the substrate 110, a wiring layer 173 is provided, and the surface layer chip 174 is mounted on the wiring layer 173. The surface layer chip 174 can be a front-mounted chip or a flip chip, and the number of the surface layer chips 174 can be one or more, which is not specifically limited here. It can be understood that a dielectric layer is coated on the surface of the plastic package 152, and the wiring layer 173 is formed through processes such as exposure and development.

[0076] One end of the fourth electrical connection pillar 172 is electrically connected to the wiring layer 173, and the other end is electrically connected to the second front-mounted chip 165. With this arrangement, the indirect electrical connection between the upper wiring layer 173, the surface chip 174, and the underlying substrate 110 can be achieved. Compared with the structure in which the upper wiring layer 173 is directly connected to the substrate 110 through an electrical connection pillar, the fourth electrical connection pillar 172 has a shorter length, a shorter transmission path, higher transmission efficiency, and lower transmission loss.

[0077] It can be understood that the number of the fourth electrical connection pillars 172 is multiple. A part of the fourth electrical connection pillars 172 is used to achieve the functional electrical connection between the second front-mounted chip 165 and the wiring layer 173, and another part of the fourth electrical connection pillars 172 serves as an electrostatic guiding pillar and is connected to the grounding line on the second front-mounted chip 165, which can adsorb and guide the static electricity in the wiring layer 173 and between the surface chips 174 to complete the static electricity release of the wiring layer 173 and the surface chip 174.

[0078] Combined Figure 5 Optionally, one or more first front-mounted chips 161 are stacked on the first flip-chip 120. A first metal layer 183 is provided between the first flip-chip 120 and the first front-mounted chip 161. The chip packaging structure 100 further includes a shielding layer 182 and a third electrical connection pillar 181. The shielding layer 182 is grounded. In this embodiment, the shielding layer 182 is a metal layer provided on the surface of the plastic package 152 and can be formed by sputtering metal on the upper surface and the peripheral side surface of the plastic package 152. A grounding wiring is provided in the substrate 110 and extends to the side wall to be connected to the shielding layer 182.

[0079] The third electrical connection pillar 181 is arranged in a direction perpendicular to the substrate 110. One end of the third electrical connection pillar 181 is connected to the first metal layer 183, and the other end is connected to the shielding layer 182. In this way, the first metal layer 183 can serve as an electrostatic release layer to guide the static electricity ions to the shielding layer 182 for release. In addition, this structure can also achieve the electromagnetic shielding of the entire packaging structure and the partition electromagnetic shielding of the chips on both sides of the third electrical connection pillar 181. It is also beneficial to improve the heat dissipation performance of the overall structure.

[0080] Optionally, an adhesive layer 184 is covered on the side of the first metal layer 183 away from the substrate 110. The adhesive layer 184 can achieve the mounting and fixing of the first front-mounted chip 161, and the third electrical connection pillar 181 passes through the adhesive layer 184 and is electrically connected to the first metal layer 183. That is, the first metal layer 183 is provided below the adhesive layer 184, thus avoiding the fracture or void of the adhesive layer 184 caused by electromigration.

[0081] In this embodiment, the plastic package 152 encapsulates the first flip chip 120, the second flip chip 130, the third flip chip 140, and the first through-chip 161. It should be noted that the ground pad on the first through-chip 161 is wire-bonded to the substrate 110. The first through-chip 161 is also provided with an electrostatic pad. An electrostatic channel 163 is formed between the first through-chip 161 and the second flip chip 130. Electrostatic ions are led out along the electrostatic channel 163 to the ground pad or the first metal layer 183 to achieve the function of electrostatic discharge.

[0082] Combined with Figure 6 , an embodiment of the present invention also provides a packaging method for preparing the aforementioned chip packaging structure 100. The packaging method is generally as follows:

[0083] Provide a substrate 110. The substrate 110 can be a substrate or a lead frame, or a substrate 110 made of an organic wiring layer, silicon-based, or germanium-based, etc. Among them, functional pads and ground pads are designed on the substrate 110. The first flip chip 120, the second flip chip 130, and the third flip chip 140 are sequentially mounted on the substrate 110. Each flip chip is reflow soldered to the functional pads on the substrate 110 through bottom bumps or electrical connecting posts. A bottom fill 151 is formed by a dispensing process to protect the solder joints at the bottom of the chips. A plastic package 152 is formed by a plastic encapsulation process to protect the entire stacked structure. The ball mounting process is used again to form solder balls 190 on the back of the substrate 110. Finally, the packaging structure is separated into individual products by a dicing process to complete the manufacturing process.

[0084] Optionally, Figure 5 The packaging method of the structure shown is generally as follows:

[0085] Combined with Figure 7 and Figure 8 , provide a substrate 110, and mount the first flip chip 120 on the substrate 110. A first metal layer 183 is formed on the side of the first flip chip 120 away from the substrate 110.

[0086] Vertical metal posts, that is, the third electrical connecting posts 181, are formed on the first metal layer 183.

[0087] A glue layer 184 is coated on the side of the first flip chip 120 away from the substrate 110, and the first through-chip 161 is mounted. The first through-chip 161 is wire-bonded to the substrate 110.

[0088] The second flip chip 130 and the third flip chip 140 are sequentially stacked and mounted horizontally. Optionally, after mounting the second flip chip 130, the second through-chip 165 can be mounted according to the actual situation. In some embodiments, the second through-chip 165 can also be omitted.

[0089] Fill the bottom underfill 151 and perform plastic encapsulation. After plastic encapsulation, grind the upper surface of the plastic encapsulated body 152 to expose the third electrical connection post 181. Solder ball implantation is carried out, and then it is cut and separated into single products.

[0090] Perform surface metal sputtering on the single product to form a shielding layer 182. The shielding layer 182 is electrically connected to the third electrical connection post 181 exposed on the surface of the plastic encapsulated body 152. The encapsulation process is completed.

[0091] Optionally, Figure 4 The encapsulation method of the shown structure is generally as follows:

[0092] Combine Figure 9 , provide a substrate 110, and mount the first flip chip 120 on the substrate 110.

[0093] Coat an adhesive layer 184 on the side of the first flip chip 120 away from the substrate 110, and mount the first front-mounted chip 161. The first front-mounted chip 161 and the substrate 110 are wire-bonded.

[0094] Stack and mount the second flip chip 130 on the first front-mounted chip 161. An electrostatic channel 163 is formed between the second flip chip 130 and the first front-mounted chip 161. The second flip chip 130 is connected to the substrate 110 through the first electrical connection post 131.

[0095] Mount the second front-mounted chip 165 on the second flip chip 130. Mount the third flip chip 140 on the second front-mounted chip 165. An electrostatic channel 163 is formed between the third flip chip 140 and the second front-mounted chip 165.

[0096] Mount the bridging chip 171 on two adjacent second front-mounted chips 165.

[0097] Apply glue to form the bottom underfill 151. Perform plastic encapsulation to form the plastic encapsulated body 152. Solder balls are implanted on the back of the substrate 110.

[0098] Open an opening on the plastic encapsulated body 152, electroplate metal to form the fourth electrical connection post 172. Fabricate a wiring layer 173 on the surface of the plastic encapsulated body 152, and the wiring layer 173 is electrically connected to the fourth electrical connection post 172. Mount the surface chip 174 above the wiring layer 173.

[0099] Cut and separate into single products. The process is completed.

[0100] In this embodiment, the first electrical connection post 131, the second electrical connection post 141, the third electrical connection post 181, and the fourth electrical connection post 172 are respectively made of metal posts, such as copper posts, etc., which are not specifically limited here.

[0101] In summary, the chip encapsulation structure 100 and the encapsulation method provided by the embodiments of the present invention have the following beneficial effects:

[0102] For the chip packaging structure 100 provided by an embodiment of the present invention, a plurality of flip chips are stacked on a substrate 110, and each flip chip is electrically connected to the substrate 110. Each flip chip is provided with a column and an electrical connection column for connecting to the substrate 110. There is a spacing between the column and the substrate 110. In this way, the capillary action of the underfill 151 can be enhanced by using the column, which is beneficial to the flow of the colloid and improves the filling performance of the colloid, reduces the risk of voids or cracks in the underfill 151 under the phenomenon of electromigration, improves the reliability of the packaging structure, and is also beneficial to improving the heat dissipation performance.

[0103] A first front-mounted chip 161 is mounted on the first flip chip 120, and the second flip chip 130 is stacked on the first front-mounted chip 161. An electrostatic channel 163 can be formed between the second flip chip 130 and the first front-mounted chip 161 to play a role in electrostatic discharge. And by providing a shielding layer 182 and a third electrical connection column 181, technical effects of electromagnetic shielding and partition shielding can be achieved.

[0104] The packaging method provided by an embodiment of the present invention is used to prepare the above-mentioned chip packaging structure 100 to improve the reliability of the packaging structure.

[0105] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; any modifications, equivalent replacements, improvements, etc. should be included within the protection scope of the present invention.

Claims

1. A chip packaging structure, characterized in that: include: substrate; A first flip chip; the first flip chip is attached to the substrate and electrically connected to the substrate; a second flip chip, the second flip chip being at least partially mounted to the first flip chip; the second flip chip being provided with a first electrical connection column, the first electrical connection column being electrically connected to the substrate; the second flip chip being provided with a first column; a third flip chip, the third flip chip being at least partially mounted to the second flip chip; the third flip chip being provided with a second electrical connection column, the second electrical connection column being electrically connected to the substrate; the third flip chip being provided with a second column; The first pillar is located between the first electrical connection pillar and the first flip chip, and there is a distance between the first pillar and the substrate; The second pillar is located between the second electrical connection pillar and the second flip chip, and there is a distance between the second pillar and the substrate.

2. The chip packaging structure according to claim 1, characterized in that: One end of the first column away from the second flip chip is lower than or flush with a side surface of the first flip chip close to the substrate; And / or, one end of the second pillar away from the third flip chip is lower than a side surface of the second flip chip close to the substrate.

3. The chip packaging structure according to claim 2, characterized in that: The distance of the second pillar below a surface of the second flip chip close to the substrate is greater than or equal to half the height of the first pillar.

4. The chip packaging structure according to claim 1, characterized in that: A third column is also provided on the side of the second flip chip provided with the first column; the third column is mounted on the side of the first flip chip away from the substrate; A fourth column is also provided on the side of the third flip chip where the second column is provided; the fourth column is mounted on a side of the second flip chip away from the substrate.

5. The chip packaging structure according to claim 4, characterized in that: The second flip chip is provided with a first passivation layer, and the first pillar and the third pillar are connected to the first passivation layer; The third flip chip is provided with a second passivation layer, and the second column and the fourth column are connected to the second passivation layer.

6. The chip packaging structure according to claim 4, characterized in that: A first upright chip is mounted on a side of the first flip chip away from the substrate; the second flip chip is at least partially mounted on the first upright chip; The first front-mounted chip is provided with a first grounding pad, the substrate is provided with a second grounding pad, and the first grounding pad and the second grounding pad are connected by wire bonding; A gap is provided between the third pillar and the first front-mounted chip to form an electrostatic channel.

7. The chip packaging structure according to claim 6, characterized in that: A second front-mounted chip is mounted on a side of the second flip chip away from the substrate; the third flip chip is at least partially mounted on the second front-mounted chip; The second front-mounted chip is provided with a third ground pad, and the third ground pad is wire-bonded to the first ground pad; A gap is provided between the fourth pillar and the second front-mounted chip to form an electrostatic channel.

8. The chip packaging structure according to claim 7, characterized in that: It also includes a bridge chip, the second flip chips include at least two, each of the second flip chips is provided with the second front-mounted chip; the bridge chip is electrically connected to the two second front-mounted chips respectively.

9. The chip packaging structure according to claim 8, characterized in that: It also includes a fourth electrical connection column and a surface chip; the third flip chip is provided with a wiring layer on the side away from the substrate, and the surface chip is mounted on the wiring layer; one end of the fourth electrical connection column is electrically connected to the wiring layer, and the other end is electrically connected to the second face-up chip.

10. The chip packaging structure according to claim 6, characterized in that: A first metal layer is provided between the first flip chip and the first face-up chip; The chip packaging structure also includes a plastic package, a shielding layer and a third electrical connection column; the plastic package covers the first flip chip, the second flip chip, the third flip chip and the first face-up chip; the shielding layer is grounded; one end of the third electrical connection column is connected to the first metal layer, and the other end is connected to the shielding layer.

11. The chip packaging structure according to claim 10, characterized in that: A side of the first metal layer away from the substrate is covered with a glue layer; the third electrical connection column passes through the glue layer and is electrically connected to the first metal layer.

12. A packaging method, characterized in that: Used to prepare a chip packaging structure as claimed in any one of claims 1 to 11.

Images