Multi-level system-in-package module with embedded die and redistributed bottom features

Abstract

The invention relates to a multi-level system-in-package module with embedded die and redistributed bottom features. The present disclosure relates to a multi-level system-in-package (SIP) module having a double-sided module and a redistribution structure underlying the double-sided module. The double-sided module includes a laminate, a top component attached to a top surface of the laminate, a bottom component attached to a bottom surface of the laminate, and a plurality of copper pillars, and a bottom molding compound formed on the bottom surface of the laminate and encapsulating at least a side surface of the bottom assembly and a side surface of each copper pillar. A bottom surface of the bottom molding compound is part of a bottom surface of the double-sided module. The redistribution structure includes a redistribution layer having a plurality of patterned conductive features separated from each other. Each patterned conductive feature is coupled to at least one of the bottom component and the copper pillar.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 542,742 filed on October 5, 2023 and U.S. Provisional Patent Application No. 63 / 627,389 filed on January 31, 2024, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to a multi-level system-in-package (SIP) module having one or more embedded dies and redistributed bottom features, and a process for manufacturing the redistributed bottom features of the SIP module. Background Art

[0004] With the popularity of portable consumer electronic products such as smartphones and tablet computers, double-sided modules have become increasingly attractive in microelectronic devices to achieve dense electronic devices with a small footprint.

[0005] However, a system-in-package (SIP) module with a double-sided structure utilizing a ball grid array (BGA) may result in a relatively large overall thickness of the final product and have limitations on the input / output (I / O) density. This is because each solder ball of the BGA has a relatively large size (in both horizontal and vertical dimensions). Alternatively, when the double-sided SIP structure utilizes a land grid array (LGA), the final product may have a relatively small footprint, but the input / output (I / O) location at the bottom of the SIP module is still limited (e.g., the I / O is only located in certain bottom areas of the SIP module with non-uniform fine pitch). It is challenging to obtain sufficient interconnection between the device within the double-sided SIP module and the higher-level assembly (e.g., printed circuit board, PCB) when the higher-level assembly has a uniform and coarse connection pitch.

[0006] In addition, for SIP modules with a double-sided structure, heat dissipation is another challenge, especially for high frequency and high power applications.

[0007] Therefore, in order to adapt to the low profile and small footprint requirements of portable products, provide sufficient connections and uniform I / O for higher-level assemblies, and enhance thermal and electrical performance, it is an object of the present disclosure to provide an improved design of a SIP module and a process for manufacturing the SIP module. Summary of the invention

[0008] The present disclosure relates to a multi-level system-in-package (SIP) module having one or more embedded dies and a redistribution bottom feature, and a process for manufacturing the redistribution bottom feature of the SIP module. The disclosed multi-level SIP module includes a double-sided module and a redistribution structure located below the bottom surface of the double-sided module. The double-sided module includes a laminate, at least one top component, a top molding compound, a bottom component, a plurality of copper pillars, and a bottom molding compound. At least one top component is attached to the top surface of the laminate, and the top molding compound is formed on the top surface of the laminate to encapsulate at least one top component. The bottom component and the copper pillar are attached to the bottom surface of the laminate, and the bottom molding compound is formed on the bottom surface of the laminate and at least encapsulates the side surface of the bottom component and the side surface of each of the copper pillars. The top surface of the double-sided module is the top surface of the top molding compound, the side surface of the double-sided module is a combination of the side surface of the top molding compound, the side surface of the laminate, and the side surface of the bottom molding compound, and the bottom surface of the double-sided module is at least composed of the bottom surface of the bottom molding compound. The redistribution structure includes a redistribution layer having a plurality of patterned conductive features separated from each other. Each of the patterned conductive features is coupled to at least one of a bottom component and a copper pillar.

[0009] In one embodiment of a multi-level SIP module, the bottom component is a flip chip die, and each copper pillar has the same height. Herein, the bottom surface of the bottom molding compound, the backside surface of the flip chip die, and the end surface of each copper pillar are coplanar and constitute the bottom surface of the double-sided module. The flip chip die is a silicon (Si) die.

[0010] In one embodiment of the multi-level SIP module, the redistribution structure further includes a first dielectric pattern having a plurality of first openings. The first dielectric pattern is directly below the bottom surface of the double-sided module so that the first dielectric pattern contacts the backside surface of the flip chip die and contacts the end surface of each copper pillar. The first opening is positioned so that the backside surface of the flip chip die and the end surface of each copper pillar are partially exposed. The patterned conductive features fill the first openings to couple with the bottom component and the copper pillar, respectively, and extend below the first dielectric pattern. The first dielectric pattern is formed by a photoimageable dielectric (PID) layer or a non-photoimageable deposited film.

[0011] In one embodiment of the multi-level SIP module, the redistribution structure further includes a seed layer having a plurality of discrete seed layer segments. The seed layer completely and directly covers the exposed surface within each first opening and extends below a portion of the first dielectric pattern, such that the seed layer contacts the backside surface of the flip chip die and the end surface of each copper pillar. Each patterned conductive feature is in direct contact with a corresponding one of the discrete seed layer segments, such that each patterned conductive feature is coupled to at least one of the bottom component and the copper pillar via a corresponding one of the discrete seed layer segments.

[0012] In one embodiment of the multi-level SIP module, the redistribution structure further includes a plurality of additional patterned conductive features and a second dielectric pattern having a plurality of second openings. The second dielectric pattern is directly located below the first dielectric pattern to partially encapsulate each patterned conductive feature. In this article, each patterned conductive feature is partially exposed through one or more corresponding second openings in the second openings of the second dielectric pattern. The additional patterned conductive features fill the plurality of second openings to couple with the plurality of patterned conductive features, respectively, and extend below the second dielectric pattern. The second dielectric pattern is formed by a PID layer or a non-photoimageable deposited film.

[0013] In one embodiment of the multi-level SIP module, the redistribution structure further includes an additional seed layer having a plurality of discrete additional seed layer sections. The additional seed layer completely and directly covers the exposed surface within each second opening and extends below a portion of the second dielectric pattern, so that the additional seed layer is in contact with each patterned conductive feature. Each additional patterned conductive feature is in direct contact with a corresponding one of the discrete additional seed layer sections, so that the additional patterned conductive features are respectively coupled to the patterned conductive features via a corresponding one of the discrete additional seed layer sections. The redistribution structure further includes a coating that completely covers each additional patterned conductive feature and is configured to enable each additional patterned conductive feature to have a solderable surface. In this article, the coating is formed of one of chemical nickel gold (ENIG), organic solderability preservative (OSP), chemical nickel palladium gold (ENEPIG), and a solder alloy.

[0014] In one embodiment of the multi-level SIP module, the redistribution structure further includes a seed layer having a plurality of discrete seed layer segments. The seed layer contacts the bottom surface of the double-sided module and partially covers the bottom surface so as to contact the backside surface of the flip chip die and the end surface of each copper pillar. Each of the plurality of patterned conductive features is in direct contact with a corresponding one of the discrete seed layer segments, so that each patterned conductive feature is coupled to at least one of the bottom component and the copper pillar via a corresponding one of the discrete seed layer segments.

[0015] In one embodiment of the multi-level SIP module, the redistribution structure further includes a plurality of additional patterned conductive features and a dielectric pattern having a plurality of openings. The dielectric pattern is directly below the bottom surface of the double-sided module to partially encapsulate each patterned conductive feature. In this article, each patterned conductive feature is partially exposed through one or more corresponding openings in the openings of the dielectric pattern. The additional patterned conductive features fill the openings to couple with the patterned conductive features and extend below the dielectric pattern. The dielectric pattern is formed by a PID layer or a non-photoimageable deposited film.

[0016] In one embodiment of the multi-level SIP module, the redistribution structure further includes an additional seed layer having a plurality of discrete additional seed layer sections. The additional seed layer completely and directly covers the exposed surface within each opening and extends below a portion of the dielectric pattern so that the additional seed layer contacts each patterned conductive feature. Each additional patterned conductive feature is in direct contact with a corresponding one of the discrete additional seed layer sections so that the additional patterned conductive features are coupled to the patterned conductive features via a corresponding one of the discrete additional seed layer sections, respectively. The redistribution structure further includes a coating that completely covers each additional patterned conductive feature and is configured to enable each additional patterned conductive feature to have a solderable surface. The coating is formed of one of ENIG, OSP, ENEPIG, and a solder alloy.

[0017] In one embodiment of the multi-level SIP module, the bottom surface of the bottom molding compound vertically extends beyond the backside surface of the flip chip die and is coplanar with the end surface of at least one of the copper pillars. The bottom molding compound has a plurality of molding compound holes, and at least one of the molding compound holes is confined within the backside surface of the flip chip die and extends from the bottom surface of the bottom molding compound to the backside surface of the flip chip die to partially expose the backside surface of the flip chip die. The flip chip die is one of a gallium arsenide (GaAs) die, a Si die, and a gallium nitride (GaN) die.

[0018] In one embodiment of the multi-level SIP module, the redistribution structure further includes a seed layer having a plurality of discrete seed layer segments. The seed layer contacts and partially covers the bottom surface of the double-sided module and completely and directly covers the exposed surface within each molding compound hole, such that the seed layer contacts the backside surface of the flip chip die and the end surface of at least one of the copper pillars. The patterned conductive features are respectively in direct contact with the discrete seed layer segments and fill the molding compound holes.

[0019] In one embodiment of the multi-level SIP module, the copper pillars have different heights, wherein some of the copper pillars have a first height, and the remaining copper pillars of the copper pillars have a second height higher than the first height. The bottom surface of the bottom molding compound vertically extends beyond the end surface of each of the certain copper pillars of the copper pillars, and is coplanar with the end surface of each of the remaining copper pillars of the copper pillars. At least one of the copper pillars is included in the remaining copper pillars of the copper pillars. Some of the molding compound holes are respectively confined within the end surface of some of the copper pillars of the copper pillars, and extend from the bottom surface of the bottom molding compound to the end surface of some of the copper pillars of the copper pillars, respectively, to partially expose each of the certain copper pillars of the copper pillars.

[0020] In one embodiment of the multi-level SIP module, the redistribution structure further includes a seed layer having a plurality of discrete seed layer segments. The seed layer contacts and partially covers the bottom surface of the double-sided module, and completely and directly covers the exposed surface within each molding compound hole, so that the seed layer contacts the backside surface of the flip chip die and the end surface of each copper pillar. The patterned conductive features are respectively in direct contact with the discrete seed layer segments and fill the molding compound holes.

[0021] In one embodiment of a multi-level SIP module, the bottom component is a flip chip die having a plurality of die copper pillars. In this article, the backside surface of the flip chip die is attached to the bottom surface of the laminate, and the die copper pillars extend toward the bottom surface of the double-sided module. Each copper pillar has the same height and is attached to the bottom surface of the laminate. The bottom surface of the bottom mold compound, the tip surface of each die copper pillar, and the end surface of each copper pillar are coplanar and constitute the bottom surface of the double-sided module. The flip chip die is one of a GaAs die, a Si die, and a GaN die.

[0022] In one embodiment of the multi-level SIP module, the redistribution structure further includes a first dielectric pattern having a plurality of first openings. The first dielectric pattern is directly below the bottom surface of the double-sided module so that the first dielectric pattern contacts the tip surface of each bare die copper pillar and the end surface of each copper pillar of the flip chip die. The first opening is positioned so that the tip surface of each bare die copper pillar and the end surface of each copper pillar are partially exposed. The patterned conductive features fill the first openings to couple with the copper pillars of the bottom component and the bare die copper pillars, respectively, and extend below the first dielectric pattern.

[0023] In one embodiment of the multi-level SIP module, the redistribution structure further includes a seed layer having a plurality of discrete seed layer segments. The seed layer completely and directly covers the exposed surface within each first opening and extends below a portion of the first dielectric pattern, such that the seed layer contacts the tip surface of each die copper pillar and the end surface of each copper pillar. Each patterned conductive feature is in direct contact with a corresponding one of the discrete seed layer segments, such that each patterned conductive feature is coupled to at least one of the bottom component and the copper pillar via a corresponding one of the discrete seed layer segments.

[0024] According to one embodiment, the multi-level SIP module further includes a shielding structure that completely covers the top surface of the bifacial module and completely covers the side surfaces of the bifacial module, but does not cover the bottom surface of the bifacial module where the redistribution structure is located.

[0025] In one embodiment of the multi-level SIP module, at least one top component is one of a flip chip die, a wire bond die, a surface mount device (SMD), a filter, a Si device, a power amplifier (PA), and a passive component.

[0026] In one embodiment of the multi-level SIP module, the bottom component is one of a flip chip die, a SMD, a filter, a Si device, a PA, and a passive component.

[0027] In one embodiment of the multi-level SIP module, the redistribution structure further comprises a coating layer, the coating layer completely covering each patterned conductive feature and configured to enable each patterned conductive feature to have a solderable surface. The coating layer is formed of one of ENIG, OSP, ENEPIG and a solder alloy.

[0028] In one embodiment of a multi-level SIP module, the redistribution layers are formed of copper.

[0029] In one embodiment of the multi-level SIP module, the redistribution layer is configured to provide at least one of a heat dissipation path for bottom components, a ground plane, an inductive element, and a connection pitch change of the multi-level SIP module.

[0030] In one embodiment of the multi-level SIP module, each patterned conductive feature is one of a metal pad, a metal trace, and a metal via.

[0031] According to one embodiment, a communication device includes a control system, a baseband processor, a receiving circuit system, and a transmitting circuit system. In this article, at least one or any combination of the control system, the baseband processor, the transmitting circuit system, and the receiving circuit system is implemented in a multi-stage SIP module, and the multi-stage SIP module includes a double-sided module and a redistribution structure located below the bottom surface of the double-sided module. In this article, the double-sided module includes a laminate, at least one top component, a top molding compound, a bottom component, a plurality of copper pillars, and a bottom molding compound. At least one top component is attached to the top surface of the laminate, and the top molding compound is formed on the top surface of the laminate to encapsulate at least one top component. The bottom component and the copper pillar are attached to the bottom surface of the laminate, and the bottom molding compound is formed on the bottom surface of the laminate, and at least the side surface of the bottom component and the side surface of each of the copper pillars are encapsulated. The top surface of the double-sided module is the top surface of the top mold compound, the side surface of the double-sided module is the combination of the side surface of the top mold compound, the side surface of the laminate, and the side surface of the bottom mold compound, and the bottom surface of the double-sided module is at least composed of the bottom surface of the bottom mold compound. The redistribution structure includes a redistribution layer having a plurality of patterned conductive features separated from each other. Each patterned conductive feature is coupled to at least one of the bottom component and the copper pillar.

[0032] According to one embodiment, a method for manufacturing a rewiring bottom feature of a SIP module begins with providing a double-sided module, the double-sided module comprising a laminate, at least one top component, a top molding compound, a bottom component, a plurality of copper pillars, and a bottom molding compound. In this article, at least one top component is attached to the top surface of the laminate, and the top molding compound is formed on the top surface of the laminate to encapsulate at least one top component. The bottom component and the copper pillar are attached to the bottom surface of the laminate, and the bottom molding compound is formed on the bottom surface of the laminate, and at least the side surface of each of the side surfaces of the bottom component and the copper pillars is encapsulated. The top surface of the double-sided module is the top surface of the top molding compound, the side surface of the double-sided module is a combination of the side surface of the top molding compound, the side surface of the laminate, and the side surface of the bottom molding compound, and the bottom surface of the double-sided module is at least composed of the bottom surface of the bottom molding compound. Next, a rewiring structure is formed, which is located below the bottom surface of the double-sided module. The rewiring structure includes a plurality of patterned conductive features separated from each other. Each patterned conductive feature is coupled to at least one of the bottom component and the copper pillar.

[0033] On the other hand, any of the aforementioned aspects, and / or various individual aspects and features as described herein, may be combined individually or together to obtain additional advantages. Unless otherwise indicated herein, any of the various features and elements disclosed herein may be combined with one or more other disclosed features and elements.

[0034] Those skilled in the art will appreciate the scope of the present disclosure and understand additional aspects thereof after reading the following detailed description of the preferred embodiments and the related drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The accompanying drawings incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

[0036] Figure 1 An exemplary multi-level system-in-package (SIP) module having an exemplary bottom redistribution structure is illustrated in accordance with some embodiments.

[0037] Figure 2 A flow chart is provided that illustrates an exemplary process for fabricating an exemplary bottom redistribution structure of an exemplary multi-level SIP module according to some embodiments of the present disclosure.

[0038] Figures 3 to 12 Alternative multi-level SIP modules with alternative bottom redistribution structures according to some embodiments and corresponding processes for manufacturing these alternative bottom redistribution structures are described respectively.

[0039] Fig.13According to some embodiments of the present disclosure, Figure 1 , Figure 3 , Figure 5 , Figure 7 , Fig. 9 and Fig.11 Block diagram of a multi-level SIP communication device as described in .

[0040] It should be understood that for the sake of clarity of explanation, Figures 1 to 13 May not be drawn to scale. DETAILED DESCRIPTION

[0041] The embodiments set forth below represent information necessary to enable those skilled in the art to practice the embodiments and to illustrate the best mode for practicing the embodiments. After reading the following description with reference to the accompanying drawings, a person of ordinary skill in the art will understand the concepts of the present disclosure and will appreciate the applications of these concepts not specifically set forth herein. It should be understood that these concepts and applications are within the scope of the present disclosure and the appended claims.

[0042] It will be appreciated that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish different elements. For example, without departing from the scope of the present disclosure, the first element may be referred to as the second element, and similarly, the second element may be referred to as the first element. As used herein, the term "and / or" includes any and all combinations of one or more items in the associated listed items.

[0043] It should be understood that when an element such as a layer, region or substrate is referred to as "on another element" or "extending to" another element, it can be directly on another element or directly extend to another element, or there can also be an intermediate element. On the contrary, when an element is referred to as "directly on another element" or "directly extending to another element", there is no intermediate element. Similarly, it should be understood that when an element such as a layer, region or substrate is referred to as "above another element" or "extending above another element", it can be directly above another element or directly extend above another element, or there can also be an intermediate element. On the contrary, when an element is referred to as "directly above another element" or "directly above another element" extends, there is no intermediate element. It will also be understood that when an element is referred to as "connected" or "coupled" to another element, it can be directly connected or coupled to another element, or there can be an intermediate element. On the contrary, when an element is referred to as "directly connected" or "directly coupled" to another element, there is no intermediate element.

[0044] Relative terms such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical" may be used herein to describe the relative relationship of one element, layer or region to another element, layer or region as illustrated in the figures. It should be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the accompanying drawings. For non-limiting example, when the structure in the figure is turned upside down, the "below" / "above" relationship will be reversed.

[0045] The terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" are also intended to include the plural forms. It should also be understood that when used herein, the terms "comprises", "comprising", "includes", and / or "including" specify the presence of the features, integers, steps, operations, elements, and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups thereof.

[0046] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will be further understood that, unless expressly defined herein, the terms used herein should be interpreted as having a meaning consistent with their meaning in the context of this specification and the relevant art, and will not be interpreted in an idealized or overly formal sense.

[0047] Embodiments are described herein with reference to schematic illustrations of embodiments of the present disclosure. In this way, the actual sizes of layers and elements may be different, and it is expected that they will be different from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. For example, a region described or described as a square or rectangle may have a circular or curved feature, and a region shown as a straight line may have some irregularities. Therefore, the region illustrated in the figure is schematic, and its shape is not intended to illustrate the precise shape of the region of the device, and is not intended to limit the scope of the present disclosure. In addition, for illustrative purposes, the size of a structure or region may be enlarged relative to other structures or regions, and therefore a structure or region is provided to illustrate the general structure of the present invention, and may be drawn to scale or may not be drawn to scale. Common elements between the accompanying drawings may be shown in this article with common element numbers, and may not be described subsequently.

[0048] The present disclosure relates to a multi-level system-in-package (SIP) module having one or more embedded dies and a redistribution bottom feature, and a process for manufacturing the redistribution bottom feature of the multi-level SIP module. In particular, the disclosed multi-level SIP module is composed of a double-sided module and a redistribution structure, wherein the double-sided module contains one or more embedded dies and a plurality of copper pillars, and the redistribution structure is formed under the double-sided module at the bottom of the SIP module by using a photo-defined technology. The redistribution structure allows the implementation of thermal / ground planes and inductive / matching elements for the multi-level SIP module while providing uniform connection spacing to higher-level assemblies (e.g., customer printed circuit boards).

[0049] Figure 1 An exemplary multi-level SIP module 10 is illustrated, according to some embodiments of the present disclosure, consisting of an exemplary double-sided module 12 and an exemplary redistribution structure 14 located below the double-sided module 12. Herein, the double-sided module 12 includes a laminate 16, a top pad 18, a bottom pad 20, one or more top wiring traces 22, one or more bottom wiring traces 24, one or more top components 26, one or more bottom components 28, a plurality of copper pillars 30, a top mold compound 32, and a bottom mold compound 34.

[0050] The laminate 16 may have a thickness between 100 μm and 400 μm and is formed by alternating prepreg (PPG) layers and metal layers in a vertical direction (not shown). The top pad 18, the bottom pad 20, one or more top wiring traces 22, and one or more bottom wiring traces 24 are formed of a metal material such as copper. The top pad 18 is formed on the top surface of the laminate 16 and is configured to accommodate one or more top components 26. Each top pad 18 may have the same or different sizes and appropriate shapes, such as circular, square, etc. One or more top wiring traces 22 are also formed on the top surface of the laminate 16 and are configured to interconnect between certain top pads 18 or connect to a metal layer (not shown) within the laminate 16 between certain top pads 18.

[0051] Bottom pads 20 are formed on the bottom surface of the laminate 16 and are configured to accommodate one or more bottom components 28 and to accommodate copper pillars 30. Each bottom pad 20 may have the same or different sizes and suitable shapes, such as circular, square, etc. One or more bottom wiring traces 24 are formed on the bottom surface of the laminate 16 and are configured to interconnect between certain bottom pads 20 or to connect to a metal layer (not shown) within the laminate 16 between certain bottom pads 20.

[0052] For the purpose of this illustration, one or more top components 26 include a first top surface mount device (SMD) 26-1, a second top SMD 26-2, and a top flip chip die 26-3 with a top die solder ball 27. In different applications, there may be fewer or more top components 26 attached to the top surface of the laminate 16 via corresponding top pads 18, respectively. The top components 26 may be other electrical components, such as wire bonded dies, flip chip dies with die copper pillars, filters, silicon (Si) devices, power amplifiers (PAs), and / or passive components. The top components 26 may be mounted to the top pads 18 with or without adhesive material (e.g., the first top SMD 26-1 and the second top SMD 26-2 are mounted to the corresponding top pads 18 with a top adhesive material 29, while the top die solder balls 27 of the top flip chip die 26-3 are directly attached to the corresponding top pads 18). The top components 26 may also be electrically connected to corresponding metal layers (not shown) within the laminate 16, respectively. A top mold compound 32 is formed on the top surface of laminate 16 to encapsulate each top component 26, any portion of each top pad 18 not covered by the corresponding top component 26, and one or more top wiring traces 22. Top mold compound 32 may be an organic epoxy system or the like.

[0053] In addition, for the purpose of this illustration, one or more bottom components 28 are bottom flip chip dies, which include bottom die solder balls 31 attached to the bottom surface of the laminate 16 via corresponding bottom pads 20, respectively. The copper pillars 30 protruding from the bottom surface of the laminate 16 and surrounding the bottom flip chip die 28 include a first copper pillar 30-1, a second copper pillar 30-2, and a third copper pillar 30-3. In different applications, there may be more bottom components 28 mounted on the bottom surface of the laminate 16 via corresponding bottom pads 20, respectively, and in different layout configurations (e.g., all copper pillars 30 are positioned at one horizontal side of the bottom flip chip die 28), there may be fewer or more copper pillars 30 mounted on the bottom surface of the laminate 16 via corresponding bottom pads 20, respectively. The bottom component 28 may be other electrical components, such as SMD, wire bonded die, flip chip die with die copper pillars, filters, Si devices, PAs, and / or passive components. The bottom component 28 is mounted to the bottom pad 20 with or without an adhesive material. Each copper pillar 30 may have the same height, the same or different horizontal dimensions, and an appropriate shape, such as a cylindrical shape, a cube, a cuboid, etc. The bottom component 28 and the copper pillar 30 may also be electrically connected to corresponding metal layers (not shown) within the laminate 16, respectively. A bottom mold compound 34 is formed on the bottom surface of the laminate 16 to encapsulate any portion of each bottom pad 20 not covered by the corresponding bottom component 28, one or more bottom wiring traces 24, the side surface of the bottom component 28, and the side surface of each copper pillar 30. Therefore, the backside surface of the bottom flip chip die 28 (herein and hereinafter, the backside surface of one flip chip die refers to the surface away from the active area of ​​the flip chip die and opposite to the die solder ball / die copper pillar) and the end surface of each copper pillar 30 (herein and hereinafter, the end surface of one copper pillar refers to the surface of the copper pillar away from the laminate 16) are exposed by the bottom mold compound 34. The bottom mold compound 34 may be an organic epoxy system, etc. The top mold compound 32 and the bottom mold compound 34 may be formed of the same or different materials.

[0054] Herein, the top surface of the double-sided module 12 is the top surface of the top mold compound 32. The side surface of the double-sided module 12 is a combination of the side surface of the top mold compound 32, the side surface of the laminate 16, and the side surface of the bottom mold compound 34. The bottom surface of the double-sided module 12 is a combination of the bottom surface of the bottom mold compound 34, the backside surface of the bottom flip chip die 28, and the end surface of each copper pillar 30 (i.e., the bottom surface of the bottom mold compound 34, the backside surface of the bottom flip chip die 28, and the end surface of each copper pillar 30 are coplanar).

[0055] The redistribution structure 14 below the double-sided module 12 includes a first dielectric pattern 36 having a plurality of first openings 38 (for clarity, only one first opening is labeled with a reference numeral), a seed layer 40, and a redistribution layer 42. Herein, the first dielectric pattern 36 is directly below the bottom surface of the double-sided module 12, so that the first dielectric pattern 36 contacts the bottom surface of the bottom mold compound 34, the backside surface of the bottom flip chip die 28, and the end surface of each copper pillar 30. The first openings 38 are positioned so that the backside surface of the bottom flip chip die 28 and the end surface of each copper pillar 30 can be partially exposed. For the purpose of this illustration, there are two first openings 38 confined within the end surface of the first copper pillar 30-1, three first openings 38 confined within the backside surface of the bottom flip chip die 28, one first opening 38 confined within the end surface of the second copper pillar 30-2, and one first opening 38 confined within the end surface of the third copper pillar 30-3. In different applications, there may be fewer or more first openings 38 in the first dielectric pattern 36 to partially expose the backside / end surface of one bottom component 28 / copper pillar 30 .

[0056] The seed layer 40 completely and directly covers the exposed surface within each first opening 38 and extends below a portion of the first dielectric pattern 36. In this article and below, completely covering the surface means covering at least 99% of the surface. Typically, the seed layer 40 includes a plurality of discrete seed layer segments 40S, and each seed layer segment 40S is itself a continuous piece. As shown in this figure, the first seed layer segment 40S-1 covers all first openings 38 confined within the bottom flip chip die 28 and the first copper pillar 30-1, as well as the first dielectric pattern 36 between and adjacent to these first openings. The second seed layer segment 40S-2 covers the first openings 38 confined within the second copper pillar 30-2, and the first dielectric pattern 36 adjacent to the corresponding first openings 38. The third seed layer segment 40S-3 covers the first openings 38 confined within the third copper pillar 30-3, and the first dielectric pattern 36 adjacent to the corresponding first openings 38. The first seed layer section 40S-1, the second seed layer section 40S-2, and the third seed layer section 40S-3 are separated from each other.

[0057] The redistribution layer 42 may be formed of a metal material (e.g., copper) and include a plurality of patterned conductive features 42P, which may be metal pads, metal traces, metal vias, etc. Each patterned conductive feature 42P is in direct contact with a corresponding seed layer segment 40S, which is a deposition / plating base for the patterned conductive feature 42P (described in more detail below). Thus, each patterned conductive feature 42P fills one or more corresponding first openings 38 and extends below the first dielectric pattern 36. In this embodiment, the redistribution layer 42 includes three patterned conductive features 42P. The first patterned conductive feature 42P-1 is in direct contact with the first seed layer segment 40S-1, fills the first opening 38 confined within the bottom flip chip die 28 and the first copper pillar 30-1, and is electrically and / or thermally coupled to the bottom flip chip die 28 and the first copper pillar 30-1. The second patterned conductive feature 42P-2 is in direct contact with the second seed layer section 40S-2, fills the first opening 38 confined within the second copper pillar 30-2, and is electrically and / or thermally coupled to the second copper pillar 30-2. The third patterned conductive feature 42P-3 is in direct contact with the third seed layer section 40S-3, fills the first opening 38 confined within the third copper pillar 30-3, and is electrically and / or thermally coupled to the third copper pillar 30-3.

[0058] In some applications, the seed layer 40 may be omitted so that the redistribution layer 42 may be in direct contact with the backside surface of the bottom flip chip die 28 and the end surface (not shown) of each copper pillar 30 and still fill each first opening 38. In some applications, the redistribution layer 42 may include fewer or more patterned conductive features 42P with different coverage, and the seed layer 40 may include fewer or more discrete seed layer segments 40S corresponding to the discrete patterned conductive features 42P. In addition, the redistribution structure 14 may further include a coating 44 that completely covers each patterned conductive feature 42P and is configured to enable each patterned conductive feature 42P to have a solderable surface. The coating 44 may be formed of chemical nickel gold (ENIG), organic solderability preservative (OSP), chemical nickel palladium gold (ENEPIG), a solder alloy, or other materials, as long as it can maintain the solderability of the patterned conductive features 42P.

[0059] It should be clearly noted that the redistribution structure 14 enables metallization (e.g., the first patterned conductive feature 42P-1) below the bottom flip chip die 28 in order to provide an additional heat dissipation path for the bottom flip chip die 28. In addition, a certain patterned conductive feature 42P (e.g., the first patterned conductive feature 42P-1) may be sized large enough to implement a ground plane and / or an inductive / matching element. The redistribution structure 14 may also change the connection spacing of the multi-level SIP module 10 (e.g., the first patterned conductive feature 42P-1, the second patterned conductive feature 42P-2, and the third patterned conductive feature 42P-3 are positioned at substantially equal intervals). Without the redistribution structure 14, the copper pillar 30 itself cannot enhance the heat dissipation performance of the bottom flip chip die 28, and cannot provide a large pad for a ground plane and / or an inductive / matching element. Additionally, without the redistribution structure 14, the copper pillars 30 themselves would provide uneven pitches for higher level assemblies (eg, the second copper pillar 30-2 and the third copper pillar 30-3 are positioned at a finer pitch, while the first copper pillar 30-1 is positioned relatively far from the second copper pillar 30-2 and the third copper pillar 30-3).

[0060] In addition, the multi-stage SIP module 10 may further include a shielding structure 46 that completely covers the top surface of the bifacial module 12 and completely covers the side surfaces of the bifacial module 12, but does not cover the bottom surface where the redistribution structure 14 of the bifacial module 12 is located. The shielding structure 46 may include two or more stacked layers and be formed of two or more of copper, aluminum, silver, gold, nickel, and other conductive materials.

[0061] Figure 2 Provided are instructions for manufacturing a Figure 1 10. Although the flowchart and associated steps are described in series, they are not necessarily dependent on the order. Some steps may be performed in a different order than presented. In addition, the process within the scope of the present disclosure may include more than Figure 2 There may be fewer or more steps as described in .

[0062] Initially, the bifacial module 12 having the bottom component 28 and the copper pillars 30 is provided in an inverted orientation (step 102) such that the bottom surface and the top surface of the bifacial module 12 are reversed. In this document, for the sake of clarity, the first surface and the second surface (opposite to the first surface) are used to refer to the bottom surface and the top surface of the bifacial module 12 in the original orientation, respectively (as shown in FIG. Figure 1). The backside surface of the bottom flip chip die 28 and the end surface of each copper pillar 30 are exposed at the first surface (i.e., the original bottom surface) of the double-sided module 12 facing upward. The second surface (i.e., the original top surface) of the double-sided module 12 faces downward. Herein, a grinding process can be used to expose the backside surface of the bottom flip chip die 28 and the end surface of each copper pillar 30.

[0063] Next, a first dielectric layer is applied over the entire first surface of the bifacial module 12 (step 104). The first dielectric layer may be a photoimageable dielectric (PID) layer or a non-photoimageable film (e.g., a build-up film). A first opening 38 is then formed through the first dielectric layer to provide a first dielectric pattern 36 (step 106). The first opening 38 is formed at a position such that the backside surface of the bottom flip chip die 28 and the end surface of each copper pillar 30 may be partially exposed. Each first opening 38 is confined within the backside surface of the bottom flip chip die 28 or one end surface of the corresponding copper pillar 30. The first opening 38 may be formed by laser drilling photoimaging (for PID layers) or laser ablation (for non-photoimageable films) without the need for a protective mask.

[0064] A complete continuous seed layer is applied above the first dielectric pattern 36 and completely and directly covers the exposed surface in each first opening 38 (step 108). A first patterned plating photoresist is then provided above the complete continuous seed layer (step 110). The first portion of the complete continuous seed layer is covered by the first patterned plating photoresist, and the second portion of the complete continuous seed layer is exposed by the first patterned plating photoresist (that is, the second portion of the complete continuous seed layer is a discrete seed layer segment 40S of the seed layer 40 in the final product). Each first opening 38 is confined in the second portion of the complete continuous seed layer and is not covered by the first patterned plating photoresist. Next, copper is plated by the first patterned plating photoresist to form a redistribution layer 42 having a plurality of patterned conductive features 42P (step 112). In this article, the complete continuous seed layer (especially the second portion of the complete continuous seed layer) is a plating base for patterned conductive features 42P. Each patterned conductive feature 42P covers and contacts a corresponding second portion of the entire continuous seed layer and fills one or more corresponding first openings 38 .

[0065] After forming the redistribution layer 42, the first patterned plating photoresist is removed (step 114), and the first portion of the complete continuous seed layer covered by the first patterned plating photoresist is also removed (step 116). The first portion of the complete continuous seed layer can be removed by an etching process. The second portion of the complete continuous seed layer, which is respectively covered by the patterned conductive features 42P (i.e., not covered by the first patterned plating photoresist), is retained and becomes a discrete segment 40S constituting the seed layer 40. Then a coating 44 is applied to each patterned conductive feature 42P of the redistribution layer 42 to complete the redistribution structure 14 at the first surface of the double-sided module 12 (step 118). The coating 44 completely covers each patterned conductive feature 42P and is configured so that each patterned conductive feature 42P can have a solderable surface. The coating 44 can be formed of ENIG, OSP, ENEPIG, a solder alloy or other materials, as long as it can maintain the solderability of the patterned conductive features 42P.

[0066] Finally, the bifacial module 12 with the redistribution structure 14 is flipped upside down back to its original orientation, and a shielding structure 46 is formed above the bifacial module 12 to provide a multi-level SIP module 10 (step 119). Herein, the redistribution structure 14 is located below the bifacial module 12, at a first surface of the bifacial module 12, and the second surface of the bifacial module 12 faces upward. The shielding structure 46 completely covers the second (top) surface of the bifacial module 12 and completely covers the side surfaces of the bifacial module 12, but does not cover the first (bottom) surface of the bifacial module 12 where the redistribution structure 14 is located.

[0067] In order to provide uniform connection spacing with consistent feature size, the redistribution structure 14 below the bifacial module 12 may further include additional levels. Figure 3 As illustrated in FIG. 1 , in addition to the first dielectric pattern 36, the seed layer 40, and the redistribution layer 42, the redistribution structure 14 may also include a second dielectric pattern 48 having a second opening 50, an additional seed layer 52, and an additional redistribution layer 54. The second dielectric pattern 48 is located below the first dielectric pattern 36 to partially encapsulate each patterned conductive feature 42P. One or more portions of each patterned conductive feature 42P are exposed through the corresponding one or more second openings 50 of the second dielectric pattern 48. For the purpose of this illustration, there are four second openings 50 confined within the first patterned conductive feature 42P-1, one second opening 50 confined within the second patterned conductive feature 42P-2, and one second opening 50 confined within the third patterned conductive feature 42P-3. In different applications, there may be fewer or more second openings 50 to partially expose a patterned conductive feature 42P.

[0068] The additional seed layer 52 completely and directly covers the exposed surface within each second opening 50 and extends under a portion of the second dielectric pattern 48. As shown in this figure, the additional seed layer 52 includes four discrete segments 52S. The first additional seed layer segment 52S-1 covers two second openings 50 confined within a first portion of the first patterned conductive feature 42P-1 (e.g., a left portion of the first patterned conductive feature 42P-1), and covers a portion of the second dielectric pattern 48 between and adjacent to the two second openings 50. The second additional seed layer segment 52S-2 covers one second opening 50 confined within the second patterned conductive feature 42P-2, and a portion of the second dielectric pattern 48 adjacent to the corresponding second opening 50. The third additional seed layer segment 52S-3 covers one second opening 50 confined within the third patterned conductive feature 42P-3, and a portion of the second dielectric pattern 48 adjacent to the corresponding second opening 50. The fourth additional seed layer segment 52S-4 covers the two second openings 50 confined within the second portion of the first patterned conductive feature 42P-1 (e.g., the right portion of the first patterned conductive feature 42P-1), and covers a portion of the second dielectric pattern 48 between and adjacent to the two second openings 50. The first additional seed layer segment 52S-1, the second additional seed layer segment 52S-2, the third additional seed layer segment 52S-3, and the fourth additional seed layer segment 52S-4 are separated from each other.

[0069] The additional redistribution layer 54 may be formed of copper and include a plurality of discrete additional patterned conductive features 54P, which may be metal pads, metal traces, metal vias, etc. Each additional patterned conductive feature 54P is in direct contact with a corresponding additional seed layer segment 52S, which is a deposition / plating base for the additional patterned conductive feature 54P (described in more detail below). Thus, each additional patterned conductive feature 54P fills one or more corresponding second openings 50 and extends below the second dielectric pattern 48. In this embodiment, the additional redistribution layer 54 includes four additional patterned conductive features 54P. The first additional patterned conductive feature 54P-1 is in direct contact with the first additional seed layer segment 52S-1, fills two second openings 50 confined within a first portion of the first patterned conductive feature 42P-1, and is electrically and / or thermally coupled to the first patterned conductive feature 42P-1. The second additional patterned conductive feature 54P-2 is in direct contact with the second additional seed layer segment 52S-2, fills the second opening 50 confined within the second patterned conductive feature 42P-2, and is electrically and / or thermally coupled to the second patterned conductive feature 42P-2. The third additional patterned conductive feature 54P-3 is in direct contact with the third additional seed layer segment 52S-3, fills the second opening 50 confined within the third patterned conductive feature 42P-3, and is electrically and / or thermally coupled to the third patterned conductive feature 42P-3. The fourth additional patterned conductive feature 54P-4 is in direct contact with the fourth additional seed layer segment 52S-4, fills the two second openings 50 confined within the second portion of the first patterned conductive feature 42P-1, and is electrically and / or thermally coupled to the first patterned conductive feature 42P-1.

[0070] Herein, the additional patterned conductive features 54P may be of the same size and separated from each other at the same intervals, thereby providing a uniform connection spacing with consistent feature sizes for the multi-level SIP module 10. In some applications, the additional seed layer 52 may be omitted, so that the additional redistribution layer 54 may be in direct contact with each patterned conductive feature 42P (not shown) and still fill each second opening 50. In some applications, the additional redistribution layer 54 may include fewer or more additional patterned conductive features 54P with different coverage / positions, and the additional seed layer 52 may include fewer or more discrete additional seed layer segments 52S corresponding to the discrete additional patterned conductive features 54P. The second patterned dielectric 48 and the additional redistribution layer 54 may also enable additional embedded features, such as inductors, in the redistribution structure 14. In addition, the redistribution structure 14 may further include a coating 44 that completely covers each additional patterned conductive feature 54P and is configured to enable each additional patterned conductive feature 54P to have a solderable surface. Coating 44 may be formed of ENIG, OSP, ENEPIG, solder alloys, or other materials as long as it can maintain the solderability of additional patterned conductive features 54P.

[0071] Figure 4 Provided are instructions for manufacturing a Figure 3 10. Although the flowchart and associated steps are described in series, they are not necessarily dependent on the order. Some steps may be performed in a different order than presented. In addition, the process within the scope of the present disclosure may include more than Figure 4 There may be fewer or more steps as described in . Figure 4 The flowchart described in Figure 2 , and further includes process steps for providing the second dielectric pattern 48 with a second opening 50 , an additional seed layer 52 , and an additional redistribution layer 54 to complete the redistribution structure 14 .

[0072] After forming the redistribution layer 42, the first patterned plating photoresist is removed, and a seed layer 40 having discrete seed layer segments 40S is provided, and a second dielectric layer is applied over the first dielectric pattern 36 to encapsulate each patterned conductive feature 42P (step 120). The second dielectric layer can be a PID layer or a non-photoimageable film (e.g., a buildup film). A second opening 50 is then formed through the second dielectric layer to provide a second dielectric pattern 48 (step 122). The second opening 50 is formed at a position where each patterned conductive feature 42P can be partially exposed. Each second opening 50 is confined within one of the patterned conductive features 42P. The second opening 50 can be formed by laser drilling photoimaging (for PID layers) or laser ablation (for non-photoimageable films).

[0073] An additional complete continuous seed layer is applied above the second dielectric pattern 48 and completely and directly covers the exposed surface in each second opening 50 (step 124). A second patterned plating photoresist is then provided above the additional complete continuous seed layer (step 126). The first portion of the additional complete continuous seed layer is covered by the second patterned plating photoresist, and the second portion of the additional complete continuous seed layer is exposed by the second patterned plating photoresist (that is, the second portion of the additional complete continuous seed layer is a discrete additional seed layer segment 52S of the additional seed layer 52 in the final product). In this article, each second opening 50 is confined in the second portion of the additional complete continuous seed layer and is not covered by the second patterned plating photoresist. Next, copper is plated by the second patterned plating photoresist to form an additional redistribution layer 54 with discrete additional patterned conductive features 54P (step 128). In this article, the additional complete continuous seed layer (especially the second portion of the additional complete continuous seed layer) is a plating substrate for additional patterned conductive features 54P. Each additional patterned conductive feature 54P covers and contacts a corresponding second portion of the additional complete continuous seed layer and fills one or more corresponding second openings 50 .

[0074] After forming the additional redistribution layer 54, the second patterned plating photoresist is removed (step 130), and the first portion of the additional complete continuous seed layer covered by the second patterned plating photoresist is also removed (step 132). The first portion of the additional complete continuous seed layer can be removed by an etching process. The second portion of the additional complete continuous seed layer, which is respectively covered by the additional patterned conductive features 54P (i.e., not covered by the second patterned plating photoresist), is retained and becomes a discrete additional seed layer segment 52S constituting the additional seed layer 52. Then a coating 44 is applied to each additional patterned conductive feature 54P of the additional redistribution layer 54 to complete the redistribution structure 14 (step 134). The coating 44 completely covers each additional patterned conductive feature 54P and is configured so that each additional patterned conductive feature 54P can have a solderable surface. The coating 44 can be formed of ENIG, OSP, ENEPIG, a solder alloy or other materials, as long as it can maintain the solderability of the additional patterned conductive features 54P.

[0075] Finally, the bifacial module 12 with the redistribution structure 14 is flipped upside down back to its original orientation, and a shielding structure 46 is formed over the bifacial module 12 to provide a multi-level SIP module 10 (step 136). Herein, the redistribution structure 14 is located below the bifacial module 12, at a first surface of the bifacial module 12, and the second surface of the bifacial module 12 faces upward. The shielding structure 46 completely covers the second (top) surface of the bifacial module 12 and completely covers the side surfaces of the bifacial module 12, but does not cover the first (bottom) surface of the bifacial module 12 where the redistribution structure 14 is located.

[0076] In some embodiments, the first dielectric pattern 36 may be omitted in the redistribution structure 14 of the multi-level SIP module 10. Figure 5 . In this article, the bottom surface of the double-sided module 12 is a combination of the bottom surface of the bottom mold compound 34, the backside surface of the bottom flip chip die 28, and the bottom surface of each copper pillar 30. The seed layer 40 contacts the bottom surface of the double-sided module 12 and partially covers the bottom surface. For the purpose of this illustration, the seed layer 40 includes three discrete seed layer sections 40S. The first seed layer section 40S-1 covers the backside surface of the bottom flip chip die 28, the end surface of the first copper pillar 30-1, and a portion of the bottom surface of the bottom mold compound 34 between the bottom flip chip die 28 and the first copper pillar 30-1. The second seed layer section 40S-2 covers the end surface of the second copper pillar 30-2 and the portion of the bottom surface of the bottom mold compound 34 adjacent to the second copper pillar 30-2. The third seed layer section 40S-3 covers the end surface of the third copper pillar 30-3 and the portion of the bottom surface of the bottom mold compound 34 adjacent to the third copper pillar 30-3. The first seed layer section 40S-1, the second seed layer section 40S-2, and the third seed layer section 40S-3 are separated from each other.

[0077] Each patterned conductive feature 42P remains in direct contact with the corresponding seed layer segment 40S to couple to the bottom flip chip die 28 and / or corresponding copper pillar(s) 30 . In this embodiment, the redistribution layer 42 includes a first patterned conductive feature 42P-1 in direct contact with the first seed layer segment 40S-1 (e.g., a portion between the bottom flip chip die 28 and the first copper pillar 30-1 covering the back side surface of the bottom flip chip die 28, the end surface of the first copper pillar 30-1, and the bottom surface of the bottom molding compound 34), a second patterned conductive feature 42P-2 in direct contact with the second seed layer segment 40S-2 (e.g., a portion adjacent to the second copper pillar 30-2 covering the end surface of the second copper pillar 30-2 and the bottom surface of the bottom molding compound 34), and a third patterned conductive feature 42P-3 in direct contact with the third seed layer segment 40S-3 (e.g., a portion adjacent to the third copper pillar 30-3 covering the end surface of the third copper pillar 30-3 and the bottom surface of the bottom molding compound 34).

[0078] In some applications, the seed layer 40 may be omitted so that the redistribution layer 42 may be in direct contact with the backside surface of the bottom flip chip die 28 and the end surface (not shown) of each copper pillar 30. In some applications, the redistribution layer 42 may include fewer or more patterned conductive features 42P with different coverage, and the seed layer 40 may include fewer or more discrete seed layer segments 40S corresponding to the discrete patterned conductive features 42P. In addition, the redistribution structure 14 may further include a coating 44 that completely covers each patterned conductive feature 42P and is configured to enable each patterned conductive feature 42P to have a solderable surface. The coating 44 may be formed of ENIG, OSP, ENEPIG, a solder alloy, or other materials as long as it can maintain the solderability of the patterned conductive features 42P.

[0079] In this illustration, the redistribution structure 14 also provides additional heat dissipation paths for the bottom flip chip die 28 and may have a large feature (e.g., the first patterned conductive feature 42P-1) to implement a ground plane and / or an inductive / matching element. The redistribution structure 14 enables the connection pitch of the multi-level SIP module 10 to vary (e.g., the first patterned conductive feature 42P-1, the second patterned conductive feature 42P-2, and the third patterned conductive feature 42P-3 are positioned at substantially equal intervals).

[0080] Figure 6 Provided are instructions for manufacturing a Figure 510. Although the flowchart and associated steps are described in series, they are not necessarily dependent on the order. Some steps may be performed in a different order than presented. In addition, the process within the scope of the present disclosure may include more than Figure 6 There may be fewer or more steps as described in .

[0081] Initially, the bifacial module 12 having the bottom component 28 and the copper pillars 30 is provided in an inverted orientation (step 202, similar to step 102), such that the bottom surface and the top surface of the bifacial module 12 are swapped. In this document, for the sake of clarity, the first surface and the second surface (opposite to the first surface) are used to refer to the bottom surface and the top surface of the bifacial module 12 in the original orientation, respectively (as shown in FIG. Figure 5 ). The backside surface of the bottom flip chip die 28 and the end surface of each copper pillar 30 are exposed at the first surface (i.e., the original bottom surface) of the double-sided module 12 facing upward. The second surface (i.e., the original top surface) of the double-sided module 12 faces downward. Herein, a grinding process may be applied to expose the backside surface of the bottom flip chip die 28 and the end surface of each copper pillar 30.

[0082] Next, a complete continuous seed layer is applied over the entire first surface of the double-sided module 12 and completely and directly covers the entire first surface (step 204). A first patterned plating photoresist is then provided over the complete continuous seed layer (step 206). The first portion of the complete continuous seed layer is covered by the first patterned plating photoresist, and the second portion of the complete continuous seed layer is exposed by the first patterned plating photoresist (i.e., the second portion of the complete continuous seed layer is a discrete seed layer segment 40S of the seed layer 40 in the final product). In this article, the end surface of each copper column 30 and the back side surface of the bottom component 28 are not covered by the first patterned plating photoresist. Then copper is plated by the first patterned plating photoresist to form a redistribution layer 42 with discrete patterned conductive features 42P (step 208). The complete continuous seed layer (especially the second portion of the complete continuous seed layer) is a plating substrate for patterned conductive features 42P. Each patterned conductive feature 42P covers the corresponding second portion of the complete continuous seed layer and contacts the corresponding second portion.

[0083] After forming the redistribution layer 42, the first patterned plating photoresist is removed (step 210), and the first portion of the complete continuous seed layer covered by the first patterned plating photoresist is also removed (step 212). The first portion of the complete continuous seed layer can be removed by an etching process. The second portion of the complete continuous seed layer, which is respectively covered by the patterned conductive features 42 (i.e., not covered by the first patterned plating photoresist), is retained and becomes a discrete seed layer segment 40S constituting the seed layer 40. Then a coating 44 is applied to each patterned conductive feature 42P of the redistribution layer 42 to complete the redistribution structure 14 at the first surface of the double-sided module 12 (step 214). The coating 44 completely covers each patterned conductive feature 42P and is configured so that each patterned conductive feature 42P can have a solderable surface. The coating 44 can be formed of ENIG, OSP, ENEPIG, a solder alloy or other materials, as long as it can maintain the solderability of the patterned conductive features 42P.

[0084] Finally, the bifacial module 12 with the redistribution structure 14 is flipped upside down back to its original orientation, and a shielding structure 46 is formed above the bifacial module 12 to provide a multi-level SIP module 10 (step 215). Herein, the redistribution structure 14 is located below the bifacial module 12, at a first surface of the bifacial module 12, and the second surface of the bifacial module 12 faces upward. The shielding structure 46 completely covers the second (top) surface of the bifacial module 12 and completely covers the side surfaces of the bifacial module 12, but does not cover the first (bottom) surface of the bifacial module 12 where the redistribution structure 14 is located.

[0085] In order to provide a uniform connection pitch with consistent feature size for the multi-level SIP module 10, the redistribution structure 14 may further include an additional redistribution layer 54 having discrete additional patterned conductive features 54P and a dielectric pattern 56 having openings 58 (only one opening is labeled with a reference numeral for clarity), as shown in FIG. Figure 7 . The dielectric pattern 56 is located below the bottom surface of the double-sided module 12 to partially encapsulate each patterned conductive feature 42P. One or more portions of each patterned conductive feature 42P are exposed through corresponding one or more openings 58 of the dielectric pattern 56. For the purpose of this illustration, there are four openings 58 confined within the first patterned conductive feature 42P-1, one opening 58 confined within the second patterned conductive feature 42P-2, and one opening 58 confined within the third patterned conductive feature 42P-3. In different applications, there may be fewer or more openings 58 in the dielectric pattern 56 to partially expose one patterned conductive feature 42P.

[0086] The additional seed layer 52 completely and directly covers the exposed surface within each opening 58 and extends under a portion of the dielectric pattern 56. As shown in this figure, the additional seed layer 52 includes four discrete additional seed layer segments 52S. The first additional seed layer segment 52S-1 covers two openings 58 confined within a first portion of the first patterned conductive feature 42P-1 (e.g., a left portion of the first patterned conductive feature 42P-1), and covers a portion of the dielectric pattern 56 between and adjacent to the two openings 58. The second additional seed layer segment 52S-2 covers one opening 58 confined within the second patterned conductive feature 42P-2, and a portion of the dielectric pattern 56 adjacent to the corresponding opening 58. The third additional seed layer segment 52S-3 covers one opening 58 confined within the third patterned conductive feature 42P-3, and a portion of the dielectric pattern 56 adjacent to the corresponding opening 58. The fourth additional seed layer segment 52S-4 covers the two openings 58 confined within the second portion of the first patterned conductive feature 42P-1 (e.g., the right portion of the first patterned conductive feature 42P-1), and covers a portion of the dielectric pattern 56 between and adjacent to the two openings 58. The first additional seed layer segment 52S-1, the second additional seed layer segment 52S-2, the third additional seed layer segment 52S-3, and the fourth additional seed layer segment 52S-4 are separated from each other.

[0087] Each additional patterned conductive feature 54P is in direct contact with a corresponding additional seed layer segment 52S, which is a deposition / plating base for the additional patterned conductive feature 54 (described in more detail below). Therefore, each additional patterned conductive feature 54P fills one or more corresponding openings 58 and extends below the dielectric pattern 56. In this embodiment, the additional redistribution layer 54 includes four additional patterned conductive features 54P. The first additional patterned conductive feature 54P-1 is in direct contact with the first additional seed layer segment 52S-1 and fills two openings 58 confined within the first portion of the first patterned conductive feature 42P-1. The second additional patterned conductive feature 54P-2 is in direct contact with the second additional seed layer segment 52S-2 and fills the openings 58 confined within the second patterned conductive feature 42P-2. The third additional patterned conductive feature 54P-3 is in direct contact with the third additional seed layer segment 52S-3 and fills the opening 58 confined within the third patterned conductive feature 42P-3, and the fourth additional patterned conductive feature 54P-4 is in direct contact with the fourth additional seed layer segment 52S-4 and fills the two openings 58 confined within the second portion of the first patterned conductive feature 42P-1. In this context, the additional patterned conductive features 54P may have the same size and be separated from each other by the same interval, thereby providing a uniform connection pitch with a consistent feature size for the multi-level SIP module 10.

[0088] In some applications, the additional seed layer 52 may be omitted so that the additional redistribution layer 54 may be in direct contact with each patterned conductive feature 42P (not shown) and still fill each opening 58 within the dielectric pattern 56. In some applications, the additional redistribution layer 54 may include fewer or more additional patterned conductive features 54P with different coverage / positions, and the additional seed layer 52 may include fewer or more discrete additional seed layer segments 52S corresponding to the discrete additional patterned conductive features 54P. The dielectric pattern 56 and the additional patterned conductive features 54P may also enable additional embedded features, such as inductors, in the redistribution structure 14. In addition, the redistribution structure 14 may further include a coating 44 that completely covers each additional patterned conductive feature 54P and is configured to enable each additional patterned conductive feature 54P to have a solderable surface. The coating 44 may be formed of ENIG, OSP, ENEPIG, a solder alloy, or other material, as long as it can maintain the solderability of the additional patterned conductive features 54P.

[0089] Figure 8 Provided are instructions for manufacturing a Figure 7 10. Although the flowchart and associated steps are described in series, they are not necessarily dependent on the order. Some steps may be performed in a different order than presented. In addition, the process within the scope of the present disclosure may include more than Figure 8 There may be fewer or more steps as described in . Figure 8 The flowchart described in Figure 6 , and further includes process steps for providing dielectric pattern 56 with openings 58 , additional seed layers 52 , and additional redistribution layers 54 to complete redistribution structure 14 .

[0090] After forming the redistribution layer 42, removing the first patterned plating photoresist and providing a seed layer 40 having discrete seed layer segments 40S, a dielectric layer is applied over the first surface (e.g., the original bottom surface) of the double-sided module 12 to encapsulate each patterned conductive feature 42P (step 216). The dielectric layer can be a PID layer or a non-photoimageable film (e.g., a buildup film). Then, openings 58 are formed through the dielectric layer to provide a dielectric pattern 56 (step 218). The openings 58 are formed at locations where each patterned conductive feature 42P can be partially exposed. Each opening 58 is confined within one of the patterned conductive features 42P. The openings 58 can be formed by laser drilling photoimaging (for PID layers) or laser ablation (for non-photoimageable films).

[0091] An additional complete continuous seed layer is applied over the dielectric pattern 56 and completely and directly covers the exposed surface in each opening 58 (step 220). A second patterned plating photoresist is then provided over the additional complete continuous seed layer (step 222). The first portion of the complete continuous seed layer is covered by the second patterned plating photoresist, and the second portion of the complete continuous seed layer is exposed by the second patterned plating photoresist (that is, the second portion of the additional complete continuous seed layer is a discrete additional seed layer segment 52S of the additional seed layer 52 in the final product). In this article, each opening 58 is confined in the second portion of the additional complete continuous seed layer and is not covered by the second patterned plating photoresist. Next, copper is plated by the second patterned plating photoresist to form an additional redistribution layer 54 with discrete additional patterned conductive features 54P (step 224). In this article, the additional complete continuous seed layer (especially the second portion of the additional complete continuous seed layer) is a plating substrate for additional patterned conductive features 54P. Each additional patterned conductive feature 54P covers and contacts a corresponding second portion of the additional complete continuous seed layer and fills one or more corresponding openings 58 .

[0092] After forming the additional redistribution layer 54, the second patterned plating photoresist is removed (step 226), and the first portion of the additional complete continuous seed layer covered by the second patterned plating photoresist is also removed (step 228). The first portion of the additional complete continuous seed layer can be removed by an etching process. The second portion of the additional complete continuous seed layer, which is respectively covered by the additional patterned conductive features 54P (i.e., not covered by the second patterned plating photoresist), is retained and becomes a discrete additional seed layer segment 52S constituting the additional seed layer 52. Then a coating 44 is applied to each additional patterned conductive feature 54P of the additional redistribution layer 54 to complete the redistribution structure 14 (step 230). The coating 44 completely covers each additional patterned conductive feature 54P and is configured so that each additional patterned conductive feature 54P can have a solderable surface. The coating 44 can be formed of ENIG, OSP, ENEPIG, a solder alloy or other materials, as long as it can maintain the solderability of the additional patterned conductive features 54P.

[0093] Finally, the bifacial module 12 with the redistribution structure 14 is flipped upside down back to its original orientation, and a shielding structure 46 is formed over the bifacial module 12 to provide a multi-level SIP module 10 (step 232). Herein, the redistribution structure 14 is located below the bifacial module 12, at a first surface of the bifacial module 12, and the second surface of the bifacial module 12 faces upward. The shielding structure 46 completely covers the second (top) surface of the bifacial module 12 and completely covers the side surfaces of the bifacial module 12, but does not cover the first (bottom) surface of the bifacial module 12 where the redistribution structure 14 is located.

[0094] In some embodiments, the copper pillars 30 may have different heights, and the bottom component 28 may be shorter than some of the copper pillars 30. Therefore, the backside surface of the bottom component 28 and / or the end surface of one or more copper pillars 30 may not be exposed at the bottom surface of the bifacial module 12, such as Fig. 9 . For the purpose of this illustration, the bottom component 28 and the second copper pillar 30-2 are shorter than the first copper pillar 30-1 and the third copper pillar 30-3. The bottom surface of the bottom molding compound 34 extends vertically beyond the backside surface of the bottom component 28 and vertically beyond the end surface of the second copper pillar 30-2, while the end surfaces of the first copper pillar 30-1, the third copper pillar 30-3 and the bottom surface of the bottom molding compound 34 still constitute the bottom surface of the double-sided module 12.

[0095] Herein, the bottom mold compound 34 has a plurality of mold compound holes 60: three first mold compound holes 60-1 (for clarity, only one first mold compound hole is labeled with a reference numeral) are confined within the backside surface of the bottom component 28 and each extends from the bottom surface of the bottom mold compound 34 (i.e., the bottom surface of the bifacial module 12) to the backside surface of the bottom component 28, and one second mold compound hole 60-2 is confined within the end surface of the second copper pillar 30-2 and extends from the bottom surface of the bottom mold compound 34 (i.e., the bottom surface of the bifacial module 12) to the bottom surface of the second copper pillar 30-2. Therefore, the backside surface of the bottom component 28 and the end surface of the second copper pillar 30-2 are partially exposed through the mold compound holes 60. In different applications, there may be fewer or more bottom components 28 and / or fewer or more copper pillars 30 that are not exposed at the bottom surface of the bifacial module 12. In addition, the bottom mold compound 34 may include fewer or more mold compound holes 60 to partially expose the backside surface of the bottom component 28 and / or the end surface of one or more copper pillars 30. The bottom flip chip die 28 may be a gallium arsenide (GaAs) die, a Si die, a gallium nitride (GaN) die, or others.

[0096] Herein, the redistribution structure 14 in the multi-level SIP module 10 includes a seed layer 40 and a redistribution layer 42 without a dielectric pattern. The seed layer 40 completely and directly covers the exposed surface within each mold compound hole 60 so as to contact the backside surface of the bottom component 28 and the end surface of the second copper pillar 30-2. In addition, the seed layer 40 contacts and covers the end surfaces of the first copper pillar 30-1 and the third copper pillar 30-3 and a portion of the bottom surface of the bottom mold compound 34. In particular, the seed layer 40 includes three discrete segments 40S. The first seed layer segment 40S-1 covers the bottom surface of the first copper pillar 30-1, the surface confined within the bottom component 28 within all the first mold compound holes 60-1, and the portion of the bottom surface of the bottom mold compound 34 surrounding the bottom component 28 and the first copper pillar 30-1. The second seed layer segment 40S-2 covers the surface confined within the second copper pillar 30-2 within the second compound hole 60-2 and a portion of the bottom surface of the bottom mold compound 34 adjacent to the second copper pillar 30-2. The third seed layer segment 40S-3 covers the bottom surface of the third copper pillar 30-3 and a portion of the bottom surface of the bottom mold compound 34 adjacent to the third copper pillar 30-3. The first seed layer segment 40S-1, the second seed layer segment 40S-2, and the third seed layer segment 40S-3 are separated from each other.

[0097] Each patterned conductive feature 42P is still in direct contact with the corresponding seed layer segment 40S. In this embodiment, the redistribution layer 42 includes three patterned conductive features 42P. The first patterned conductive feature 42P-1 is in direct contact with the first seed layer segment 40S-1, fills the first mold compound hole 60-1 confined within the bottom flip chip die 28, and is electrically and / or thermally coupled to the bottom flip chip die 28 and the first copper pillar 30-1. The second patterned conductive feature 42P-2 is in direct contact with the second seed layer segment 40S-2, fills the second mold compound hole 60-2 confined within the second copper pillar 30-2, and is electrically and / or thermally coupled to the second copper pillar 30-2. The third patterned conductive feature 42P-3 is in direct contact with the third seed layer segment 40S-3, and is electrically and / or thermally coupled to the third copper pillar 30-3.

[0098] In some applications, the seed layer 40 may be omitted so that the redistribution layer 42 may be in direct contact with the backside surface of the bottom flip chip die 28 and the end surface of the second copper pillar 30-2 through the mold compound hole 60, and in direct contact with the end surfaces of the first copper pillar 30-1 and the third copper pillar 30-3. In some applications, the redistribution layer 42 may include fewer or more patterned conductive features 42P with different coverage, and the seed layer 40 may include fewer or more discrete seed layer segments 40S corresponding to the discrete patterned conductive features 42P. In addition, the redistribution structure 14 may further include a coating 44 that completely covers each patterned conductive feature 42P and is configured to enable each patterned conductive feature 42P to have a solderable surface. The coating 44 may be formed of ENIG, OSP, ENEPIG, a solder alloy, or other materials as long as it can maintain the solderability of the patterned conductive features 42P.

[0099] Fig.10 Provided are instructions for manufacturing a Fig. 9 10. Although the flowchart and associated steps are described in series, they are not necessarily dependent on the order. Some steps may be performed in a different order than presented. In addition, the process within the scope of the present disclosure may include more than Fig.10 There may be fewer or more steps as described in .

[0100] Initially, a complete bifacial module is provided in an inverted orientation (step 302). Herein, the complete bifacial module is similar to the bifacial module 12, except that in the complete bifacial module, each copper pillar 30 and the bottom flip chip die 28 are completely encapsulated by the bottom mold compound 34. Due to the inverted orientation, each copper pillar 30, the bottom flip chip die 28, and the bottom mold compound 34 are flipped to the upper side of the complete bifacial module. For clarity, a first surface and a second surface (opposite to the first surface) are used to represent the bottom surface and the top surface, respectively, of the complete bifacial module in the original orientation (i.e., in the orientation in which each copper pillar 30, the bottom flip chip die 28, and the bottom mold compound 34 are located at the lower side of the complete bifacial module).

[0101] Next, the bottom mold compound 34 is ground down until the upward facing end surfaces of certain copper pillars 30 (e.g., the end surfaces of the first copper pillar 30-1 and the third copper pillar 30-3) are exposed through the bottom mold compound 34 (step 304). After the grinding step, the backside surface of the bottom flip chip die 28 and the end surfaces of the remaining copper pillars 30 (e.g., the end surface of the second copper pillar 30-2) are still covered by the bottom mold compound 34. The mold compound holes 60 are then formed into the bottom mold compound 34 to provide the double-sided module 12 in an inverted orientation (step 306). For clarity, the first surface and the second surface (opposite to the first surface) are used to represent the bottom surface and the top surface of the double-sided module 12 in the original orientation (e.g., the bottom surface and the top surface, respectively). Fig. 9 ). The mold compound holes 60 are formed at positions that partially expose the backside surface of the bottom flip chip die 28 (e.g., the first mold compound hole 60-1 partially exposes the backside surface of the bottom flip chip die 28) and partially expose the end surface of each remaining copper pillar 30 (e.g., the second mold compound hole 60-2 partially exposes the end surface of the second copper pillar 30-2). Each mold compound hole 60 is confined within the backside surface of the bottom flip chip die 28 or one end surface of the corresponding copper pillar 30 (e.g., the second copper pillar 30-2). The mold compound holes 60 can be formed by laser drilling.

[0102] A complete continuous seed layer is applied to completely and directly cover the exposed surface in each mold compound hole 60 and the entire first surface of the double-sided module 12 (step 308). A patterned plating photoresist is then provided above the complete continuous seed layer (step 310). The first portion of the complete continuous seed layer is covered by the patterned plating photoresist, and the second portion of the complete continuous seed layer is exposed by the patterned plating photoresist (that is, the second portion of the complete continuous seed layer is a discrete seed layer segment 40S of the seed layer 40 in the final product). In this article, each mold compound hole 60, the end surface of the first copper pillar 30-1, and the end surface of the third copper pillar 30-3 are not covered by the patterned plating photoresist. Next, copper is plated by the patterned plating photoresist to form a redistribution layer 42 with discrete patterned conductive features 42P (step 312). In this article, the complete continuous seed layer (especially the second portion of the complete continuous seed layer) is the plating base of the patterned conductive features 42P. Each patterned conductive feature 42P covers and contacts a corresponding second portion of the entire continuous seed layer.

[0103] After forming the redistribution layer 42, the patterned plating photoresist is removed (step 314), and the first portion of the complete continuous seed layer covered by the patterned plating photoresist is also removed (step 316). The first portion of the complete continuous seed layer can be removed by an etching process. The second portion of the complete continuous seed layer, which is respectively covered by the patterned conductive features 42P (i.e., not covered by the patterned plating photoresist), is retained and becomes a discrete seed layer segment 40S constituting the seed layer 40. Then a coating 44 is applied to each patterned conductive feature 42P of the redistribution layer 42 to complete the redistribution structure 14 (step 318). The coating 44 completely covers each patterned conductive feature 42P and is configured so that each patterned conductive feature 42P can have a solderable surface. The coating 44 can be formed of ENIG, OSP, ENEPIG, a solder alloy or other materials, as long as it can maintain the solderability of the patterned conductive features 42P.

[0104] Finally, the bifacial module 12 with the redistribution structure 14 is flipped upside down back to its original orientation, and a shielding structure 46 is formed above the bifacial module 12 to provide a multi-level SIP module 10 (step 320). Herein, the redistribution structure 14 is located below the bifacial module 12, at a first surface of the bifacial module 12, and the second surface of the bifacial module 12 faces upward. The shielding structure 46 completely covers the second (top) surface of the bifacial module 12 and completely covers the side surfaces of the bifacial module 12, but does not cover the first (bottom) surface of the bifacial module 12 where the redistribution structure 14 is located.

[0105] In some embodiments, one or more bottom components 28 may be a flip chip die having die copper pillars 62, such as Fig.11. For the purpose of this illustration, the bottom flip chip die 28 includes three die copper pillars 62: a first die copper pillar 62-1, a second die copper pillar 62-2, and a third die copper pillar 62-3. In different applications, the double-sided module 12 may include more bottom flip chip dies 28 with die copper pillars 62, and the bottom flip chip die 28 may include fewer or more die copper pillars 62. In this article, the backside surface of the bottom flip chip die 28 is not exposed at the bottom of the double-sided module 12. Instead, the backside surface of the bottom flip chip die 28 is attached to the bottom surface of the laminate 16 using a bottom adhesive material 64, and the tip surface of each die copper pillar 62 is exposed at the bottom of the double-sided module 12 (that is, the tip surface of each die copper pillar 62 is not covered by the bottom mold compound 34). In this article and below, the tip surface of a die copper pillar refers to the surface of the die copper pillar away from the active area of ​​the flip chip die. The bottom surface of the double-sided module 12 is a combination of the bottom surface of the bottom mold compound 34, the tip surface of each die copper pillar 62, and the end surface of each copper pillar 30. In this posture configuration, the bottom flip chip die 28 can be a GaAs die, a Si die, a GaN die, or others, but must have a die copper pillar 62 as an interconnect.

[0106] The redistribution structure 14 below the double-sided module 12 includes a first dielectric pattern 36 having a first opening 38, a seed layer 40, and a redistribution layer 42. The first dielectric pattern 36 is located directly below the bottom surface of the double-sided module 12, so that the first dielectric pattern 36 contacts the bottom surface of the bottom mold compound 34, the end surface of each copper pillar 30, and the tip surface of each die copper pillar 62 of the bottom flip chip die 28. The first openings 38 are positioned so that the end surface of each copper pillar 30 and the tip surface of each die copper pillar 62 can be partially exposed. For the purpose of this illustration, there are two first openings 38 limited within the end surface of the first copper pillar 30-1, one first opening 38 limited within each die copper pillar 62, one first opening 38 limited within the end surface of the second copper pillar 30-2, and one first opening 38 limited within the end surface of the third copper pillar 30-3. In different applications, there may be fewer or more first openings 38 to partially expose the end surface of each copper pillar 30 and the tip surface of each die copper pillar 62 .

[0107] The seed layer 40 completely and directly covers the exposed surface within each first opening 38 and extends under a portion of the first dielectric pattern 36. As shown in this figure, the seed layer 40 includes four discrete segments 40S. The first seed layer segment 40S-1 covers all first openings 38 confined within the first copper pillar 30-1 and the first die copper pillar 62-1 of the bottom flip chip die 28, and portions of the first dielectric pattern 36 between and adjacent to these first openings 38. The second seed layer segment 40S-2 covers the first openings 38 confined within the second copper pillar 30-2, and portions of the first dielectric pattern 36 adjacent to the corresponding first openings 38. The third seed layer segment 40S-3 covers the first openings 38 confined within the third copper pillar 30-3, and portions of the first dielectric pattern 36 adjacent to the corresponding first openings 38. The fourth seed layer segment 40S-4 covers the two first openings 38 confined within the second die copper pillar 62-2 and the third die copper pillar 62-3 of the bottom flip chip die 28, and a portion of the first dielectric pattern 36 between and adjacent to the two first openings 38. The first seed layer segment 40S-1, the second seed layer segment 40S-2, the third seed layer segment 40S-3, and the fourth seed layer segment 40S-4 are separated from each other.

[0108] Each patterned conductive feature 42P is in direct contact with a corresponding seed layer segment 40S, which is a deposition / plating base for the patterned conductive feature 42P (described in more detail below). Therefore, each patterned conductive feature 42P fills one or more corresponding first openings 38 and extends below the first dielectric pattern 36. In this embodiment, the redistribution layer 42 includes four patterned conductive features 42P. The first patterned conductive feature 42P-1 is in direct contact with the first seed layer segment 40S-1, fills the first opening 38 confined within the first copper pillar 30-1 and the first die copper pillar 62-1 of the bottom flip chip die 28, and is electrically and / or thermally coupled to the first die copper pillar 62-1 and the first copper pillar 30-1 of the bottom flip chip die 28. The second patterned conductive feature 42P-2 is in direct contact with the second seed layer segment 40S-2, fills the first opening 38 confined within the second copper pillar 30-2, and is electrically and / or thermally coupled to the second copper pillar 30-2. The third patterned conductive feature 42P-3 is in direct contact with the third seed layer segment 40S-3, fills the first opening 38 confined within the third copper pillar 30-3, and is electrically and / or thermally coupled to the third copper pillar 30-3. The fourth patterned conductive feature 42P-4 is in direct contact with the fourth seed layer segment 40S-4, fills the first opening 38 confined within the second die copper pillar 62-2 and the third die copper pillar 62-3 of the bottom flip chip die 28, and is electrically and / or thermally coupled to the second die copper pillar 62-2 and the third die copper pillar 62-3 of the bottom flip chip die 28.

[0109] In some applications, the seed layer 40 may be omitted so that the redistribution layer 42 may be in direct contact with the end surface of each copper pillar 30 and the tip surface (not shown) of each die copper pillar 62 of the bottom flip chip die 28 and still fill each first opening 38. In some applications, the redistribution layer 42 may include fewer or more patterned conductive features 42P with different coverage, and the seed layer 40 may include fewer or more discrete seed layer segments 40S corresponding to the discrete patterned conductive features 42P. In addition, the redistribution structure 14 may further include a coating 44 that completely covers each patterned conductive feature 42P and is configured to enable each patterned conductive feature 42P to have a solderable surface. The coating 44 may be formed of ENIG, OSP, ENEPIG, a solder alloy, or other materials as long as it can maintain the solderability of the patterned conductive features 42P.

[0110] Fig.12 Provided are instructions for manufacturing a Fig.11 10. Although the flowchart and associated steps are described in series, they are not necessarily dependent on the order. Some steps may be performed in a different order than presented. In addition, the process within the scope of the present disclosure may include more than Fig.12 There may be fewer or more steps as described in .

[0111] Initially, the bifacial module 12 is provided in an inverted orientation (step 402) such that the bottom surface and the top surface of the bifacial module 12 are reversed. In this document, for the sake of clarity, the first surface and the second surface (opposite to the first surface) are used to refer to the bottom surface and the top surface of the bifacial module 12 in the original orientation, respectively (eg, Fig.11 ). The bottom surface of each copper pillar 30 and the tip surface of each die copper pillar 62 of the bottom flip chip die 28 are exposed at the first surface (i.e., the original bottom surface) of the double-sided module 12 facing upward. The second surface (i.e., the original top surface) of the double-sided module 12 faces downward. Herein, a grinding process or a laser drilling process may be applied to expose the end surface of each copper pillar 30 and the tip surface of each die copper pillar 62 of the bottom flip chip die 28.

[0112] Next, a first dielectric layer is applied over the entire first surface of the bifacial module 12 (step 404). The first dielectric layer may be a PID layer or a non-photoimageable film (e.g., a build-up film). A first opening 38 is then formed through the first dielectric layer to provide a first dielectric pattern 36 (step 406). The first opening 38 is formed at a position where the end surface of each copper pillar 30 and the tip surface of each die copper pillar 62 of the bottom flip chip die 28 can be partially exposed. Each first opening 38 is confined within one end surface of the corresponding copper pillar 30 or one tip surface of the corresponding die copper pillar 62 of the bottom flip chip die 28. The first opening 38 can be formed by laser drilling photoimaging (for PID layers) or laser ablation (for non-photoimageable films) without the need for a protective mask.

[0113] A complete continuous seed layer is applied above the first dielectric pattern 36 and completely and directly covers the exposed surface in each first opening 38 (step 408). A first patterned plating photoresist is then provided above the complete continuous seed layer (step 410). The first portion of the complete continuous seed layer is covered by the first patterned plating photoresist, and the second portion of the complete continuous seed layer is exposed by the first patterned plating photoresist (that is, the second portion of the complete continuous seed layer is a discrete seed layer segment 40S of the seed layer 40 in the final product). Each first opening 38 is confined in the second portion of the complete continuous seed layer and is not covered by the first patterned plating photoresist. Next, copper is plated by the first patterned plating photoresist to form a redistribution layer 42 with discrete patterned conductive features 42P (step 412). In this article, the complete continuous seed layer (especially the second portion of the complete continuous seed layer) is a plating base for patterned conductive features 42P. Each patterned conductive feature 42P covers and contacts a corresponding second portion of the entire continuous seed layer and fills one or more corresponding first openings 38 .

[0114] After forming the redistribution layer 42, the first patterned plating photoresist is removed (step 414), and the first portion of the complete continuous seed layer covered by the first patterned plating photoresist is also removed (step 416). The first portion of the complete continuous seed layer can be removed by an etching process. The second portion of the complete continuous seed layer, which is respectively covered by the patterned conductive features 42P (i.e., not covered by the first patterned plating photoresist), is retained and becomes a discrete seed layer segment 40S constituting the seed layer 40. Then a coating 44 is applied to each patterned conductive feature 42P of the redistribution layer 42 to complete the redistribution structure 14 (step 418). The coating 44 completely covers each patterned conductive feature 42P and is configured so that each patterned conductive feature 42P can have a solderable surface. The coating 44 can be formed of ENIG, OSP, ENEPIG, a solder alloy or other materials, as long as it can maintain the solderability of the patterned conductive features 42P.

[0115] Finally, the bifacial module 12 with the redistribution structure 14 is flipped upside down back to its original orientation, and a shielding structure 46 is formed above the bifacial module 12 to provide a multi-level SIP module 10 (step 420). Herein, the redistribution structure 14 is located below the bifacial module 12, at a first surface of the bifacial module 12, and the second surface of the bifacial module 12 faces upward. The shielding structure 46 completely covers the second (top) surface of the bifacial module 12 and completely covers the side surfaces of the bifacial module 12, but does not cover the first (bottom) surface of the bifacial module 12 where the redistribution structure 14 is located.

[0116] Regardless of the configuration, the redistribution structure 14 enables metallization below the bottom component 28 to provide an additional heat dissipation path for the bottom component 28. In addition, the redistribution structure 14 is suitable for accommodating large metal features to implement ground planes and / or inductor / matching components. Figure 3 and Figure 7 In the case of one or two levels of dielectric patterns and two levels of patterned conductive features as shown in FIG, the redistribution structure 14 can also provide uniform connection spacing (with consistent feature size) to higher-level assemblies. In addition, the redistribution structure 14 encapsulates the bottom surface of the double-sided module 12 to provide protection from the environment, handling, and testing, which will improve the overall reliability of the multi-level SIP module 10. In different applications, the redistribution structure 14 can include more levels of dielectric patterns and more levels of patterned conductive features, which have Figure 1 , Figure 3 , Figure 5 , Figure 7 , Fig. 9 and Fig.11 The different combinations shown in .

[0117] According to aspects disclosed herein, multi-level SIP modules and methods for providing adequate connectivity and uniform I / O and enhancing thermal and electrical performance may be provided or integrated into any processor-based electronic device. Examples include, but are not limited to, base stations, military application devices, set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, global positioning system (GPS) devices, mobile phones, cellular phones, smart phones, session initiation protocol (SIP) phones, tablet computers, phablets, servers, computers, portable computers, mobile computing devices, wearable computing devices (e.g., smart watches, health or fitness trackers, glasses, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, drones, and multirotors.

[0118] refer to Fig.13 , the concepts described above can be implemented in various types of communication devices 500, such as the communication devices listed in the previous paragraph. The communication device 500 will generally include a control system 502, a baseband processor 504, a transmit circuit system 506, a receive circuit system 508, an antenna switching circuit system 510, a plurality of antennas 512, and a user interface circuit system 514. Herein, at least one or any combination of the control system 502, the baseband processor 504, the transmit circuit system 506, and the receive circuit system 508 can be implemented in a multi-stage SIP module 10 (e.g., in one or more top components 26 and / or one or more bottom components 28), such as Figure 1 , Figure 3 , Figure 5 , Figure 7 , Fig. 9 and Fig.11 As shown in and described above.

[0119] In a non-limiting example, control system 502 may be a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC), as examples. In this regard, control system 502 may include at least a microprocessor, embedded memory circuits, and a communication bus interface. Receive circuit system 508 receives radio frequency signals from one or more base stations via antenna 512 and through antenna switching circuit system 510. Low noise amplifiers and filters of receive circuit system 508 cooperate to amplify and remove broadband interference from the received signal for processing. Down-conversion and digitization circuit system (not shown) then down-converts the filtered received signal to an intermediate or baseband frequency signal, which is then digitized into one or more digital streams using (one or more) analog-to-digital converters (ADCs).

[0120] The baseband processor 504 processes the digitized received signal to extract the information or data bits conveyed in the received signal. Such processing typically includes demodulation, decoding, and error correction operations, which will be discussed in more detail below. The baseband processor 504 is typically implemented in one or more digital signal processors (DSPs) and ASICs.

[0121] For transmission, the baseband processor 504 receives digitized data, which may represent voice, data, or control information, from the control system 502, and encodes the digitized data for transmission. The encoded data is output to the transmit circuit system 506, where a digital / analog converter (DAC) converts the digital encoded data into an analog signal, and a modulator modulates the analog signal onto a carrier signal at one or more desired transmit frequencies. A power amplifier amplifies the modulated carrier signal to a level suitable for transmission and delivers the modulated carrier signal to an antenna 512 through an antenna switching circuit system 510. Multiple antennas 512 and duplicate transmit circuit systems 506 and receive circuit systems 508 may provide spatial diversity. Those skilled in the art will understand the modulation and processing details.

[0122] It is contemplated that any of the aforementioned aspects, and / or the various individual aspects and features described herein, may be combined to obtain additional advantages. Unless otherwise indicated herein, any of the various embodiments disclosed herein may be combined with one or more other disclosed embodiments.

[0123] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered to be within the scope of the concepts disclosed herein and the claims below.

Claims

1. A multi-level system-in-package (SIP) module, comprising: A double-sided module comprising a laminate, at least one top component, a top molding compound, a bottom component, a plurality of copper pillars, and a bottom molding compound, wherein: The at least one top component is attached to a top surface of the laminate, and the top molding compound is formed on the top surface of the laminate to encapsulate the at least one top component; The bottom component and the plurality of copper pillars are attached to a bottom surface of the laminate; and the bottom molding compound formed on the bottom surface of the laminate encapsulates at least a side surface of the bottom component and a side surface of each of the plurality of copper pillars; and The top surface of the bifacial module is the top surface of the top molding compound, the side surfaces of the bifacial module are a combination of the side surfaces of the top molding compound, the side surfaces of the laminate, and the side surfaces of the bottom molding compound, and the bottom surface of the bifacial module is constituted by at least the bottom surface of the bottom molding compound; and A redistribution structure located below the bottom surface of the bifacial module, wherein: The redistribution structure comprises a redistribution layer having a plurality of patterned conductive features separated from each other; and • Each of the plurality of patterned conductive features is coupled to at least one of the plurality of copper pillars and the bottom component.

2. The multi-level SIP module according to claim 1, wherein: ● The bottom component is a flip chip die; ● Each of the plurality of copper pillars has the same height; and • A bottom surface of the bottom molding compound, a backside surface of the flip chip die, and an end surface of each of the plurality of copper pillars are coplanar and constitute a bottom surface of the double-sided module.

3. The multi-level SIP module of claim 2, wherein the flip chip die is a silicon (Si) die.

4. The multi-level SIP module according to claim 2, wherein: The redistribution structure further comprises a first dielectric pattern having a plurality of first openings; The first dielectric pattern is directly below the bottom surface of the double-sided module, such that the first dielectric pattern contacts the backside surface of the flip-chip die and the end surface of each of the plurality of copper pillars; The plurality of first openings are positioned such that a backside surface of the flip chip die and an end surface of each of the plurality of copper pillars are partially exposed; and The plurality of patterned conductive features fill the plurality of first openings to couple with the bottom component and the plurality of copper pillars, respectively, and extend under the first dielectric pattern.

5. The multi-level SIP module of claim 4, wherein the first dielectric pattern is formed of a photoimageable dielectric PID layer. 6 . The multi-level SIP module of claim 4 , wherein the first dielectric pattern is formed of a non-photoimageable buildup film.

7. The multi-level SIP module according to claim 4, wherein: The redistribution structure further comprises a seed layer having a plurality of discrete seed layer sections; The seed layer completely and directly covers the exposed surface within each of the plurality of first openings and extends below a portion of the first dielectric pattern, such that the seed layer contacts a backside surface of the flip chip die and an end surface of each of the plurality of copper pillars; and ●Each of the plurality of patterned conductive features is in direct contact with a corresponding one of the plurality of discrete seed layer segments, so that each of the plurality of patterned conductive features is coupled to at least one of the plurality of copper pillars and the bottom component via a corresponding one of the plurality of discrete seed layer segments.

8. The multi-level SIP module according to claim 4, wherein: The redistribution structure further comprises a plurality of additional patterned conductive features and a second dielectric pattern having a plurality of second openings; the second dielectric pattern being directly below the first dielectric pattern to partially encapsulate each of the plurality of patterned conductive features, wherein each of the plurality of patterned conductive features is partially exposed through one or more corresponding second openings of the plurality of second openings of the second dielectric pattern; and The plurality of additional patterned conductive features fill the plurality of second openings to be respectively coupled with the plurality of patterned conductive features and extend under the second dielectric pattern. 9 . The multi-level SIP module of claim 8 , wherein the second dielectric pattern is formed of a PID layer.

10. The multi-level SIP module of claim 8, wherein the second dielectric pattern is formed of a non-photoimageable buildup film.

11. The multi-level SIP module according to claim 8, wherein: • the redistribution structure further comprises an additional seed layer having a plurality of discrete additional seed layer sections; The additional seed layer completely and directly covers the exposed surface within each of the plurality of second openings and extends under portions of the second dielectric pattern such that the additional seed layer is in contact with each of the plurality of patterned conductive features; and • Each of the plurality of additional patterned conductive features is in direct contact with a corresponding one of the plurality of discrete additional seed layer segments, such that the plurality of additional patterned conductive features are coupled to the plurality of patterned conductive features via a corresponding one of the plurality of discrete additional seed layer segments, respectively.

12. The multi-level SIP module according to claim 8, wherein the redistribution structure further comprises a coating, the coating completely covering each of the plurality of additional patterned conductive features and configured to enable each of the plurality of additional patterned conductive features to have a solderable surface, wherein the coating is formed of one of chemical nickel gold (ENIG), organic solderability preservative (OSP), chemical nickel palladium gold (ENEPIG), and a solder alloy.

13. The multi-level SIP module according to claim 2, wherein: The redistribution structure further comprises a seed layer having a plurality of discrete seed layer sections; The seed layer contacts and partially covers a bottom surface of the bifacial module so as to contact a backside surface of the flip chip die and an end surface of each of the plurality of copper pillars; and ●Each of the plurality of patterned conductive features is in direct contact with a corresponding one of the plurality of discrete seed layer segments, so that each of the plurality of patterned conductive features is coupled to at least one of the plurality of copper pillars and the bottom component via a corresponding one of the plurality of discrete seed layer segments.

14. The multi-level SIP module according to claim 13, wherein: The redistribution structure further comprises a plurality of additional patterned conductive features and a dielectric pattern having a plurality of openings; The dielectric pattern is directly below the bottom surface of the bifacial module to partially encapsulate each of the plurality of patterned conductive features, wherein each of the plurality of patterned conductive features is partially exposed through one or more corresponding openings of the plurality of openings of the dielectric pattern; and The plurality of additional patterned conductive features fill the plurality of openings to be respectively coupled with the plurality of patterned conductive features and extend under the dielectric pattern.

15. The multi-level SIP module of claim 14, wherein the dielectric pattern is formed of a PID layer.

16. The multi-level SIP module of claim 14, wherein the dielectric pattern is formed of a non-photoimageable build-up film.

17. The multi-level SIP module according to claim 14, wherein: • the redistribution structure further comprises an additional seed layer having a plurality of discrete additional seed layer sections; The additional seed layer completely and directly covers the exposed surface within each of the plurality of openings and extends under portions of the dielectric pattern such that the additional seed layer is in contact with each of the plurality of patterned conductive features; and • Each of the plurality of additional patterned conductive features is in direct contact with a corresponding one of the plurality of discrete additional seed layer segments, such that the plurality of additional patterned conductive features are coupled to the plurality of patterned conductive features via a corresponding one of the plurality of discrete additional seed layer segments, respectively.

18. The multi-level SIP module according to claim 14, wherein the redistribution structure further comprises a coating, the coating completely covering each of the plurality of additional patterned conductive features and configured such that each of the plurality of additional patterned conductive features has a solderable surface, wherein the coating is formed of one of ENIG, OSP, ENEPIG and a solder alloy.

19. The multi-level SIP module according to claim 1, wherein: A bottom surface of the bottom mold compound extends vertically beyond the backside surface of the flip chip die and is coplanar with an end surface of at least one of the plurality of copper pillars; and ●The bottom molding compound has a plurality of molding compound holes, wherein at least one of the plurality of molding compound holes is confined within the back side surface of the flip chip die and extends from the bottom surface of the bottom molding compound to the back side surface of the flip chip die to partially expose the back side surface of the flip chip die. 20 . The multi-level SIP module of claim 19 , wherein the flip chip die is one of a gallium arsenide (GaAs) die, a Si die, and a gallium nitride (GaN) die.

21. The multi-level SIP module of claim 19, wherein: The redistribution structure further comprises a seed layer having a plurality of discrete seed layer sections; the seed layer contacts and partially covers a bottom surface of the bifacial module and completely and directly covers an exposed surface within each of the plurality of molding compound holes such that the seed layer contacts a backside surface of the flip chip die and an end surface of the at least one of the plurality of copper pillars; and • The plurality of patterned conductive features are respectively in direct contact with the plurality of discrete seed layer segments and fill the plurality of molding compound holes.

22. The multi-level SIP module according to claim 19, wherein: The plurality of copper pillars have different heights, wherein some of the plurality of copper pillars have a first height and the remaining copper pillars of the plurality of copper pillars have a second height higher than the first height; a bottom surface of the bottom molding compound extending vertically beyond an end surface of each of the certain copper pillars of the plurality of copper pillars and being coplanar with an end surface of each of the remaining copper pillars of the plurality of copper pillars, wherein the at least one of the plurality of copper pillars is included in the remaining copper pillars of the plurality of copper pillars; and ● Certain of the multiple molding compound holes are respectively confined within the end surfaces of the certain copper pillars among the multiple copper pillars, and respectively extend from the bottom surface of the bottom molding compound to the end surfaces of the certain copper pillars among the multiple copper pillars to partially expose each of the certain copper pillars among the multiple copper pillars.

23. The multi-level SIP module according to claim 22, wherein: The redistribution structure further comprises a seed layer having a plurality of discrete seed layer sections; the seed layer contacts and partially covers a bottom surface of the bifacial module and completely and directly covers an exposed surface within each of the plurality of molding compound holes such that the seed layer contacts a backside surface of the flip chip die and an end surface of each of the plurality of copper pillars; and The plurality of patterned conductive features are respectively in direct contact with the plurality of discrete seed layer segments and fill the plurality of molding compound holes.

24. The multi-level SIP module according to claim 1, wherein: The bottom component is a flip chip die having a plurality of die copper pillars, wherein a backside surface of the flip chip die is attached to a bottom surface of the laminate and the plurality of die copper pillars extend toward a bottom surface of the bifacial module; • Each of the plurality of copper pillars has the same height and is attached to a bottom surface of the laminate; and A bottom surface of the bottom molding compound, a tip surface of each of the plurality of die copper pillars of the flip chip die, and an end surface of each of the plurality of copper pillars are coplanar and constitute a bottom surface of the double-sided module.

25. The multi-level SIP module of claim 24, wherein the flip chip die is one of a GaAs die, a Si die, and a GaN die.

26. The multi-level SIP module of claim 24, wherein: The redistribution structure further comprises a first dielectric pattern having a plurality of first openings; The first dielectric pattern is directly below the bottom surface of the double-sided module so that the first dielectric pattern contacts the tip surface of each of the plurality of die copper pillars of the flip-chip die and the end surface of each of the plurality of copper pillars; The plurality of first openings are positioned such that a tip surface of each of the plurality of die copper pillars and an end surface of each of the plurality of copper pillars are partially exposed; and The plurality of patterned conductive features fill the plurality of first openings to couple with the plurality of copper pillars of the bottom component and the plurality of die copper pillars, respectively, and extend under the first dielectric pattern.

27. The multi-level SIP module of claim 26, wherein the first dielectric pattern is formed of a PID layer.

28. The multi-level SIP module of claim 26, wherein the first dielectric pattern is formed of a non-photoimageable build-up film.

29. The multi-level SIP module of claim 26, wherein: The redistribution structure further comprises a seed layer having a plurality of discrete seed layer sections; the seed layer completely and directly covers the exposed surface within each of the plurality of first openings and extends below a portion of the first dielectric pattern, such that the seed layer contacts a tip surface of each of the plurality of die copper pillars and an end surface of each of the plurality of copper pillars; and ●Each of the plurality of patterned conductive features is in direct contact with a corresponding one of the plurality of discrete seed layer segments, so that each of the plurality of patterned conductive features is coupled to at least one of the plurality of copper pillars and the bottom component via the corresponding one of the plurality of discrete seed layer segments.

30. The multi-level SIP module of claim 1, further comprising a shielding structure that completely covers the top surface of the bifacial module and completely covers the side surfaces of the bifacial module, but does not cover the bottom surface of the bifacial module where the redistribution structure is located.

31. The multi-level SIP module of claim 1, wherein the at least one top component is one of a flip chip die, a wire bond die, a surface mount device (SMD), a filter, a Si device, a power amplifier (PA), and a passive component.

32. The multi-level SIP module of claim 1, wherein the bottom component is one of a flip chip die, a SMD, a filter, a Si device, a PA, and a passive component.

33. A multi-level SIP module according to claim 1, wherein the redistribution structure further includes a coating, which completely covers each of the plurality of patterned conductive features and is configured so that each of the plurality of patterned conductive features has a solderable surface, wherein the coating is formed of one of ENIG, OSP, ENEPIG and a solder alloy.

34. The multi-level SIP module of claim 1, wherein the redistribution layer is formed of copper.

35. The multi-level SIP module of claim 1, wherein the redistribution layer is configured to provide at least one of a heat dissipation path for the bottom component, a ground plane, an inductive element, and a connection pitch change of the multi-level SIP module.

36. The multi-level SIP module of claim 1, wherein each of the plurality of patterned conductive features is one of a metal pad, a metal trace, and a metal via.

37. A communication device, comprising: ●Control system; Baseband processor; ●Receiving circuit system; as well as transmit circuitry, wherein at least one or any combination of the control system, the baseband processor, the transmit circuitry, and the receive circuitry is implemented in a multi-stage SIP module comprising a double-sided module and a redistribution structure located below a bottom surface of the double-sided module, wherein: The bifacial module comprises a laminate, at least one top component, a top molding compound, a bottom component, a plurality of copper pillars, and a bottom molding compound; The at least one top component is attached to the top surface of the laminate, and the top molding compound is formed on the top surface of the laminate to encapsulate the at least one top component; The bottom component and the plurality of copper pillars are attached to the bottom surface of the laminate, and the bottom molding compound formed on the bottom surface of the laminate encapsulates at least the side surface of the bottom component and the side surface of each of the plurality of copper pillars; The top surface of the bifacial module is the top surface of the top molding compound, the side surfaces of the bifacial module are a combination of the side surfaces of the top molding compound, the side surfaces of the laminate, and the side surfaces of the bottom molding compound, and the bottom surface of the bifacial module is constituted by at least the bottom surface of the bottom molding compound; The redistribution structure comprises a redistribution layer having a plurality of patterned conductive features separated from each other; and • Each of the plurality of patterned conductive features is coupled to at least one of the plurality of copper pillars and the bottom component.

38. A method comprising: ● Providing a bifacial module, the bifacial module comprising a laminate, at least one top component, a top molding compound, a bottom component, a plurality of copper pillars, and a bottom molding compound, wherein: The at least one top component is attached to the top surface of the laminate, and the top molding compound is formed on the top surface of the laminate to encapsulate the at least one top component; The bottom component and the plurality of copper pillars are attached to the bottom surface of the laminate, and the bottom molding compound formed on the bottom surface of the laminate encapsulates at least the side surface of the bottom component and the side surface of each of the plurality of copper pillars; and The top surface of the bifacial module is the top surface of the top molding compound, the side surfaces of the bifacial module are a combination of the side surfaces of the top molding compound, the side surfaces of the laminate, and the side surfaces of the bottom molding compound, and the bottom surface of the bifacial module is constituted by at least the bottom surface of the bottom molding compound; and ● forming a redistribution structure, the redistribution structure being located below the bottom surface of the bifacial module, wherein: The redistribution structure comprises a redistribution layer having a plurality of patterned conductive features separated from each other; and • Each of the plurality of patterned conductive features is coupled to at least one of the plurality of copper pillars and the bottom component.

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