Semiconductor package

Abstract

A semiconductor package includes a first semiconductor chip including a semiconductor substrate having an active surface and a passive surface, a device layer on the active surface, a first chip pad on the device layer, and first and second through electrodes penetrating the semiconductor substrate, wherein at least one of the first die pads is connected to the first through electrode and at least one of the first die pads is connected to the second through electrode; a redistribution structure including a redistribution layer on the passive surface of the semiconductor substrate and a redistribution via connected to the redistribution layer; a contact pad on an upper surface of the redistribution structure; and a second semiconductor chip on the redistribution structure and including a second chip pad connected to the contact pad.

Description

Technical Field

[0001] Example embodiments of the present disclosure relate to a semiconductor package and a method of manufacturing the same. Background Art

[0002] Recently, the demand for portable devices in the electronic product market has been increasing rapidly, and therefore, there is a continuous demand for miniaturization and lightweighting of electronic components mounted on products. When reducing the size and weight of electronic components, there is also a need to increase the integration density of semiconductor packages used in electronic components.

[0003] In order to improve the scaling and integration density of electronic components, various semiconductor packaging technologies have been actively studied. In particular, the development of technologies to maintain package reliability by suppressing delamination or cracks in redistribution paths even under thermal stress and external impact during the manufacturing process or use environment has become crucial. Summary of the invention

[0004] Example embodiments provide a semiconductor package having improved reliability against thermal stress and external impact and a method of manufacturing the semiconductor package.

[0005] Additional aspects will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the presented embodiments.

[0006] According to an aspect of an example embodiment, a semiconductor package may include: a first semiconductor chip, the first semiconductor chip including a semiconductor substrate having an active surface and an inactive surface, a device layer located on the active surface, a first chip pad located on the device layer, and a first through-electrode and a second through-electrode penetrating the semiconductor substrate, wherein at least one of the first chip pads is connected to the first through-electrode and at least one of the first chip pads is connected to the second through-electrode; a redistribution structure, the redistribution structure including a redistribution layer located on the inactive surface of the semiconductor substrate and a redistribution path connected to the redistribution layer; a contact pad, the contact pad being located on an upper surface of the redistribution structure; and a second semiconductor chip, the second semiconductor chip being located on the redistribution structure and including a second chip pad connected to the contact pad, wherein the contact pad includes a first contact pad connected to the first through-electrode through the redistribution layer and a second contact pad vertically overlapping the second through-electrode, the redistribution structure further including at least one post via penetrating the redistribution structure and connecting the second contact pad to the second through-electrode, and the redistribution structure further including a contact path connecting the first contact pad to the redistribution layer.

[0007] According to an aspect of example embodiments, a semiconductor package may include: a first redistribution structure, the first redistribution structure including a first redistribution layer and a first redistribution via connected to the first redistribution layer; a semiconductor chip, the semiconductor chip being located on the first redistribution structure and including a chip pad connected to the first redistribution layer; a molding portion, the molding portion being located on the first redistribution structure and at least partially surrounding the semiconductor chip; a second redistribution structure, the second redistribution structure being located on the molding portion and including a second redistribution layer and a second redistribution via connected to the second redistribution layer; a contact pad, the contact pad being located on an upper surface of the second redistribution structure; and and a first vertical connecting conductor and a second vertical connecting conductor, wherein the first vertical connecting conductor and the second vertical connecting conductor are located on the first redistribution structure and connect the first redistribution layer to the second redistribution layer, wherein the contact pad comprises a first contact pad connected to the first vertical connecting conductor through the second redistribution layer and a second contact pad vertically overlapping the second vertical connecting conductor, the first contact pad is horizontally offset from the first vertical connecting conductor, the second redistribution structure further comprises a contact path connecting the first contact pad to the second redistribution layer, and the second redistribution structure further comprises a column path connecting the second contact pad to the second vertical connecting conductor.

[0008] According to an aspect of example embodiments, a semiconductor package may include: a first semiconductor chip, the first semiconductor chip including a semiconductor substrate having an active surface and an inactive surface opposite to the active surface, a device layer located on the active surface, a first chip pad located on the device layer, and a through-electrode penetrating the semiconductor substrate and connected to the first chip pad; a redistribution structure, the redistribution structure being located on the inactive surface of the first semiconductor chip; a first contact pad and a second contact pad, the first contact pad and the second contact pad being located on an upper surface of the redistribution structure, wherein the second contact pad vertically overlaps with one of the through-electrodes; and a second semiconductor chip, the second semiconductor chip being located on the redistribution structure and having a first contact pad and a second contact pad connected to the first contact pad, respectively. A second chip pad comprising a contact pad and a second contact pad of the second semiconductor chip, wherein the redistribution structure comprises a first insulating layer located on the upper surface of the first semiconductor chip, a redistribution layer located on the first insulating layer, a redistribution path penetrating the first insulating layer and connecting the redistribution layer to the through-electrode, and a second insulating layer located on the first insulating layer and at least partially covering the redistribution layer, the first contact pad is located on the second insulating layer, and the redistribution structure further comprises a contact path penetrating the second insulating layer and connected to the redistribution layer, and the second contact pad is located on the second insulating layer, and the redistribution structure further comprises a column path penetrating the first insulating layer and the second insulating layer and connected to the one through-electrode vertically overlapping with the second contact pad.

[0009] According to one aspect of an example embodiment, a method for manufacturing a semiconductor package may include: preparing a structure including a first connecting pad and a second connecting pad; forming a first insulating layer on the structure with an uncured photosensitive insulating material; using a photolithography process to form a first hole penetrating the first insulating layer and connected to the first connecting pad, wherein the first insulating layer is cured by the photolithography process; forming a redistribution path in the first hole; forming a redistribution layer connected to the redistribution path on the first insulating layer; forming a second insulating layer on the first insulating layer to at least partially cover the redistribution layer; curing the second insulating layer; forming a second hole penetrating the second insulating layer and connected to the redistribution layer; using a dry etching process to form a through hole penetrating the first insulating layer and the second insulating layer, the through hole being connected to the second connecting pad; forming a contact path in the second hole; forming a first contact pad connected to the contact path on the second insulating layer; forming a column path in the through hole; and forming a second contact pad connected to the column path on the second insulating layer.

[0010] According to an aspect of an example embodiment, a method for manufacturing a semiconductor package may include: preparing a structure including a first connecting pad and a second connecting pad; forming a first insulating layer on the structure using an uncured first photosensitive insulating material; forming a first hole penetrating the first insulating layer and connected to the first connecting pad using a first photolithography process, wherein the first insulating layer is cured by the first photolithography process; forming a redistribution path in the first hole; forming a redistribution layer connected to the redistribution path on the first insulating layer; forming a second insulating layer on the first insulating layer using an uncured second photosensitive insulating material to at least partially cover the redistribution layer; forming a second hole penetrating the second insulating layer and connected to the redistribution layer using a second photolithography process, wherein the second insulating layer is cured by the second photolithography process; forming a contact path in the second hole; forming a first contact pad connected to the contact path on the second insulating layer; forming a through hole penetrating the first insulating layer and the second insulating layer using a dry etching process, the through hole being connected to the second connecting pad; forming a column path in the through hole; and forming a second contact pad connected to the column path on the second insulating layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other aspects, features and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 is a cross-sectional view illustrating a semiconductor package according to one or more example embodiments;

[0013] Figure 2 is a diagram illustrating a method of performing a Figure 1 A plan view of the semiconductor package taken along line II';

[0014] Figure 3 is a diagram illustrating a method according to one or more example embodiments Figure 1 an enlarged view of a portion "A" of the illustrated semiconductor package;

[0015] Figure 4 is a cross-sectional view illustrating a semiconductor package according to one or more example embodiments;

[0016] Figure 5A is a cross-sectional view illustrating a semiconductor package according to one or more example embodiments;

[0017] Figure 5B is a diagram illustrating a method of performing a Figure 5A A plan view of a post via taken along line II-II';

[0018] Fig. 6A and Figure 6B is a cross-sectional view illustrating a semiconductor package according to one or more example embodiments;

[0019] Fig. 7A and Figure 7B is a cross-sectional view illustrating a semiconductor package according to one or more example embodiments;

[0020] FIG. 8A to FIG. 8E is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to one or more example embodiments;

[0021] 9A to 9D is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to one or more example embodiments; and

[0022] FIG. 10A to FIG. 10C is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to one or more example embodiments. DETAILED DESCRIPTION

[0023] Hereinafter, an exemplary embodiment of the present disclosure will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the accompanying drawings, and their redundant descriptions will be omitted. The embodiments described herein are exemplary embodiments, and therefore, the present disclosure is not limited thereto and may be implemented in various other forms.

[0024] As used herein, expressions such as "at least one of...", when preceding a list of elements, modify the entire list of elements, rather than the individual elements of the list. For example, the expression "at least one of a, b, and c" should be understood to include only a; only b; only c; both a and b; both a and c; both b and c; or all of a, b, and c.

[0025] It should be understood that when an element or layer is referred to as being “on,” “over,” “on,” “under,” “under,” “connected to,” or “coupled to” another element or layer, it can be directly on, directly over, directly on, directly under, directly under, directly under, directly connected to or coupled to another element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly over,” “directly on,” “directly under,” “directly under,” “directly under,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers.

[0026] Figure 1 is a cross-sectional view illustrating a semiconductor package according to one or more example embodiments. Figure 2 is a diagram illustrating a method of performing a Figure 1 1 is a plan view of the semiconductor package taken along line II'. Figure 3 is a diagram illustrating a method according to one or more example embodiments Figure 1 An enlarged view of portion 'A' of a semiconductor package is illustrated.

[0027] refer to Figure 1 and Figure 2 According to some embodiments, a semiconductor package 200 may include a first semiconductor chip 140 provided as a base structure, a redistribution structure 150 disposed on the first semiconductor chip 140 and having a redistribution layer 155 and a redistribution via 156 , and a second semiconductor chip 170 mounted on the redistribution structure 150 .

[0028] The first semiconductor chip 140 according to some embodiments may include: a semiconductor substrate 141 having an active surface 141A and an inactive surface 141B disposed opposite to each other; a device layer 142 disposed on the active surface 141A of the semiconductor substrate 141; a first chip pad 145 disposed on the device layer 142; and a through electrode 147 including, for example, a first through electrode 147a and a second through electrode 147b, penetrating the semiconductor substrate 141 and electrically connected to the first chip pad 145. In some embodiments, the first through electrode 147a may refer to a through electrode that is horizontally offset (e.g., does not vertically overlap) from a contact pad 157P of a contact layer 157 and may therefore be referred to as a non-overlapping through electrode 147a, while the second through electrode 147b may refer to a through electrode that vertically overlaps with a contact pad 167P of a contact layer 167 and may therefore be referred to as an overlapping through electrode 147b, as will be described in detail later. As used herein, the phrase "penetrate" may refer to a component completely penetrating or partially penetrating a layer, other component, etc. Moreover, the upper surface (inactive surface 141B) of the semiconductor substrate 141 may include a back insulating layer 149. For example, the semiconductor substrate 141 may include silicon (Si), germanium (Ge), and gallium arsenide (GaAs). In an example embodiment, the active surface 141A may include an active region doped with impurities, and a plurality of active / passive devices (e.g., transistors) may be formed in the active region. The device layer 142 may be constructed as a wiring structure including a wiring circuit 142L connected to the device. The first chip pad 145 may be disposed on the device layer 142, may be connected to the wiring circuit 142L, and may be connected to the through electrode 147 through the wiring circuit 142L. As Figure 3 (as well as Figure 4 ), the through electrode 147 may have an upper end 147T substantially coplanar with an upper surface 149T of the back insulating layer 149. In some embodiments, the upper end 147T of the through electrode 147 may be directly connected to a connection pad 155P (e.g., a redistribution pad) of the redistribution structure 150, but the embodiment is not limited thereto.

[0029] In some embodiments, the first semiconductor chip 140 may further include an additional back side pad connected to the upper end 147T of the through electrode 147, and an additional back side insulating layer may be provided on the back side insulating layer 149. The additional back side insulating layer may have an upper surface substantially coplanar with an upper surface of the additional back side pad.

[0030] In some embodiments, the passivation layer 191 may be disposed on the lower surface of the first semiconductor chip 140 (i.e., the surface on which the device layer 142 is formed). Through the opening of the passivation layer 191, the under-bump metal (UBM) layer 192 and the electrical connection metal 195 may be electrically connected to the first chip pad 145. The semiconductor package 200 may be physically connected and / or electrically connected to an external device (e.g., a motherboard) through the UBM layer 192 and the electrical connection metal 195. The electrical connection metal 195 may be disposed on the UBM layer 192. The electrical connection metal 195 may include a solder of a low melting point metal, for example, tin (Sn)-aluminum (Al)-copper (Cu). In some embodiments, a conductive column may also be included instead of the UBM layer 192. Alternatively, a redistribution substrate having a redistribution layer similar to the redistribution structure 150 may also be disposed on the active surface 141A of the first semiconductor chip 140.

[0031] In some embodiments, the redistribution structure 150 may be disposed on the first semiconductor chip 140 , and may include a redistribution circuit electrically connecting the first semiconductor chip 140 to the second semiconductor chip 170 mounted on an upper surface of the redistribution structure 150 .

[0032] The redistribution structure 150 may include a plurality of insulating layers 151, redistribution elements such as redistribution layers 155 and connection pads 155P, and redistribution paths 156 that penetrate the insulating layers 151 and connect the redistribution layers 155 and connection pads 155P disposed at different heights to each other. At least one redistribution layer 155 and connection pads 155P disposed at different heights may be connected to each other through the redistribution paths 156, and a multi-layer redistribution circuit may be formed. Furthermore, the redistribution structure 150 may include contact layers 157 and 167 for connecting to the second semiconductor chip 170.

[0033] The contact layers 157 and 167 may correspond to redistribution elements. That is, the contact layers 157 and 167 may form a redistribution circuit together with the redistribution layer 155 and the connection pad 155P. The contact layers 157 and 167 according to some embodiments may include a first contact layer 157 that does not overlap (e.g., is horizontally offset from) the through-electrode 147 to be connected in the vertical direction (e.g., a through-electrode such as the through-electrode 147a) and a second contact layer 167 that overlaps the through-electrode 147 to be connected in the vertical direction (e.g., a through-electrode such as the through-electrode 147b).

[0034] In some embodiments, the first contact layer 157 and the second contact layer 167 may have different structures for connecting to corresponding through electrodes 147 of the first semiconductor chip 140 .

[0035] refer to Figure 3 According to some embodiments, the redistribution structure 150 may include connection pads 155P respectively connected to the through electrodes 147 on the first semiconductor chip 140, a first insulating layer 151a arranged on the first semiconductor chip 140 and covering the connection pads 155P, a redistribution layer 155 arranged on the first insulating layer 151a and extending in a horizontal direction, a redistribution path 156 penetrating the first insulating layer 151a and connecting the connection pads 155P to the redistribution layer 155, and a second insulating layer 151b arranged on the first insulating layer 151a and covering the redistribution layer 155.

[0036] The connection pads 155P may be disposed on the through electrodes 147 to be connected to the redistribution layer 155. A portion of the connection pads 155P may include a redistribution element for interconnecting with other through electrodes 147 or changing a position of the connection pads, and thus, the connection pads 155P may correspond to a portion of a redistribution circuit.

[0037] In some embodiments, the first contact layer 157 and the second contact layer 167 may include first and second contact pads 157P and 167P disposed on the second insulating layer 151b, respectively. The first and second contact pads 157P and 167P may have a planar arrangement corresponding to that of the second chip pads 175 of the second semiconductor chip 170 to be mounted on the redistribution structure 150.

[0038] Each first contact layer 157 may include a contact via 157V extending from a first contact pad 157P and penetrating the second insulating layer 151b. The contact via 157V may connect the first contact pad 157P to the redistribution layer 155. The first contact pad 157P may be connected to a connection pad 155P located on the through electrode 147a through the redistribution layer 155 extending in a horizontal direction.

[0039] The second contact layer 167 may include a pillar via 167V extending from the second contact pad 167P and penetrating the first and second insulating layers 151a and 151b. The pillar via 167V may connect the second contact pad 167P to the connection pad 155P on the through electrode 147b without passing through the redistribution layer 155.

[0040] Therefore, in some embodiments, unlike the connection path of the first contact pad 157P and the connection pad 155P, the connection path of the second contact pad 167P and the connection pad 155P can be implemented by an integrated structure called a column path 167V. Unlike a stacked structure (having an interface) formed by two or more metal forming processes (e.g., an electroplating process), the integrated structure may refer to a structure formed by a single metal forming process without an interface. Therefore, unlike a general stacked structure, the integrated column path 167V according to some embodiments can have greater durability to prevent peeling problems caused by thermal shock, etc.

[0041] In some embodiments, the pillar via 167V may have a substantially vertical side surface S2. The profile of the side surface S2 of the pillar via 167V may be determined by a process of forming a hole for the first insulating layer 151a and the second insulating layer 151b. The hole for the pillar via 167V may be formed by curing the first insulating layer 151a and the second insulating layer 151b and processing these layers, and may be formed by, for example, dry etching.

[0042] Therefore, the column via 167V may have a substantially vertical side surface S2. In some embodiments, the contact via 157V may also have a substantially vertical side surface S1 similar to the side surface S2 of the column via 167V. This structure may indicate that the hole (see FIG. 14 ) that forms the column via 167V may be formed. Fig.8D ) The formation of the hole of the contact via 157V is performed in a similar manner (e.g., simultaneously). In some embodiments, the redistribution via 156 may have an inclined side surface Sa such that its width Wa decreases in a vertically downward direction, and the inclined side surface Sa may be different from the side surface S1 of the contact via 157V and the side surface S2 of the pillar via 167V.

[0043] In some embodiments, the width W2 of the pillar via 167V may be greater than the width Wa of the redistribution via 156. The width W1 of the contact via 157V may be greater than the width W2 of the pillar via 167V. Since the height of the pillar via 167V is greater than the height of the contact via 157V, the above-mentioned width condition W1>W2 may be conducive to forming the pillar via 167V and the contact via 157V at similar heights by the electroplating process (see Fig. 8E ).

[0044] In some embodiments, the redistribution structure 150 may be disposed on the second semiconductor chip 170, and may further include connection pads 155P respectively disposed on the through electrodes 147. A portion of the connection pads 155P (also referred to as non-overlapping connection pads 155P) may be disposed on the through electrode 147a electrically connected to the first contact pad 157P (i.e., may be disposed on the through electrode 147a that does not overlap (e.g., is horizontally offset from) the first contact pad 157P), and at least one other connection pad 155P (also referred to as overlapping connection pad 155P) may be disposed on the through electrode 147b that overlaps the second contact pad 167P, and may be directly connected to the pillar via 167V.

[0045] The connection pads 155P, the redistribution layer 155, and the contact layers 157 and 167 disposed at different heights may be connected to each other through the redistribution vias 156 and the contact vias 157V, and a multi-layer redistribution circuit may be formed. The redistribution structure 150 according to some embodiments is illustrated as a double-layer structure including two insulating layers 151a and 151b, but in other embodiments, the redistribution structure 150 may be implemented to include three or more insulating layers and two or more redistribution layers 155.

[0046] In some embodiments, the first insulating layer 151a and the second insulating layer 151b may use a photosensitive insulating material such as a photosensitive insulating (PID) resin. When the first insulating layer 151a and the second insulating layer 151b are formed of a photosensitive insulating resin, the redistribution layer 155 may be formed into a fine pattern using a photolithography process. In some embodiments, at least one insulating layer 151 may include a thermosetting resin such as an epoxy resin or a thermoplastic resin such as polyimide.

[0047] The redistribution layer 155 may be disposed on the first insulating layer 151a and may be connected to the connection pad 155P through a redistribution via 156 penetrating the first insulating layer 151a. The redistribution via 156 may be formed together with the redistribution layer 155 using the same electroplating process at the same height (e.g., the same insulating layer 151a). For example, the redistribution layer 155 may include a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. In some embodiments, the redistribution layer 155 may include additional patterns having various functions (e.g., a grounding pattern).

[0048] The redistribution via 156 may have a tapered structure determined according to a formation direction. In some embodiments, the redistribution via 156 may have a width that gradually decreases from an upper surface of the redistribution structure 150 toward a lower surface of the redistribution structure 150 .

[0049] Similar to the redistribution layer 155 and the redistribution path 156, the first contact pad 157P and the contact path 157V can be formed by the same electroplating process, and the second contact pad 167P and the column path 167V can also be formed by the same electroplating process. For example, the contact layers 157 and 167 may include a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) or their alloys. In some embodiments, the contact path 157V and the column path 167V may include copper (Cu), and the first contact pad 157P and the second contact pad 167P may include nickel (Ni). In some embodiments, a surface treatment layer 169 may be included on each of the first contact pad 157P and the second contact pad 167P. For example, the surface treatment layer 169 may include gold (Au).

[0050] The second semiconductor chip 170 may be mounted on the redistribution structure 150 and may be connected to the redistribution layer 155 through the first contact layer 157 and the second contact layer 167. The second semiconductor chip 170 may include a second chip pad 175 disposed on the lower surface, and the second chip pad 175 may be connected to the first contact pad 157P and the second contact pad 167P, respectively, through a conductive bump 197 such as a microbump. Figure 1 As illustrated, the non-conductive film 182 may be disposed in a space between the second semiconductor chip 170 and the redistribution structure 150 to at least partially surround the conductive bump 197. In some embodiments, the non-conductive film 182 may be replaced with an underfill resin.

[0051] In some embodiments, the molding portion 185 may be formed to at least partially surround the second semiconductor chip 170 on the redistribution structure 150. The molding portion 185 may have an upper surface substantially coplanar with an upper surface of the second semiconductor chip 170. For example, the molding portion 185 may include an insulating resin such as epoxy molding compound (EMC).

[0052] Therefore, in the redistribution structure 150 according to some embodiments, a pillar via 167V penetrating the plurality of insulating layers 151a and 151b may be provided between the second contact pad 167P and the connection pad 155P (or the through-electrode 147) instead of the stacked via structure. Unlike a general stacked via structure, the pillar via 167V may have an integrated structure without an interface between metals, thereby solving the delamination problem between metals due to thermal shock.

[0053] The pillar via 167V may be formed in various structures instead of the stacked via structure. Also, the formation of the pillar via 167V may vary depending on the process of forming other elements and the method of coupling the elements.

[0054] Figure 4 , Figure 5A , Fig. 6A and Figure 6B A semiconductor package according to various example embodiments is illustrated and may be Figure 3 corresponding parts, and can be understood as illustrating Figure 1 Magnified view of the portion in .

[0055] Figure 4 is a cross-sectional view illustrating a semiconductor package according to one or more example embodiments.

[0056] refer to Figure 4 , except that the first contact pad 157P′ and the contact via 157V′ may be configured differently from the first contact pad 157P and the contact via 157V in the aforementioned example embodiment, the semiconductor package 200A according to some embodiments may be similar to Figures 1 to 3 The semiconductor package 200 shown is similar. Therefore, unless otherwise indicated, Figures 1 to 3 The description in the illustrated example embodiments may be combined with the description in the preceding example embodiments.

[0057] In some embodiments, the side surface S2 of the pillar via 167V may be substantially vertical, whereas the contact via 157V' may have an inclined side surface S1' so that its width W1' decreases in a vertically downward direction. The redistribution via 156 may have an inclined side surface Sa similar to the side surface of the contact via 157V' so that its width Wa decreases in a vertically downward direction.

[0058] The first contact pad 157P′ may be formed together with the contact via 157V′, and the same process as that for forming the second contact pad 167P and the pillar via 167V may be used (see 9A to 9D In some embodiments, the width W1' of the contact via 157V' may be constructed without considering the width W2 of the pillar via 167V, and in some embodiments, the width W2 of the pillar via 167V' may be equal to or greater than the width W1' of the contact via 157V'.

[0059] Figure 5A is a cross-sectional view illustrating a semiconductor package according to one or more example embodiments. Figure 5B is a diagram illustrating a method of performing a Figure 5A A plan view of the column passage taken along line II-II'.

[0060] refer to Figure 5A and Figure 5BIn addition to the configuration in which a plurality of pillar vias 167V′ are provided and the configuration in which the redistribution via 156 may have a vertical side surface, the semiconductor package 200B according to some embodiments may be similar to Figures 1 to 3 The semiconductor package 200 shown is similar. Therefore, unless otherwise indicated, Figures 1 to 3 The description of some of the illustrated embodiments may be combined with the description of the preceding example embodiments.

[0061] In some embodiments, a plurality of pillar vias 167V' may be disposed under the second contact pad 167P. The second contact pad 167P and the connection pad 155P overlapping therewith may be connected to each other through the plurality of pillar vias 167V'. Figure 5B , four column passages 167V' are illustrated, but the embodiment is not limited thereto, and the plurality of column passages 167V' may include two, three or more passages.

[0062] Each pillar via 167V' may have a relatively small width, and may achieve a stable connection between the second contact pad 167P and the connection pad 155P while reducing the total volume. Therefore, when the contact via 157V and the pillar via 167V' are formed at the same time, even when the width W1 of the contact via 157V is slightly increased, the contact via 157V may have a volume similar to that of the pillar via 167V'. That is, the width W1 of the contact via 157V according to some embodiments may be designed to be less than Figure 3 Width of the contact via in the illustrated embodiment.

[0063] Also, in some embodiments, similar to the contact via 157V′ and the pillar via 167V, the redistribution via 156 may have a substantially vertical side surface Sa. The first insulating layer 151a may be cured (see FIG. 10A to FIG. 10C ) and thereafter a hole is formed to obtain the profile of the side surface of this redistribution passage 156.

[0064] In some embodiments, the connection pad 155P may not be disposed on the through electrode 147 b overlapping the second contact pad 167P in the vertical direction.

[0065] Fig. 6A and Figure 6B is a cross-sectional view illustrating a semiconductor package according to one or more example embodiments.

[0066] refer to Fig. 6A , except that the connection pad 155P is not disposed on the through electrode 147b overlapping the second contact pad 167P in the vertical direction, the structure may be similar to Figure 3 The illustrated semiconductor package 200 configures a semiconductor package 200C according to some embodiments.

[0067] Therefore, in some embodiments, the pillar via 167V may be directly connected to the overlapping through-electrode 147b. The connection pad 155P may be disposed on each through-electrode (eg, the through-electrode 147a horizontally offset from the contact pad 157P) among the through-electrodes 147 except the overlapping through-electrode 147b.

[0068] refer to Figure 6B , except that the connection pad 155P may not be disposed on the through electrode 147b overlapping the second contact pad 167P in the vertical direction and the width of the pillar via 167V may be increased, it may be similar to Figure 4 The illustrated semiconductor package 200A configures a semiconductor package 200D according to some embodiments.

[0069] In some embodiments, the pillar via 167V may be directly connected to the overlapping through-electrode 147b. Fig. 6A and Figure 6B When a connection pad is not provided under the column via 167V, the back insulating layer 149 can be used as an etch stop layer instead of a connection pad in the process of forming a hole for the column via 167V. In some embodiments, the width W2' of the column via 167V is not limited to the connection pad area and can be substantially increased. For example, the width W2' of the column via 167V can be substantially the same as the width of the second contact pad 167P.

[0070] The redistribution structure 150 disposed between the first semiconductor chip 140 and the second semiconductor chip 170 may be connected to the first semiconductor chip 140 through the through-electrodes 147 of the first semiconductor chip 140 , and may electrically connect the first semiconductor chip 140 to the second semiconductor chip 170 .

[0071] As a redistribution substrate, the example embodiments disclosed herein may be beneficially applicable to packages having various structures including the following structure: the structure further includes a first redistribution structure on the lower surface of the first semiconductor chip 140. In this case, the first redistribution structure may be electrically connected to the second redistribution structure through a vertical connection conductor disposed on its upper surface. Therefore, the first semiconductor chip 140 connected to the first redistribution structure and the second semiconductor chip 170 connected to the second redistribution structure may be interconnected.

[0072] Fig. 7A and Figure 7B is a cross-sectional view illustrating a semiconductor package according to one or more example embodiments.

[0073] First, refer to Fig. 7A, a semiconductor package 300A according to some embodiments may include a first redistribution structure 120, a semiconductor chip 140 mounted on the first redistribution structure 120, a molding portion 130 disposed on the first redistribution structure 120 and sealing the semiconductor chip 140, and a second redistribution structure 150 disposed on the molding portion 130. Also, the semiconductor package 300A may further include a frame 110, first and second passivation layers 191A and 191B, a UBM layer 192, and an electrical connection metal 195.

[0074] The first redistribution structure 120 may include a first redistribution layer 125 for redistributing the chip pads 145 of the semiconductor chip 140. The first redistribution structure 120 may be physically and / or electrically connected to an external device (eg, a main board) through the UBM layer 192 and the electrical connection metal 195.

[0075] The first redistribution structure 120 may include a plurality of insulating layers 121 and a first redistribution layer 125 disposed on each insulating layer 121, and a redistribution via 126 penetrating each insulating layer 121 and connecting a chip pad 145 of the semiconductor chip 140 to the first redistribution layer 125 at another height. The first redistribution structure 120 according to some embodiments is illustrated as including three insulating layers 121 and three first redistribution layers 125, each having a redistribution via 126. In some embodiments, the first redistribution structure 120 may include one or two or more insulating layers 121 and the first redistribution layer 125.

[0076] The frame 110 may be disposed on the first redistribution structure 120 and may include a cavity in which the semiconductor chip 140 is accommodated. The frame 110 may include a wiring structure 115 electrically connecting the upper surface to the lower surface. In some embodiments, the wiring structure 115 may be provided as a vertical connection conductor connecting the first redistribution structure 120 and the second redistribution structure 150 to each other.

[0077] According to some embodiments, the wiring structure 115 may include three wiring layers (such as a first wiring layer 112a, a second wiring layer 112b, and a third wiring layer 112c) and a first wiring via 113a and a second wiring via 113b connecting the first wiring layer 112a, the second wiring layer 112b, and the third wiring layer 112c, but the embodiment is not limited thereto, and in some embodiments, the wiring structure 115 may have a different number of layers and structures. The first redistribution layer 125 (especially the uppermost first redistribution layer) may be connected to the chip pad 145 of the semiconductor chip 140 and the wiring structure 115 through the first redistribution via 146.

[0078] Thus, the wiring structure 115 may be connected to the first redistribution layer 125 of the first redistribution structure 120, and may be electrically connected to the semiconductor chip 140 through the first redistribution structure 120. The frame 110 according to some embodiments may include a first insulating layer 111a, a first wiring layer 112a contacting the first redistribution structure 120 and buried in the first insulating layer 111a, a second wiring layer 112b disposed on the first insulating layer 111a at a side opposite to the buried side of the first wiring layer 112a, a second insulating layer 111b disposed on the first insulating layer 111a and covering the second wiring layer 112b, and a third wiring layer 112c disposed on the second insulating layer 111b. The first wiring layer 112a, the second wiring layer 112b, and the third wiring layer 112c may be electrically connected to each other through first wiring vias 113a and second wiring vias 113b penetrating the first insulating layer 111a and the second insulating layer 111b, respectively.

[0079] In some embodiments, the second redistribution structure 150 may be disposed on the semiconductor chip 140. Similar to the first redistribution structure 120, the second redistribution structure 150 may include an insulating layer 151, a second redistribution layer (including a lower redistribution layer 155a and an upper redistribution layer 155b) disposed at different heights, and a second redistribution via (including a lower redistribution via 156a and an upper redistribution via 156b) penetrating the insulating layer 151 and connected to the lower redistribution layer 155a and the upper redistribution layer 155b, respectively. Specifically, the lower redistribution layer 155a may be connected to the wiring structure 115 (especially the third wiring layer 112c) through the lower redistribution via 156a penetrating the molding portion 130. The upper redistribution layer 155b may be connected to the lower redistribution layer 155a through the upper redistribution via 156b penetrating the insulating layer 151.

[0080] In some embodiments, the first contact layer 157 and the second contact layer 167 may include a first contact pad 157P and a second contact pad 167P disposed on the insulating layer 151, respectively. In some embodiments, the first contact layer 157 may be formed with an upper redistribution layer 155b and an upper redistribution via 156b. An additional semiconductor chip mounted on the second redistribution structure 150 and connected to the first contact pad 157P and the second contact pad 167P may not be provided.

[0081] The wiring structure 115 may include a first vertical connecting conductor 115x (also known as a non-overlapping wiring structure) that is horizontally offset from the contact pad 157P (i.e., does not overlap with the contact pad 157P) and a second vertical connecting conductor 115y (also known as an overlapping wiring structure) that vertically overlaps with the contact pad 167P.

[0082] The contact via 157V may extend from the first contact pad 157P and may penetrate the insulating layer 151. The contact via 157V may connect the first contact pad 157P to the upper redistribution layer 155b. The first contact pad 157P may be connected to the third wiring layer 112c on the non-overlapping wiring structure 115 (e.g., the vertical connection conductor 115x) through the second redistribution layer (including the lower redistribution layer 155a and the upper redistribution layer 155b) extending in the horizontal direction.

[0083] The pillar via 167V may extend from the second contact pad 167P and may penetrate the region of the insulating layer 151 and the mold portion 130. The pillar via 167V may connect the second contact pad 167P to the third wiring layer 112c disposed on the overlapped wiring structure 115 (e.g., the vertical connection conductor 115y) without passing through the second redistribution layer (including the lower redistribution layer 155a and the upper redistribution layer 155b).

[0084] Therefore, in some embodiments, the pillar via 167V connecting the second contact pad 167P to the third wiring layer 112c may have an integrated structure without an interface, so that the pillar via 167V may have greater durability against peeling problems due to thermal shock.

[0085] Furthermore, column passage 167V may have substantially vertical side surfaces. Figure 4 As described in , unlike the side surface S2 of the pillar path 167V, the contact path 157V may have an inclined side surface. Similar to the second redistribution path (including the lower redistribution path 156a and the upper redistribution path 156b), the contact path 157V may have an inclined side surface so that its width decreases in the vertical downward direction.

[0086] The semiconductor package according to some embodiments may include a first passivation layer 191A and a second passivation layer 191B. The first passivation layer 191A and the second passivation layer 191B may protect the first redistribution structure 120 and the second redistribution structure 150 from external physical damage and chemical damage, respectively. The first passivation layer 191A may be disposed on the lower surface of the first redistribution structure 120 and may include a plurality of first openings. The UBM layer 192 may be disposed on the first passivation layer 191A and may be connected to the first redistribution layer 125 through the openings, respectively. The second passivation layer 191B may be disposed on the upper surface of the second redistribution structure 150 and may include a plurality of second openings PH that open the pad area. For example, the first passivation layer 191A and the second passivation layer 191B may include an insulating material such as a prepreg, an Ajinomoto built-up film (ABF), FR-4, a bismaleimide triazine (BT) solder resist, or a PID.

[0087] The semiconductor chip 140 according to some embodiments may include a semiconductor substrate having an active surface on which various devices are formed, a chip pad 145 connected to the various devices, and a passivation film 148 protecting the active surface. The semiconductor substrate 141 may include, for example, silicon (Si), germanium (Ge), or gallium arsenide (GaAs). The chip pad 145 may be an element for electrically connecting the semiconductor chip 140 to another element (the first redistribution layer 125), and may include, for example, aluminum (Al) or copper (Cu). The passivation film 148 may include an oxide film and / or a nitride film.

[0088] The semiconductor chip 140 may be a processor chip. For example, the semiconductor chip 140 may include a microprocessor, a graphics processor, a signal processor, a network processor, a chipset, an audio codec, a video codec, an application processor or a system on chip, an application specific integrated circuit (IC) (ASIC) or a power management IC (PMIC), but some embodiments thereof are not limited thereto. For example, the microprocessor may include a single core or multiple cores. In some embodiments, the semiconductor chip 140 may be implemented as a volatile memory chip and / or a non-volatile memory chip. For example, a volatile memory chip may include a dynamic random access memory (DRAM), a static RAM (SRAM), a thyristor RAM (TRAM), a zero capacitor RAM (ZRAM) or a dual transistor RAM (TTRAM). Moreover, a non-volatile memory chip may include, for example, flash memory, a magnetic RAM (MRAM), a spin transfer torque MRAM (STT-MRAM), a ferroelectric RAM (FRAM), a phase change RAM (PRAM), a resistive RAM (RRAM), a nanotube RRAM, a polymer RAM, a nano floating gate memory, a holographic memory, a molecular electronic memory or an insulator resistance change memory.

[0089] The molding part 130 may protect the frame 110 and the semiconductor chip 140. For example, the material of the molding part 130 may include a thermosetting resin such as epoxy resin or a thermoplastic resin such as polyimide. In some embodiments, the molding part 130 may be formed of EMC.

[0090] In the aforementioned exemplary embodiments, the vertical connection conductors connected to the redistribution layer of the redistribution structure and connected to the upper surface of the semiconductor package may be implemented in the form of a wiring structure of a frame, but the vertical connection conductors may be provided on the redistribution structure without a frame structure, and may also be provided as conductive pillars penetrating the molded portion. These exemplary embodiments are illustrated in Figure 7B middle.

[0091] refer to Figure 7B, except that a configuration in which a conductive pillar 115P may be provided instead of a frame and a configuration in which the second redistribution structure 150 may include two insulating layers 151a and 151b, may be similar to Fig. 7A The illustrated semiconductor package 300A configures a semiconductor package 300B according to some embodiments. Therefore, unless otherwise indicated, Figures 1 to 3 and Fig. 7A The description of some of the illustrated embodiments may be combined with the description of the preceding example embodiments.

[0092] The semiconductor package 300B according to some embodiments may be a semiconductor package formed at the wafer level. The semiconductor package 300B may include a vertical connection conductor for interconnecting the first redistribution structure 120 with the second redistribution structure 150, and the vertical connection conductor may be provided as a conductive pillar 115P such as a copper (Cu) pillar. The conductive pillar 115P may be formed to penetrate the mold portion 130 that seals the semiconductor chip 140. The first redistribution layer 125 and the second redistribution layer (including the lower redistribution layer 155a and the upper redistribution layer 155b) may be electrically connected to each other through the conductive pillar 115P. In some embodiments, the conductive pillar 115P may have an upper end that is substantially coplanar with the upper surface of the mold portion 130.

[0093] In some embodiments, the second redistribution structure 150 may be disposed on the mold portion 130. The second redistribution structure 150 may include insulating layers 151a and 151b, second redistribution layers (including a lower redistribution layer 155a and an upper redistribution layer 155b) disposed on the insulating layers 151a and 151b, respectively, and second redistribution vias (including a lower redistribution via 156a and an upper redistribution via 156b) penetrating the insulating layers 151a and 151b and connected to the second redistribution layers (including the lower redistribution layer 155a and the upper redistribution layer 155b), respectively. Specifically, the lower redistribution layer 155a may be connected to the conductive pillar 115P through the lower redistribution via 156a penetrating the first insulating layer 151a. The upper redistribution layer 155b may be connected to the lower redistribution layer 155a through the upper redistribution via 156b penetrating the second insulating layer 151b.

[0094] In some embodiments, the first contact layer 157 and the second contact layer 167 may include a first contact pad 157P and a second contact pad 167P disposed on the second insulating layer 151b, respectively. In some embodiments, the contact path 157V may extend from the first contact pad 157P and may penetrate the second insulating layer 151b. The contact path 157V may connect the first contact pad 157P to the upper redistribution layer 155b. The first contact pad 157P may be connected to the conductive pillar 115P2 through the second redistribution layer (including the lower redistribution layer 155a and the upper redistribution layer 155b) extending in the horizontal direction. That is, the conductive pillar 115P2 may be horizontally offset from the contact pad 157P so that the conductive pillar 115P2 does not overlap with the contact pad 157P.

[0095] The pillar via 167V may extend from the second contact pad 167P and may penetrate the first insulating layer 151a and the second insulating layer 151b. The pillar via 167V may connect the second contact pad 167P to the conductive pillar 115P1 without passing through the second redistribution layer (including the lower redistribution layer 155a and the upper redistribution layer 155b). That is, the contact pad 167P may vertically overlap the conductive pillar 115P1.

[0096] Therefore, in some embodiments, the pillar via 167V connecting the second contact pad 167P to the conductive pillar 115P1 may have an integrated structure without an interface, so that the pillar via 167V may have greater durability against peeling problems due to thermal shock.

[0097] FIG. 8A to FIG. 8E is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to one or more example embodiments. The manufacturing method according to some embodiments may be understood as Figure 3 The manufacturing process of the semiconductor package 200 is shown.

[0098] refer to Fig. 8A , a first semiconductor chip 140 having first and second connection pads 155P1 and 155P2 may be prepared, and a first insulating layer 151 a ′ may be formed on the first semiconductor chip 140 using an uncured photosensitive insulating material.

[0099] In some embodiments, the first insulating layer 151a' may be configured as an uncured insulating layer and may include, for example, a photosensitive insulating material such as PID. The connection pads including the first connection pad 155P1 and the second connection pad 155P2 may be disposed on the through electrode 147, and in some embodiments, the first connection pad 155P1 may include a redistribution element for interconnecting with another through electrode 147 or for changing the position of the pad, and thus may be understood as part of a redistribution circuit.

[0100] The structure to which some embodiments can be applied is not limited to a semiconductor chip having through electrodes, and can also be usefully applied to various structures having a redistribution structure for interconnection disposed in a vertical direction on its upper surface. Fig. 7A and Figure 7B A lower package structure is shown having vertical connecting conductors (eg, structures 115 and 115P).

[0101] Afterwards, refer to Figure 8B , a first hole H1 connected to the first connection pad 155P1 may be formed through the first insulating layer 151a' using a photolithography process.

[0102] The first insulating layer 151a' may be cured by a photolithography process (exposure and development) (to form the first insulating layer 151a). Similarly, the second connection pad 155P2 may still be covered by the first insulating layer 151a. The second connection pad 155P2 may be a contact pad ( Fig. 8E The second contact pad 167P in the figure overlaps the connecting pad.

[0103] Afterwards, refer to Figure 8C , the first hole H1 may be filled with a redistribution via 156. A redistribution layer 155 connected to the redistribution via 156 may be formed on the first insulating layer 151a and the redistribution via 156 filled in the first hole H1, and a second insulating layer 151b′ may be formed on the first insulating layer 151a to cover the redistribution layer 155.

[0104] The redistribution layer 155 and the redistribution via 156 may be formed together by a plating process such as electrolytic plating. The second insulating layer 151b' may be configured as an uncured insulating layer and, for example, may include a photosensitive material similar to the first insulating layer, but some embodiments thereof are not limited thereto.

[0105] Afterwards, refer to Fig.8D , the second insulating layer 151 b ′ may be cured (to form the second insulating layer 151 b ), and the second hole H2 for the contact via and the through hole TH for the pillar via may be formed using the mask M1 .

[0106] The second hole H2 may penetrate the second insulating layer 151b and may be connected to the redistribution layer 155. The through hole TH may penetrate the first insulating layer 151a and the second insulating layer 151b and may be connected to the second connection pad 155P2. The second hole H2 and the through hole TH may be simultaneously formed in the cured first insulating layer 151a and the second insulating layer 151b using a dry etching process. Therefore, unlike the first hole H1 having an inclined sidewall, the second hole H2 and the through hole TH obtained by the dry etching process may have substantially vertical sidewalls. These sidewalls may respectively define contact paths ( Fig. 8E "157V" in the column path ( Fig. 8E The profile of the side surface of the “167V” in FIG.

[0107] In the process of forming the second hole H2, the redistribution layer 155 may be used as an etching stop layer. Also, during the process of forming the through hole TH, the connection pad 155P may be used as an etching stop layer. Through the etching stop layer, the second hole H2 and the through hole TH having different depths may be formed. The width W1 of the second hole H2 may be formed to be greater than the width W2 of the through hole TH.

[0108] Afterwards, refer to Fig. 8E , the second hole H2 and the through hole TH may be filled with metal, thereby forming the first contact layer 157 and the second contact layer 167 .

[0109] The process of forming the first contact layer 157 and the second contact layer 167 may be performed simultaneously using an electroplating process such as electrolytic plating. The first contact layer 157 may include a contact path 157V filled in the second hole H2 and a first contact pad 157P formed on the second insulating layer 151b and connected to the contact path 157V. The second contact layer 167 may include a column path 167V filled in the through hole TH and a second contact pad 167P formed on the second insulating layer 151b and connected to the column path 167V. The second hole H2 and the through hole TH may be filled simultaneously to form the contact path 157V and the column path 167V. The width of the through hole TH may be adjusted according to the width of the second hole H2 so that the contact path 157V and the column path 167V are formed at a similar height (dashed line).

[0110] In some embodiments, contact via 157V and pillar via 167V may include a metal different from the metal of first contact pad 157P and second contact pad 167P. For example, contact via 157V and pillar via 167V may include copper, while first contact pad 157P and second contact pad 167P may include nickel. In addition, surface treatment layer 169 may include gold (Au).

[0111] 9A to 9Dis a cross-sectional view illustrating a method of manufacturing a semiconductor package according to one or more example embodiments. The manufacturing method according to some embodiments may be understood as manufacturing Figure 4 The process of the semiconductor package 200A is shown.

[0112] Later on you can FIG. 8A to FIG. 8C After a series of processes in Fig.9A The second hole H2' may be formed by a photolithography process when the second insulating layer 151 is in an uncured state. The second hole H2' may penetrate the second insulating layer 151b and may be connected to the redistribution layer 155. The second insulating layer 151a may be cured by this photolithography process (exposure and development). FIG. 8A to FIG. 8E In the second hole H2, since the second hole H2' is formed by a photolithography process in some embodiments, the second hole H2' may have an inclined sidewall.

[0113] Afterwards, refer to Fig. 9B , the contact via 157V' may fill the second hole H2', and a first contact pad 157P' connected to the contact via 157V' may be formed on the second insulating layer 151b. Similar to the formation of the redistribution layer 155 and the redistribution via 156, the contact via 157V' and the first contact pad 157P' may be formed by an electroplating process.

[0114] Afterwards, refer to Fig. 9C , a through hole TH connected to the second connection pad 155P2 can be formed using a mask M2.

[0115] This process may be performed by a dry etching process. The through hole TH may penetrate the first insulating layer 151a and the second insulating layer 151b and may be connected to the second connection pad 155P2. Unlike the inclined sidewall of the second hole H2' formed in the previous process, the through hole TH formed by the dry etching process may have a substantially vertical sidewall.

[0116] Afterwards, refer to Fig.9D , a second contact layer 167 may be formed on the through hole TH using a mask M3. The second contact layer 167 may be disposed on the second insulating layer 151b and the pillar via 167V filled in the through hole TH, and a second contact pad 167P connected to the pillar via 167V may be formed.

[0117] FIG. 10A to FIG. 10C is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to one or more example embodiments. The manufacturing method according to some embodiments may be understood as manufacturing Figure 5A The process of the semiconductor package 200B is shown.

[0118] Fig. 10A The process in can be understood as Fig.9A Specifically, a first insulating layer 151a may be formed on the first semiconductor chip 140 to cover the first connection pad 155P1 and the second connection pad 155P2, and the first insulating layer 151a may be cured. Thereafter, using a dry etching process, a first hole H1' that penetrates the first insulating layer 151a and is connected to the first connection pad 155P1 may be formed. The first hole H1' formed in this process may have a substantially vertical sidewall.

[0119] Afterwards, refer to Fig. 10B , a redistribution via 156 may fill the first hole H1′, a redistribution layer 155 connected to the redistribution via 156 may be formed on the first insulating layer 151a and the redistribution via 156 filled in the first hole H1′, and a second insulating layer 151b′ may be formed on the first insulating layer 151a to cover the redistribution layer 155.

[0120] Afterwards, refer to Fig. 10C , the second insulating layer 151b' may be cured (to form the second insulating layer 151b), and using the mask M4, a second hole H2 penetrating the second insulating layer 151b and connected to the redistribution layer 155 and a through hole TH' penetrating the first insulating layer 151a and the second insulating layer 151b and connected to the second connection pad 155P2 may be formed. The mask M4 may include an opening area for a plurality of through holes TH' in the via area. The second hole H2 and the through hole TH' may be formed using a dry etching process, and each hole may have a substantially vertical sidewall. Thereafter, by performing an electroplating process, a through hole having a substantially vertical sidewall may be formed. Figure 5A and Figure 5B The semiconductor package 200B of the illustrated first contact layer and the second contact layer.

[0121] According to example embodiments, a column via penetrating multiple insulating layers may be provided between a contact pad and a connection pad (or a through-electrode) vertically overlapping each other. Unlike a general stacked via structure, the column via may have an integrated structure without a metal interface, so that the delamination problem may be solved even when stress is concentrated.

[0122] Each embodiment provided in the above description is not exclusive of association with one or more features of another example or another embodiment that is additionally provided herein or that is not provided herein but is consistent with the present disclosure.

[0123] While example embodiments have been illustrated and described above, it will be appreciated by those skilled in the art that modifications and variations can be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A semiconductor package, comprising: A first semiconductor chip, the first semiconductor chip comprising a semiconductor substrate having an active surface and an inactive surface, a device layer located on the active surface, a first chip pad located on the device layer, and a first through electrode and a second through electrode, wherein the first through electrode and the second through electrode penetrate the semiconductor substrate, at least one of the first chip pads is connected to the first through electrode and at least one of the first chip pads is connected to the second through electrode; a redistribution structure comprising a redistribution layer on the inactive surface of the semiconductor substrate and a redistribution via connected to the redistribution layer; a contact pad located on an upper surface of the redistribution structure; and a second semiconductor chip located on the redistribution structure and comprising a second chip pad connected to the contact pad, The contact pads include a first contact pad connected to the first through-electrode through the redistribution layer and a second contact pad vertically overlapping the second through-electrode, wherein the redistribution structure further comprises at least one pillar via penetrating the redistribution structure and connecting the second contact pad to the second through-electrode, and The redistribution structure further includes a contact path connecting the first contact pad to the redistribution layer.

2. The semiconductor package according to claim 1, wherein: The redistribution structure further includes a first insulating layer located on the upper surface of the first semiconductor chip and a second insulating layer located on the first insulating layer. Wherein, the redistribution layer is located on the first insulating layer, and The redistribution via penetrates the first insulating layer and connects the redistribution layer to the first through-electrode.

3. The semiconductor package according to claim 2, wherein: The first contact pad and the second contact pad are located on the second insulating layer, wherein the contact via penetrates the second insulating layer and connects the first contact pad to the redistribution layer, and Wherein, the at least one pillar via penetrates the first insulating layer and the second insulating layer.

4. The semiconductor package according to claim 1, wherein: The at least one post via and the contact via each have a vertical side surface.

5. The semiconductor package according to claim 4, wherein: The at least one post via has a width that is smaller than a width of the contact via.

6. The semiconductor package according to claim 4, wherein: The redistribution via has a width that decreases vertically downward.

7. The semiconductor package according to claim 1, wherein: The at least one column passage has a vertical side surface, and The contact passage has an inclined side surface so that the contact passage has a width that decreases vertically downward.

8. The semiconductor package according to claim 7, wherein: The redistribution via has an inclined side surface such that the redistribution via has a width that decreases vertically downward.

9. The semiconductor package according to claim 7, wherein: The at least one pillar via includes a plurality of pillar vias connected to the second contact pad.

10. The semiconductor package according to claim 1, wherein The redistribution via has vertical side surfaces.

11. The semiconductor package according to claim 1, wherein: The at least one pillar via has a width greater than a width of the redistribution via.

12. The semiconductor package according to claim 1, wherein The at least one column passage has an integral structure.

13. The semiconductor package according to claim 1, wherein: The first semiconductor chip further includes a back side insulating layer having an upper surface substantially coplanar with upper surfaces of the first through electrodes and the second through electrodes.

14. The semiconductor package according to claim 1, wherein The redistribution structure further includes a first connection pad and a second connection pad respectively located on the first through-electrode and the second through-electrode. wherein the first connection pad is connected to the redistribution layer through the redistribution path and to the first contact pad through the redistribution layer, and Wherein, the second connecting pad is connected to the second contact pad through the at least one pillar via.

15. A semiconductor package, comprising: a first redistribution structure comprising a first redistribution layer and a first redistribution via connected to the first redistribution layer; a semiconductor chip located on the first redistribution structure and comprising a chip pad connected to the first redistribution layer; a molding portion located on the first redistribution structure and at least partially surrounding the semiconductor chip; a second redistribution structure located on the molding portion and comprising a second redistribution layer and a second redistribution via connected to the second redistribution layer; a contact pad, the contact pad being located on an upper surface of the second redistribution structure; as well as a first vertical connecting conductor and a second vertical connecting conductor, the first vertical connecting conductor and the second vertical connecting conductor being located on the first redistribution structure and connecting the first redistribution layer to the second redistribution layer, The contact pads include a first contact pad connected to the first vertical connection conductor through the second redistribution layer and a second contact pad vertically overlapping the second vertical connection conductor, and the first contact pad is horizontally offset from the first vertical connection conductor. wherein the second redistribution structure further comprises a contact path connecting the first contact pad to the second redistribution layer, and The second redistribution structure further includes a pillar via connecting the second contact pad to the second vertical connection conductor.

16. The semiconductor package according to claim 15, wherein: The pillar via and the contact via each have a vertical side surface, and The second redistribution path has a width that decreases vertically downward.

17. The semiconductor package according to claim 16, wherein: The post via has a width that is smaller than a width of the contact via.

18. The semiconductor package according to claim 15, wherein: The column passage has an integrated structure including vertical side surfaces, wherein the contact passage has an inclined side surface so that the contact passage has a width that decreases vertically downward, and The second redistribution via has an inclined side surface such that the second redistribution via has a width that decreases vertically downward.

19. The semiconductor package according to claim 15, further comprising: a frame located on the first redistribution structure and at least partially surrounding the semiconductor chip, The first vertical connection conductor and the second vertical connection conductor each include a wiring structure connecting an upper surface of the frame to a lower surface of the frame.

20. A semiconductor package, comprising: A first semiconductor chip, the first semiconductor chip comprising a semiconductor substrate having an active surface and an inactive surface opposite to the active surface, a device layer located on the active surface, a first chip pad located on the device layer, and a through electrode penetrating the semiconductor substrate and connected to the first chip pad; a redistribution structure located on the inactive surface of the first semiconductor chip; a first contact pad and a second contact pad, the first contact pad and the second contact pad being located on an upper surface of the redistribution structure, wherein the second contact pad vertically overlaps one of the through electrodes; and a second semiconductor chip located on the redistribution structure and comprising second chip pads connected to the first contact pads and the second contact pads, respectively, The redistribution structure includes a first insulating layer located on the upper surface of the first semiconductor chip, a redistribution layer located on the first insulating layer, a redistribution path penetrating the first insulating layer and connecting the redistribution layer to the through-electrode, and a second insulating layer located on the first insulating layer and at least partially covering the redistribution layer. wherein the first contact pad is located on the second insulating layer, and the redistribution structure further comprises a contact path penetrating the second insulating layer and connected to the redistribution layer, and The second contact pad is located on the second insulating layer, and the redistribution structure further includes a pillar via that penetrates the first insulating layer and the second insulating layer and is connected to the one through-electrode vertically overlapping the second contact pad.

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