Charge pump circuit and electronic device

Abstract

The present invention provides a charge pump circuit and an electronic device, wherein the circuit includes a voltage control module and a charge pump, wherein the voltage control module includes a comparison unit and a voltage control unit. The charge pump circuit is used to compare and process the boost voltage and the reference output voltage to obtain a first comparison signal, and to compare and process the first comparison signal with the floating ground voltage of the first node to obtain a second comparison signal; the first end of the voltage control unit receives the functional voltage, and the second end is coupled to the first node, and the first node is also grounded through a tail current source. The conduction degree of the voltage control unit is controlled by the second comparison signal to control the voltage of the first node, thereby controlling the voltage value of the floating ground voltage. The input end of the charge pump receives the functional voltage, and its ground end is coupled to the first node. The charge pump is used to boost the functional voltage and output the boost voltage. The rail voltage difference of the working voltage of the charge pump of the present invention is small, so that the voltage stress of the charge pump is small and the EMC performance is good.

Description

Technical Field

[0001] The present invention relates to the field of power electronics, and in particular to a charge pump circuit and electronic equipment. Background Art

[0002] In automotive systems, high-side switches are generally located between the power supply and the load, and are used to directly control whether the power supply is supplying power to the load. This enables the automotive system to quickly cut off the power supply when abnormal conditions such as overload, short circuit or overtemperature are detected, thereby protecting the safety of the load and the system.

[0003] Since the high-side switch is usually an N-channel MOSFET, its conduction requires the gate voltage (Vgs) to be higher than the source voltage (V s ) to a certain value. In order to ensure the reliable conduction of the high-side switch and reduce the conduction loss of the high-side switch, a charge pump circuit is usually required to boost the functional voltage of the automotive system so that the driving voltage of the high-side switch is higher than the functional voltage.

[0004] The functional voltage range of automotive systems is usually 5.5V to 48V. The current charge pump can only achieve such a wide range of boost requirements by increasing the number of charge pump stages. However, a larger number of charge pump stages usually leads to problems such as increased converter power consumption, reduced conversion efficiency, and increased stress on the pump-up capacitor. In addition, the charge pump generates surge current when charging and discharging the pump-up capacitor, which deteriorates the EMC performance of the automotive system.

[0005] Therefore, how to realize a charge pump with a wide voltage range while ensuring low voltage stress and good EMC performance has become a technical problem that urgently needs to be solved in the industry. Summary of the invention

[0006] The present invention provides a charge pump circuit and electronic equipment, which solve the technical problem of how to realize a charge pump with a wide voltage range while taking into account low voltage stress of the charge pump and good EMC performance.

[0007] According to a first aspect of the present invention, an embodiment of the present invention provides a charge pump circuit, including a voltage control module and a charge pump; the voltage control module includes a comparison unit and a voltage control unit; wherein:

[0008] The power supply terminal of the comparison unit receives a functional voltage, the ground terminal receives a first voltage, the first input terminal receives a boost voltage, the second input terminal receives a reference output voltage, and the third input terminal is coupled to a first node to receive a floating voltage; the voltage difference between the functional voltage and the first voltage is a preset voltage value; the comparison unit is used to compare the boost voltage and the reference output voltage to obtain a first comparison signal, and compare the first comparison signal with the floating voltage to obtain a second comparison signal;

[0009] The first terminal of the voltage control unit receives the functional voltage, the second terminal of the voltage control unit is coupled to the first node, the first node is also grounded through a tail current source, and the control terminal receives the second comparison signal. The conduction degree of the voltage control unit is controlled by the second comparison signal to control the voltage of the first node and determine the voltage value of the floating voltage.

[0010] The input terminal of the charge pump receives the functional voltage, and the ground terminal of the charge pump is coupled to the first node. The charge pump is used for boosting the functional voltage and outputting the boosted voltage.

[0011] Optionally, the comparison unit includes a first amplifier and a second amplifier:

[0012] The power supply terminal of the first amplifier receives the functional voltage, the ground terminal receives the first voltage, the non-inverting input terminal receives the boost voltage, the inverting input terminal receives the reference output voltage, and the output terminal outputs the first comparison signal;

[0013] The power supply terminal of the second amplifier receives the functional voltage, the ground terminal receives the first voltage, the non-inverting input terminal receives the first comparison signal, the inverting input terminal is coupled to the first node to receive the floating voltage, and the output terminal outputs the second comparison signal.

[0014] Optionally, the voltage control unit includes a first NMOS tube and a first capacitor;

[0015] The drain of the first NMOS tube receives the functional voltage, the source of the first NMOS tube is coupled to the first node, and the gate of the first NMOS tube receives the second comparison signal;

[0016] A first terminal of the first capacitor receives the functional voltage, and a second terminal of the first capacitor is coupled to the first node.

[0017] Optionally, the charge pump comprises:

[0018] A first diode, a second diode, a third diode, a first charge pump current source, a second charge pump current source, a first pumping capacitor, a second pumping capacitor, an output filter capacitor, a first switch, a second switch, a third switch, and a fourth switch;

[0019] The anode of the first diode, the first end of the first charge pump current source and the first end of the second charge pump current source all receive the functional voltage, the second end of the first charge pump current source is coupled to the first end of the first switch, the second end of the first switch is coupled to the first end of the second switch, the cathode of the first diode is respectively coupled to the anode of the second diode and the first end of the first pumping capacitor, the second end of the first pumping capacitor is coupled to the first end of the second switch, and the second end of the second switch is coupled to the first node;

[0020] Wherein, the control end of the first switch receives the second differential clock signal, and the second switch receives the first differential clock signal;

[0021] The second end of the second charge pump current source is coupled to the first end of the third switch, the second end of the third switch is coupled to the first end of the fourth switch, the cathode of the second diode is coupled to the anode of the third diode and the first end of the second pumping capacitor respectively, the second end of the second pumping capacitor is coupled to the first end of the fourth switch, and the second end of the fourth switch is coupled to the first node;

[0022] The control end of the third switch receives the first differential clock signal, and the second switch receives the second differential clock signal; the current provided by the second charge pump current source is equal to the current provided by the first charge pump current source;

[0023] The first end of the output filter capacitor is coupled to the cathode of the third diode, the cathode of the third diode is also used to output the boost voltage, and the second end of the output filter capacitor is coupled to the first node.

[0024] Optionally, the charge pump circuit further includes an EMC performance optimization module, which includes: a sampling unit and a current control unit;

[0025] The output end of the charge pump outputs the boost voltage through the sampling unit, and the sampling unit is used to obtain the current value of the load current;

[0026] The current control unit is coupled to the sampling unit, and the current control unit is configured as follows:

[0027] Based on the magnitude of the load current, at least a first current control signal is output to control the magnitude of the current provided by the tail current source, wherein the current value of the load current is proportional to the magnitude of the current provided by the tail current source.

[0028] Optionally, the current control unit is further configured as:

[0029] Based on the magnitude of the load current, a second current control signal is output to control the magnitude of the current provided by the first charge pump current source and the magnitude of the current provided by the second charge pump current source, wherein the magnitude of the current provided by the first charge pump current source and the magnitude of the current provided by the second charge pump current source are both proportional to the current value of the load current.

[0030] Optionally, the charge pump further includes: a third charge pump current source and a fourth charge pump current source;

[0031] The third charge pump current source is coupled between the second switch and the first node, and the fourth charge pump current source is coupled between the fourth switch and the first node;

[0032] Wherein, the current magnitude provided by the third charge pump current source and the current magnitude provided by the fourth charge pump current source are both controlled by the second current control signal.

[0033] Optionally, the sampling unit includes a sampling resistor; the current control unit includes a first bias resistor, a second bias resistor, a first PMOS tube, a second PMOS tube, a first bias current source, a second bias current source, a second NMOS tube, a third PMOS tube, a fourth PMOS tube, a third NMOS tube and a fifth PMOS tube;

[0034] The first end of the first bias resistor is coupled to the first end of the sampling resistor, the second end of the first bias resistor is respectively coupled to the source of the first PMOS tube and the drain of the second NMOS tube, the drain of the first PMOS tube is grounded through the first bias current source, the gate of the first PMOS tube is respectively coupled to the gate and drain of the second PMOS tube, the gate of the second NMOS tube is coupled to the drain of the first PMOS tube, and the source of the second NMOS tube is respectively coupled to the drain and gate of the third PMOS tube;

[0035] The source of the third PMOS tube is grounded, the gate of the third PMOS tube is coupled to the gate of the fourth PMOS tube, the gate of the third PMOS tube is also used to output the first current control signal, the source of the fourth PMOS tube is grounded, the drain thereof is coupled to the source of the third NMOS tube, the gate of the third NMOS tube receives a low voltage supply voltage, the drain of the third NMOS tube is respectively coupled to the drain and the gate of the fifth PMOS tube, the gate of the fifth PMOS tube is also used to output the second current control signal, and the source of the fifth PMOS tube is coupled to the cathode of the third diode;

[0036] The source of the second PMOS tube is coupled to the second end of the sampling resistor through the second bias resistor, and the drain of the second PMOS tube is grounded through the second bias current source.

[0037] Optionally, the charge pump circuit further includes a fourth NMOS transistor, and the tail current source includes a third bias current source and a fifth NMOS transistor;

[0038] The drain of the fourth NMOS transistor is coupled to the first node, the gate thereof receives the low voltage supply voltage, the source thereof is coupled to the first end of the third bias current source, and the second end of the third bias current source is grounded;

[0039] The drain of the fifth NMOS transistor is coupled to the first end of the third bias current source, the source thereof is grounded, and the gate thereof receives the first current control signal.

[0040] Optionally, the first charge pump current source includes a sixth PMOS transistor, and the second charge pump current source includes a seventh PMOS transistor;

[0041] The source of the sixth PMOS tube is coupled to the anode of the first diode to receive the functional voltage, the drain of the sixth PMOS tube is coupled to the first end of the first switch, and the gate of the sixth PMOS tube is coupled to the gate of the fifth PMOS tube to receive the second current control signal;

[0042] The first end of the seventh PMOS tube is coupled to the anode of the first diode to receive the functional voltage, the drain thereof is coupled to the first end of the second switch, and the gate thereof is coupled to the gate of the fifth PMOS tube to receive the second current control signal.

[0043] Optionally, the charge pump circuit further includes an eighth PMOS tube and a sixth NMOS tube, the third charge pump current source includes a seventh NMOS tube, and the fourth charge pump current source includes an eighth NMOS tube;

[0044] The seventh NMOS transistor is coupled between the second switch and the first node, and the eighth NMOS transistor is coupled between the fourth switch and the first node;

[0045] The source of the eighth PMOS tube is coupled to the anode of the first diode, and the gate thereof is coupled to the gate of the fifth PMOS tube. The drain of the eighth PMOS tube is respectively coupled to the drain and gate of the sixth NMOS tube. The source of the sixth NMOS tube is coupled to the first node, and the gate thereof is respectively coupled to the gate of the seventh NMOS tube and the gate of the eighth NMOS tube.

[0046] Optionally, the low level voltage value of the first differential clock signal and the low level voltage value of the second differential clock signal are both equal to the voltage value of the floating voltage, and the high level voltage value of the first differential clock signal and the high level voltage value of the second differential clock signal are both equal to the voltage value of the functional voltage.

[0047] According to a second aspect of the present invention, an embodiment of the present invention provides an electronic device, comprising a charge pump circuit as described in any one of the first aspects of the present invention.

[0048] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0049] In the charge pump circuit and electronic device of the technical solution of the present invention, the circuit includes a voltage control module and a charge pump, and the voltage control module includes a comparison unit and a voltage control unit. The charge pump circuit is used to compare and process the boost voltage and the reference output voltage to obtain a first comparison signal, and compare and process the first comparison signal with the floating ground voltage of the first node to obtain a second comparison signal; the first end of the voltage control unit receives the functional voltage, and the second end is coupled to the first node. The first node is also grounded through a tail current source. The conduction degree of the voltage control unit is controlled by the second comparison signal to control the voltage of the first node, and then control the voltage value of the floating ground voltage. The input end of the charge pump receives the functional voltage, and its ground end is coupled to the first node. The charge pump is used to boost the functional voltage and output the boost voltage. Since the working voltage rail pressure difference of the charge pump of the present invention is small, the voltage stress of the charge pump is small and the EMC performance is good.

[0050] Furthermore, since the working voltage rail voltage difference of the charge pump of the present invention is small, the charging and discharging current of the capacitor changes relatively slowly, so that the pump-up capacitor in the charge pump of the present invention can be coupled to the functional voltage to directly boost the functional voltage.

[0051] Furthermore, the charge pump of the present invention may also include a first charge pump current source, a second charge pump current source, a third charge pump current source and a fourth charge pump current source. The symmetry and uniformity of the current transfer characteristics within the clock cycle are maintained by the third charge pump current source and the fourth charge pump current source, thereby reducing transient current spikes and electromagnetic interference.

[0052] Furthermore, the charge pump circuit of the present invention also includes an EMC performance optimization module, including: a sampling unit and a current control unit; the output end of the charge pump outputs a boost voltage through the sampling unit, and the sampling unit is used to obtain the current value of the load current; the current control unit is coupled to the sampling unit and is configured to: based on the size of the load current, at least output a first current control signal to control the current size provided by the tail current source, wherein the current value of the load current is proportional to the current size provided by the tail current source. Thus, the present invention limits the current flowing into the ground from the first node through the tail current source, thereby improving the EMC performance, and the size of the tail current source changes with the load current, and also optimizes the static current under light load, reduces power consumption, and not only that, but also ensures the stability of the boost voltage under heavy load.

[0053] Furthermore, the EMC performance optimization module of the present invention is also used to output a second current control signal based on the size of the load current to control the size of the current provided by the current source in the charge pump, so that the size of the current provided by the current source in the charge pump is proportional to the current value of the load current, thereby not only fully optimizing the EMC performance when the circuit is lightly loaded, but also reducing the light load loss of the charge pump. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0055] Figure 1 It is a structural schematic diagram of a current-controlled charge pump provided by an embodiment of the prior art;

[0056] Figure 2 It is a working timing diagram of a differential clock signal provided by an embodiment of the prior art;

[0057] Figure 3 It is a schematic diagram of the operation of a current-controlled charge pump in the Φ1 phase provided by an embodiment of the prior art;

[0058] Figure 4 It is a schematic diagram of the operation of a current-controlled charge pump in the Φ2 phase provided by an embodiment of the prior art;

[0059] Figure 5 The EMC performance of a current-controlled charge pump provided by an embodiment of the prior art is shown in FIG. Figure 1 ;

[0060] Figure 6The EMC performance of a current-controlled charge pump provided by an embodiment of the prior art is shown in FIG. Figure 2 ;

[0061] Figures 7 to 13 FIG. 1 is a schematic diagram of a charge pump circuit according to an embodiment of the present invention. Figures 1 to 6 . DETAILED DESCRIPTION

[0062] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0063] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0064] The technical solution of the present invention is described in detail with specific embodiments below. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0065] As described in the background art, it is difficult to realize a charge pump with a wide voltage range in the prior art while also taking into account the problem of low voltage stress of the charge pump.

[0066] Functional voltage V of automotive systems s The range is usually 5.5V to 48V. The high-side switch chip is connected between the functional voltage and the load to achieve multi-functional protection. The charge pump topology is widely used in high-side switch chips due to its simple structure, small size, low cost, and small ripple. The charge pump converts the functional voltage V s (5.5V~48V) is converted to the voltage required by the high-side switch (V s+5V), thereby achieving full conduction of the power switch and reducing the conduction loss of the high-side switch. However, the charge pump will generate surge current when charging and discharging the pump-up capacitor, which will deteriorate the EMC performance of the automotive system.

[0067] It should be understood that the electromagnetic compatibility (EMC) performance mentioned in the present invention refers to the degree of electromagnetic disturbance (Electromagnetic Disturbance) generated by the equipment to the environment during normal operation.

[0068] Please refer to Figure 1 , Figure 1 A current-controlled charge pump is shown, comprising: a first diode D1, a second diode D2, a third diode D3, a first charge pump current source I c1 , the second charge pump current source I c2 , the third charge pump current source I c3 , the fourth charge pump current source I c4 , the first pumping capacitor C1, the second pumping capacitor C2, the output filter capacitor C BUF , a first switch S1, a second switch S2, a third switch S3 and a fourth switch S4;

[0069] The anode of the first diode D1 receives the functional voltage V s , the first charge pump current source I c1 The first end of the third charge pump current source I c3 The first end receives the second voltage V DD , the first charge pump current source I c1 The second end of the first switch S1 is coupled to the first end of the first switch S1, the second end of the first switch S1 is coupled to the first end of the second switch S2, the cathode of the first diode D1 is coupled to the anode of the second diode D2 and the first end of the first pumping capacitor C1 respectively, the second end of the first pumping capacitor C1 is coupled to the first end of the second switch S2, and the second end of the second switch S2 is connected to the first end of the second charge pump current source I c2 Grounding;

[0070] The control end of the first switch S1 receives the second differential clock signal CLKN, the control end of the second switch S2 receives the first differential clock signal CLKP, and the voltage amplitudes of the first differential clock signal and the second differential clock signal CLKN are both the second voltage V DD Voltage value;

[0071] The third charge pump current source I c3The second end of the third switch S3 is coupled to the first end of the third switch S3, the second end of the third switch S3 is coupled to the first end of the fourth switch S4, the cathode of the second diode D2 is coupled to the anode of the third diode D3 and the first end of the second pumping capacitor C2 respectively, the second end of the second pumping capacitor C2 is coupled to the first end of the fourth switch S4, and the second end of the fourth switch S4 is connected to the fourth charge pump current source I c4 Grounding;

[0072] Wherein, the control end of the third switch S3 receives the first differential clock signal CLKP, and the control end of the fourth switch S4 receives the second differential clock signal CLKN;

[0073] The output filter capacitor C BUF The first end of the diode D3 is coupled to the cathode of the third diode D3, and the cathode of the third diode D3 is also used to output the boost voltage V CP , the output filter capacitor C BUF The second end receives the functional voltage V s .

[0074] It can be seen that this topology transfers the charge from the functional voltage V s Transfer to output V CP , achieving the boost function. The four constant current sources limit the charge and discharge current of the pump boost capacitor, avoiding the generation of surge current, thereby optimizing the EMC performance of the charge pump.

[0075] Please refer to Figure 2 , Figure 2 1 shows the working timing of the first differential clock signal CLKP and the second differential clock signal CLKN. It can be seen that the voltage amplitudes of the first differential clock signal CLKP and the second differential clock signal CLKN are both the second voltage V DD The voltage value of the clock signal is 50%.

[0076] in:

[0077] Vclkp, which can be understood as the waveform of the first differential clock signal CLKP;

[0078] Vclkn, which can be understood as the waveform of the second differential clock signal CLKN;

[0079] Φ1 can be understood as the phase for charging the first pumping capacitor C1;

[0080] Φ2 can be understood as the phase for charging the second pumping capacitor C2.

[0081] Figure 3FIG. 1 shows the working state of the current-controlled charge pump in the Φ1 phase. It can be seen that in the Φ1 phase, the first switch S1 and the fourth switch S4 are disconnected, the second switch S2 and the third switch S3 are closed, and V s The charge ΔQ1 is transferred to capacitor C1, and capacitor C2 transfers the charge ΔQ1 to filter capacitor C BUF and the load transfers charge ΔQ out , load I L Extracting I from the charge pump L T s / 2, where T s is the period of the first differential clock signal CLKP;

[0082] Figure 4 FIG. 2 shows the working state of the current-controlled charge pump in the Φ2 phase. It can be seen that in the Φ2 phase, the first switch S1 and the fourth switch S4 are closed, the second switch S2 and the third switch S3 are disconnected, the capacitor C1 transfers the charge ΔQ2 to the capacitor C2, and the load I L Extracting I from the charge pump L T s / 2 magnitude charge.

[0083] When the charge pump is in steady state, the charges C1, C2 and C BUF The conservation of charge can be deduced that in steady state, ΔQ1=ΔQ2=ΔQ out =I L T s Therefore, node V n1 、V n2 and V cp The voltage can be recursively described by the following formula.

[0084]

[0085]

[0086]

[0087] During the charge transfer process, the charge and discharge current of the pump capacitor is I c1 ~I c4 Limited to I c , thereby limiting the outflow V s The current I cpump1 and the current flowing into the ground I cpump2 ,in:

[0088] When 2I L =I c When in the Φ1 phase, I cpump1 =I c3 =I c , Icpump2 =I c2 =I c ;

[0089] In the Φ2 phase, I cpump1 =I c1 =I c , I cpump2 =I c4 =I c .

[0090] In this case, I cpump1 and I cpump2 No large drop will occur and it can be approximately considered as a constant value, thus avoiding the generation of surge current and optimizing the EMC performance of the charge pump.

[0091] However, in phase Φ1, the voltage on the pump capacitor C1 is V c1 =V s ; In the Φ2 phase, the voltage on the pump capacitor C2 is V c2 =V s +V DD -I L T s / C, the voltage stress of the pump capacitor increases with the number of charge pump stages. In applications with a wide voltage range, such as automotive systems, due to the functional voltage V s V s The range is usually 5.5V to 48V. For a two-stage current-controlled charge pump, when V DD When =5V, the maximum voltage stress of the pump-up capacitor can reach 53V.

[0092] Therefore, for an integrated charge pump, in order to meet the voltage stress requirements, a high-voltage capacitor needs to be used on the chip, that is, both the first pumping capacitor C1 and the second pumping capacitor C2 need to be high-voltage capacitors. However, the capacitance per unit area of ​​high-voltage capacitors is low, and a small pumping capacitor capacitance will result in a large charge pump ripple; a high-voltage capacitor with a large capacitance will consume a large chip area and increase the chip cost. It can be seen that the existing wide voltage range charge pump does not have the advantages of small size and low cost.

[0093] Not only that, Figure 1 The current controlled charge pump shown is not stable enough and does not optimize the EMC noise sufficiently.

[0094] When the circuit is in steady state, the charges C1, C2 and C BUF Charge conservation, the following relationship exists: ΔQ1=ΔQ2=ΔQ out =I L T s .

[0095] Since the pump capacitor needs to transfer I L T is a charge of magnitude 2I L Less than I c , constitute I c1 ~I c4 The transistor will be forced to leave the saturation region, making the actual output current less than I c , or even decrease to 0 in advance to ensure that the average value I of the current source within one clock cycle is limited c avr is equal to the load current I L In this case, the outflow V s The current I cpump1 and the current flowing into the ground I cpump2 It is not constant and current drops may occur.

[0096] Specifically, please refer to Figure 5 as well as Figure 6 , Figure 5 as well as Figure 6 Shows Figure 1 The circuit shown has I cpump1 / I cpump2 The ratio of changes can be used to obtain the EMC performance of the circuit;

[0097] Please refer to Figure 5 , it can be seen that when 2I L ≈I c When the current limit I c1 ~I c4 remains almost constant, so at I cpump1 and I cpump2 A smaller current drop is generated on the charge pump, so that the charge pump has better EMC performance;

[0098] Please refer to Figure 6 , it can be seen that when 2I L < c , limiting current I c1 ~I c4 The value of I cpump1 and I cpump2 This will cause the charge pump to generate a large surge current, thereby deteriorating the EMC performance of the charge pump.

[0099] ​For automotive systems, the charge pump circuit will be connected to the power supply line in the form of long wires (generally more than 5m), which are usually inductive and resistive. When surge current flows into the long wires, a voltage drop will occur on the long wires, which will affect every device connected to the long wires. In addition, the long wires can act as radiating antennas in a wide frequency range, further deteriorating the EMC performance of the automotive system.

[0100] Moreover, when the load current suddenly increases, according to the above formula, it can be concluded that the boost voltage V CP The voltage value will decrease as the load current increases. For devices that require precise voltage, this charge pump obviously cannot meet the requirements.

[0101] In order to solve the above problems, an embodiment of the present invention provides a charge pump circuit, wherein a voltage control module in the circuit includes a comparison unit for comparing the boost voltage V CP and a reference output voltage to obtain a first comparison signal, and compare the first comparison signal with the floating ground voltage of the first node to obtain a second comparison signal; a voltage control unit, a first terminal of which receives a functional voltage V s , the second end is coupled to the first node, the first node is also grounded through the tail current source, the conduction degree of the voltage control unit is controlled by the second comparison signal to control the voltage of the first node, and then control the voltage value of the floating voltage; the charge pump, the input end receives the functional voltage V s , the ground terminal is coupled to the first node, and the charge pump is used to s Perform voltage boost processing and output boost voltage V CP Since the working voltage rail pressure difference of the charge pump of the present invention is small, the voltage stress of the charge pump is small and the EMC performance is good.

[0102] 14. Please refer to Figure 7 The charge pump circuit provided by the embodiment of the present invention includes: a voltage control module and a charge pump 20; the voltage control module includes a comparison unit 11 and a voltage control unit 12; wherein:

[0103] The power supply terminal of the comparison unit 11 receives a functional voltage V s , whose ground terminal receives the first voltage VSSH, and whose first input terminal receives the boost voltage V CP , whose second input terminal receives the reference output voltage V REF , the third input terminal of which is coupled to the first node to receive the floating voltage VSSCP, the functional voltage V s The voltage difference between the first voltage VSSH and the first voltage VSSH is a preset voltage value;

[0104] The comparison unit 11 is used to compare the boost voltage V CPAnd the reference output voltage V REF A comparison process is performed to obtain a first comparison signal, and the first comparison signal is compared with the floating voltage VSSCP to obtain a second comparison signal.

[0105] The first terminal of the voltage control unit 12 receives the functional voltage V s , a second end of which is coupled to the first node, the first node is also connected to the ground VSS through the tail current source I1, and a control end of which receives the second comparison signal;

[0106] The conduction degree of the voltage control unit 12 is controlled by the second comparison signal to control the voltage of the first node and determine the voltage value of the floating voltage VSSCP.

[0107] The input terminal of the charge pump 20 receives the functional voltage V s , a ground terminal of which is coupled to the first node;

[0108] The charge pump 20 is used to s Perform voltage boost processing and output the boost voltage V CP .

[0109] Generally, a charge pump includes a pumping capacitor, which is used to store and transfer charge, thereby increasing the voltage.

[0110] In the embodiment of the present invention, the voltage stress of each stage of the pumping capacitor in the charge pump 20 is in a corresponding multiple relationship with the preset voltage value. Specifically, the voltage stress of the first stage of the pumping capacitor is 1 times the preset voltage value, the voltage stress of the second stage of the pumping capacitor is 2 times the preset voltage value, and so on.

[0111] As an example, the preset voltage value may be 5V, that is, the first voltage VSSH=VS-5V, of course, the present invention is not limited thereto, and the voltage value of the preset voltage value may be set according to system requirements. Then the voltage stress of the first-stage pump-up capacitor is 5V, the voltage stress of the second-stage pump-up capacitor is 10V, and so on.

[0112] It can be seen that the present invention generates the floating voltage VSSCP by means of negative feedback, so that the charge pump 20 can generate a voltage higher than the functional voltage V based on the floating voltage VSSCP. s The fixed output significantly reduces the voltage stress of the internal pump-up capacitor of the charge pump 20, avoids the use of high-voltage capacitors, and gives full play to the advantages of small size and low cost of the charge pump 20. Moreover, since the working voltage rail pressure difference of the charge pump 20 of the present invention is small, the EMC performance of the charge pump 20 is better.

[0113] The voltage control module is now further described.

[0114] In one implementation, please refer to Figure 8 , the comparison unit 11 includes a first amplifier OTA1 and a second amplifier OTA2:

[0115] The power supply terminal of the first amplifier OTA1 receives the functional voltage V s , whose ground terminal receives the first voltage VSSH, and whose non-inverting input terminal receives the boost voltage V CP , whose inverting input receives the reference output voltage V REF , whose output terminal outputs the first comparison signal VSSCP_REF;

[0116] The power supply terminal of the second amplifier OTA2 receives the functional voltage V s , a ground terminal receives a first voltage VSSH, a non-inverting input terminal receives the first comparison signal VSSCP_REF, an inverting input terminal is coupled to the first node to receive a floating voltage VSSCP, and an output terminal outputs the second comparison signal.

[0117] Among them, the reference output voltage V REF Used to accurately set the boost voltage V CP The first comparison signal VSSCP_REF can be understood as a reference value of the floating voltage VSSCP.

[0118] In a preferred embodiment, please refer to Fig. 9 The positive input terminal of the first amplifier OTA1 receives the boost voltage V through a voltage divider unit formed by a first resistor R1 and a second resistor R2. CP Therefore, the reference output voltage V REF It can be a lower voltage value.

[0119] Please continue to refer to Figure 8 The voltage control unit 12 includes a first NMOS tube M1 and a first capacitor C C ;

[0120] The drain of the first NMOS tube M1 receives the functional voltage V s , a source thereof is coupled to the first node, and a gate thereof receives the second comparison signal;

[0121] The first capacitor C C The first end receives the functional voltage V s , a second end of which is coupled to the first node.

[0122] Among them, the first capacitor C CIt can be understood as a compensation capacitor, which is used to provide a main pole to stabilize the system.

[0123] It can be seen that the voltage control module detects the boost voltage V output by the charge pump 20 through the first amplifier OTA1. CP With reference output voltage V REF The error value of the first comparison signal VSSCP_REF is generated, and the second amplifier OTA2 detects the error value between the first comparison signal VSSCP_REF and the first node, adjusts the gate voltage of the first NMOS tube M1, and then adjusts the value of the floating voltage VSSCP, thereby controlling the voltage VCP output by the charge pump 20.

[0124] The tail current source I1 limits the current flowing from the first node into the ground wire VSS, thereby improving the EMC performance. As an example, the ground wire VSS can be understood as a power ground, of course, the present invention is not limited to this, and it can also be other ground ports.

[0125] Based on this, the charge pump 20 is further described.

[0126] In one implementation, please refer to Figure 8 , the charge pump 20 comprises:

[0127] The first diode D1, the second diode D2, the third diode D3, the first charge pump current source I c1 , the second charge pump current source I c2 , the first pumping capacitor C1, the second pumping capacitor C2, the output filter capacitor C BUF , a first switch S1, a second switch S2, a third switch S3 and a fourth switch S4;

[0128] The anode of the first diode D1 and the first charge pump current source I c1 The first end of the second charge pump current source I c2 The first end receives the functional voltage V s , the first charge pump current source I c1 The second end of the first switch S1 is coupled to the first end of the first switch S1, the second end of the first switch S1 is coupled to the first end of the second switch S2, the cathode of the first diode D1 is coupled to the anode of the second diode D2 and the first end of the first pumping capacitor C1 respectively, the second end of the first pumping capacitor C1 is coupled to the first end of the second switch S2, and the second end of the second switch S2 is coupled to the first node;

[0129] Wherein, the control end of the first switch S1 receives the second differential clock signal CLKN, and the second switch S2 receives the first differential clock signal CLKP;

[0130] The second charge pump current source I c2 The second end of the second diode D2 is coupled to the first end of the third switch S3, the second end of the third switch S3 is coupled to the first end of the fourth switch S4, the cathode of the second diode D2 is coupled to the anode of the third diode D3 and the first end of the second pumping capacitor C2, the second end of the second pumping capacitor C2 is coupled to the first end of the fourth switch S4, and the second end of the fourth switch S4 is coupled to the first node;

[0131] The control end of the third switch S3 receives the first differential clock signal CLKP, and the second switch S2 receives the second differential clock signal CLKN; the second charge pump current source I c2 The current provided is equal to the first charge pump current source I c1 The amount of current provided;

[0132] The output filter capacitor C BUF The first end of the diode D3 is coupled to the cathode of the third diode D3, and the cathode of the third diode D3 is also used to output the boost voltage V CP , the output filter capacitor C BUF The second end of is coupled to the first node.

[0133] exist Figure 8 In the example, the core circuit of the charge pump 20 is controlled by two-phase clocks CLKN and CLKP, the phase difference between the first differential clock signal CLKP and the second differential clock signal CLKN is 180°, and the clock signal duty cycle is 50%. The low level voltage value of the first differential clock signal CLKP and the low level voltage value of the second differential clock signal CLKN are both equal to the voltage value of the floating voltage VSSCP, and the high level voltage value of the first differential clock signal CLKP and the high level voltage value of the second differential clock signal CLKN are both equal to the functional voltage V s Voltage value.

[0134] The first charge pump current source I c1 And the second charge pump current source I c2 is a limiting current source for limiting the charging current of the charge pump 20, thereby improving the EMC performance.

[0135] It can be seen that relative to Figure 1 The charge pump 20 shown in the figure has a relatively gentle change in the charge and discharge current of the capacitor because the present invention reduces the voltage rail voltage difference, thereby appropriately reducing part of the current limiting current source while maintaining good EMC performance, that is, only the first charge pump current source I c1 And the second charge pump current source Ic2 The same function can be achieved.

[0136] Moreover, since the present invention reduces the voltage rail voltage difference, the charging and discharging current of the capacitor changes relatively slowly, so that the present invention can also directly use the current flowing through the positive electrode of the first diode D1 to charge the corresponding pump-up capacitor, which is equivalent to the pump-up capacitor (C1, C2) in the charge pump 20 being coupled to the functional voltage V s , the pumping capacitor directly affects the functional voltage V s Boost the voltage and simplify the circuit.

[0137] In a preferred embodiment, please refer to Fig. 9 The charge pump 20 further includes: a third charge pump current source I c3 And the fourth charge pump current source I c4 ;

[0138] The third charge pump current source I c3 The fourth charge pump current source I is coupled between the second switch S2 and the first node. c4 Coupled between the fourth switch S4 and the first node.

[0139] It can be seen that, through four current sources with the same current, the present invention can maintain the symmetry and uniformity of the current transmission characteristics within the clock cycle, thereby reducing transient current spikes and electromagnetic interference.

[0140] Considering that the load current will also affect the EMC noise of the charge pump 20, in a preferred embodiment, the present invention can also adaptively adjust the value of the current source according to the load current, thereby fully optimizing the EMC noise under light load and reducing static power consumption.

[0141] In a specific implementation, please refer to Fig.10 , the charge pump circuit further includes an EMC performance optimization module, the EMC performance optimization module includes: a sampling unit 31 and a current control unit 32;

[0142] The output end of the charge pump 20 outputs the boost voltage V through the sampling unit 31. CP , the sampling unit 31 is used to obtain the current value of the load current;

[0143] The current control unit 32 is coupled to the sampling unit 31, and the current control unit 32 is configured as follows:

[0144] Based on the magnitude of the load current, at least a first current control signal Ctrl1 is output to control the magnitude of the current provided by the tail current source I1 , wherein the current value of the load current is proportional to the magnitude of the current provided by the tail current source I1 .

[0145] It can be seen that by controlling the tail current source I1 to follow the load current change, the quiescent current of the circuit under light load can be optimized. Moreover, when the load current increases, by controlling the tail current source I1 to follow the load current change, the boost voltage V CP The voltage difference of the floating voltage VSSCP becomes larger, ensuring the output boost voltage V CP stability.

[0146] Specifically, after adding the voltage control circuit, the load I L When the voltage V changes, the loop will dynamically adjust the floating voltage VSSCP, thereby changing the voltage amplitude of the clock signal, and finally maintaining the VCP voltage value stable. CP The amplitude of the differential clock signal has the following relationship:

[0147]

[0148] Among them, V REF The reference output voltage V REF The voltage value, V CK It is the voltage amplitude of the first differential clock signal CLKP or the voltage amplitude of the second differential clock signal CLKN.

[0149] In a preferred embodiment, please refer to Fig.11 , the current control unit 32 is further configured as:

[0150] Based on the magnitude of the load current, a second current control signal Ctrl2 is output to control the first charge pump current source I c1 The current size provided by the second charge pump current source I c2 The current magnitude provided, wherein the first charge pump current source I c1 The current size provided by the second charge pump current source I c2 The magnitude of the current provided is directly proportional to the current value of the load current.

[0151] It can be seen that by controlling the first charge pump current source I c1 And the second charge pump current source I c2 Both follow the load current change, and when the circuit is lightly loaded, the current flowing into the first charge pump current source I c1 And the second charge pump current source I c2 The current (i.e. I cpump1 ) drops, optimizes the EMC performance under light load, and can also reduce the light load loss of the charge pump 20.

[0152] In the above Fig. 9 In the example, the charge pump 20 further includes a third charge pump current source I c3 And the fourth charge pump current source I c4 It can be seen that the third charge pump current source I c3 The fourth charge pump current source I is coupled between the second switch S2 and the first node. c4 Coupled between the fourth switch S4 and the first node.

[0153] On the basis that the current control unit 32 outputs the second current control signal Ctrl2, the third charge pump current source I c3 The current provided by the fourth charge pump current source I c4 The magnitude of the provided current is controlled by the second current control signal Ctrl2.

[0154] Therefore, the present invention ensures that the current provided by the current source in the charge pump 20 is consistent in magnitude.

[0155] The specific structure inside the EMC performance optimization module is now described.

[0156] Please refer to Fig.12 The sampling unit 31 includes a sampling resistor R sense The current control unit 32 includes a first bias resistor R b1 , the second bias resistor R b2 , a first PMOS tube M2, a second PMOS tube M3, a first bias current source I B21 , the second bias current source I B22 , a second NMOS tube M4, a third PMOS tube M5, a fourth PMOS tube M6, a third NMOS tube M7 and a fifth PMOS tube M8;

[0157] The first bias resistor R b1 The first end is coupled to the sampling resistor R sense The first end of the first bias resistor R b1 The second end of the first bias current source I is respectively coupled to the source of the first PMOS tube M2 and the drain of the second NMOS tube M4. The drain of the first PMOS tube M2 is connected to the drain of the second NMOS tube M4 through the first bias current source I B21 grounded, the gate of the first PMOS tube M2 is respectively coupled to the gate and drain of the second PMOS tube M3, the gate of the second NMOS tube M4 is coupled to the drain of the first PMOS tube M2, and the source of the second NMOS tube M4 is respectively coupled to the drain and gate of the third PMOS tube M5;

[0158] The source of the third PMOS tube M5 is grounded, the gate of the third PMOS tube M5 is coupled to the gate of the fourth PMOS tube M6, the gate of the third PMOS tube M5 is also used to output the first current control signal Ctrl1, the source of the fourth PMOS tube M6 is grounded, the drain thereof is coupled to the source of the third NMOS tube M7, the gate of the third NMOS tube M7 receives the low voltage supply voltage VDD, the drain of the third NMOS tube M7 is respectively coupled to the drain and the gate of the fifth PMOS tube M8, the gate of the fifth PMOS tube M8 is also used to output the second current control signal Ctrl2, the source of the fifth PMOS tube M8 is coupled to the cathode of the third diode D3;

[0159] The source of the second PMOS tube M3 is connected to the second bias resistor R b2 Coupled to the sampling resistor R sense The drain of the second PMOS tube M3 is connected to the second bias current source I B22 Ground VSS.

[0160] The first bias resistor R b1 The resistance value of the second bias resistor R b2 The resistance values ​​of the first bias current source I B21 The current provided is equal to the second bias current source I B22 The current provided is of the same magnitude.

[0161] The third NMOS transistor M7 is used to achieve voltage isolation. As an example, the low voltage supply voltage VDD may be 5V, but the present invention is not limited to this, and may be other voltages.

[0162] On this basis, in order to control the tail current source I1, in a specific implementation manner, please continue to refer to Fig.12 The charge pump circuit further includes a fourth NMOS tube M9, and the tail current source I1 includes a third bias current source I B1 And the fifth NMOS tube M 10 ;

[0163] The drain of the fourth NMOS transistor M9 is coupled to the first node, the gate thereof receives the low voltage supply voltage VDD, and the source thereof is coupled to the third bias current source I B1 The first end of the third bias current source I B1 The second end is grounded to VSS;

[0164] The fifth NMOS tube M 10 The drain of B1A first end of the device has a source electrode grounded, and a gate electrode receiving the first current control signal Ctrl1.

[0165] The fourth NMOS tube M9 is used for voltage isolation, and the third bias current source I B1 It is used to provide a minimum current to avoid the tail current source I1 being turned off when no-load. 10 A controllable current source is formed.

[0166] To control the first charge pump current source I c1 And the second charge pump current source I c2 For a specific implementation, please continue to refer to Fig.12 , the first charge pump current source I c1 Including the sixth PMOS tube M 11 , the second charge pump current source I c2 Including the seventh PMOS tube M 12 ;

[0167] The sixth PMOS tube M 11 The source of the first diode D1 is coupled to the anode of the first diode D1 to receive the functional voltage V s , a drain of which is coupled to the first end of the first switch S1, and a gate of which is coupled to the gate of the fifth PMOS tube M8 to receive the second current control signal Ctrl2;

[0168] The seventh PMOS tube M 12 The first end of the diode D1 is coupled to the anode of the first diode D1 to receive the functional voltage V s , a drain of which is coupled to the first end of the second switch S2, and a gate of which is coupled to the gate of the fifth PMOS tube M8 to receive the second current control signal Ctrl2.

[0169] Now Fig.12 The working principle of the EMC performance optimization module shown is explained.

[0170] The sampling unit 31 is connected by a sampling resistor R sense The voltage across the two ends is converted into a current I sense Output, for the current control unit 32, negative feedback makes Figure 8 The voltages at node A and node B are equal, so the current I flowing through the second NMOS tube M4 is sense and the load current I L The relationships are as follows:

[0171] V A +(I sense +I B2 )Rb -V B -I B2 R b =I L R sense

[0172]

[0173] Among them, V A is the voltage value at node A, V B is the voltage value at node B, I B2 is the first bias current source I B21 The current value provided by the second bias current source I B22 The current value provided, R b is the first bias resistor R b1 Or the second bias resistor R b2 The resistance value, R sense is the sampling resistor R sense resistance value.

[0174] When the width-to-length ratio of the fourth PMOS tube M6 is K1 times that of the third PMOS tube M5, the fifth NMOS tube M 10 The width-to-length ratio of the seventh PMOS tube M is K2 times that of the third PMOS tube M5. 12 and the sixth PMOS tube M 11 When the width-to-length ratio of the fourth PMOS tube M6 is K3 times, the tail current source I1 and the first charge pump current source I c1 , the second charge pump current source I c2 The current values ​​provided have the following relationship:

[0175]

[0176]

[0177] It can be seen that the tail current source I1 and the first charge pump current source I c1 And the second charge pump current source I c2 The magnitude of the current provided varies with the load current, so that the present invention can fully optimize the EMC performance under light load and reduce the light load loss of the charge pump 20.

[0178] When the charge pump 20 has four current sources, please refer to Fig.13 In one embodiment, the charge pump circuit further includes an eighth PMOS transistor M 13 , the sixth NMOS tube M 14 , the third charge pump current source I c3 Including the seventh NMOS tube M 16 , the fourth charge pump current source Ic4 Including the eighth NMOS tube M 15 ;

[0179] The seventh NMOS tube M 16 The eighth NMOS transistor M is coupled between the second switch S2 and the first node. 15 coupled between the fourth switch S4 and the first node;

[0180] The eighth PMOS tube M 13 The source of the transistor is coupled to the anode of the first diode D1, and the gate of the transistor is coupled to the gate of the fifth PMOS transistor M8. 13 The drains of the sixth NMOS tube M are respectively coupled to 14 The drain and gate of the sixth NMOS tube M 14 The source of each of the transistors is coupled to the first node, and the gate of each of the transistors is coupled to the seventh NMOS transistor M. 16 The gate of the eighth NMOS tube M 15 of the gate.

[0181] Of course, the present invention does not limit the specific implementation of the current source, and those skilled in the art can select a suitable circuit implementation as needed. As long as the current source can be controlled by the first current control signal Ctrl1 or the second current control signal Ctrl2, it is within the protection scope of the present invention.

[0182] In addition, an embodiment of the present invention further provides an electronic device, comprising the charge pump circuit as described in any one of the above items.

[0183] As an example, the electronic device may be an LED driver, a sensor, a communication device, etc. of an automotive system. Of course, the present invention is not limited to the application system and device, and technicians in this field can apply the charge pump circuit provided by the present invention to suitable equipment as needed.

[0184] In summary, the present invention sets the voltage control module in the circuit to include a comparison unit 11 for comparing the boost voltage V CP And the reference output voltage V REF The first comparison signal VSSCP_REF is obtained by comparison processing, and the first comparison signal VSSCP_REF is compared with the floating voltage VSSCP of the first node to obtain a second comparison signal; the voltage control unit 12, the first terminal of which receives the functional voltage V s, the second end is coupled to the first node, the first node is also grounded through the tail current source I1, the conduction degree of the voltage control unit 12 is controlled by the second comparison signal to control the voltage of the first node, thereby controlling the voltage value of the floating voltage VSSCP; the charge pump 20, the input end receives the functional voltage V s , the ground terminal is coupled to the first node, the charge pump 20 is used to s Perform voltage boost processing and output boost voltage V CP Since the working voltage rail voltage difference of the charge pump 20 of the present invention is small, the voltage stress of the charge pump 20 is small and the EMC performance is good.

[0185] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A charge pump circuit, characterized in that: It includes a voltage control module and a charge pump; the voltage control module includes a comparison unit and a voltage control unit; wherein: The power supply terminal of the comparison unit receives a functional voltage, the ground terminal receives a first voltage, the first input terminal receives a boost voltage, the second input terminal receives a reference output voltage, and the third input terminal is coupled to a first node to receive a floating voltage; the voltage difference between the functional voltage and the first voltage is a preset voltage value; the comparison unit is used to compare the boost voltage and the reference output voltage to obtain a first comparison signal, and compare the first comparison signal with the floating voltage to obtain a second comparison signal; The first terminal of the voltage control unit receives the functional voltage, the second terminal of the voltage control unit is coupled to the first node, the first node is also grounded through a tail current source, and the control terminal receives the second comparison signal. The conduction degree of the voltage control unit is controlled by the second comparison signal to control the voltage of the first node and determine the voltage value of the floating voltage. The input terminal of the charge pump receives the functional voltage, and the ground terminal of the charge pump is coupled to the first node. The charge pump is used for boosting the functional voltage and outputting the boosted voltage.

2. The charge pump circuit according to claim 1, wherein: The comparison unit includes a first amplifier and a second amplifier: The power supply terminal of the first amplifier receives the functional voltage, the ground terminal receives the first voltage, the non-inverting input terminal receives the boost voltage, the inverting input terminal receives the reference output voltage, and the output terminal outputs the first comparison signal; The power supply terminal of the second amplifier receives the functional voltage, the ground terminal receives the first voltage, the non-inverting input terminal receives the first comparison signal, the inverting input terminal is coupled to the first node to receive the floating voltage, and the output terminal outputs the second comparison signal.

3. The charge pump circuit according to claim 2, wherein: The voltage control unit includes a first NMOS tube and a first capacitor; The drain of the first NMOS tube receives the functional voltage, the source of the first NMOS tube is coupled to the first node, and the gate of the first NMOS tube receives the second comparison signal; A first terminal of the first capacitor receives the functional voltage, and a second terminal of the first capacitor is coupled to the first node.

4. The charge pump circuit according to claim 1, wherein: The charge pump comprises: A first diode, a second diode, a third diode, a first charge pump current source, a second charge pump current source, a first pumping capacitor, a second pumping capacitor, an output filter capacitor, a first switch, a second switch, a third switch, and a fourth switch; The anode of the first diode, the first end of the first charge pump current source and the first end of the second charge pump current source all receive the functional voltage, the second end of the first charge pump current source is coupled to the first end of the first switch, the second end of the first switch is coupled to the first end of the second switch, the cathode of the first diode is respectively coupled to the anode of the second diode and the first end of the first pumping capacitor, the second end of the first pumping capacitor is coupled to the first end of the second switch, and the second end of the second switch is coupled to the first node; Wherein, the control end of the first switch receives the second differential clock signal, and the second switch receives the first differential clock signal; The second end of the second charge pump current source is coupled to the first end of the third switch, the second end of the third switch is coupled to the first end of the fourth switch, the cathode of the second diode is coupled to the anode of the third diode and the first end of the second pumping capacitor respectively, the second end of the second pumping capacitor is coupled to the first end of the fourth switch, and the second end of the fourth switch is coupled to the first node; The control end of the third switch receives the first differential clock signal, and the second switch receives the second differential clock signal; the current provided by the second charge pump current source is equal to the current provided by the first charge pump current source; The first end of the output filter capacitor is coupled to the cathode of the third diode, the cathode of the third diode is also used to output the boost voltage, and the second end of the output filter capacitor is coupled to the first node.

5. The charge pump circuit according to claim 4, wherein: The charge pump circuit further includes an EMC performance optimization module, which includes: a sampling unit and a current control unit; The output end of the charge pump outputs the boost voltage through the sampling unit, and the sampling unit is used to obtain the current value of the load current; The current control unit is coupled to the sampling unit, and the current control unit is configured as follows: Based on the magnitude of the load current, at least a first current control signal is output to control the magnitude of the current provided by the tail current source, wherein the current value of the load current is proportional to the magnitude of the current provided by the tail current source.

6. The charge pump circuit according to claim 5, characterized in that The current control unit is further configured as: Based on the magnitude of the load current, a second current control signal is output to control the magnitude of the current provided by the first charge pump current source and the magnitude of the current provided by the second charge pump current source, wherein the magnitude of the current provided by the first charge pump current source and the magnitude of the current provided by the second charge pump current source are both proportional to the current value of the load current.

7. The charge pump circuit according to claim 6, wherein: The charge pump further comprises: a third charge pump current source and a fourth charge pump current source; The third charge pump current source is coupled between the second switch and the first node, and the fourth charge pump current source is coupled between the fourth switch and the first node; Wherein, the current magnitude provided by the third charge pump current source and the current magnitude provided by the fourth charge pump current source are both controlled by the second current control signal.

8. The charge pump circuit according to claim 7, wherein: The sampling unit includes a sampling resistor; the current control unit includes a first bias resistor, a second bias resistor, a first PMOS tube, a second PMOS tube, a first bias current source, a second bias current source, a second NMOS tube, a third PMOS tube, a fourth PMOS tube, a third NMOS tube and a fifth PMOS tube; The first end of the first bias resistor is coupled to the first end of the sampling resistor, the second end of the first bias resistor is respectively coupled to the source of the first PMOS tube and the drain of the second NMOS tube, the drain of the first PMOS tube is grounded through the first bias current source, the gate of the first PMOS tube is respectively coupled to the gate and drain of the second PMOS tube, the gate of the second NMOS tube is coupled to the drain of the first PMOS tube, and the source of the second NMOS tube is respectively coupled to the drain and gate of the third PMOS tube; The source of the third PMOS tube is grounded, the gate of the third PMOS tube is coupled to the gate of the fourth PMOS tube, the gate of the third PMOS tube is also used to output the first current control signal, the source of the fourth PMOS tube is grounded, the drain thereof is coupled to the source of the third NMOS tube, the gate of the third NMOS tube receives a low voltage supply voltage, the drain of the third NMOS tube is respectively coupled to the drain and the gate of the fifth PMOS tube, the gate of the fifth PMOS tube is also used to output the second current control signal, and the source of the fifth PMOS tube is coupled to the cathode of the third diode; The source of the second PMOS tube is coupled to the second end of the sampling resistor through the second bias resistor, and the drain of the second PMOS tube is grounded through the second bias current source.

9. The charge pump circuit according to claim 8, characterized in that The charge pump circuit further includes a fourth NMOS transistor, and the tail current source includes a third bias current source and a fifth NMOS transistor; The drain of the fourth NMOS transistor is coupled to the first node, the gate thereof receives the low voltage supply voltage, the source thereof is coupled to the first end of the third bias current source, and the second end of the third bias current source is grounded; The drain of the fifth NMOS transistor is coupled to the first end of the third bias current source, the source thereof is grounded, and the gate thereof receives the first current control signal.

10. The charge pump circuit according to claim 8, wherein: The first charge pump current source includes a sixth PMOS transistor, and the second charge pump current source includes a seventh PMOS transistor; The source of the sixth PMOS tube is coupled to the anode of the first diode to receive the functional voltage, the drain of the sixth PMOS tube is coupled to the first end of the first switch, and the gate of the sixth PMOS tube is coupled to the gate of the fifth PMOS tube to receive the second current control signal; The first end of the seventh PMOS tube is coupled to the anode of the first diode to receive the functional voltage, the drain is coupled to the first end of the second switch, and the gate is coupled to the gate of the fifth PMOS tube to receive the second current control signal.

11. The charge pump circuit according to claim 10, wherein: The charge pump circuit further includes an eighth PMOS tube and a sixth NMOS tube, the third charge pump current source includes a seventh NMOS tube, and the fourth charge pump current source includes an eighth NMOS tube; The seventh NMOS transistor is coupled between the second switch and the first node, and the eighth NMOS transistor is coupled between the fourth switch and the first node; The source of the eighth PMOS tube is coupled to the anode of the first diode, and the gate thereof is coupled to the gate of the fifth PMOS tube. The drain of the eighth PMOS tube is respectively coupled to the drain and gate of the sixth NMOS tube. The source of the sixth NMOS tube is coupled to the first node, and the gate thereof is respectively coupled to the gate of the seventh NMOS tube and the gate of the eighth NMOS tube.

12. The charge pump circuit according to claim 4, wherein: The low level voltage value of the first differential clock signal and the low level voltage value of the second differential clock signal are both equal to the voltage value of the floating voltage, and the high level voltage value of the first differential clock signal and the high level voltage value of the second differential clock signal are both equal to the voltage value of the functional voltage.

13. An electronic device, characterized in that: The invention comprises a charge pump circuit as claimed in any one of claims 1 to 11.

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