Buffer output control circuit and method and LDO circuit applying buffer output control circuit and method

Abstract

According to the buffer output control circuit, the buffer output control method and the LDO circuit applying the buffer output control circuit, the second control signal generation circuit and the second transistor are arranged, and in the dropout state, the second control signal generation circuit generates the high-level second control signal based on the error amplification signal to control the second transistor to be switched on; the potential of the control end of the power tube is pulled down to the ground, the problem of voltage loss on the control end of the power tube in the prior art is avoided, the power tube can be completely conducted in the state, the output voltage changes along with the input voltage, the voltage difference between the output voltage and the input voltage is small, and then the system loss can be reduced; and compared with the prior art, the power tube with a smaller area can be adopted to realize the same technical index. When the output voltage is in a voltage stabilization state, the second control signal generation circuit generates a low-level second control signal based on the error amplification signal to control the second transistor to be turned off, namely, in the state, the buffer output control circuit does not affect the work of the power tube.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and specifically to a buffer output control circuit, method, and LDO circuit using the same. Background Technology

[0002] Low dropout regulators (LDOs) are widely used in mobile phones, servers, automobiles, and many other fields due to their good voltage regulation performance and ability to operate under low dropout conditions. In LDO circuits, as the size of the power transistor increases, the parasitic capacitance at the control terminal of the power transistor creates a pole in the loop. This parasitic pole can cause difficulties in the compensation of the entire loop. To solve this problem, existing technologies typically add a buffer between the control terminal of the power transistor and the error amplifier to push this parasitic pole to a higher frequency, thereby improving the system's stability and dynamic performance. Figure 1 This is a schematic diagram of a buffer in the prior art (a buffer with diode connection). The structure is simple to design, and the equivalent impedance on the power transistor control terminal is 1 / gm, where gm is the transconductance of transistor M1. Figure 2 This is another schematic diagram of a buffer in the prior art (a source follower type buffer), and the equivalent impedance on the power transistor control terminal is also 1 / gm. Figure 1 and Figure 2 Although the structure of the buffer is simple, it consumes a large amount of current under heavy load, resulting in high system power consumption. Figure 2 In the structure shown, when the input voltage is close to the output voltage (i.e., in dropout mode, where the output voltage follows the input voltage), due to the presence of transistor M1, the control terminal potential of power transistor M0 is equal to the source potential of transistor M1, which is 0+VGS1 (in dropout mode, the error amplification signal VEA is basically zero). This causes power transistor M0 to be unable to fully turn on (i.e., fully conduct), resulting in a large difference between the input voltage and the output voltage, increasing system losses. Figure 3 This is another schematic diagram of a buffer in the prior art (a buffer of the form of a super source follower), and this type of buffer is relative to... Figure 1 and Figure 2 In the structure shown, the equivalent impedance of the power transistor control terminal is 1 / (gm1*gm2*ro1), where gm1 is the transconductance of transistor M1, gm2 is the equivalent transconductance of transistor Q1, and ro1 is the equivalent output impedance at the second terminal (drain) of transistor M1, which is relative to... Figure 1 and Figure 2 The structure in Figure 3In the existing structure, the equivalent impedance at the control terminal of the power transistor is smaller, which is more conducive to pushing the poles generated by parasitic capacitance to higher frequencies and can save power consumption under heavy load. However, in dropout mode, there is also a voltage drop problem, that is, the control terminal of the power transistor M0 cannot be pulled down to a potential close to ground, causing the power transistor M0 to not be fully turned on, resulting in a large difference between the input voltage and the output voltage, increasing system losses. Therefore, it is necessary to propose a new circuit structure to solve the problems existing in the prior art. Summary of the Invention

[0003] To address the aforementioned technical problems, this invention provides a buffer output control circuit, a method, and an LDO circuit using the same.

[0004] According to a first aspect of the present invention, a buffer output control circuit is provided, wherein the buffer receives an error amplification signal and outputs a first control signal, and the control terminal of a power transistor receives the first control signal to convert an input voltage into an output voltage; the buffer includes a first current source, a first transistor, a second current source, and an amplifier; a first terminal of the first current source receives the input voltage, a second terminal of the first current source is connected to a first terminal of the first transistor, a second terminal of the first transistor is connected to a first terminal of the second current source, the second terminal of the second current source is grounded, the control terminal of the first transistor receives the error amplification signal, the amplifier is connected between the first terminal of the first transistor and the ground terminal, and the second terminal of the first transistor is connected to the input terminal of the amplifier; the first control signal is output at the first terminal of the first transistor; both the power transistor and the first transistor are P-type transistors; characterized in that...

[0005] The output control circuit includes a second control signal generation circuit and a second transistor; the second control signal generation circuit generates the second control signal based on the error amplification signal; the first terminal of the second transistor is grounded, the second terminal of the second transistor is connected to the control terminal of the power transistor, and the control terminal of the second transistor receives the second control signal.

[0006] Specifically, when the output voltage follows the change of the input voltage, the second control signal generation circuit controls the second transistor to turn on based on the error amplification signal, so as to pull the first control signal down to ground; when the output voltage is in a regulated state, the second control signal generation circuit controls the second transistor to turn off based on the error amplification signal.

[0007] Optionally, the second control signal generation circuit includes a voltage drop generation circuit, a fifth transistor, and a third current source. The first terminal of the voltage drop generation circuit receives the input voltage. The second terminal of the voltage drop generation circuit is connected to the first terminal of the fifth transistor. The second terminal of the fifth transistor is connected to the control terminal of the third current source and the second transistor. The second terminal of the third current source is grounded. The control terminal of the fifth transistor receives the error amplification signal. The fifth transistor is a P-type transistor.

[0008] When the output voltage follows the change of the input voltage, the voltage drop generation circuit works, the error amplification signal controls the fifth transistor to turn on, and a high-level second control signal is output at the second terminal of the fifth transistor to control the second transistor to turn on;

[0009] When the output voltage is in a regulated state, the voltage drop between the input voltage and the control terminal of the fifth transistor is less than the sum of the voltage drop on the voltage drop generation circuit and the conduction threshold of the fifth transistor, so the fifth transistor is turned off, and the third current source pulls the control terminal of the second transistor to ground, so the second transistor is turned off.

[0010] Optionally, the voltage drop generation circuit includes a third transistor and a fourth transistor connected in series. The first terminal of the third transistor is the first terminal of the voltage drop generation circuit. The control terminal of the third transistor is connected to its second terminal and to the first terminal of the fourth transistor. The control terminal of the fourth transistor is connected to its second terminal, and the second terminal of the fourth transistor is the second terminal of the voltage drop generation circuit.

[0011] Optionally, the second control signal generation circuit includes a comparator, the first input terminal of which receives the error amplification signal, and the second input terminal of which receives a first threshold or a second threshold.

[0012] When the error amplification signal is lower than the first threshold, the comparator outputs a high-level second control signal to control the second transistor to turn on;

[0013] When the error amplification signal is higher than the second threshold, the comparator outputs a low-level second control signal to control the second transistor to turn off.

[0014] Optionally, both the third transistor and the fourth transistor are P-type transistors.

[0015] Optionally, the amplifier is an N-type transistor.

[0016] Optionally, the first current source and / or the second current source are dynamic current sources related to the load current.

[0017] The present invention also provides an LDO circuit, including an error amplifier, a buffer, and a power transistor, wherein the buffer is connected between the output terminal of the error amplifier and the control terminal of the power transistor; the error amplifier generates an error amplification signal based on a comparison between a feedback voltage of the output voltage and a reference voltage; the buffer receives the error amplification signal and outputs a first control signal, and the control terminal of the power transistor receives the first control signal to convert the input voltage into the output voltage; characterized in that the LDO circuit further includes the buffer output control circuit described above.

[0018] This invention also provides a buffer output control method, wherein the buffer receives an error amplification signal and outputs a first control signal, and a power transistor converts an input voltage into an output voltage based on the first control signal; the buffer includes a first current source, a first transistor, a second current source, and an amplifier; a first terminal of the first current source receives the input voltage, a second terminal of the first current source is connected to a first terminal of the first transistor, a second terminal of the first transistor is connected to a first terminal of the second current source, a second terminal of the second current source is grounded, a control terminal of the first transistor receives the error amplification signal, the amplifier is connected between the first terminal of the first transistor and the ground terminal, and a second terminal of the first transistor is connected to the input terminal of the amplifier; a first control signal is output at the first terminal of the first transistor; both the power transistor and the first transistor are P-type transistors; characterized in that...

[0019] A second transistor is disposed between the control terminal and the ground terminal of the power transistor. When the output voltage follows the change of the input voltage, the second transistor is turned on based on the error amplification signal, and the first control signal is pulled down to ground. When the output voltage is in a regulated state, the second transistor is turned off based on the error amplification signal.

[0020] Optionally, a voltage drop generation circuit, a fifth transistor, and a third current source are provided between the input voltage and the ground terminal. The first terminal of the voltage drop generation circuit receives the input voltage, the second terminal of the voltage drop generation circuit is connected to the first terminal of the fifth transistor, the second terminal of the fifth transistor is connected to the control terminal of the third current source and the second transistor, the second terminal of the third current source is grounded, and the control terminal of the fifth transistor receives the error amplification signal. The fifth transistor is a P-type transistor.

[0021] When the output voltage follows the change of the input voltage, the voltage drop generation circuit works, the error amplification signal controls the fifth transistor to turn on, and a high-level second control signal is output at the second terminal of the fifth transistor to control the second transistor to turn on;

[0022] When the output voltage is in a regulated state, the voltage drop between the input voltage and the control terminal of the fifth transistor is less than the sum of the voltage drop on the voltage drop generation circuit and the conduction threshold of the fifth transistor, so the fifth transistor is turned off, and the third current source pulls the control terminal of the second transistor to ground, so the second transistor is turned off.

[0023] or,

[0024] The error amplification signal is compared with a first threshold or a second threshold. When the error amplification signal is lower than the first threshold, a high-level second control signal is output to control the second transistor to turn on.

[0025] When the error amplification signal is higher than the second threshold, a low-level second control signal is output to control the second transistor to turn off.

[0026] The beneficial effects of the present invention include at least the following:

[0027] The buffer output control circuit, method, and LDO circuit using the present invention, by setting a second control signal generation circuit and a second transistor, in dropout state, the second control signal generation circuit generates a high-level second control signal based on the error amplification signal to control the second transistor to conduct, thereby pulling the control terminal potential of the power transistor down to ground. This avoids the voltage loss problem existing on the control terminal of the power transistor in the prior art, allowing the power transistor to conduct fully in this state, with the output voltage following the input voltage change and the voltage difference between the two being small, thus reducing system losses. Moreover, compared with the prior art, a smaller area power transistor can be used to achieve the same technical specifications. When the output voltage is in a regulated state, the second control signal generation circuit generates a low-level second control signal based on the error amplification signal to control the second transistor to turn off. That is, in this state, the buffer output control circuit does not affect the operation of the power transistor.

[0028] It should be noted that the above general description and the following detailed description are exemplary and explanatory only, and do not limit the present invention. Attached Figure Description

[0029] Figure 1 A schematic diagram of a buffer in the prior art is shown;

[0030] Figure 2 Another schematic diagram of a buffer in the prior art is shown;

[0031] Figure 3 Another schematic diagram of a buffer in the prior art is shown;

[0032] Figure 4 A schematic diagram of a buffer output control circuit provided by the present invention is shown.

[0033] Figure 5 A schematic diagram of the buffer used in this invention is shown;

[0034] Figure 6 This invention illustrates a specific embodiment of the buffer output control circuit provided by the present invention;

[0035] Figure 7 A schematic diagram of an LDO circuit provided by the present invention is shown. Detailed Implementation

[0036] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in various forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of the invention.

[0037] To address the problems existing in the prior art, this invention proposes a buffer output control circuit. Figure 4 This is a schematic diagram of a buffer output control circuit proposed in this invention. The buffer output control circuit 10 includes a second control signal generation circuit and a second transistor M2. The input terminal of the second control signal generation circuit receives an error amplification signal VEA and generates a second control signal V2 based on the error amplification signal VEA. The first terminal of the second transistor M2 is grounded (i.e., connected to the ground terminal), and the second terminal of the second transistor M2 is connected to the control terminal of the power transistor M0. The control terminal of the second transistor M2 receives the second control signal V2. Specifically, when the output voltage VOUT follows the input voltage VIN (i.e., in dropout mode), VEA is essentially zero. In this state, the second control signal generation circuit generates a high-level second control signal V2 based on the error amplification signal VEA, controlling the second transistor M2 to conduct, thereby pulling the control terminal potential of the power transistor M0 down to ground. When the output voltage VOUT is in a regulated state, the second control signal generation circuit generates a low-level second control signal V2 based on the error amplification signal VEA, controlling the second transistor M2 to turn off. That is, in this state, the buffer output control circuit does not affect the operation of the power transistor M0. This invention addresses the voltage drop problem at the control terminal of power transistor M0 by using a second transistor M2. In dropout mode, a high-level second control signal V2 is generated based on the error amplification signal VEA to control the conduction of the second transistor M2, thereby pulling the control terminal potential of power transistor M0 to ground. This avoids the voltage drop problem at the control terminal of power transistor M0 in existing technologies, allowing power transistor M0 to conduct fully. The output voltage VOUT follows the input voltage VIN, and the voltage difference between them is small, thus reducing system losses. Furthermore, this invention incorporates a buffer output control circuit, which, compared to existing technologies... Figure 3The same technical specifications can be achieved using a smaller area power transistor in the structure described above.

[0038] Figure 5 The diagram shows the schematic of the buffer 20 used in this invention. The buffer includes a first current source I1, a first transistor M1, a second current source I2, and an amplifier. The first terminal of the first current source I1 receives the input voltage VIN. The second terminal of the first current source I1 is connected to the first terminal of the first transistor M1. The second terminal of the first transistor M1 is connected to the first terminal of the second current source I2. The second terminal of the second current source I2 is grounded. The control terminal of the first transistor M1 receives the error amplification signal VEA. The amplifier is connected between the first terminal of the first transistor M1 and the ground terminal. The second terminal of the first transistor M1 is connected to the input terminal of the amplifier. The first terminal of the first transistor M1 outputs a first control signal V1. The control terminal of the power transistor M0 receives the first control signal V1 to convert the input voltage VIN into an output voltage VOUT. The amplifier can be... Figure 3 The N-type transistor Q1 shown can also be constructed using other types of structures. In this case, the equivalent impedance of the power transistor control terminal is 1 / (gm1*gm2*ro1), which is related to... Figure 3 The difference is that, in this case, gm2 represents the equivalent transconductance of the amplifier. Both power transistor M0 and the first transistor M1 are P-type transistors; the control terminals mentioned above refer to the gate of power transistor M0 or the first transistor M1.

[0039] The buffer output control circuit will be described next. Figure 6 The diagram shown is a schematic of a buffer output control circuit provided by the present invention. In this diagram, the buffer 20 adopts... Figure 3The structure shown in the figure is not limited to this, and the amplifier in the buffer can also adopt other structures. In this figure, the second control signal generation circuit includes a voltage drop generation circuit 30, a fifth transistor M5, and a third current source I3. The first terminal of the voltage drop generation circuit 30 receives the input voltage VIN, the second terminal of the voltage drop generation circuit 30 is connected to the first terminal of the fifth transistor M5, the second terminal of the fifth transistor M5 is connected to the first terminal of the third current source I3 and the control terminal of the second transistor M2, the second terminal of the third current source I3 is grounded, and the control terminal of the fifth transistor M5 receives the error amplification signal VEA. The fifth transistor is a P-type transistor. When the output voltage VOUT changes with the input voltage VIN (i.e., in dropout state), the voltage drop generation circuit 30 works, the fifth transistor M5 is turned on based on the error amplification signal VEA (the error amplification signal VEA is close to zero potential at this time), and a high level is output at the second terminal of the fifth transistor M5 to control the second transistor M2 to turn on. At this time, the first control signal V1 is pulled down to ground potential, and the power transistor M0 will be fully turned on to reduce the difference between the input voltage and the output voltage, thereby reducing system losses. When the output voltage VOUT is in a regulated state, the voltage drop between the input voltage VIN and the control terminal of the fifth transistor M5 is less than the sum of the voltage drop across the voltage drop generation circuit and the conduction threshold of the fifth transistor M5. Therefore, the fifth transistor M5 is turned off, and the third current source I3 pulls the control terminal of the second transistor M2 to ground, turning off the second transistor M2. In other words, in this state, the buffer output control circuit does not affect the normal operation of the power transistor M0. Furthermore, Figure 6 The diagram illustrates a specific embodiment of a voltage drop generation circuit 30. The voltage drop generation circuit 30 includes a third transistor M3 and a fourth transistor M4 connected in series. The first terminal of the third transistor M3 is the first terminal of the voltage drop generation circuit 30. The control terminal of the third transistor M3 is connected to its second terminal and also connected to the first terminal of the fourth transistor M4. The control terminal of the fourth transistor M4 is connected to its second terminal, and the second terminal of the fourth transistor M4 is the second terminal of the voltage drop generation circuit 30. In this embodiment, both the third transistor M3 and the fourth transistor M4 are P-type transistors. It should be noted that... Figure 6 The voltage drop generation circuit 30 shown is only one example of the present invention, and other structures can be used to achieve the same function as the present invention.

[0040] In another embodiment of the present invention, the second control signal generation circuit may include a comparator. The first input terminal of the comparator receives an error amplification signal VEA, and the second input terminal of the comparator receives a first threshold or a second threshold. When the error amplification signal VEA is lower than the first threshold, the comparator outputs a high level as a second control signal V2 to control the second transistor M2 to turn on; when the error amplification signal VEA is higher than the second threshold, the comparator outputs a low level as a second control signal V2 to control the second transistor M2 to turn off. The values ​​of the first threshold and the second threshold can be set according to the actual circuit.

[0041] Furthermore, the first current source and / or the second current source in the buffer circuit can be designed as a dynamic current source related to the load to improve the driving capability of the buffer.

[0042] Furthermore, the error amplification signal VEA can be a signal that has been compensated by a compensation circuit.

[0043] The present invention also provides an LDO circuit, such as Figure 7 As shown, the circuit includes an error amplifier, a buffer 20, and a power transistor M0. The buffer 20 is connected between the output terminal of the error amplifier and the control terminal of the power transistor M0. The error amplifier generates an error amplification signal VEA based on the comparison between the feedback voltage VFB of the output voltage VOUT and the reference voltage VREF. The buffer receives the error amplification signal VEA and outputs a first control signal V1. The control terminal of the power transistor M0 receives the first control signal V1 to convert the input voltage VIN into the output voltage VOUT. The LDO circuit also includes the buffer output control circuit 10 mentioned above. Through the buffer output control circuit 10, when the output voltage VOUT changes with the input voltage VIN, the first control signal V1 is pulled down to ground. When the output voltage VOUT is in a regulated state, it will not affect the operation of the power transistor M0.

[0044] The present invention also provides a buffer output control method, which has the functions of the buffer output control circuit described above, as detailed in the above description, and will not be elaborated here.

[0045] In summary, the buffer output control circuit, method, and LDO circuit using the present invention, by setting a second control signal generation circuit and a second transistor, in dropout state, the second control signal generation circuit generates a high-level second control signal based on the error amplification signal to control the second transistor to conduct, thereby pulling the control terminal potential of the power transistor down to ground. This avoids the voltage loss problem existing at the control terminal of the power transistor in the prior art, allowing the power transistor to conduct completely in this state, with the output voltage following the input voltage change and the voltage difference between the two being small, thus reducing system losses. Moreover, compared with the prior art, a smaller area power transistor can be used to achieve the same technical specifications. When the output voltage is in a regulated state, the second control signal generation circuit generates a low-level second control signal based on the error amplification signal to control the second transistor to turn off. That is, in this state, the buffer output control circuit does not affect the operation of the power transistor.

[0046] Finally, it should be noted that the above embodiments are merely examples for clearly illustrating the present invention and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A buffer output control circuit, the buffer receiving an error amplified signal and outputting a first control signal, a control terminal of a power transistor receiving the first control signal to convert an input voltage into an output voltage; the buffer comprising a first current source, a first transistor, a second current source and an amplifier; a first terminal of the first current source receiving the input voltage, a second terminal of the first current source connecting with a first terminal of the first transistor, a second terminal of the first transistor connecting with a first terminal of the second current source, a second terminal of the second current source grounding, a control terminal of the first transistor receiving the error amplified signal, the amplifier connecting between the first terminal of the first transistor and a ground terminal, a second terminal of the first transistor connecting with an input terminal of the amplifier; the first control signal outputting at the first terminal of the first transistor; the power transistor and the first transistor both being P-type transistors; characterized in that, the output control circuit comprising a second control signal generating circuit and a second transistor; the second control signal generating circuit generating the second control signal based on the error amplified signal; a first terminal of the second transistor grounding, a second terminal of the second transistor connecting with the control terminal of the power transistor, a control terminal of the second transistor receiving the second control signal; wherein, when the output voltage follows the input voltage, the second control signal generating circuit controls the second transistor to turn on based on the error amplified signal to pull down the first control signal to ground; when the output voltage is in a steady state, the second control signal generating circuit controls the second transistor to turn off based on the error amplified signal.

2. The output control circuit according to claim 1, characterized in that, the second control signal generating circuit comprising a voltage drop generating circuit, a fifth transistor and a third current source, a first terminal of the voltage drop generating circuit receiving the input voltage, a second terminal of the voltage drop generating circuit connecting with a first terminal of the fifth transistor, a second terminal of the fifth transistor connecting with the third current source and the control terminal of the second transistor, a second terminal of the third current source grounding, a control terminal of the fifth transistor receiving the error amplified signal, the fifth transistor being a P-type transistor; when the output voltage follows the input voltage, the voltage drop generating circuit works, the error amplified signal controls the fifth transistor to turn on, a high level second control signal outputting at the second terminal of the fifth transistor controls the second transistor to turn on; when the output voltage is in a steady state, a voltage drop between the input voltage and the control terminal of the fifth transistor is less than a sum of a voltage drop on the voltage drop generating circuit and a turn-on threshold of the fifth transistor, the fifth transistor turns off, the third current source pulls down the control terminal of the second transistor to ground, and the second transistor turns off.

3. The output control circuit according to claim 2, characterized by The voltage drop generating circuit comprises a third transistor and a fourth transistor connected in series, a first end of the third transistor is a first end of the voltage drop generating circuit, a control end of the third transistor is connected with a second end of the third transistor and a first end of the fourth transistor, a control end of the fourth transistor is connected with a second end of the fourth transistor, and a second end of the fourth transistor is a second end of the voltage drop generating circuit.

4. The output control circuit of claim 1, wherein The second control signal generating circuit comprises a comparator, a first input end of the comparator receives the error amplification signal, and a second input end of the comparator receives a first threshold value or a second threshold value. When the error amplification signal is lower than the first threshold value, the comparator outputs a high-level second control signal to control the second transistor to be turned on. When the error amplification signal is higher than the second threshold value, the comparator outputs a low-level second control signal to control the second transistor to be turned off.

5. The output control circuit according to claim 3, characterized by The third transistor and the fourth transistor are both P-type transistors.

6. The output control circuit of claim 1, wherein The amplifier is an N-type transistor.

7. The output control circuit of claim 1, wherein The first current source and / or the second current source are dynamic current sources related to a load current.

8. An LDO circuit comprising an error amplifier, a buffer, and a power transistor, the buffer being connected between an output of the error amplifier and a control terminal of the power transistor; the error amplifier generating an error amplified signal based on a comparison of a feedback voltage of the output voltage and a reference voltage; the buffer receiving the error amplified signal and outputting a first control signal, the control terminal of the power transistor receiving the first control signal to convert an input voltage into the output voltage; characterized in that, The LDO circuit further comprises the buffer output control circuit of any one of claims 1-7. 9.A buffer output control method, the buffer receiving an error amplification signal and outputting a first control signal, a power transistor converting an input voltage into an output voltage based on the first control signal; the buffer comprising a first current source, a first transistor, a second current source and an amplifier; a first end of the first current source receiving the input voltage, a second end of the first current source being connected with a first end of the first transistor, a second end of the first transistor being connected with a first end of the second current source, a second end of the second current source being grounded, a control end of the first transistor receiving the error amplification signal, the amplifier being connected between the first end of the first transistor and a ground end, and a second end of the first transistor being connected with an input end of the amplifier; the first control signal being output at the first end of the first transistor; the power transistor and the first transistor being both P-type transistors; characterized in that, a second transistor is arranged between a control end of the power transistor and the ground end, wherein when the output voltage follows the input voltage, the second transistor is controlled to be turned on based on the error amplification signal to pull down the first control signal to the ground; and when the output voltage is in a steady state, the second transistor is controlled to be turned off based on the error amplification signal.

10. The output control method according to claim 9, characterized by, a voltage drop generating circuit, a fifth transistor and a third current source are arranged between the input voltage and the ground end, a first end of the voltage drop generating circuit receiving the input voltage, a second end of the voltage drop generating circuit being connected with a first end of the fifth transistor, a second end of the fifth transistor being connected with the third current source and a control end of the second transistor, a second end of the third current source being grounded, and a control end of the fifth transistor receiving the error amplification signal, the fifth transistor being a P-type transistor. When the output voltage follows the input voltage, the voltage drop generating circuit works, the error amplifier signal controls the fifth transistor to turn on, and a high-level second control signal output at the second end of the fifth transistor controls the second transistor to turn on; When the output voltage is in a steady state, the voltage drop between the input voltage and the control end of the fifth transistor is less than the sum of the voltage drop on the voltage drop generating circuit and the turn-on threshold of the fifth transistor, the fifth transistor is turned off, and the third current source pulls down the control end of the second transistor to ground, so that the second transistor is turned off; Or, The error amplifier signal is compared with the first threshold or the second threshold, and when the error amplifier signal is lower than the first threshold, a high-level second control signal is output to control the second transistor to turn on; When the error amplifier signal is higher than the second threshold, a low-level second control signal is output to control the second transistor to turn off.

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