Adaptive path selection logic generating circuit and dual path rectifier, radio frequency energy harvesting system

Abstract

The application belongs to the technical field of integrated circuits, and discloses a self-adaptive path selection logic generating circuit, a double-path rectifier and a radio frequency energy collection system. The self-adaptive path selection logic generating circuit comprises a voltage sampling and holding sub-circuit, a dynamic latch comparator sub-circuit and a control signal generating sub-circuit. The application further discloses a double-path rectifier comprising the self-adaptive path selection logic generating circuit, and a radio frequency energy collection system comprising the double-path rectifier. The path switching logic provided by the application can realize optimal power point switching within a large range of load resistance values. The double-path rectifier provided by the application can improve the conversion efficiency and sensitivity of the rectifier, widen the input power range, and continuously widen the application range of the radio frequency energy collection system. The application is suitable for integrated circuit design for radio frequency energy collection.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of integrated circuits, and relates to a self-adaptive path selection logic generating circuit and a dual-path rectifier and a radio frequency energy collection system. BACKGROUND

[0002] Energy collection is a technology for wirelessly powering electronic devices, which in recent years has provided more power supply solutions for people in the fields of Internet of Things, biomedical and industrial application devices. Among them, radio frequency energy collection has become an excellent solution for powering circuits in wearable electronic devices, radio frequency identification (RFID), implantable medical devices due to its flexibility and convenience. However, the radio frequency signals in the environment often exhibit low power density characteristics, so it is necessary to study high-efficiency energy conversion circuits at low power levels.

[0003] The radio frequency energy collection system mainly includes an energy source, an antenna, a matching network, a rectifier, an energy management circuit and an energy storage element. Among them, the RF-DC rectifier plays a role in converting alternating radio frequency energy into direct current signals and powering the subsequent system, and is a key module of the entire radio frequency energy collection system, which plays a decisive role in the energy conversion efficiency of the system.

[0004] Currently, the main challenges of the RF-DC rectifier are the small power density of the radio frequency energy in the environment, the low energy conversion efficiency of the rectifier, and the narrow input power range for maintaining high conversion efficiency of the rectifier. In the current mainstream research on rectifiers, two commonly used topologies are cross-coupled and Dickson rectifiers. The cross-coupled rectifier has a higher rectification efficiency at low input power due to the biasing effect of the internal nodes on the gate of the rectifier tube. The Dickson rectifier has a higher energy conversion efficiency at high input power due to the one-way conduction connection form of the rectifier tube, which suppresses the reverse leakage current of the rectifier at high input power. Therefore, in order to combine the advantages of the two topologies, some research has proposed a dual-path rectifier scheme. However, the energy distribution problem and the best path switching point finding problem in the dual-path rectifier result in poor sensitivity and conversion efficiency of the system.

[0005] For example, the Chinese invention patent with the authorization announcement number CN114244149B discloses a dual-path RF-DC rectifier applied to a radio frequency energy collection system, which introduces a dynamically selected dual-path structure. However, 1, the rectifier uses the auxiliary rectification paths RVG and NVG to provide VREF and VSS signals for the comparator CMP, and uses the comparison of the output voltage V OUT and the output voltage V REF of the auxiliary path RVG to output a switch selection signal SW; since the load of the RVG is a capacitive load and the load of the rectification path is a resistive load, the path selection logic cannot guarantee that VREF greater than V OUT When, the energy conversion efficiency of the second-order full NMOS rectifier is greater than that of the second-order cross-coupled rectifier, and vice versa; 2、V OUT The load resistance has a great influence, and it is difficult to ensure accurate path selection and high energy conversion efficiency in a large load variation range; 3、The rectifier switching switch only has a switch between the rectifier and the ground, and the rectifier path cannot be completely turned off. The rectifier path that is turned off during energy collection causes crosstalk to the turned-on rectifier path, resulting in energy loss. SUMMARY

[0006] The first object of the present application is to provide an adaptive path selection logic generation circuit, which provides path switching logic capable of achieving optimal power point switching in a large range of load resistance values;

[0007] The second object of the present application is to provide a dual-path rectifier containing the adaptive path selection logic generation circuit described above, to improve the conversion efficiency and sensitivity of the rectifier, widen the input power range, and continuously expand the application range of the radio frequency energy collection system;

[0008] The third object of the present application is to provide a radio frequency energy collection system containing the dual-path rectifier described above.

[0009] An adaptive path selection logic generation circuit, comprising a voltage sampling and holding sub-circuit, a dynamic latch comparator sub-circuit, and a control signal generation sub-circuit;

[0010] The control signal generation sub-circuit is powered by the load voltage, and simultaneously generates first to fourth sampling control signals in response to the load voltage, and outputs them to the voltage sampling and holding sub-circuit;

[0011] The voltage sampling and holding sub-circuit samples the load voltage in response to the first to fourth sampling control signals, and generates a first sampling and holding voltage and a second sampling and holding voltage, and outputs the first sampling and holding voltage and the second sampling and holding voltage to the dynamic latch comparator sub-circuit;

[0012] The control signal generation sub-circuit is powered by the load voltage, and simultaneously generates first to fourth sampling control signals in response to the load voltage, and outputs them to the voltage sampling and holding sub-circuit;

[0013] The dynamic latch comparator sub-circuit generates a first comparison control signal and a second comparison control signal in response to the first sampling and holding voltage, the second sampling and holding voltage, the first latch control signal, and the second latch control signal, and outputs them to the control signal generation sub-circuit;

[0014] The control signal generating sub-circuit generates the first to fourth timing control signals in response to the first comparison control signal and the second comparison control signal, and outputs to the external circuit.

[0015] As a limitation, the control signal generating sub-circuit includes a current-starved ring oscillator, a nine-stage frequency divider, a sample-and-hold signal generating sub-module, a charge pump sub-module, a latch control signal generating sub-module, and a switch control signal generating sub-module.

[0016] The current-starved ring oscillator includes first to fifth ring oscillator minimum units connected in series, and the output terminal of the fifth ring oscillator minimum unit is connected to the input terminal of the nine-stage frequency divider through two serial inverters. The current-starved ring oscillator is externally connected to a load voltage, generates a clock signal in response to the load voltage, and outputs to the nine-stage frequency divider through two serial inverters. The nine-stage frequency divider generates first to ninth clock signals in response to the clock signal.

[0017] The fifth and sixth output terminals of the nine-stage frequency divider are connected to the clock control input terminal of the sample-and-hold signal generating sub-module, and the seventh to ninth output terminals are connected to the pulse signal input terminal of the sample-and-hold signal generating sub-module through a logic gate circuit.

[0018] The nine-stage frequency divider outputs the fifth and sixth clock signals to the sample-and-hold signal generating sub-module, and outputs the fifth to ninth clock signals to the logic gate circuit. The logic gate circuit generates first to fourth single-peak pulse signals in response to the fifth to ninth clock signals, and outputs the first to fourth single-peak pulse signals to the sample-and-hold signal generating sub-module, the second and third single-peak pulse signals to the latch control signal generating sub-module, and the third single-peak pulse signal to the switch control signal generating sub-module.

[0019] The sample-and-hold signal generating sub-module generates first to third path selection first stage enable signals, a first sample signal, a second sample signal, a first hold control signal, and a second hold control signal in response to the fifth clock signal, the sixth clock signal, and the first to fourth single-peak pulse signals. The first sample signal, the second sample signal, the first hold control signal, and the second hold control signal are output to the charge pump sub-module. The third path selection first stage enable signal is output to the latch control signal generating sub-module.

[0020] The charge pump sub-module generates first to fourth sample control signals in response to the first sample signal, the second sample signal, the first hold control signal, and the second hold control signal, and outputs to the voltage sample-and-hold sub-circuit.

[0021] The latch control signal generating submodule generates the first latch control signal, the second latch control signal and the switching control signal in response to the second single-peak pulse signal, the third single-peak pulse signal and the third path selection first stage enable signal, and outputs the first latch control signal and the second latch control signal to the dynamic latch comparator subcircuit, and outputs the switching control signal to the switch control signal generating submodule;

[0022] The dynamic latch comparator subcircuit generates the first comparison control signal and the second comparison control signal in response to the first sampling holding voltage, the second sampling holding voltage, the first latch control signal and the second latch control signal, and outputs the first comparison control signal and the second comparison control signal to the switch control signal generating submodule;

[0023] The switch control signal generating submodule generates the first to fourth timing control signals in response to the third single-peak pulse signal, the switching control signal, the first comparison control signal and the second comparison control signal, and outputs the first to fourth timing control signals to the external circuit.

[0024] As a second limitation, the voltage sampling holding subcircuit includes a first sampling path subcircuit and a second sampling path subcircuit;

[0025] The first sampling path subcircuit includes a first to third NMOS tube, a first capacitor and a second capacitor; and the second sampling path subcircuit includes a fourth to sixth NMOS tube, a third capacitor and a fourth capacitor;

[0026] The drain of the first NMOS tube and the fourth NMOS tube is connected to a load voltage, the gate of the first NMOS tube and the third NMOS tube is connected to a first sampling control signal, the gate of the second NMOS tube is connected to a third sampling control signal, the gate of the fourth NMOS tube and the sixth NMOS tube is connected to a second sampling control signal, and the gate of the fifth NMOS tube is connected to a fourth sampling control signal;

[0027] The source of the first NMOS tube is connected to the drain of the second NMOS tube through the first capacitor, and is connected to ground; the source of the second NMOS tube is connected to the drain of the third NMOS tube through the second capacitor, and is connected to ground; the source of the third NMOS tube is connected to ground; and the common end of the second NMOS tube, the third NMOS tube and the second capacitor is an output end of a first sampling holding voltage;

[0028] The source of the fourth NMOS tube is connected to the drain of the fifth NMOS tube through the third capacitor, and is connected to ground; the source of the fifth NMOS tube is connected to the drain of the sixth NMOS tube through the fourth capacitor, and is connected to ground; the source of the sixth NMOS tube is connected to ground; and the common end of the fifth NMOS tube, the sixth NMOS tube and the fourth capacitor is an output end of a second sampling holding voltage;

[0029] In the first sampling path sub-circuit sampling holding stage, the initial state, the first sampling control signal is high, the second to fourth sampling control signals are low, at this time, the first capacitor samples the load voltage, the voltage on the second capacitor is reset; then keep the third sampling control signal high, the first sampling control signal, the second sampling control signal and the fourth sampling control signal are low, at this time the charge stored on the first capacitor is divided by the second capacitor, the second capacitor outputs the first sampling holding voltage;

[0030] In the second sampling path sub-circuit sampling holding stage, the initial state, the second sampling control signal is high, the first sampling control signal, the third sampling control signal and the fourth sampling control signal are low, at this time, the third capacitor samples the load voltage, the voltage on the fourth capacitor is reset; then keep the fourth sampling control signal high, the first to third sampling control signals are low, at this time the charge stored on the third capacitor is divided by the fourth capacitor, the fourth capacitor outputs the second sampling holding voltage.

[0031] A dual-path rectifier comprising the adaptive path selection logic generation circuit.

[0032] As a limitation, the dual-path rectifier further comprises a ground path switch module, an RF-DC rectifier module and a load path switch module; the RF-DC rectifier module is connected to an RF signal source, and the output end of the load path switch module is connected to a load circuit; the ground path switch module comprises a first ground path switch submodule and a second ground path switch submodule; the load path switch module comprises a first load path switch submodule and a second load path switch submodule;

[0033] Wherein, the RF-DC rectifier module comprises a low-power path circuit based on a second-order cross-coupled rectifier and a high-power path circuit based on a second-order all-NMOS rectifier device;

[0034] The RF+ input end of the low-power path circuit and the high-power path circuit is connected to the RF+ signal of the RF signal source, and the RF- input end is connected to the RF- signal of the RF signal source;

[0035] The low-power path circuit V IN The output end of the first ground path switch submodule is connected to V out The first input end of the first load path switch submodule is connected to V IN The first input end of the first load path switch submodule is connected to V outa switch from the terminal to the load; the first input terminal of the first pair of ground path switch sub-modules is connected with the first timing control signal, the second input terminal is connected with the third timing control signal, and the first pair of ground path switch sub-modules is controlled to be closed or turned off by the first timing control signal and the third timing control signal; the second input terminal of the first pair of load path switch sub-modules is connected with the first timing control signal, and the first pair of load path switch sub-modules is controlled to be closed or turned off by the first timing control signal;

[0036] the high-power path circuit V IN the output terminal of the second pair of ground path switch sub-modules is connected with the second timing control signal, the second input terminal is connected with the fourth timing control signal, and the second pair of ground path switch sub-modules is controlled to be closed or turned off by the second timing control signal and the fourth timing control signal; the second input terminal of the second pair of load path switch sub-modules is connected with the second timing control signal, and the second pair of load path switch sub-modules is controlled to be closed or turned off by the second timing control signal. out the first input terminal of the second pair of load path switch sub-modules is connected with the second timing control signal, and the second pair of load path switch sub-modules is controlled to be closed or turned off by the second timing control signal. IN the second pair of load path switch sub-modules is connected with the second timing control signal, and the second pair of load path switch sub-modules is controlled to be closed or turned off by the second timing control signal. out a switch from the terminal to the load; the first input terminal of the first pair of ground path switch sub-modules is connected with the first timing control signal, the second input terminal is connected with the third timing control signal, and the first pair of ground path switch sub-modules is controlled to be closed or turned off by the first timing control signal and the third timing control signal; the second input terminal of the first pair of load path switch sub-modules is connected with the first timing control signal, and the first pair of load path switch sub-modules is controlled to be closed or turned off by the first timing control signal;

[0037] As a further limitation, the first pair of ground path switch sub-modules is composed of a first PMOS tube and a seventh NMOS tube, the source of the first PMOS tube is connected with the substrate and the drain of the seventh NMOS tube, serving as the output terminal of the first pair of ground path switch sub-modules, and the drain of the first PMOS tube, the source of the seventh NMOS tube and the substrate are grounded; the gate of the first PMOS tube serves as the first input terminal of the first pair of ground path switch sub-modules, and the gate of the seventh NMOS tube serves as the second input terminal of the first pair of ground path switch sub-modules;

[0038] The second pair of ground path switch sub-modules is composed of a second PMOS tube and an eighth NMOS tube, the source of the second PMOS tube is connected with the substrate and the drain of the eighth NMOS tube, serving as the output terminal of the second pair of ground path switch sub-modules, and the drain of the second PMOS tube, the source of the eighth NMOS tube and the substrate are grounded; the gate of the second PMOS tube serves as the first input terminal of the second pair of ground path switch sub-modules, and the gate of the eighth NMOS tube serves as the second input terminal of the second pair of ground path switch sub-modules;

[0039] The first load path switching submodule consists of a third PMOS transistor, and the second load path switching submodule consists of a fourth PMOS transistor. The drain of the third PMOS transistor serves as the first input terminal of the first load path switching submodule, and the gate of the third PMOS transistor serves as the second input terminal of the first load path switching submodule. The drain of the fourth PMOS transistor serves as the first input terminal of the second load path switching submodule, and the gate of the fourth PMOS transistor serves as the second input terminal of the second load path switching submodule. The source of the third PMOS transistor and the substrate, and the source of the fourth PMOS transistor and the substrate are connected together, serving as the output terminal of the load path switching module.

[0040] A radio frequency energy harvesting system includes the aforementioned dual-path rectifier.

[0041] The adaptive path selection logic generation circuit in this invention provides path switching logic that can achieve optimal power point switching within a wide range of load resistance values.

[0042] The dual-path rectifier in this invention can improve the conversion efficiency and sensitivity of the rectifier, and broaden the input power range, thereby continuously expanding the application scope of radio frequency energy harvesting systems.

[0043] This invention designs a low-power path circuit based on a second-order cross-coupled rectifier and a high-power path circuit based on a second-order all-NMOS rectifier. Simultaneously, a ground-based path switch module is designed as the V0 for both the high-power and low-power path circuits. IN The end-to-ground switch is designed to function as both a high-power path circuit and a low-power path circuit. out The end-to-load switching is time-controlled by an adaptive path selection logic circuit. The path switching logic involves turning on the high-power path circuit and the low-power path circuit respectively, and sampling and holding the load voltage during each stage. By comparing the load voltage under the two rectified paths, the rectified path with the higher load voltage is selectively turned on, while the rectified path with the lower load voltage is turned off. This ensures that the rectified path with higher energy conversion efficiency is correctly selected during path switching, reduces the energy distribution of idle rectified paths, realizes adaptive path switching, and ensures the search for the optimal path switching point.

[0044] The path switching logic used in this invention has a high tolerance for load changes and can achieve accurate selection of the rectification path and efficient energy harvesting within a large range of load changes.

[0045] The application adopts the switching scheme on the two current transmission paths of the RF-DC rectifier module to the ground and the RF-DC rectifier module to the load, realizes good turn-off effect of the rectifier, reduces the crosstalk of the turn-off path to the turn-on path, and increases the energy conversion efficiency.

[0046] Compared with the double-path RF-DC rectifier applied to the radio frequency energy collection system disclosed in the Chinese invention patent with the authorization announcement No.CN114244149B, the application reduces the use of two auxiliary rectification paths and reduces the energy waste.

[0047] The application belongs to the technical field of integrated circuits, can improve the conversion efficiency and sensitivity of the rectifier, widen the input power range, and continuously widen the application range of the radio frequency energy collection system. BRIEF DESCRIPTION OF DRAWINGS

[0048] The accompanying drawings are used to provide a further understanding of the application, and constitute a part of the specification, together with the embodiments of the application, for explaining the application, and do not constitute a limitation on the application.

[0049] In the drawings:

[0050] Figure 1 It is the circuit principle block diagram of the application embodiment 1;

[0051] Figures 2A-2J It is the circuit diagram of each module of the control signal generation sub-circuit and the dynamic latch comparator sub-circuit of the application embodiment 1;

[0052] Figure 3 It is the circuit principle diagram of the voltage sampling and holding sub-circuit of the application embodiment 1;

[0053] Figure 4 It is the control signal timing diagram of the voltage sampling and holding sub-circuit in the application embodiment 2;

[0054] Figure 5 It is the circuit principle diagram of the application embodiment 2;

[0055] Figure 6 It is the trend chart of the conversion efficiency of the double-path rectifier in the application embodiment with the input power. DETAILED DESCRIPTION

[0056] The preferred embodiments of the application are described below in combination with the drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the application, and are not used to limit the application.

[0057] Embodiment 1: an adaptive path selection logic generation circuit

[0058] As Figure 1As shown, this embodiment includes a voltage sample-and-hold sub-circuit, a dynamic latch comparator sub-circuit, and a control signal generation sub-circuit. The control signal generation sub-circuit is generated by the load voltage V. rect Power supply, and simultaneously responding to the load voltage V rect And generate the first sampling control signal V S1 Second sampling control signal V S2 Third sampling control signal V H1 and the fourth sampling control signal V H2 The signal is then output to the voltage sample-and-hold sub-circuit. The voltage sample-and-hold sub-circuit responds to the first sampling control signal V. S1 Second sampling control signal V S2 Third sampling control signal V H1 and the fourth sampling control signal V H2 And for the load voltage V rect Sampling is performed, and a first sample-and-hold voltage V is generated. INP Second sample holding voltage V INN The first sample-and-hold voltage V INP Second sample holding voltage V INN The output is sent to the dynamic latch comparator sub-circuit. The control signal generation sub-circuit is powered by the load voltage V. rect Power supply, and in response to load voltage V rect This generates the first latch control signal V. lock Second latch control signal V unlock The output is then sent to the dynamic latch comparator sub-circuit; the dynamic latch comparator sub-circuit responds to the first sample-and-hold voltage V. INP Second sampling and holding voltage V INN First latch control signal V lock Second latch control signal V unlock This generates the first comparison control signal COMP. P Second comparison control signal COMP N The signal is then output to the control signal generation sub-circuit. The control signal generation sub-circuit responds to the first comparison control signal COMP. P Second comparison control signal COMP N And thus generate the first timing control signal V S1P Second timing control signal V S2P Third timing control signal V S1N and the fourth timing control signal V S2N It is then output to an external circuit.

[0059] Specifically, such as Figure 2AAs shown, the control signal generating sub-circuit comprises a current starvation ring oscillator, a nine-stage frequency divider, a sample-and-hold signal generating sub-module, a charge pump sub-module, a latch control signal generating sub-module and a switch control signal generating sub-module.

[0060] As shown in Figure 2B , the current starvation ring oscillator comprises first to fifth ring oscillation minimum units connected in cascade, NMOS transistor M NA1 and PMOS transistor M PA1 , which provides a bias current for the ring oscillation, the source and substrate of PMOS transistor M PA1 are connected to a load voltage V rect , the drain of PMOS transistor M PA1 is connected to the drain of NMOS transistor M NA1 , the source and substrate of NMOS transistor M NA1 are connected to ground gnd. The gate of PMOS transistor M PA1 is connected to the gates of PMOS transistors M PA2 , M PA3 , M PA4 , M PA5 and M PA6 , and the gates of NMOS transistors M NA1 , M NA2 , M NA3 , M NA4 , M NA5 and M NA6 are connected to a bias voltage V bias .

[0061] , wherein the structure of the ring oscillation minimum unit is that the source and substrate of the PMOS transistor are connected to a load voltage V rect , and the drain of the PMOS transistor is connected to the power supply end of the inverter INV. The substrate and source of the NMOS transistor are connected to ground gnd, and the drain of the NMOS transistor is connected to the ground gnd of the inverter.

[0062] , wherein the five-stage ring oscillation minimum units are connected in cascade, the output end of the inverter of the first to fourth ring oscillation minimum units is connected to the input end of the inverter of the next-stage ring oscillation minimum unit, and the output end of the inverter INV A5 of the fifth ring oscillation minimum unit is connected to the input end of the inverter INV A1 of the first ring oscillation minimum unit. The output of the inverter INV A5 of the fifth ring oscillation minimum unit passes through inverters INV A6 and INV A7 to form a clock signal CLK and is output to the nine-stage frequency divider.

[0063] In this application, referring to Figure 2C , the nine-stage frequency divider is composed of a plurality of nine-stage D flip-flops connected in cascade, wherein the D flip-flops are connected in a D interface connection The Q interface connects to the Clk interface of the next stage D flip-flop. The Clk interface of the first stage D flip-flop is connected to the clock signal CLK output from the current-starved ring oscillator.

[0064] The nine-stage frequency divider of this application generates the first to ninth clock signals CLK in response to the clock signal CLK. 1stg ~CLK 9stg Among them, the Q interfaces of the fifth to ninth stage D flip-flops sequentially output the fifth clock signal to the ninth clock signal CLK. 5stg CLK 6stg CLK 7stg CLK 8stg and CLK 9stg .

[0065] The fifth and sixth stage outputs of the nine-stage frequency divider in this application, namely the Q interfaces of the fifth and sixth stage D flip-flops, are directly connected to the clock control input of the sample-and-hold signal generation submodule. On the other hand, they are connected together with the seventh to ninth stage outputs, namely the Q interfaces of the seventh to ninth stage D flip-flops, to the pulse signal input of the sample-and-hold signal generation submodule through a logic gate circuit that generates a MONO signal.

[0066] The nine-stage frequency divider in this application divides the fifth clock signal CLK into... 5stg and the sixth clock signal CLK 6stg The output is sent to the sample-and-hold signal generation submodule, and on the other hand, the fifth to ninth clock signals CLK are also output. 1stg ~CLK 9stg Output to a logic gate circuit; the logic gate circuit responds to the fifth to ninth clock signals CLK. 1stg ~CLK 9stg The first single-peak pulse signal to the fourth single-peak pulse signal MONO1 to MONO4 are generated. On the one hand, the first single-peak pulse signal to the fourth single-peak pulse signal MONO1 to MONO4 are output to the sample and hold signal generation submodule. On the other hand, the second single-peak pulse signal MONO2 and the third single-peak pulse signal MONO3 are output to the latch control signal generation submodule. On the third hand, the third single-peak pulse signal MONO3 is output to the switch control signal generation submodule.

[0067] Specifically, as shown in Figure 2, see [link to Figure 2]. Figure 2D As shown, the logic gate circuit of this application consists of four minimum units, the structure of which is a NAND gate. BNThe two signal inputs of the NAND gate NAND are connected to the signals CLK[10-N]stg and CLK[10-(N+1)]stg, respectively BN The output of the NAND gate NAND is connected to the input of the inverter INV BN The output of the inverter INV BN outputs the signal MONO N , wherein N = 1, 2, 3, 4.

[0068] Referring to Figure 2E , the sampling and holding signal generation submodule of the present application generates first path to third path selection first stage enable signals STAGE1-STAGE3, a first sampling signal Sample1, a second sampling signal Sample2, a first holding control signal HOLD1 and a second holding control signal HOLD2 in response to a fifth clock signal CLK 5stg , a sixth clock signal CLK 6stg , first to fourth unipolar pulse signals MONO1-MONO4, and outputs the first sampling signal Sample1, the second sampling signal Sample2, the first holding control signal HOLD1 and the second holding control signal HOLD2 to the charge pump submodule on the one hand; and outputs the third path selection first stage enable signal STAGE3 to the latch control signal generation submodule on the other hand.

[0069] Specifically, as shown in Figure 2E , in the sampling and holding signal generation submodule of the present application, the input of the BUFFER C1 is connected to the first unipolar pulse signal MONO1, the output of the BUFFER C1 outputs the first sampling signal Sample1 and is connected to the input of the inverter INV C1 ; the input of the BUFFER C2 is connected to the second unipolar pulse signal MONO2, the output of the BUFFER C2 outputs the first path selection first stage enable signal STAGE1; the two inputs of the NAND gate NAND C1 are connected to the outputs of the inverters INV C1 and the BUFFER C2 , respectively; the output of the NAND gate NAND C1 is connected to the input of the inverter INV C2 , and the output of the inverter INV C2 outputs the first holding control signal HOLD1. The input of the inverter INV C3 is connected to the third unipolar pulse signal MONO3; the two inputs of the NAND gate NAND C2 are connected to the outputs of the inverters INV C3and the output terminal of the fourth single peak pulse signal MONO4 are connected to the input terminal of the inverter INV C2 and the output terminal of the inverter INV C4 .

[0070] In the sample-and-hold signal generation submodule of the present application, the input terminal of the BUFFER C3 is connected to the sixth clock signal CLK 6stg and the two input terminals of the NAND gate NAND C3 are respectively connected to the output terminal of the inverter INV C4 and the output terminal of the BUFFER C3 , the output terminal of the NAND gate NAND C3 is connected to the input terminal of the inverter INV C5 , the output terminal of the inverter INV C5 outputs the third path selection first stage enable signal STAGE3. The input terminal of the inverter INV C6 is connected to the second single peak pulse signal MONO2, and the two input terminals of the NAND gate NAND C4 are respectively connected to the output terminal of the inverter INV C6 and the sixth clock signal CLK 6stg , the output terminal of the NAND gate NAND C4 is connected to the input terminal of the inverter INV C7 , the output terminal of the inverter INV C7 outputs the second path selection first stage enable signal STAGE2.

[0071] In the sample-and-hold signal generation submodule of the present application, the input terminal of the BUFFER C4 is connected to the fifth clock signal CLK 5stg , the two input terminals of the NAND gate NAND C5 are respectively connected to the signal third path selection first stage enable signal STAGE3 and the output terminal of the BUFFER C4 , the output terminal of the NAND gate NAND C5 is connected to the input terminal of the inverter INV C8 , the output terminal of the inverter INV C8 outputs the second sampling signal Sample2. The input terminal of the inverter INV C9 is connected to the output terminal of the BUFFER C4 , the two input terminals of the NAND gate NAND C6 are respectively connected to the output terminal of the inverter INV C9 and the third single peak pulse signal STAGE3, the output terminal of the NAND gate NAND C6 is connected to the input terminal of the inverter INV C10 , the output terminal of the inverter INV C10The output end of the second holding control signal Hold2 outputs a second holding control signal Hold2.

[0072] As shown in Figure 2E , the charge pump sub-module of the present application generates a first sampling control signal S S1 , a second sampling control signal S S2 , a third sampling control signal S H1 and a fourth sampling control signal S H2 in response to the first sampling signal Sample1, the second sampling signal Sample2, the first holding control signal Hold1 and the second holding control signal Hold2, and outputs them to the voltage sampling and holding sub-circuit.

[0073] In the present application, the minimum unit structure of the charge pump sub-module is as shown in Figure 2F : the input end of the inverter INV D1 is connected to the input signal input, the output end of the inverter INV D1 is connected to one end of the capacitor C1, the input end of the inverter INV D2 and the input end of INVD3. The other end of the capacitor C1 is connected to the source of the NMOS transistor M NC1 and the gate of M NC2 , one end of the capacitor C2 is connected to the output end of the inverter INVD2, and the other end is connected to the gate of the NMOS transistor M NC1 , the source of M NC2 and the power supply end of the inverter INVD3. The drains of the NMOS transistors M NC1 and M NC1 are connected to the load voltage V rect , and the substrate is connected to the ground gnd. The inverter INVD3 outputs the boosted signal Output.

[0074] In the present application, as shown in Figure 2G , the latch control signal generation sub-module generates a first latch control signal V lock , a second latch control signal V unlock and a switching control signal SwitchH in response to the second single-peak pulse signal MONO2, the third single-peak pulse signal MONO3 and the third path selection first stage enable signal STAGE3. On the one hand, the first latch control signal V lock , the second latch control signal V unlock are output to the dynamic latch comparator sub-circuit, and on the other hand, the switching control signal SwitchH is output to the switch control signal generation sub-module.

[0075] As shown in Figure 2I , in the latch control signal generation sub-module of the present application, the input end of the inverter INV E1 is connected to the second single-peak pulse signal MONO2, and the NAND gate NANDE2 The two input terminals are respectively connected to the inverter INV E1 The output terminal and the third single-peak pulse signal MONO3, NAND gate E1 The output terminal is connected to the inverter INV. E2 The input terminal of the NOR gate. E1 The two input terminals are respectively connected to the inverter INV E2 The output terminal and the third path select the first stage enable signal STAGE3, or the NOR gate. E1 The output terminal is connected to the inverter INV. E3 The input terminal of the inverter INV E3 The output terminal outputs the switching control signal SwitchH.

[0076] In this application, in the latch control signal generation submodule, BUFFER E1 The input terminal is connected to the third single-peak pulse signal MONO3, or the NOR gate. E2 The two input terminals are connected to the BUFFER. E1 The output terminal and the third path select the first stage enable signal STAGE3, or the NOR gate. E2 The output terminal is connected to the inverter INV. E4 The input terminal of the inverter INV E4 The output terminal outputs the first latch control signal V lock Inverter INV E5 The input terminal is connected to the first latch control signal V. lock Inverter INV E5 The output terminal outputs the second latch control signal V unlock .

[0077] In this application, the dynamic latch comparator subcircuit responds to the first sample-and-hold voltage V. INP Second sample-and-hold voltage V INN First latch control signal V lock Second latch control signal V unlock This generates the first comparison control signal COMP. N Second comparison control signal COMP P It is then output to the switch control signal generation submodule.

[0078] Figure 2H The circuit topology of the dynamic latch comparator sub-circuit is given below, with PMOS transistor M. PB1 The source and substrate are connected to the load voltage V. rect The gate of PMOS transistor MPB1 is connected to the first latch control signal V. lock The drain of PMOS transistor MPB1 is connected to PMOS transistor M.PB2 and M PB3 of the source. The PMOS tube M PB2 and M PB3 of the substrate are connected to the load voltage V rect , and the gate is connected to the drain of the opposite party, respectively. The PMOS tube M PB2 of the drain outputs the second comparison control signal COMP P , and the PMOS tube M PB3 of the drain is connected to the first comparison control signal COMP N . The NMOS tube M NB1 and M NB2 of the drain is connected to the PMOS tube M PB2 of the drain, and the NMOS tube M NB3 and M NB4 of the drain is connected to the PMOS tube M PB3 of the drain, and the NMOS tube M NB2 of the gate is connected to the PMOS tube M PB2 of the gate, and the NMOS tube M NB3 of the gate is connected to the PMOS tube M PB3 of the gate, and the NMOS tube M NB1 , M NB2 , M NB3 and M NB4 of the source and the substrate are all connected to the ground gnd.

[0079] In the dynamic latch comparator sub-circuit of the present application, the PMOS tube M PB4 and M PB5 of the source and the substrate are connected to the load voltage V rect ; the gate of the PMOS tube M PB4 and the gate of the PMOS tube M PB5 are both connected to the second latch control signal V unlock ; the drain of the PMOS tube M PB4 is connected to the drain of the NMOS tube M NB5 and is connected to the gate of the NMOS tube M NB1 , and the drain of the PMOS tube M PB5 is connected to the drain of the NMOS tube M NB6 and is connected to the gate of the NMOS tube M NB4 . The substrate of the NMOS tube M NB5 is connected to the ground gnd, and the gate is connected to the first sample and hold voltage V INP . The substrate of the NMOS tube M NB6 is connected to the ground gnd, and the gate is connected to the second sample and hold voltage V INN . The drain of the NMOS tube M NB7 is connected to the drain of the NMOS tube M NB5 and M NB6 of the source, and the NMOS tube MNB7 The source and substrate are connected to ground, gnd, NMOS transistor M NB7 The gate is connected to the second latch control signal V. unlock .

[0080] The switch control signal generation submodule of this application responds to the third single-peak pulse signal MONO3, the switching control signal SwitchH, and the first comparison control signal COMP. N Second comparison control signal COMP P And thus generate the first timing control signal V S1P Second timing control signal V S2P Third timing control signal V S1N and the fourth timing control signal V S2N It is then output to an external circuit.

[0081] like Figure 2J As shown, in the switch control signal generation submodule of this application, the NOR gate... E3 The two input terminals are respectively connected to the third single-peak pulse signal MONO3 and the first comparison control signal COMP. N NOR gate E3 The output terminal outputs the first timing control signal V. S1P Inverter INV E6 The output terminal is connected to the first timing control signal V. S1P Inverter INV E6 The output terminal is connected to the input terminal of a charge pump CP, and the output terminal of the charge pump CP outputs a third timing control signal V. S1N ;

[0082] In the switch control signal generation submodule of this application, the NOR gate... E4 The two input terminals are respectively connected to the switching control signal SwitchH and the second comparison control signal COMP. P NOR gate E4 The output terminal outputs the second timing control signal V. S2P Inverter INV E7 The output terminal is connected to the second timing control signal V. S2P Inverter INV E7 The output terminal of one of the charges is connected to the input terminal of another charge pump CP, and the output terminal of the charge pump CP outputs a fourth timing control signal V. S2N .

[0083] like Figure 3 As shown, in this embodiment, the voltage sample-and-hold sub-circuit includes a first sampling path sub-circuit and a second sampling path sub-circuit; the first sampling path sub-circuit includes a first to a third NMOS transistor M. A1 ~MA3 , the first capacitor C S1 , and the second capacitor C H1 ; the second sampling path sub-circuit comprises fourth to sixth NMOS tubes M A4 ~M A6 , the third capacitor C S2 , and the fourth capacitor C H2 . The drain of the first NMOS tube M A1 and the fourth NMOS tube M A4 is connected to a load voltage V rect , the gate of the first NMOS tube M A1 and the third NMOS tube M A3 is connected to a first sampling control signal V S1 , the gate of the second NMOS tube M A2 is connected to a third sampling control signal V H1 , the gate of the fourth NMOS tube M A4 and the sixth NMOS tube M A6 is connected to a second sampling control signal V S2 , and the gate of the fifth NMOS tube M A5 is connected to a fourth sampling control signal V H2 .

[0084] The source of the first NMOS tube M A1 is connected to ground gnd through the first capacitor C S1 on one hand and connected to the drain of the second NMOS tube M A2 on the other hand, the source of the second NMOS tube M A2 is connected to ground gnd through the second capacitor C H1 on one hand and connected to the drain of the third NMOS tube M A3 on the other hand, and the source of the third NMOS tube M A3 is connected to ground gnd; the common terminal of the second NMOS tube M A2 , the third NMOS tube M A3 , and the second capacitor C H1 serves as an output terminal of a first sampling holding voltage V INP .

[0085] The source of the fourth NMOS tube M A4 is connected to ground gnd through the third capacitor C S2 on one hand and connected to the drain of the fifth NMOS tube M A5 on the other hand, the source of the fifth NMOS tube M A5 is connected to ground gnd through the fourth capacitor C H2 on one hand and connected to the drain of the sixth NMOS tube M A6 on the other hand, and the source of the sixth NMOS tube M A6 is connected to ground gnd; the common terminal of the fifth NMOS tube MA5 , the sixth NMOS transistor M A6 and the fourth capacitor C H2 the common end as the output end of the second sample-and-hold voltage V INN .

[0086] The voltage sample-and-hold sub-circuit control signal timing is shown in Figure 4 : in the first sample path sub-circuit sample-and-hold phase, the initial state, the first sample control signal V S1 is high, the second to fourth sample control signals V S2 , V H1 , V H2 are all low, at this time, the first capacitor C S1 samples the load voltage V rect , and the voltage on the second capacitor C H1 is reset; then keep the third sample control signal V H1 high, the first sample control signal V S1 , the second sample control signal V S2 and the fourth sample control signal V H2 are all low, at this time the charge stored on the first capacitor C S1 is divided by the second capacitor C H1 , and the second capacitor C H1 outputs the first sample-and-hold voltage V INP . In the second sample path sub-circuit sample-and-hold phase, the initial state, the second sample control signal V H1 is high, the first sample control signal V S1 , the third sample control signal V H1 and the fourth sample control signal V H2 are all low, at this time, the third capacitor C S2 samples the load voltage V rect , and the voltage on the fourth capacitor C H2 is reset; then keep the fourth sample control signal V H2 high, the first to third sample control signals V S1 , V S2 , V H1 are all low, at this time the charge stored on the third capacitor C S2 is divided by the fourth capacitor V H2 , and the fourth capacitor V H2 outputs the second sample-and-hold voltage V INN .

[0087] Example 2 dual-path rectifier

[0088] As shown in Figure 5As shown, the embodiment includes the adaptive path selection logic generation circuit in embodiment 1, and further includes a ground path switch module, an RF-DC rectifier module and a load path switch module. The RF-DC rectifier module is externally connected with an RF signal source, and the output end of the load path switch module is externally connected with a load circuit; the ground path switch module includes a first ground path switch submodule and a second ground path switch submodule; the load path switch module includes a first load path switch submodule and a second load path switch submodule.

[0089] The RF-DC rectifier module includes a low-power path circuit based on a 2nd-order cross-coupled rectifier and a high-power path circuit based on a 2nd-order full NMOS rectifier device. The RF+ input end of the low-power path circuit and the high-power path circuit is connected with the RF+ signal of the RF signal source, and the RF- input end is connected with the RF- signal of the RF signal source.

[0090] The low-power path circuit V IN is connected with the output end of the first ground path switch submodule, and V out is connected with the first input end of the first load path switch submodule, and the first ground path switch submodule constitutes the V IN to ground switch of the low-power path circuit, and the first load path switch submodule constitutes the V out to load switch of the low-power path circuit; the first input end of the first ground path switch submodule is connected with a first timing control signal, the second input end is connected with a third timing control signal, and the closing and turning off of the first ground path switch submodule is controlled by the first timing control signal and the third timing control signal; the second input end of the first load path switch submodule is connected with the first timing control signal, and the closing and turning off of the first load path switch submodule is controlled by the first timing control signal.

[0091] The high-power path circuit V IN is connected with the output end of the second ground path switch submodule, and V out is connected with the first input end of the second load path switch submodule, and the second ground path switch submodule constitutes the V IN to ground switch of the high-power path circuit, and the second load path switch submodule constitutes the V out to load switch of the high-power path circuit; the first input end of the second ground path switch submodule is connected with a second timing control signal, the second input end is connected with a fourth timing control signal, and the closing and turning off of the second ground path switch submodule is controlled by the second timing control signal and the fourth timing control signal; the second input end of the second load path switch submodule is connected with the second timing control signal, and the closing and turning off of the second load path switch submodule is controlled by the second timing control signal.

[0092] Specifically, as shown in Figure 5 , the first ground path switch submodule is composed of a first PMOS transistor M P1and the seventh NMOS transistor M N1 The source of the first PMOS transistor M P1 is connected with the substrate, the drain of the seventh NMOS transistor M N1 is connected with the output terminal of the first ground path switch sub-module. The drain of the first PMOS transistor M P1 , the source and the substrate of the seventh NMOS transistor M N1 are grounded gnd; the gate of the first PMOS transistor M P1 is connected with the first timing control signal V S1P as the first input terminal of the first ground path switch sub-module, and the gate of the seventh NMOS transistor M N1 is connected with the third timing control signal V S1N .

[0093] As shown in Figure 5 , the second ground path switch sub-module is composed of a second PMOS transistor M P2 and an eighth NMOS transistor M N2 , the source of the second PMOS transistor M P2 is connected with the substrate, the drain of the eighth NMOS transistor M N2 is connected with the output terminal of the second ground path switch sub-module. The drain of the second PMOS transistor M P2 , the source and the substrate of the eighth NMOS transistor M N2 are grounded gnd; the gate of the second PMOS transistor M P2 is connected with the second timing control signal V S2P as the first input terminal of the second ground path switch sub-module, and the gate of the eighth NMOS transistor M N2 is connected with the fourth timing control signal V S2N as the second input terminal of the second ground path switch sub-module.

[0094] As shown in Figure 5 , the first load path switch sub-module is composed of a third PMOS transistor M P3 , and the second load path switch sub-module is composed of a fourth PMOS transistor M P4 . The drain of the third PMOS transistor M P3 is connected with the first input terminal of the first load path switch sub-module, and the gate of the third PMOS transistor M P3 is connected with the first timing control signal V S1P as the second input terminal of the first load path switch sub-module; the drain of the fourth PMOS transistor M P4 is connected with the first input terminal of the second load path switch sub-module, and the gate of the fourth PMOS transistor M P4 is connected with the second timing control signal V S2PThe third PMOS transistor M P3 The source and substrate, the fourth PMOS transistor M P4 The source and substrate are connected together, serving as the output of the load path switching module connected to an external load circuit, such as a parallel capacitor C. L Resistance R L The capacitor C in parallel L Resistance R L The other end is grounded.

[0095] The following describes the underlying logic of how the ground path switch module and the load path switch module are used to control the opening and closing of the rectifier path in this embodiment.

[0096] like Figure 5 As shown, when the switch control signals VS1N and VS2P are high and VS1P and VS2N are low, the path switch of the second-order cross-coupled rectifier is open, and the path switch of the second-order all-NMOS rectifier is closed. At this time, the path of the second-order cross-coupled rectifier is low-impedance to the RF source, and the path of the second-order all-NMOS rectifier is high-impedance to the RF source. RF energy mainly flows into the path of the second-order cross-coupled rectifier. Similarly, when the switch control signals VS1N and VS2P are low and VS1P and VS2N are high, the path switch of the second-order cross-coupled rectifier is closed, and the path switch of the second-order all-NMOS rectifier is open. At this time, the path of the second-order cross-coupled rectifier is high-impedance to the RF source, and the path of the second-order all-NMOS rectifier is low-impedance to the RF source. RF energy mainly flows into the path of the second-order all-NMOS rectifier.

[0097] As can be seen from the above analysis, this example achieves the switching between the conduction mode and the shutdown mode of the rectifier path by controlling the gate voltage of the two switches.

[0098] Figure 6 The graph shows the trend of conversion efficiency (PCE) of a dual-path rectifier as a function of input power. Generally, rectifiers using a single-type topology exhibit a single-peak PCE curve, while those using a dual-path rectifier show a different trend. Figure 6 As can be seen, the PCE curve of the dual-path rectifier provided in this embodiment reaches a peak at -7dBm and then shows a continuing upward trend after -4dBm. This indicates that the dual-path rectifier combines the advantages of high energy conversion efficiency at low input power by cross-coupled topology rectifiers and high energy conversion efficiency at high input power by all-NMOS topology rectifiers, thus broadening the dynamic energy harvesting range of the rectifier.

[0099] Example 3 Radio Frequency Energy Harvesting System

[0100] The embodiment provides a radio frequency energy collection system, which comprises the dual-path rectifier in the embodiment 2. Further comprising an antenna, a matching network, a rectifier, an energy management circuit and an energy storage element; the dual-path rectifier converts the alternating radio frequency energy into a direct current signal and supplies power for the whole radio frequency energy collection system.

Claims

1. Adaptive routing logic generation circuitry, characterized by, The voltage sampling holding sub-circuit, the dynamic latch comparator sub-circuit and the control signal generating sub-circuit are included. The control signal generating sub-circuit is powered by the load voltage, generates the first to fourth sampling control signals in response to the load voltage, and outputs to the voltage sampling holding sub-circuit. The voltage sampling holding sub-circuit samples the load voltage in response to the first to fourth sampling control signals, generates the first and second sampling holding voltages, and outputs the first and second sampling holding voltages to the dynamic latch comparator sub-circuit. The control signal generating sub-circuit is powered by the load voltage, generates the first and second latch control signals in response to the load voltage, and outputs to the dynamic latch comparator sub-circuit. The dynamic latch comparator sub-circuit generates the first and second comparison control signals in response to the first and second sampling holding voltages, the first and second latch control signals, and outputs to the control signal generating sub-circuit. The control signal generating sub-circuit generates the first to fourth timing control signals in response to the first and second comparison control signals, and outputs to the external circuit.

2. The adaptive path selection logic generation circuit of claim 1, wherein, The control signal generating sub-circuit includes a current-starved ring oscillator, a nine-stage frequency divider, a sample-and-hold signal generating sub-module, a charge pump sub-module, a latch control signal generating sub-module and a switch control signal generating sub-module. The current-starved ring oscillator includes first to fifth ring oscillator minimum units connected in series, and the output of the fifth ring oscillator minimum unit is connected to the input of the nine-stage frequency divider through two series inverters; the current-starved ring oscillator is powered by the load voltage, generates a clock signal in response to the load voltage, and outputs to the nine-stage frequency divider through two series inverters; the nine-stage frequency divider generates first to ninth clock signals in response to the clock signal. The fifth and sixth stage outputs of the nine-stage frequency divider are connected to the clock control input of the sample-and-hold signal generating sub-module, and are connected to the seventh to ninth stage outputs through a logic gate circuit to the pulse signal input of the sample-and-hold signal generating sub-module. The nine-stage frequency divider outputs the fifth and sixth clock signals to the sample-and-hold signal generating sub-module, and outputs the fifth to ninth clock signals to the logic gate circuit; the logic gate circuit generates first to fourth single-peak pulse signals in response to the fifth to ninth clock signals, outputs the first to fourth single-peak pulse signals to the sample-and-hold signal generating sub-module, outputs the second and third single-peak pulse signals to the latch control signal generating sub-module, and outputs the third single-peak pulse signal to the switch control signal generating sub-module. The sampling and holding signal generating sub-module generates the first to third path selection first stage enable signals, the first sampling signal, the second sampling signal, the first holding control signal and the second holding control signal in response to the fifth clock signal, the sixth clock signal, the first to fourth single-peak pulse signals, and outputs the first sampling signal, the second sampling signal, the first holding control signal and the second holding control signal to the charge pump sub-module on one hand, and outputs the third path selection first stage enable signal to the latch control signal generating sub-module on the other hand; The charge pump sub-module generates the first to fourth sampling control signals in response to the first sampling signal, the second sampling signal, the first holding control signal and the second holding control signal, and outputs the first to fourth sampling control signals to the voltage sampling and holding sub-circuit; The latch control signal generating sub-module generates the first latch control signal, the second latch control signal and the switching control signal in response to the second single-peak pulse signal, the third single-peak pulse signal and the third path selection first stage enable signal, and outputs the first latch control signal and the second latch control signal to the dynamic latch comparator sub-circuit on one hand, and outputs the switching control signal to the switch control signal generating sub-module on the other hand; The dynamic latch comparator sub-circuit generates the first comparison control signal and the second comparison control signal in response to the first sampling and holding voltage, the second sampling and holding voltage, the first latch control signal and the second latch control signal, and outputs the first comparison control signal and the second comparison control signal to the switch control signal generating sub-module; The switch control signal generating sub-module generates the first to fourth timing control signals in response to the third single-peak pulse signal, the switching control signal, the first comparison control signal and the second comparison control signal, and outputs the first to fourth timing control signals to the external circuit.

3. The adaptive routing logic generation circuit of claim 1 or 2, wherein, The voltage sampling and holding sub-circuit comprises a first sampling path sub-circuit and a second sampling path sub-circuit; The first sampling path sub-circuit comprises the first to third NMOS tubes, a first capacitor and a second capacitor, and the second sampling path sub-circuit comprises the fourth to sixth NMOS tubes, a third capacitor and a fourth capacitor; The drain of the first NMOS tube and the drain of the fourth NMOS tube are connected to a load voltage, the gate of the first NMOS tube and the gate of the third NMOS tube are connected to the first sampling control signal, the gate of the second NMOS tube is connected to the third sampling control signal, the gate of the fourth NMOS tube and the gate of the sixth NMOS tube are connected to the second sampling control signal, and the gate of the fifth NMOS tube is connected to the fourth sampling control signal; The source of the first NMOS tube is connected to the drain of the second NMOS tube on one hand, and connected to the ground through the first capacitor on the other hand, the source of the second NMOS tube is connected to the drain of the third NMOS tube on one hand, and connected to the ground through the second capacitor on the other hand, and the source of the third NMOS tube is connected to the ground; the common end of the second NMOS tube, the third NMOS tube and the second capacitor is used as an output end of the first sampling and holding voltage. The source of the fourth NMOS tube is connected with the drain of the fifth NMOS tube on one hand and grounded on the other hand, the source of the fifth NMOS tube is connected with the drain of the sixth NMOS tube on one hand and grounded on the other hand, and the source of the sixth NMOS tube is grounded; the common terminal of the fifth NMOS tube, the sixth NMOS tube and the fourth capacitor is the output terminal of the second sample and hold voltage; In the sample and hold stage of the first sample path sub-circuit, the first sample control signal is high, and the second to fourth sample control signals are low, at this time, the first capacitor samples the load voltage, and the voltage on the second capacitor is reset; then the third sample control signal is kept high, and the first, second and fourth sample control signals are low, at this time, the charge stored on the first capacitor is divided by the second capacitor, and the second capacitor outputs the first sample and hold voltage; In the sample and hold stage of the second sample path sub-circuit, the second sample control signal is high, and the first, third and fourth sample control signals are low, at this time, the third capacitor samples the load voltage, and the voltage on the fourth capacitor is reset; then the fourth sample control signal is kept high, and the first to third sample control signals are low, at this time, the charge stored on the third capacitor is divided by the fourth capacitor, and the fourth capacitor outputs the second sample and hold voltage.

4. A dual path rectifier characterized by, The adaptive path selection logic generation circuit of any one of claims 1 to 3.

5. The dual path rectifier of claim 4, wherein, The dual-path rectifier further comprises a ground path switch module, an RF-DC rectifier module and a load path switch module; the RF-DC rectifier module is externally connected with an RF signal source, and the output terminal of the load path switch module is externally connected with a load circuit; the ground path switch module comprises a first ground path switch submodule and a second ground path switch submodule; the load path switch module comprises a first load path switch submodule and a second load path switch submodule; The RF-DC rectifier module comprises a low-power path circuit based on a second-order cross-coupled rectifier and a high-power path circuit based on a second-order all-NMOS rectifier device; The RF+ input terminals of the low-power path circuit and the high-power path circuit are connected with the RF+ signal of the RF signal source, and the RF- input terminals are connected with the RF- signal of the RF signal source; Low power path circuit V IN The output end of the first pair of ground path switch sub-modules is connected to the first input end of the first pair of load path switch sub-modules, and the first pair of ground path switch sub-modules constitute a low power path circuit V out The first input end of the first pair of load path switch sub-modules is connected to the output end of the first pair of ground path switch sub-modules, and the first pair of load path switch sub-modules constitute a low power path circuit V IN The second input end of the first pair of load path switch sub-modules is connected to the output end of the first pair of ground path switch sub-modules, and the first pair of load path switch sub-modules constitute a low power path circuit V out The second input end of the first pair of load path switch sub-modules is connected to the output end of the first pair of ground path switch sub-modules, and the first pair of load path switch sub-modules constitute a low power path circuit V high power path circuit V IN the output end of the second pair of ground path switch sub-modules, V out the first input end of the second pair of load path switch sub-modules, the second pair of ground path switch sub-modules constituting the high power path circuit, V IN the switch to ground, the second pair of load path switch sub-modules constituting the high power path circuit, V out the switch to load; the first input end of the second pair of ground path switch sub-modules is connected with the second timing control signal, the second input end is connected with the fourth timing control signal, and the closing and turning off of the switch is controlled by the second timing control signal and the fourth timing control signal; the second input end of the second pair of load path switch sub-modules is connected with the second timing control signal, and the closing and turning off of the switch is controlled by the second timing control signal.

6. The dual path rectifier of claim 5, wherein, The first ground path switch submodule is composed of a first PMOS tube and a seventh NMOS tube, the source of the first PMOS tube is connected with the substrate and the drain of the seventh NMOS tube, serving as the output terminal of the first ground path switch submodule, the drain of the first PMOS tube, the source of the seventh NMOS tube and the substrate are grounded, the gate of the first PMOS tube serves as the first input terminal of the first ground path switch submodule, and the gate of the seventh NMOS tube serves as the second input terminal of the first ground path switch submodule; The second ground path switch sub-module is composed of a second PMOS tube and an eighth NMOS tube, the source of the second PMOS tube is connected with the substrate and the drain of the eighth NMOS tube, serving as an output end of the second ground path switch sub-module, the drain of the second PMOS tube, the source of the eighth NMOS tube and the substrate are grounded; the gate of the second PMOS tube serves as a first input end of the second ground path switch sub-module, and the gate of the eighth NMOS tube serves as a second input end of the second ground path switch sub-module; The first load path switch sub-module is composed of a third PMOS tube, and the second load path switch sub-module is composed of a fourth PMOS tube; the drain of the third PMOS tube serves as a first input end of the first load path switch sub-module, and the gate of the third PMOS tube serves as a second input end of the first load path switch sub-module; the drain of the fourth PMOS tube serves as a first input end of the second load path switch sub-module, and the gate of the fourth PMOS tube serves as a second input end of the second load path switch sub-module; the source of the third PMOS tube and the source of the fourth PMOS tube are connected with the substrate, serving as an output end of the load path switch module.

7. A radio frequency energy harvesting system, characterized by, A dual-path rectifier comprising the dual-path rectifier of any one of claims 4-6.

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