Inverter circuit, inverter system, and method of controlling inverter circuit

Abstract

An inverter circuit, an inverter system, and a method of controlling an inverter circuit are provided. To reduce switching loss, the inverter circuit of the present disclosure may operate using triangular current mode (TCM) control for semiconductor devices to achieve zero voltage switching (ZVS) when semiconductor switches are turned on. Inverter circuits of the present disclosure are controlled by processing circuitry, as compared to other techniques in which the inverter circuit is operated, for example, in a continuous conduction mode (CCM), the switching device experiences hard switching when on (typically associated with body diode hard commutation), and thus experiences associated switching losses. The processing circuitry is configured to apply an intelligent frequency modulation scheme that implements TCM operation.

Description

Technical Field

[0001] The present disclosure relates to power inverter circuitry. Background Art

[0002] A non-isolated DC to AC converter (also referred to as an inverter) can be implemented using one of several switching topologies and using any of several switches, such as bipolar junction transistors (BJTs), metal oxide semiconductor field effect transistors (MOSFETs), and power transistors such as insulated gate bipolar junction transistors (IGBTs). Transistors can be implemented using silicon, gallium nitride (GaN), silicon carbide (SiC), and other materials. Efficient operation may be desired in some applications, such as converting DC power from a photovoltaic cell to AC power. Therefore, reducing losses in the inverter, such as conduction losses, switching losses, and the like, can be beneficial. Summary of the invention

[0003] In general, the present disclosure describes circuit operations for reducing switching losses of semiconductor devices associated with inverter circuits. The inverter circuit topologies of the present disclosure include H4 topologies and other derived inverter topologies, such as H5 topologies and efficient and reliable inverter concepts (HERIC) topologies. In order to reduce switching losses, the inverter circuit of the present disclosure operates using a triangular current mode (TCM) control for semiconductor devices to achieve zero voltage switching (ZVS) when the semiconductor switches are turned on. Compared to other technologies that operate inverter circuits, such as in continuous conduction mode (CCM), where the switching devices experience hard switching (usually associated with body diode hard commutation) when turned on and therefore experience associated switching losses, the inverter circuit of the present disclosure is controlled by a processing circuit system that is configured to apply an intelligent frequency modulation scheme that implements TCM operation.

[0004] In one example, the present disclosure describes an inverter circuit including an input terminal, an output terminal, and at least four switches, the inverter circuit being configured to: receive direct current (DC) input power at the input terminal and output alternating current (AC) power at the output terminal; and receive a control signal from a controller, the controller including a processing circuit system, wherein the control signal modulates a switching frequency of the inverter circuit based at least on an instantaneous AC output current and an instantaneous AC output voltage at the output terminal, wherein the switching frequency is also based on a predetermined first AC output current, wherein the predetermined first AC output current causes each switch to be turned on with zero voltage switching (ZVS).

[0005] In another example, the present disclosure describes an inverter system, comprising: a processing circuit system configured to output a control signal; and an inverter circuit comprising an input terminal, an output terminal and at least four switches, the inverter circuit being configured to: receive direct current (DC) input power at the input terminal and output alternating current (AC) output power at the output terminal; and receive a control signal from the processing circuit system, wherein the control signal modulates a switching frequency of the inverter circuit based at least on an instantaneous AC output current and an instantaneous AC output voltage at the output terminal, wherein the switching frequency is also based on a predetermined first AC output current, wherein the predetermined first AC output current causes each switch to be turned on with zero voltage switching (ZVS).

[0006] In another example, the present disclosure describes a method for controlling an inverter circuit, the method comprising receiving, by a processing circuit system, an indication of the magnitude of a direct current (DC) input power received at an input terminal of the inverter circuit; receiving, by the processing circuit system, an indication of the instantaneous magnitude of an alternating current (AC) output power at an output terminal of the inverter circuit; transmitting, by the processing circuit system, a control signal to each switch of the inverter circuit, wherein the inverter circuit comprises at least four switches; and modulating, by the processing circuit system, a switching frequency of the inverter circuit by the control signal, wherein the switching frequency is based at least on an instantaneous AC output current and an instantaneous AC output voltage at the output terminal, and causing each switch to be turned on with zero voltage switching (ZVS).

[0007] The details of one or more examples of the disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the disclosure will become apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1A is a block diagram illustrating an example inverter circuit of the present disclosure.

[0009] Figure 1B , Figure 1C and Figure 1D is a schematic diagram illustrating an example implementation of a DC-AC converter circuit of the present disclosure.

[0010] Figure 2A is a schematic diagram showing an example inverter circuit of the present disclosure implemented using the HERIC architecture.

[0011] Figure 2B is a timing diagram showing an example AC waveform with I1 and I2 and TCM.

[0012] Figure 3 is a schematic diagram illustrating an example implementation of control circuitry of the present disclosure.

[0013] Figure 4A and Figure 4B is a timing chart comparing the operations of the inverter circuit using CCM and TCM.

[0014] Figure 5 is the switching frequency f along the positive AC half cycle SW Time plot of the changing examples.

[0015] Fig. 6A and Figure 6B is a timing diagram illustrating example operation of a HERIC topology inverter using hybrid CCM / TCM modulation.

[0016] Fig. 7A and Figure 7B It shows that Figure 6B An example of a time graph is shown in FIG. 1 , a time graph of a zoomed-in area.

[0017] Fig. 8A and Figure 8B is a timing diagram illustrating example operation of a HERIC topology inverter using hybrid CCM / TCM modulation for a power factor of unity.

[0018] Figure 8C and Fig.8D is a timing diagram illustrating example operation of a HERIC topology inverter using hybrid CCM / TCM modulation for zero power factor.

[0019] Fig. 9 is a flow chart illustrating an example operation of a HERIC topology inverter using hybrid CCM / TCM modulation of the present disclosure. DETAILED DESCRIPTION

[0020] The present disclosure describes the application of hybrid delta current mode (TCM) and continuous conduction mode (CCM) modulation schemes in inverters based on H4 topology and other derivative inverter topologies such as H5, HERIC or other topologies. When operating using the hybrid TCM / CCM modulation scheme, the inverter circuit can achieve soft switching when turning on the semiconductor switch, which can achieve a significant reduction in switching losses associated with the semiconductor switching devices.

[0021] In an embodiment of an inverter circuit of the present disclosure, the AC current output from the inverter circuit may experience a wide range of excursions from a small negative value of several amperes, such as a "minimum" operating current (I1), to up to an instantaneous peak value (I2). The control circuit system for the inverter circuit of the present disclosure can operate the inverter circuit in TCM by selecting a fixed value (low current level) of I1, which ensures ZVS operation when the switch is turned on. In some examples, I1 can be several "negative" amperes. The control circuit system can control the switching so that a predefined value of the maximum current I2 (i.e., the current value when the device will turn off) is determined based on the current demand from the load. Along the entire AC cycle, the control circuit system can change the switching frequency (f SW ) to implement TCM.

[0022] The control circuitry may operate the inverter circuit in an open loop, for example, without a zero crossing detection (ZCD) circuit for closed loop feedback. The control circuitry varies the switching frequency based on, for example, the output power, AC voltage, instantaneous values ​​of DC voltage, and the value of the output inductance.

[0023] In this way, the inverter circuit of the present disclosure can operate with soft switching when the switch is turned on. In contrast, an inverter circuit that operates only in CCM mode can have a relatively small difference between the minimum current delivered to the load and the peak current, and the inverter switch can operate with hard switching when turned on. However, in most cases, the inverter circuit of the present disclosure can maintain soft switching for most of the AC cycle under most conditions (including delivering reactive power, such as when the power factor (PF) is less than 1).

[0024] Figure 1A is a block diagram illustrating an example inverter circuit of the present disclosure. Figure 1A In the example, the system 100 is configured to receive the voltage from V DC 102 receives the DC input power and converts it into V AC-OUT AC output power at 112. Applications for using system 100 may include converting DC power from a photovoltaic (PV) source for use in a grid. The parasitic capacitance of a PV panel may benefit from an inverter topology with zero common mode and full range reactive power control that system 100 may provide for grid support.

[0025] The system 100 includes a DC-AC inverter 104 and a controller including a processing circuit system 106 operably coupled to a memory 114. The DC-AC inverter 104 outputs V via output terminals 124 and 126 connected to a "high-side" inductor L1 110 and a "low-side" inductor L2 108, respectively.AC-OUT 112.

[0026] The DC-AC inverter 104 can be implemented in any of a number of different topologies. Some examples include an H4 topology with two low-side switches and two high-side switches. In other examples, the DC-AC inverter 104 can be implemented as a HERIC topology, which is a topology configured to connect the converter to a load, such as at V AC-OUT The utility grid connected at 112 is disconnected to avoid a fluctuating potential on the DC terminals of the PV generator. The HERIC topology can achieve a zero voltage level at the output by using a bidirectional switch during the freewheeling period.

[0027] As described above, processing circuit system 106 can use a hybrid PWM scheme including TCM and CCM to control the operation of DC-AC inverter 104. TCM can cause soft switching, for example, when turning on the switches of the inverter. Soft switching can also cause reduced losses during operation and thus improve efficiency when compared to other operating techniques. For TCM modulation, the inductor current reverses polarity before turning on.

[0028] Other advantages of the circuit operation of the present disclosure may include the use of modulation strategies that implement ZVS and / or TCM in an H4-based inverter system for all operating modes including full reactive power with open-loop control. In other words, the system 100 can operate without additional hardware such as zero-crossing detection (ZCD) circuit systems found in other examples of inverter systems. Soft switching throughout the operating cycle, also referred to as the AC cycle in the present disclosure, can provide high efficiency in almost all operating points. A more efficient inverter system can help maximize the use (and / or storage) of energy generated by photovoltaic (PV) cells, thereby promoting a strategic path for decarbonization in PV system design. In some examples, based on the phase angle between current and voltage, the circuit of the present disclosure can operate in any of several operating modes, such as CCM or TCM, at different points in the operating cycle. In an example where the power factor is 1, such as the voltage and current are in phase, at least one operating mode will cause ZVS switching of at least all four switches.

[0029] Due to the improved efficiency, the system can be further improved towards higher power density by increasing the switching frequency and thus increasing the volume of the system passive devices (e.g., filter components). The volume reduction of passive components can cause size and cost savings, and realize the reduction of the bill of materials (BOM) of the associated passive components and higher switching frequencies. Other advantages can include the ultimate promotion of the use of semiconductor switches such as GaN and SiC transistors based on wide bandgap (WBG) materials. WBG semiconductors may be different from conventional semiconductors because they have larger band gaps. Bandgap refers to the energy difference between the top of the valence band and the bottom of the conduction band in a semiconductor. The larger distance enables wide bandgap semiconductor power devices to operate at higher voltages, temperatures, and frequencies. In some examples, wide bandgap semiconductor materials such as GaN and silicon carbide (SiC) can be the desired materials to be used to improve the efficiency of power converters relative to the efficiency of power converters using silicon-based transistors.

[0030] Figure 1B , Figure 1C and Figure 1D is a DC-AC converter circuit showing the content of the present disclosure, for example Figure 1A Schematic diagram of an example implementation of a DC-AC inverter 104 . Figure 1B An H4 topology is shown comprising four semiconductor switches arranged in an H-bridge. Figure 1C Shown include Figure 1B The H5 topology shows an H-bridge with a fifth semiconductor switch located between the DC input supply and the high-side switch. Figure 1D An example of a HERIC topology is shown. The HERIC topology includes Figure 1B The H-bridge shown in FIG. 1 is a bridge in which the switch node of the first half-bridge is connected to the AC output through a first inductor and the switch node of the second half-bridge is connected to the AC output through a second inductor. The switch node is connected to the AC output through a bidirectional switch or as shown in FIG. Figure 1D The example shown in the figure is connected by two switches used to connect the two switches to act as a bidirectional switch.

[0031] Figure 2A and Figure 2B Schematic diagram of a two-phase interleaved HERIC topology inverter and a timing diagram showing an example output of the inverter, respectively. Figure 2A The inverter circuit 200 is described above with respect to Figure 1A Examples of DC-AC inverters 104 are described and may have the same or similar functions and features. As described above, the techniques of the present disclosure may also be beneficial to other topologies including H4, H5, single-phase HERIC topologies, and similar inverter topologies.

[0032] exist Figure 2A In the example, the controller is Figure 1AThe processing circuit system 106 may use the above Figure 1A The hybrid TCM / CCM PWM scheme described is used to control the operation of the circuit 200. The output signal from the controller can be connected to the driver of each switch of the circuit 200, such as H1_a, H2_a, L3_b and other drivers of the circuit 200. The connection with each driver is not shown to simplify the illustration.

[0033] The controller can output the maximum and minimum current I L 206 to adjust the switching frequency to achieve TCM and the desired soft switching behavior. Figure 2B 208. The specific values ​​of the minimum current I1 208 and the maximum current I2 210 depend on the selected circuit components, the application of the circuit 200, and other similar factors. Figure 2B As shown in , the minimum current I1 208 can be a fixed value and is selected to ensure ZVS when the switch is turned on. A small negative value of I1 208, such as a value less than zero but close to zero, can be desirable to ensure ZVS for switch conduction. In some examples, the small negative value can include a current in the range of -1 to -5 amperes (-1A to -5A). Figure 2B As shown in FIG. 1 , the predefined value of I2 210 varies throughout the operating cycle and can be determined based on the instantaneous value of the reference current. The curve of I2 210 can also be described as Figure 2B The triangle I shown in L 206. The variable frequency path generated by the controller ( FIG. 2A to FIG. 2B (not shown) defines Figure 2B The frequency of the PWM carrier is controlled by the P controller or PI controller using the average current control I performed by the processing circuit system AVE The 212 strategy controls the duty cycle of each switch in each operating phase individually.

[0034] exist Figure 2AIn the example of , the inverter circuit 200 includes an input terminal to receive input power from the positive terminal and the negative terminal of Vin 202. In some examples, a resistor R1 connected in series between the positive terminal of Vin 202 and the input terminal of the circuit 200 can be a modeling impedance of Vin 202. The input terminal of the circuit 200 is connected to the high side and low side of two H bridges of the "a" H bridge formed by N-channel metal oxide semiconductor field effect transistors (MOSFETs) N1, N2, N3 and N4 and the "b" H bridge formed by N7, N8, N9 and N10. The positive terminal of Vin 202 is connected to the drain of the high side N1, N2, N7 and N8 through the resistor R1. The negative terminal of Vin 202 is connected to the source of the low side transistors N3, N4, N9 and N10.

[0035] The source of N1 is connected to the drain of N3 and the source of inductor L1 and N5. The source of N2 is connected to the drain of N4 and the source of inductor L2 and N6. Transistors N5 and N6 form a bidirectional switch that is configured to disconnect the circuit 200 from the load Vout-ac 204 during a portion of the operating cycle. Similarly, the source of N7 is connected to the drain of N9 and the source of inductor L3 and N11. The source of N8 is connected to the drain of N10 and the source of inductor L4 and N12. Transistors N11 and N12 also form a bidirectional switch that is configured to disconnect the circuit 200 from the output terminal connected to Vout-ac 204 during a portion of the AC cycle. In some examples, N5 and N6 can be replaced by a single bidirectional switch. Similarly, N11 and N12 can be replaced by a single bidirectional switch.

[0036] The TCM modulation of the present disclosure enables soft switching of the bidirectional switch not only for active power mode but also for reactive power mode, which is not possible in CCM. In the case of “active” power mode, for example, at V AB is greater than zero and I OUT (For example, I L 206) is also greater than zero, then the bidirectional switch can act as a synchronous rectifier for both CCM and TCM (ZVS). In the "reactive" power mode, for example, when V AB is greater than zero and I OUT (For example, I L 206) is less than zero, the bidirectional switch may experience hard switching in CCM, but experience ZVS in TCM. Figure 2A In the example, V AB Yes V A 230-V B 232.

[0037] In operation, and as mentioned above about Figure 2A As described, circuit 200 is configured to receive DC input power Vin 202 at input terminals and output AC power at output terminals connected to a load, such as a utility grid at Vout-ac 204. Circuit 200 may receive a control signal ( Figure 2A The control signal is based at least on the instantaneous AC output current I L 206 and the instantaneous AC output voltage Vout-ac 204 to modulate the switching frequency of the inverter circuit 200. Figure 2B As shown in , the second AC output current I2 210 is the current value when each switch is turned off in ZVS and, for most of the positive AC half cycle, the magnitude of I2 210 is greater than I1 208, and for most of the negative AC half cycle, the magnitude of I2 210 is less than I1 208. As described above, the switching frequency is also based on I1 208 and the instantaneous output current I2 210. Figure 2A and Figure 2B The switching frequency in the example of may vary throughout the AC switching cycle of the inverter circuit.

[0038] Control signals are input to driver circuits, such as driver H1_a ​​connected to the gate of N1, driver H2_a connected to the gate of N2, driver L1_a connected to the gate of N3, driver L2_a connected to the gate of N4, driver H1_b connected to the gate of N7, driver H2_b connected to the gate of N8, driver L1_b connected to the gate of N9, and driver L2_b connected to the gate of N10. For a bidirectional switch arrangement, driver H3_a is connected to the gate of N5, driver L3_a is connected to the gate of N6, driver H3_b is connected to the gate of N11, and driver L3_b is connected to the gate of N12.

[0039] Figure 3 is a schematic diagram illustrating an example implementation of a control loop configured to implement a TCM / CCM hybrid modulation scheme in accordance with one or more techniques of this disclosure. Figure 3 The control loop in the example can be composed as described above about Figures 1A to 1D , Figure 2A and Figure 2B The processing circuitry of the controller for the inverter circuit described is for example Figure 1A The processing circuit system 106 is executed. Figure 3 The control in the example can be configured to be similar to the above about Figure 2A The HERIC topology described is controlled. Figure 3 The "a" and "b" parts of Figure 2AThe "a" (phase 1) part of the circuit corresponds to the "b" (phase 2) part.

[0040] The control loop may receive an input signal from the inverter circuit and output a PWM signal from the PWM generator 340 to each driver circuit. Figure 3 In the example of FIG. 3 , the input signals include a reference current i_L_ref 300 , i_L_meas_a 304 , V_ac_meas 306 , V_dc_meas 308 , and i_L_meas_b 310 . i_L_ref 300 may be divided by a constant 302 corresponding to the number of phases in the system.

[0041] Based on the received input measurements, the circuits for phase 1 duty cycle generator 320 and phase 2 duty cycle generator 322 may output the calculated duty cycles for the associated time periods of the AC cycle to PWM generator 340. The individual duty cycle modulation for each phase follows a PWM scheme based on generating an error current that is fed to a P controller or PI controller, such as P controller_a 324 and P controller_b 326.

[0042] The PWM generator 340 also receives the frequency signal from the frequency generator 330 for calculating and generating the PWM signal to control the switching of the inverter circuit. The frequency generation block 332 of the frequency generator 330 is configured to calculate the above Figure 2B The instantaneous I2 value shown in , and the equivalent frequency is defined accordingly. Figure 3 In the example of FIG. 3 , the variable frequency PWM modulator block 342 includes a voltage controlled oscillator (VCO) ( Figure 3 The variable frequency PWM modulator block 342 may also include a comparator for generating a PWM signal. Figure 2A Describe two phases, such as "a" and "b" Figure 3 In the example of FIG. 3 , the variable frequency PWM modulator block 342 may include a comparator for each phase.

[0043] Figure 4A and Figure 4B is a timing diagram illustrating an example comparison of CCM operation and TCM operation in accordance with one or more techniques of the present disclosure. Figure 4A is shown for the HERIC inverter circuit example above about Figure 2A A timing diagram for CCM operation of the depicted circuit 200. In conventional CCM operation, the switches of the HERIC will experience hard switching when turned on.

[0044] Figure 4Bis a time diagram showing TCM operation. For TCM operation, the switches of the inverter will experience soft switching, and the reduction in losses leads to improved efficiency. Figure 4B In the example, I L 406 corresponds to the above Figure 2B Description I L 206. Similarly, I1 408, I2 410 and I L-avg 412 and Figure 2B I1 208, I2 210 and I AVE 212 corresponds. Figure 4B The switching period Tsw422, i L The change of Δi L 420 and the voltage across the power switch terminals u ls 424.

[0045] As mentioned above Figures 1A to 2B As described, for the inverter circuit of the present disclosure, the controller implements TCM by selecting a fixed small negative value for I1 408 (which ensures ZVS when the switch is turned on), while the predefined value of I2 410 is based on the instantaneous value of the reference current, such as described above with respect to Figure 3 Knowing I1 and I2, the controller can determine the on-time and off-time of the switch, as well as the equivalent switching period T according to the following formula: SW 422 and the corresponding frequency of the switching cycle:

[0046]

[0047] (For H4 topology)

[0048] (For HERIC and H5 topologies)

[0049]

[0050] Where L is the value of the output inductor, for example, Figure 1A The sum of L1 and L2 described.

[0051] As described above, along the entire AC cycle, the switching frequency f of the triangular PWM carrier SW changes to achieve TCM. The operation of the inverter circuit operates in an open loop implementation. In other words, f SWThe change is made without requiring any additional ZCD (zero crossing detection) hardware, which is usually required to detect the instantaneous inductor current passing through the zero level. That is, the inverter circuit of the present disclosure does not use a ZCD circuit to maintain ZVS (soft switching).

[0052] Figure 5 is a graph showing the switching frequency variation f along the positive AC half cycle SW A timing diagram of an example of a controller for an inverter circuit such as Figure 1A The processing circuit system 106 can be based on the above Figure 4B The controller can use the formula described in Figure 3 The example controller implementation is generated by Figure 5 The switching frequency depicted in .

[0053] Fig. 6A and Figure 6B is a timing diagram illustrating example operation of a HERIC topology inverter using hybrid CCM / TCM modulation. Fig. 6A and Figure 6B The example is based on the above Figure 2A and Figure 3 The two interleaved phases described, where the average current for each phase is such as Figure 2B I AVE 212 control, the power factor (PF) is controlled in the range from 0 to 1, and has an output power of 6 kilowatts (kW). Fig. 6A and Figure 6B The example uses example values ​​and settings to illustrate the operation of the control technique of the present disclosure. Other values ​​and settings may also be used, such as an output power (Pout) other than 6 kW.

[0054] Inductor currents I_L1 506, I_L3 508, and I_tot 510 are respectively related to the above Figure 2A The current through L1, L3 and I L 206 corresponds to. Output current I out 504 is also related to I L 206 corresponds to Vout 504. Figure 2A Vout-ac 204 and Figure 1A The inductor current I_L1 506 and I_L3 508 are Figure 6B The total current I_tot 510 is partially overlapped in the middle because they have a 180° phase shift. Figure 6B In the region indicated by 510 of FIG. 5, a controller for the inverter causes the switching frequency to be set to approximately 70 kHz. Figure 6B In the region indicated by 514 in the positive half cycle of Figure 5 f SW changes.

[0055] Fig. 7A and Figure 7B It is shown Figure 6B An example of a time map shown in FIG. 1 is a time map of a zoomed-in region. Fig. 7A The example represents the Figure 6B The inductor currents I_L1 602, I_L3 604 and I_tot 606 correspond to the 70kHz switching frequency region indicated by 512. Figure 6B I_L1 506, I_L3 508 and I_tot 510.

[0056] Figure 7B The example represents the Figure 6B Similarly, I_L1 608, I_L3 610, and I_tot 612 correspond to the 290kHz switching frequency region indicated by 514. Figure 6B I_L1 506, I_L3 508 and I_tot 510.

[0057] Fig. 8A and Figure 8B is a timing diagram showing an example operation of a HERIC topology inverter using hybrid CCM / TCM modulation for a power factor of 1. The use of the hybrid TCM / CCM modulation scheme of the present disclosure ensures that the ZVS condition can be achieved over almost the entire AC cycle, thereby achieving higher efficiency and power density. Figure 8B and Fig.8D In the example of FIG. 1 , the region indicated by 706 is a region where a controller for the inverter may operate in CCM mode and may include some hard switching during switch on time.

[0058] In other words, depending on the phase angle between the current and the voltage, the controller can cause the inverter to operate in one of several modes within the AC cycle. In the first mode, the power factor can be 1 or close to 1. A power factor of 1 indicates that the voltage and current are in phase and have low harmonic content. A power factor of zero indicates that the voltage and current are 90 degrees out of phase. In some examples, such as Figure 8B and Fig.8D As shown in , during reactive power delivery (where voltage and current are out of phase), the switch may lose the ZVS condition for a small portion of the AC cycle. In examples where voltage and current are in phase throughout the AC cycle, the inverter circuit can operate in ZVS at every operating point in the AC cycle. In other examples, such as Figure 8B and Fig.8D As shown in , the inverter circuit can operate in a mode in which there is at least some hard switching (706). Thus, in at least one of the several different operating modes, the inverter circuit operates with ZVS switching of at least all four switches.

[0059] With the above Figure 6B Similarly, the inductor currents I_L1, I_L3 and I_tot correspond to Figure 6B I_L1 506, I_L3 508 and I_tot 510. Output current I OUT 704 also corresponds to I L 206, and Vout 702 and Figure 2A Vout-ac 204 and Figure 1A The output voltage V AC-OUT 112 corresponds.

[0060] Figure 8C and Fig.8D is a timing diagram showing an example operation of a HERIC topology inverter using hybrid CCM / TCM modulation for a power factor of zero. The power converter of the present disclosure is configured to operate for any PF (from 0 to 1), thereby enabling control of apparent power even when the power to be controlled is completely reactive.

[0061] Fig. 9 is a flow chart showing an example operation of a HERIC topology inverter using hybrid CCM / TCM modulation of the present disclosure. Figure 1A and Figure 2A To describe Fig. 9 The steps are shown in the box.

[0062] The processing circuitry 106 for the DC-AC inverter circuit 104 of the system 100 may receive the DC input power V received at the input terminals 120 and 122 of the DC-AC inverter circuit 104. DC 102. In some examples, processing circuit system 106 may use a voltage divider ( Figure 1A ) or any other technique to sense V DC 102 to determine V DC 102.

[0063] In some examples, processing circuit system 106 may also receive AC power V at output terminals 124 and 126 of inverter circuit 104. AC-OUT 112 is an indication of the instantaneous magnitude (92). In other examples, the processing circuit system may also include a direct connection to V AC-OUTInstead of sensing the output current and voltage through inductors L1 110 and L2 108 , the output current and voltage can be sensed by connecting inductor 112 .

[0064] Processing circuit system 106 can also, for example, Figure 2A The driver of each switch described will control the signal ( Figure 1A or Figure 2A ) is transmitted to each switch (94) of the inverter circuit 104. In some examples, the DC-AC inverter circuit 104 may include at least four switches, such as Figure 1B The H4 topology shown in Figure 1D and Figure 2A The HERIC topology shown in Figure 1C The H5 topology shown in .

[0065] The processing circuit system 106 may be as described above with respect to Figure 5 The described method modulates the switching frequency of the inverter circuit via the control signal (96). The processing circuit system 106 can be based on the instantaneous AC output current, such as the above respectively related to Figure 2A and Figure 2B , Figure 4A and Fig. 6A Description I L 206、I L 406 and Itot 510 to determine the switching frequency. Figure 4B As described, the processing circuit system 106 can determine the output current I L The peak values ​​of I2 410 and I L The difference ΔI between the predetermined minimum value I1 of 406 and the predetermined minimum value I2 of 408 L The absolute value of 420. Figure 4B The processing circuit system 106 may also calculate the instantaneous AC output voltage at the output terminal and the time T of the switch being turned on in the AC cycle based on the formula described above. on and the time T during which the switch is turned off in the AC cycle off To determine the switching frequency f SW The processing circuitry 106 may therefore modulate the switching frequency so that each switch is switched on with zero voltage, eg, soft switching.

[0066] In one or more examples, the functions described above can be implemented in hardware, software, firmware, or any combination thereof. Figure 1A The various components of the can be implemented in hardware, software, firmware or any combination thereof. If implemented in software, the functions can be stored in a tangible computer-readable storage medium such as Figure 1AThe processing is performed on the memory 114 of the processor or hardware-based processing unit such as the processing circuit system 106.

[0067] Instructions may be executed by one or more processors, such as one or more digital signal processors (DSPs), general-purpose microprocessors, application-specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), or other equivalent integrated or discrete logic circuit systems. Therefore, the terms "processor" and "processing circuit system" used herein may refer to any of the aforementioned structures or any other structure suitable for the implementation of the techniques described herein. In addition, these techniques may be fully implemented in one or more circuits or logic elements.

[0068] The technology of the present disclosure can be implemented in a variety of devices or apparatuses including an integrated circuit (IC) or a group of ICs (e.g., a chipset). Various components, modules, or units are described in the present disclosure to emphasize the functional aspects of the devices configured to perform the disclosed technology, but the various components, modules, or units do not necessarily need to be implemented by different hardware units. On the contrary, as described above, the various units can be combined in a hardware unit or provided by a collection of interoperable hardware units including one or more processors as described.

[0069] The technology of the present disclosure may also be described in the following clauses.

[0070] Item 1: An inverter circuit comprising an input terminal, an output terminal, and at least four switches, the inverter circuit being configured to receive a direct current (DC) input power at the input and to output an alternating current (AC) output power at the output terminal; and receiving a control signal from a controller, the controller comprising a processing circuit system, wherein the control signal modulates a switching frequency of the inverter circuit based at least on an instantaneous AC output current and an instantaneous AC output voltage at the output terminal, wherein the switching frequency is also based on a predetermined first AC output current, wherein, for at least one operating mode, the predetermined first AC output current causes each switch to be configured to turn on with zero voltage switching (ZVS).

[0071] Clause 2: An inverter circuit according to clause 1, wherein, for the inverter circuit, a switching frequency varies throughout an AC switching cycle; wherein the switching frequency is also based on a second AC output current during the AC switching cycle, wherein the second AC output current is a current value when each switch is turned off, and wherein the magnitude of the second AC output current is greater than the first AC output current.

[0072] Clause 3: An inverter circuit according to any one of clauses 1 and 2, wherein the output terminal comprises a first output terminal and a second output terminal, and wherein the controller is configured to determine a time (T on ), wherein the controller is configured to determine T according to the following formula on :

[0073]

[0074] Wherein: L represents the sum of the inductance of the first inductor connected to the first output terminal of the output terminals and the inductance of the second inductor connected to the second output terminal of the output terminals, I1 represents the instantaneous magnitude of the first AC output current, I2 represents the instantaneous magnitude of the second AC output current, V IN Indicates the voltage of DC input power, V AC Indicates the instantaneous voltage of AC output power.

[0075] Clause 4: The inverter circuit of clause 3, wherein the inverter circuit comprises switches arranged in a High Efficiency and Reliable Inverter Concept (HERIC) topology, wherein the controller is configured to determine a time (T) to turn off a first switch of the at least four switches. off ), wherein the controller is configured to determine T according to the following formula off :

[0076]

[0077] Clause 5: An inverter circuit according to clause 4, wherein the switching frequency (f SW ):

[0078]

[0079] Clause 6: The inverter circuit of any of clauses 1 to 5, wherein during an AC switching cycle of the AC output power, the controller is configured to modulate a switching frequency to enable conduction of the AC output power with a current offset between the first AC output current and the second AC output current.

[0080] Clause 7: The inverter circuit of clause 6, wherein the controller is configured to apply a triangular carrier signal to modulate the variation of the switching frequency.

[0081] Clause 8: An inverter circuit according to any one of clauses 1 to 7, wherein the controller is configured to modulate the switching frequency without regard to zero crossing detection (ZCD) measurements.

[0082] Item 9: An inverter system comprising: a processing circuit system configured to output a control signal; and an inverter circuit comprising an input terminal, an output terminal and at least four switches, the inverter circuit being configured to: receive direct current (DC) input power at the input terminal and output alternating current (AC) output power at the output terminal; and receive a control signal from the processing circuit system, wherein the control signal modulates a switching frequency of the inverter circuit based at least on an instantaneous AC output current and an instantaneous AC output voltage at the output terminal, wherein the switching frequency is also based on a predetermined first AC output current, wherein, for at least one operating mode, the predetermined first AC output current causes each switch to be configured to be turned on with zero voltage switching (ZVS).

[0083] Clause 10: An inverter system according to clause 9, wherein, for the inverter circuit, the switching frequency varies throughout the AC switching cycle; wherein the switching frequency is also based on a second AC output current during the AC switching cycle, wherein the second AC input current is the current value when each switch is turned off, and wherein the second AC output current is greater in magnitude than the first AC output current.

[0084] Clause 11: The inverter system of any of clauses 9 and 10, wherein the processing circuit system is configured to determine a time (T on ), wherein the processing circuit system is configured to determine T according to the following formula on :

[0085]

[0086] Where: L is the sum of the inductance of a first inductor connected to a first one of the output terminals and the inductance of a second inductor connected to a second one of the output terminals, I1 is the instantaneous magnitude of the first AC output current, I2 is the instantaneous magnitude of the second AC output current, V IN is the voltage of the DC input power, V AC It is the instantaneous voltage of the AC output power.

[0087] Clause 12: An inverter system according to any of clauses 9 to 11, wherein the inverter circuit comprises switches arranged in a High Efficiency and Reliable Inverter Concept (HERIC) topology, wherein the processing circuit system is configured to determine a time (T) to turn off a first switch of the at least four switches. off ), wherein the processing circuit system is configured to determine T according to the following formula off :

[0088]

[0089] Clause 13: An inverter system according to clause 12, wherein the switching frequency is determined by the following formula:

[0090]

[0091] Clause 14: The inverter system of any of clauses 9 to 13, wherein during an AC switching cycle of the AC output power, the processing circuitry is configured to modulate a switching frequency to enable conduction of the AC output power with a current offset between the first AC output current and the second AC output current.

[0092] Clause 15: The inverter system of clause 14, wherein the processing circuitry is configured to apply a triangular carrier signal to modulate the variation of the switching frequency.

[0093] Clause 16: An inverter system as recited in any one of clauses 9 to 15, wherein the processing circuitry is configured to modulate the switching frequency without regard to zero crossing detection (ZCD) measurements.

[0094] Item 17: A method for controlling an inverter circuit, comprising: receiving, by a processing circuit system, an indication of the magnitude of a direct current (DC) input power received at an input terminal of the inverter circuit; receiving, by the processing circuit system, an indication of the instantaneous magnitude of an alternating current (AC) output power at an output terminal of the inverter circuit; transmitting, by the processing circuit system, a control signal to each switch of the inverter circuit, wherein the inverter circuit comprises at least four switches; modulating, by the processing circuit system, a switching frequency of the inverter circuit by means of the control signal, wherein the switching frequency is based at least on an instantaneous AC output current and an instantaneous AC output voltage at the output terminal, and such that, for at least one operating mode, each switch is configured to be turned on with zero voltage switching (ZVS).

[0095] Clause 18: The method of clause 17, further comprising determining a time (T on ), wherein the processing circuit system is configured to determine T according to the following formula on :

[0096]

[0097] Where: L is the sum of the inductance of a first inductor connected to a first one of the output terminals and the inductance of a second inductor connected to a second one of the output terminals, I1 is the instantaneous magnitude of the first AC output current, I2 is the instantaneous magnitude of the second AC output current, V IN is the voltage of the DC input power, V AC It is the instantaneous voltage of the AC output power.

[0098] Clause 19: The method of clause 18, wherein the inverter circuit comprises switches arranged in a High Efficiency and Reliable Inverter Concept (HERIC) topology, the method further comprising determining a time (T off ), wherein the processing circuit system is configured to determine T according to the following formula off :

[0099]

[0100] And the switching frequency is determined according to the following formula:

[0101]

[0102] Clause 20: The method of any of clauses 17 to 19, wherein the inverter circuit is configured to receive DC input power from the photovoltaic cell and output AC output power to a grid.

[0103] Various examples of the disclosure have been described. These and other examples are within the scope of the following claims.

Claims

1. An inverter circuit comprising an input terminal, an output terminal and at least four switches, wherein the inverter circuit is configured to: receiving direct current (DC) input power at the input terminals and outputting alternating current (AC) output power at the output terminals; and A control signal is received from a controller, the controller including processing circuitry, wherein: The control signal modulates a switching frequency of the inverter circuit based at least on an instantaneous AC output current and an instantaneous AC output voltage at the output terminal, wherein the switching frequency is further based on a predetermined first AC output current, wherein, for at least one operating mode, the predetermined first AC output current causes each switch to be configured to conduct with zero voltage switching (ZVS).

2. The inverter circuit according to claim 1, in, For the inverter circuit, the switching frequency varies throughout the AC switching cycle, wherein the switching frequency is also based on a second AC output current during the AC switching period, wherein the second AC output current is the current value when each switch is turned off, and The second AC output current is larger than the first AC output current.

3. The inverter circuit according to claim 1, wherein: The output terminals include a first output terminal and a second output terminal, and wherein the controller is configured to determine a time T for turning on a first switch of the at least four switches. on , wherein the controller is configured to determine T according to the following formula on : in: L represents the sum of a first inductance connected to the first output terminal and a second inductance connected to the second output terminal, I1 represents the instantaneous magnitude of the first AC output current, I2 represents the instantaneous magnitude of the second AC output current, V IN represents the voltage of the DC input power, and V AC Indicates the instantaneous voltage magnitude of the AC output power.

4. The inverter circuit according to claim 3, in, The inverter circuit comprises switches arranged in a highly efficient and reliable inverter concept HERIC topology, and The controller is configured to determine a time T of turning off a first switch among the at least four switches. off , wherein the controller is configured to determine T according to the following formula off :

5. The inverter circuit according to claim 4, wherein: The switching frequency f is defined according to the following formula SW :

6. The inverter circuit according to claim 1, wherein: During an AC switching cycle of the AC output power, the controller is configured to modulate the switching frequency to enable conduction of the AC output power with a current offset between the first AC output current and a second AC output current.

7. The inverter circuit according to claim 6, wherein: The controller is configured to apply a triangular carrier signal to modulate changes in the switching frequency.

8. The inverter circuit according to claim 1, wherein: The controller is configured to modulate the switching frequency and to override zero crossing detection (ZCD) measurements.

9. An inverter system, comprising: processing circuitry configured to output a control signal; as well as An inverter circuit comprising an input terminal, an output terminal and at least four switches, the inverter circuit being configured to: receiving direct current (DC) input power at the input terminal and outputting alternating current (AC) output power at the output terminal; as well as The control signal is received from the processing circuit system, wherein the control signal modulates a switching frequency of the inverter circuit based at least on an instantaneous AC output current and an instantaneous AC output voltage at the output terminal, wherein the switching frequency is further based on a predetermined first AC output current, wherein, for at least one operating mode, the predetermined first AC output current causes each switch to be configured to conduct with zero voltage switching (ZVS).

10. The inverter system according to claim 9, in, For the inverter circuit, the switching frequency varies throughout the AC switching cycle, wherein the switching frequency is further based on a second AC output current during the AC switching period, wherein the second AC output current is the current value when each switch is turned off, and The second AC output current is larger than the first AC output current.

11. The inverter system according to claim 9, wherein: The processing circuit system is configured to determine a time T for turning on a first switch of the at least four switches. on , wherein the processing circuit system is configured to determine T according to the following formula on : in: L is the sum of the inductance of a first inductor connected to a first one of the output terminals and the inductance of a second inductor connected to a second one of the output terminals, I1 is the instantaneous magnitude of the first AC output current, I2 is the instantaneous magnitude of the second AC output current, V IN is the voltage magnitude of the DC input power, and V AC is the instantaneous voltage magnitude of the AC output power.

12. The inverter system according to claim 11, in, The inverter circuit comprises switches arranged in a highly efficient and reliable inverter concept HERIC topology, and The processing circuit system is configured to determine a time T of turning off a first switch of the at least four switches. off , wherein the processing circuit system is configured to determine T according to the following formula off :

13. The inverter system according to claim 12, wherein: The switching frequency f is determined by the following formula: SW :

14. The inverter system according to claim 9, wherein: During an AC switching cycle of the AC output power, the processing circuitry is configured to modulate the switching frequency to enable conduction of the AC output power with a current offset between the first AC output current and a second AC output current.

15. The inverter system according to claim 14, wherein: The processing circuitry is configured to apply a triangular carrier signal to modulate variations in the switching frequency.

16. The inverter system according to claim 9, wherein: The processing circuitry is configured to modulate the switching frequency without regard to a zero crossing detection (ZCD) measurement.

17. A method for controlling an inverter circuit, the method comprising: receiving, by processing circuitry, an indication of a magnitude of direct current (DC) input power received at an input terminal of the inverter circuit; receiving, by the processing circuitry, an indication of an instantaneous magnitude of alternating current (AC) output power at an output terminal of the inverter circuit; transmitting, by the processing circuitry, a control signal to each switch of the inverter circuit, wherein the inverter circuit comprises at least four switches; and A switching frequency of the inverter circuit is modulated by the processing circuit system via the control signal, wherein the switching frequency is based on at least an instantaneous AC output current and an instantaneous AC output voltage at the output terminal, and such that for at least one operating mode, each switch is configured to conduct with zero voltage switching (ZVS).

18. The method according to claim 17, further comprising: Determine the time T for turning on the first switch of the at least four switches on , wherein the processing circuit system is configured to determine T according to the following formula on : in: L is the sum of the inductance of a first inductor connected to a first one of the output terminals and the inductance of a second inductor connected to a second one of the output terminals, I1 is the instantaneous magnitude of the first AC output current, I2 is the instantaneous magnitude of the second AC output current, V IN is the voltage magnitude of the DC input power, and V AC is the instantaneous voltage magnitude of the AC output power.

19. The method according to claim 18, wherein: The inverter circuit includes switches arranged in a highly efficient and reliable inverter concept HERIC topology, the method further comprising: Determine the time T for turning off the first switch of the at least four switches off , wherein the processing circuit system is configured to determine T according to the following formula off : And the switching frequency is determined according to the following formula:

20. The method according to claim 17, wherein: The inverter circuit is configured to receive the DC input power from a photovoltaic cell and output the AC output power to a grid.

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