Piecewise linear ramp compensation circuit for switching power supply

Abstract

The present application is about a piecewise linear ramp compensation circuit for a switching power supply, and relates to the technical field of integrated circuit design. The circuit includes a square wave generating circuit, a capacitor charging and discharging network circuit, a voltage regulating circuit, and a ramp current generating circuit; the square wave generating circuit, the capacitor charging and discharging network circuit, the voltage regulating circuit, and the ramp current generating circuit are connected in sequence. The circuit adopts a piecewise linear ramp compensation method, which reduces the degree of decrease in the peak current of the circuit caused by the duty cycle while eliminating the subharmonic oscillations generated by the peak current mode control, thereby improving the load carrying capacity of the switching power supply. While ensuring the simplicity of the circuit structure, the required reference signal can be generated by dividing the reference voltage input by the oscillator, thereby ensuring the operation stability of the switching power supply during the control process.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit design, and in particular to a piecewise linear ramp compensation circuit of a switching power supply. Background Art

[0002] When the switching power supply is working normally, the external output voltage needs to be compared with the internal reference voltage through feedback to stabilize the output level. The control methods for switching power supplies mainly include pulse width modulation (PWM) control, pulse frequency modulation (PFM) control and pulse skip modulation (PSM) control. Among them, the PWM voltage control mode compares the feedback of the output voltage with the internal reference through the error amplifier, and then uses the comparator signal to control the pulse width of the PWM modulator output signal to adjust the output level.

[0003] Regarding PWM control technology, various control structures have been proposed in the related art to improve the control mode. Response speed is one of the important indicators currently pursued by DC-DC converters. Since the response speed of the voltage-controlled PWM modulation mode is slow, it is impossible to feedback the load changes in time, which will lead to the problem of poor load regulation. In this case, the related art also established a current mode PWM control mechanism.

[0004] However, when current mode PWM control is adopted, harmonic oscillation will be introduced when the duty cycle is greater than 50%, which reduces the operating stability of the switching power supply during the control process. Summary of the invention

[0005] The present application relates to a piecewise linear ramp compensation circuit of a switching power supply, which can improve the operating stability of the switching power supply during the control process when the switching circuit is adjusted using current mode PWM control. The piecewise linear ramp compensation circuit of the switching power supply includes a square wave generating circuit, a capacitor charging and discharging network circuit, a voltage regulating circuit, and a ramp current generating circuit;

[0006] The square wave generating circuit, the capacitor charging and discharging network circuit, the voltage regulating circuit and the ramp current generating circuit are connected in sequence;

[0007] The square wave generating circuit includes a first comparator and a second comparator; the negative side of the first comparator is connected to a low reference voltage power supply, and the positive side is connected to a first sawtooth wave signal generating circuit; the negative side of the second comparator is connected to a high reference voltage power supply, and the positive side is connected to a second sawtooth wave signal generating circuit;

[0008] The capacitor charging and discharging network circuit includes a first PMOS tube, a second PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a first capacitor, a second capacitor and a third capacitor; the first PMOS tube is connected to the gate end of the second PMOS tube, the drain end of the second PMOS tube forms a loop with the first PMOS tube, the first NMOS tube, the second NMOS tube, the fifth NMOS tube and the third capacitor, and the source end of the first PMOS tube is connected to the power supply; the gate end of the first NMOS tube is connected to the output end of the first comparator, the source end of the first NMOS tube is connected to the first capacitor and the third NMOS tube; the gate end of the second NMOS tube is connected to the output end of the second comparator, the source end of the second NMOS tube is connected to the second capacitor and the fourth NMOS tube; the third NMOS tube is connected in parallel with the first capacitor, the fourth NMOS tube is connected in parallel with the second capacitor, and the fifth NMOS tube is connected in parallel with the third capacitor; the source end of the first capacitor, the second capacitor, the third capacitor, the source end of the third NMOS tube, the source end of the fourth NMOS tube and the source end of the fifth NMOS tube are grounded;

[0009] The voltage adjustment circuit includes a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube and a ninth NMOS tube; the gate ends of the third PMOS tube and the fourth PMOS tube are connected to the gate end of the second PMOS tube, the drain end of the third PMOS tube is connected to the drain end of the sixth NMOS tube, the drain end of the sixth PMOS tube is connected to the drain end of the seventh NMOS tube, the gate end of the third PMOS tube is opposite to the gate end of the seventh NMOS tube; the drain end of the fourth NMOS tube is connected to the drain end of the sixth NMOS tube , the drain end of the fifth NMOS tube is connected to the drain end of the seventh NMOS tube; the sixth NMOS tube and the seventh NMOS tube are grounded; the source end of the sixth NMOS tube is connected to the drain end of the eighth NMOS tube, the source end of the eighth NMOS tube and the gate end of the ninth NMOS tube; the source end of the seventh NMOS tube is connected to the drain end of the ninth NMOS tube; the source ends of the eighth NMOS tube and the ninth NMOS tube are grounded; the gate end of the fifth PMOS tube is connected to the drain ends of the first NMOS tube and the second NMOS tube, and the drain end of the fifth PMOS tube is connected to the source end of the seventh NMOS tube;

[0010] The ramp wave generating circuit includes a resistor, a sixth PMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor and a thirteenth NMOS transistor;

[0011] The gate terminal of the sixth PMOS tube is connected to the drain terminal of the fourth PMOS tube, the source terminal of the sixth PMOS tube is connected to the power supply, the drain terminal of the sixth PMOS tube is connected to the source terminal of the fifth PMOS tube and one end of the resistor; the other end of the resistor is connected to the drain terminal of the tenth NMOS tube, the source terminal of the tenth NMOS tube, the drain terminal of the thirteenth NMOS tube and the gate terminal of the eleventh NMOS tube; the gate terminal of the thirteenth NMOS tube is connected to the square wave signal with a duty cycle of 1 / 2, the source terminal of the thirteenth NMOS tube is connected to the gate terminal and the drain terminal of the twelfth NMOS tube, and the source terminal of the twelfth NMOS tube, the source terminal of the tenth NMOS tube and the source terminal of the eleventh NMOS tube are grounded.

[0012] In an optional embodiment, the output terminals of the first comparator and the second comparator are square wave signals with different duty cycles.

[0013] In an optional embodiment, the gate terminals of the first PMOS tube and the second PMOS tube are connected to form a current mirror.

[0014] In an optional embodiment, the fifth PMOS transistor is implemented as a source follower transistor, and the first PMOS transistor, the second PMOS transistor, the third PMOS transistor and the fourth PMOS transistor are implemented as current mirror transistors.

[0015] In an optional embodiment, the capacitance values ​​of the first capacitor, the second capacitor, and the third capacitor form a proportional relationship.

[0016] In an optional embodiment, the capacitance ratio of the first capacitor, the second capacitor and the third capacitor is determined by the duty cycle of the square wave output by the first NMOS transistor and the second NMOS transistor.

[0017] The beneficial effects of the technical solution provided by this application include at least:

[0018] The circuit adopts the method of piecewise linear ramp compensation, which eliminates the subharmonic oscillation generated by the peak current mode control, reduces the degree of decrease of the peak current of the circuit caused by the duty cycle, and improves the load capacity of the switching power supply. While ensuring the simplicity of the circuit structure, the required reference signal can be generated by the oscillator input reference voltage division, thereby making the operation stability of the switching power supply during the control process. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0020] Figure 1A schematic structural diagram of a piecewise linear ramp compensation circuit of a switching power supply provided by an exemplary embodiment of the present application is shown.

[0021] Figure 2 A schematic diagram of an inductor current during harmonic oscillation provided by an exemplary embodiment of the present application is shown.

[0022] Figure 3 A schematic diagram of the inductor current when ramp compensation is performed in the related art is shown.

[0023] Figure 4 The figure shows a schematic diagram of the structure of the clock generation circuit used in the present application.

[0024] Figure 5 A schematic diagram comparing the effects of a ramp compensation provided by an exemplary embodiment of the present application is shown. DETAILED DESCRIPTION

[0025] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0026] Figure 1 FIG. 1 is a schematic diagram showing a structure of a piecewise linear ramp compensation circuit of a switching power supply provided by an exemplary embodiment of the present application. Please refer to FIG. Figure 1 The piecewise linear ramp compensation circuit of the switching power supply includes a square wave generating circuit 110, a capacitor charging and discharging network circuit 120, a voltage adjusting circuit 130 and a ramp current generating circuit 140. The square wave generating circuit 110, the capacitor charging and discharging network circuit 120, the voltage adjusting circuit 130 and the ramp current generating circuit 140 are connected in sequence. The square wave generating circuit 110 includes a first comparator 111 and a second comparator 112; the negative direction of the first comparator 111 is connected to a low reference voltage power supply 113, and the positive direction is connected to a first sawtooth wave signal generating circuit, and the negative direction of the second comparator is connected to a high reference voltage power supply 114, and the positive direction is connected to a second sawtooth wave signal generating circuit. In the embodiment of the present application, the specific form of the sawtooth wave signal generating circuit can be referred to. Figure 4 shown.

[0027] The capacitor charging and discharging network circuit 120 includes a first PMOS tube 121, a second PMOS tube 122, a first NMOS tube 123, a second NMOS tube 124, a third NMOS tube 125, a fourth NMOS tube 126, a fifth NMOS tube 127, a first capacitor 128, a second capacitor 129 and a third capacitor 1210; the first PMOS tube is connected to the gate end of the second PMOS tube, the drain end of the second PMOS tube forms a loop with the first PMOS tube, the first NMOS tube, the second NMOS tube, the fifth NMOS tube and the third capacitor, and the source end of the first PMOS tube is connected to the gate end of the second PMOS tube. The power supply is terminated; the gate end of the first NMOS tube is connected to the output end of the first comparator, and the source end of the first NMOS tube is connected to the first capacitor and the third NMOS tube; the gate end of the second NMOS tube is connected to the output end of the second comparator, and the source end of the second NMOS tube is connected to the second capacitor and the fourth NMOS tube; the third NMOS tube is connected in parallel with the first capacitor, the fourth NMOS tube is connected in parallel with the second capacitor, and the fifth NMOS tube is connected in parallel with the third capacitor; the first capacitor, the second capacitor, the third capacitor, the source end of the third NMOS tube, the source end of the fourth NMOS tube, and the source end of the fifth NMOS tube are grounded.

[0028] The voltage regulating circuit 130 includes a third PMOS tube 131, a fourth PMOS tube 132, a fifth PMOS tube 133, a sixth NMOS tube 134, a seventh NMOS tube 135, an eighth NMOS tube 136 and a ninth NMOS tube 137; the gate ends of the third PMOS tube and the fourth PMOS tube are connected to the gate end of the second PMOS tube, the drain end of the third PMOS tube is connected to the drain end of the sixth NMOS tube, the drain end of the sixth PMOS tube is connected to the drain end of the seventh NMOS tube, the gate end of the third PMOS tube is opposite to the gate end of the seventh NMOS tube; the drain end of the fourth NMOS tube is connected to the drain end of the sixth NMOS tube. The drain end of the sixth NMOS tube is connected, the drain end of the fifth NMOS tube is connected to the drain end of the seventh NMOS tube; the sixth NMOS tube and the seventh NMOS tube are grounded; the source end of the sixth NMOS tube is connected to the drain end of the eighth NMOS tube, the source end of the eighth NMOS tube and the gate end of the ninth NMOS tube; the source end of the seventh NMOS tube is connected to the drain end of the ninth NMOS tube; the source ends of the eighth NMOS tube and the ninth NMOS tube are grounded; the gate end of the fifth PMOS tube is connected to the drain ends of the first NMOS tube and the second NMOS tube, and the drain end of the fifth PMOS tube is connected to the source end of the seventh NMOS tube.

[0029] The ramp wave generating circuit 140 includes a resistor 141, a sixth PMOS tube 142, a tenth NMOS tube 143, an eleventh NMOS tube 144, a twelfth NMOS tube 145 and a thirteenth NMOS tube 146; the gate end of the sixth PMOS tube is connected to the drain end of the fourth PMOS tube, the source end of the sixth PMOS tube is connected to the power supply, the drain end of the sixth PMOS tube is connected to the source end of the fifth PMOS tube and one end of the resistor; the other end of the resistor is connected to the drain end of the tenth NMOS tube, the source end of the tenth NMOS tube, the drain end of the thirteenth NMOS tube and the gate end of the eleventh NMOS tube; the gate end of the thirteenth NMOS tube is connected to the square wave signal with a duty cycle of 1 / 2, the source end of the thirteenth NMOS tube is connected to the gate end and the drain end of the twelfth NMOS tube, and the source end of the twelfth NMOS tube, the source end of the tenth NMOS tube and the source end of the eleventh NMOS tube are grounded.

[0030] In summary, the circuit provided in the embodiment of the present application adopts a piecewise linear ramp compensation method, which eliminates the subharmonic oscillation generated by the peak current mode control, reduces the degree of decrease in the peak current of the circuit caused by the duty cycle, and improves the load capacity of the switching power supply. While ensuring the simplicity of the circuit structure, the required reference signal can be generated by dividing the oscillator input reference voltage, thereby ensuring the operation stability of the switching power supply during the control process.

[0031] In an optional embodiment, the output terminals of the first comparator and the second comparator are square wave signals with different duty cycles.

[0032] In an optional embodiment, the gate terminals of the first PMOS tube and the second PMOS tube are connected to form a current mirror.

[0033] In an optional embodiment, the fifth PMOS tube is implemented as a source follower tube, and the first PMOS tube, the second PMOS tube, the third PMOS tube and the fourth PMOS tube are implemented as current mirror tubes. For the fifth PMOS tube, its source terminal voltage follows its gate terminal voltage. For the sixth PMOS tube, it is a supply tube for ramp current and the current of the fifth PMOS tube. In the embodiment of the present application, the size of the third PMOS tube is twice the size of the fourth PMOS tube, and the size of the eighth NMOS tube is the same as the size of the ninth NMOS tube, so as to ensure that a fixed current flows through the fifth PMOS tube, and its source terminal voltage follows the gate terminal voltage change.

[0034] In an optional embodiment, the capacitance values ​​of the first capacitor, the second capacitor, and the third capacitor form a proportional relationship. Optionally, the capacitance value ratio of the first capacitor, the second capacitor, and the third capacitor is determined by the duty cycle of the square wave output by the first NMOS tube and the second NMOS tube, so as to ensure that the switching power supply system does not cause subharmonic oscillation under any clock duty cycle.

[0035] Next, in combination with the relevant theories of switching power supplies, the process of determining the capacitance ratio of the first capacitor, the second capacitor, and the third capacitor of the piecewise linear ramp compensation circuit described in the present application is described:

[0036] According to the relevant theory of switching power supply, for the switching power supply with peak current mode control, the system sets the maximum peak current that the inductor current can reach. When the switch tube is turned on, the current across the inductor cannot change suddenly, and the current begins to rise linearly. When it reaches the limit value, it begins to decrease. For the step-down switching power supply, when the output voltage exceeds half of the input voltage, the clock duty cycle exceeds 50%. Please refer to Figure 2 , which shows that the disturbance amount that occurs when the duty cycle exceeds 50% increases with the period. The schematic diagram corresponding to the ramp compensation method in the related art is as follows Figure 3 As shown, by making the peak current have a certain downward trend, the disturbance is reduced with the cycle. To ensure that the disturbance is reduced at any duty cycle, the ratio of current to time, that is, the slope is often very large, resulting in a serious decrease in the peak current value with the duty cycle, affecting the system's load capacity.

[0037] Combination Figure 3 As shown in the content, when the inductor current falling slope is added, the ratio of the current disturbance after one cycle can be expressed by the following formula:

[0038]

[0039]

[0040] In the formula, ΔI1 indicates the small disturbance of the inductor current caused by errors, ΔI2 indicates the change of ΔI1 after one cycle, m1 indicates the charging slope of the inductor current when the switch is turned on, m2 indicates the inductor discharge current slope, and m3 indicates the compensation current slope. D indicates the duty cycle. It should be noted that the meaning of the above parameter representation also applies to Figure 2 In content.

[0041] According to the above formula, when the slope of the compensation current is greater than half of the slope of the inductor discharge current, the system will not have subharmonic oscillations at any duty cycle D, but the peak current will drop seriously with the duty cycle. Currents with different slopes can be used in different duty cycle segments to reduce the loss of peak current with the duty cycle. Since subharmonic oscillations will not occur when the duty cycle is less than 50%, the circuit does not need compensation. Therefore, for the embodiment of the present application, segments are set at the three-point points of the second half of the cycle, that is, the duty cycle is one-third and five-sixths. It is calculated that the required slope at the duty cycle of two-thirds is half of the maximum compensation slope, and the compensation slope at the duty cycle of five-sixths is four-fifths of the maximum compensation slope. Therefore, the ratio of the first capacitor, the second capacitor and the third capacitor is set to 3:1:4, which can eliminate subharmonic oscillations at any duty cycle.

[0042] In this case, please refer to Figure 4 , which is a circuit structure schematic diagram of the RC oscillator used in the switching power supply in the related technology. The circuit can output a square wave signal with a duty cycle of 50% and two sawtooth wave signals with different phases. The sawtooth wave signal in the second half of the cycle is sent to the reverse input terminal of the comparator, and the reference voltages of one-third and two-thirds of the peak voltage of the sawtooth wave are respectively input to the positive input terminal, so that frequency signals with duty cycles of two-thirds and five-sixths can be obtained.

[0043] Figure 5 This is a comparison diagram of the compensation current variation with period of general ramp compensation and the compensation current with the piecewise linear harmonic compensation circuit shown in the present application. Referring to the compensation curve 510 of the general ramp compensation and the corresponding compensation curve 520 of the present application, it can be seen that the circuit shown in the embodiment of the present application has a smaller current value. In this case, the peak current decreases less with the duty cycle, and the load carrying capacity of the system at a high duty cycle is enhanced.

[0044] The above are only optional embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A piecewise linear ramp compensation circuit for a switching power supply, characterized in that: The circuit includes a square wave generating circuit, a capacitor charging and discharging network circuit, a voltage regulating circuit and a ramp current generating circuit; The square wave generating circuit, the capacitor charging and discharging network circuit, the voltage regulating circuit and the ramp current generating circuit are connected in sequence; The square wave generating circuit includes a first comparator and a second comparator; the negative side of the first comparator is connected to a low reference voltage power supply, and the positive side is connected to a sawtooth wave signal generating circuit; the negative side of the second comparator is connected to a high reference voltage power supply, and the positive side is connected to the sawtooth wave signal generating circuit; The capacitor charging and discharging network circuit includes a first PMOS tube, a second PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a first capacitor, a second capacitor and a third capacitor; the first PMOS tube is connected to the gate end of the second PMOS tube, the drain end of the second PMOS tube forms a loop with the first PMOS tube, the first NMOS tube, the second NMOS tube, the fifth NMOS tube and the third capacitor, and the source end of the first PMOS tube is connected to a power supply; the gate end of the first NMOS tube is connected to the output end of the first comparator, the source end of the first NMOS tube is connected to the first capacitor and the third NMOS tube; the gate end of the second NMOS tube is connected to the output end of the second comparator, the source end of the second NMOS tube is connected to the second capacitor and the fourth NMOS tube; the third NMOS tube is connected in parallel with the first capacitor, the fourth NMOS tube is connected in parallel with the second capacitor, and the fifth NMOS tube is connected in parallel with the third capacitor; The first capacitor, the second capacitor, the third capacitor, the source end of the third NMOS tube, the source end of the fourth NMOS tube, and the source end of the fifth NMOS tube are grounded; The voltage adjustment circuit includes a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube and a ninth NMOS tube; the gate ends of the third PMOS tube and the fourth PMOS tube are connected to the gate end of the second PMOS tube, the drain end of the third PMOS tube is connected to the drain end of the sixth NMOS tube, the drain end of the sixth NMOS tube is connected to the drain end of the seventh NMOS tube, the gate end of the third PMOS tube is opposite to the gate end of the seventh NMOS tube; the drain end of the fourth NMOS tube is connected to the drain end of the sixth NMOS tube, The drain end of the fifth NMOS tube is connected to the drain end of the seventh NMOS tube; the sixth NMOS tube and the seventh NMOS tube are grounded; the source end of the sixth NMOS tube is connected to the drain end of the eighth NMOS tube, the source end of the eighth NMOS tube and the gate end of the ninth NMOS tube; the source end of the seventh NMOS tube is connected to the drain end of the ninth NMOS tube; the source ends of the eighth NMOS tube and the ninth NMOS tube are grounded; the gate end of the fifth PMOS tube is connected to the drain ends of the first NMOS tube and the second NMOS tube, and the drain end of the fifth PMOS tube is connected to the source end of the seventh NMOS tube; The ramp current generating circuit includes a resistor, a sixth PMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor and a thirteenth NMOS transistor; The gate end of the sixth PMOS tube is connected to the drain end of the fourth PMOS tube, the source end of the sixth PMOS tube is connected to a power supply, the drain end of the sixth PMOS tube is connected to the source end of the fifth PMOS tube and one end of the resistor; the other end of the resistor is connected to the drain end of the tenth NMOS tube, the source end of the tenth NMOS tube, the drain end of the thirteenth NMOS tube and the gate end of the eleventh NMOS tube; the gate end of the thirteenth NMOS tube is connected to a square wave signal with a duty cycle of 1 / 2, the source end of the thirteenth NMOS tube is connected to the gate end and the drain end of the twelfth NMOS tube, and the source end of the twelfth NMOS tube, the source end of the tenth NMOS tube and the source end of the eleventh NMOS tube are grounded.

2. The piecewise linear ramp compensation circuit of the switching power supply according to claim 1, characterized in that: The output ends of the first comparator and the second comparator are square wave signals with different duty cycles.

3. The piecewise linear ramp compensation circuit of the switching power supply according to claim 1, characterized in that: The gate terminals of the first PMOS tube and the second PMOS tube are connected to form a current mirror.

4. The piecewise linear ramp compensation circuit of the switching power supply according to claim 1, characterized in that: The fifth PMOS tube is implemented as a source follower tube, and the first PMOS tube, the second PMOS tube, the third PMOS tube and the fourth PMOS tube are implemented as current mirror tubes.

5. The piecewise linear ramp compensation circuit of the switching power supply according to claim 1, characterized in that: The capacitance values ​​of the first capacitor, the second capacitor and the third capacitor form a proportional relationship.

6. The piecewise linear ramp compensation circuit of the switching power supply according to claim 5, characterized in that: The capacitance ratio of the first capacitor, the second capacitor and the third capacitor is determined by the duty cycle of the square wave output by the first NMOS tube and the second NMOS tube.

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