A terminal impedance matching adjustment system

Abstract

The present invention discloses a terminal impedance matching adjustment system. The impedance matching network inputs an impedance matching target value and an impedance matching control signal, and adjusts the magnitude of the parallel resistor in the impedance matching network according to the impedance matching control signal to match the target value, thereby realizing the impedance adjustment function. The high-speed comparator compares the impedance matching state level with the reference level generated by the voltage division module, and outputs the comparison result to the impedance matching control signal generation module. The impedance matching control signal generation module generates a comparator control signal to the high-speed comparator, generates an impedance matching control signal to the impedance matching network and the port driver circuit, and generates a latch signal to output to the port driver circuit. The port driver circuit adjusts its own impedance according to the impedance matching control signal and the latch signal to achieve the expected impedance matching effect. The present invention can realize two impedance matching adjustment modes, namely manual and automatic, has high flexibility and applicability, and can be widely applied to various transmission line terminal devices.

Description

Technical Field

[0001] The present invention relates to the technical field of electrical circuits, and particularly relates to a terminal impedance matching adjustment system. Background Art

[0002] With the continuous increase of signal rate, the requirement for signal integrity in high-frequency signal transmission is also getting higher and higher. In the high-frequency field, signal reflection is the main factor affecting signal integrity in a single signal network. When the signal wavelength and the transmission line length are in the same order of magnitude, the reflected signal is prone to aliasing with the original signal, affecting the signal quality. The reflection phenomenon generated when the signal encounters a connection node, a load change, or a connection terminal on the transmission line, and part of the energy will be reflected in the opposite direction of the propagation direction. Signal reflection may cause phenomena such as overshoot, ringing, and jitter of the original signal.

[0003] Suppose a high-frequency signal propagates from left to right along a transmission line to a certain node. Due to some reason, the transient impedance changes, and part of the energy will be reflected in the opposite direction of the propagation direction. The magnitude of the reflected energy is determined by the characteristic impedance difference between the two regions on the left and right sides of the node. Let Vi be the incident voltage, Vr be the reflected voltage, Vo be the output voltage, Z1 represent the impedance of the region on the left side of the node, and Z2 represent the impedance of the region on the right side of the node. The reflection coefficient ρ is:

[0004]

[0005] According to Kirchhoff's current law:

[0006]

[0007] The transmission coefficient T is obtained:

[0008]

[0009] It can be seen from the above formulas that when the difference between Z1 and Z2 is larger, the reflection coefficient is larger, the reflected voltage is larger, and the final output voltage is smaller. Only when Z1 = Z2, the reflection coefficient is 0, and the transmission coefficient is 1, which means that no signal reflection occurs, that is, the impedance matching state. In the impedance matching state, the signal transmission power can be maximized, and the energy conversion performance can be improved; the signal reflection in the circuit can be reduced, and the signal quality and transmission efficiency can be improved; the signal can be stably transmitted in the system, and signal distortion and performance degradation can be avoided.

[0010] In high-speed PCB design, digital signal traces are regarded as having uniform characteristic impedance. Therefore, the most likely node to have signal reflection is the connection between the transmission line and the end device port. Therefore, if the end device of the transmission line is equipped with the ability to adjust impedance matching so that it can match the transmission line, the signal integrity problem caused by signal reflection can be effectively solved. Summary of the Invention

[0011] The object of the present invention is to provide a terminal impedance matching adjustment system to solve the problems in the background art.

[0012] To solve the above technical problems, the present invention provides a terminal impedance matching adjustment system, including an impedance matching network, a voltage division module, a high-speed comparator, an impedance matching control signal generation module, and a port drive circuit;

[0013] The impedance matching network inputs an impedance matching target value and an impedance matching control signal, and adjusts the magnitude of the parallel resistors in the impedance matching network according to the impedance matching control signal to match the impedance matching target value, realizing the impedance adjustment function;

[0014] The voltage division module generates a fixed reference level to the high-speed comparator through resistor voltage division;

[0015] The high-speed comparator compares the impedance matching state level and the reference level, and outputs the comparison result to the impedance matching control signal generation module;

[0016] The impedance matching control signal generation module generates a comparator control signal to the high-speed comparator according to the comparison result, generates an impedance matching control signal to the impedance matching network and the port drive circuit, and generates a latch signal output to the port drive circuit;

[0017] The port drive circuit adjusts its own impedance according to the impedance matching control signal and the latch signal generated by the impedance matching control signal generation module, realizing the expected impedance matching effect.

[0018] In one embodiment, the impedance matching network includes a PMOS impedance matching network and an NMOS impedance matching network;

[0019] The PMOS impedance matching network includes PMOS transistors PM1 to PM28, resistors R2, R3, and fourteen resistors R1; wherein the first ends of resistor R2 and resistor R3 are commonly connected to the output terminal OUT, and the second ends of resistor R2 and resistor R3 are commonly grounded; the sources of PMOS transistors PM1 to PM28 are all connected to the power supply VDD; the drains of every two adjacent PMOS transistors in PMOS transistors PM1 to PM28 are commonly connected to the output terminal OUT through a resistor R1; the output terminal OUT is connected to the high-speed comparator;

[0020] The NMOS impedance matching network includes NMOS transistors NM1 to NM28, resistors R5, R6, and fourteen resistors R4. The first ends of resistor R5 and resistor R6 are commonly connected to VDD, and the second ends of resistor R5 and resistor R6 are commonly connected to the output terminal OUT. The source electrodes of NMOS transistors NM1 to NM28 are all connected to the ground GND. The drain electrodes of every two adjacent NMOS transistors among NMOS transistors NM1 to NM28 are commonly connected to the output terminal OUT through a resistor R4. The output terminal OUT is connected to a high-speed comparator.

[0021] In an embodiment, the high-speed comparator includes a PMOS high-speed comparator and an NMOS high-speed comparator, which have the same structure and are respectively composed of PMOS transistors PM29 to PM32, NMOS transistors NM29 to NM33, capacitors C1 to C2, inverters INV1 to INV2, and NAND gates NAND1 to NAND2.

[0022] The source electrodes of PMOS transistors PM29 to PM32 are all connected to the power supply VDD. The gate and drain of PMOS transistor PM29 are connected together and connected to the drain of PMOS transistor PM30. The gate and drain of PMOS transistor PM32 are connected together and connected to the drain of PMOS transistor PM31. The gate of PMOS transistor PM30 is connected to the drain of PMOS transistor PM31, and the gate of PMOS transistor PM31 is connected to the drain of PMOS transistor PM30. The gate of NMOS transistor NM31 is connected to the drain of NMOS transistor NM32, and the source of NMOS transistor NM31 is connected to the drain of NMOS transistor NM29. The gate of NMOS transistor NM32 is connected to the drain of NMOS transistor NM31, and the source of NMOS transistor NM32 is connected to the drain of NMOS transistor NM30. The sources of NMOS transistor NM29 and NMOS transistor NM30 are commonly connected to the drain of NMOS transistor NM33. The gate of NMOS transistor NM29 is connected to the input pin VM, and the gate of NMOS transistor NM30 is connected to the input pin VP. The gate of NMOS transistor NM33 is connected to the input pin VREF, and the drain is connected to the ground GND.

[0023] The drain of PMOS transistor PM30 is connected to the first terminal of capacitor C1, and the drain of PMOS transistor PM31 is connected to the first terminal of capacitor C2; the second terminals of capacitor C1 and capacitor C2 are both connected to the drain of NMOS transistor NM33; the first terminal of capacitor C1 is connected to the input terminal of inverter INV1, and the first terminal of capacitor C2 is connected to the input terminal of inverter INV2; the output terminal of inverter INV1 is connected to the first input terminal of NAND gate NAND1, and the output terminal of inverter INV2 is connected to the first input terminal of NAND gate NAND2; the output terminal of NAND gate NAND1 is connected to the second input terminal of NAND gate NAND2, and the output terminal of NAND gate NAND2 is connected to the second input terminal of NAND1; the output terminal of NAND gate NAND1 is taken as the output of the high-speed comparator and sent to the impedance matching control signal generation module.

[0024] In one embodiment, the impedance matching control signal generation module includes two modes: manual adjustment and automatic adjustment;

[0025] During manual adjustment, the relevant circuits for automatic impedance matching are bypassed, and the latch signal and the impedance matching control signal are manually configured in sequence;

[0026] During automatic adjustment, the relevant circuits mainly consist of a presetable multi-bit counter and control logic, and this counter is multiplexed in the order of first adjusting the PMOS impedance matching network and then adjusting the NMOS impedance matching network; the impedance matching control signal generation module generates an impedance matching control signal to the impedance matching network and the port driving circuit according to the output result of the high-speed comparator, generates a comparator control signal to the high-speed comparator, and synchronously outputs a latch signal to the port driving circuit after the adjustment is completed.

[0027] In one embodiment, the port driving circuit includes PMOS transistors PM33~PM60, NMOS transistors NM34~NM61, 14 resistors R7, and control modules Ctrl1 and Ctrl2;

[0028] The sources of PMOS transistors PM33~PM60 are all connected to power supply VDD; the sources of NMOS transistors NM34~NM60 are all connected to ground GND;

[0029] The drains of every two adjacent PMOS transistors among PMOS transistors PM33~PM60 are connected to the drains of every two adjacent NMOS transistors among NMOS transistors NM34~NM60, and they are commonly connected to the output terminal DATA_OUT through a resistor R7;

[0030] After the impedance matching control signal generation module completes the impedance adjustment, it inputs the impedance matching control signal and the latch signal into control modules Ctrl1 and Ctrl2 at the same time, and the impedance matching control signal is C PMOS[4:0] with C NMOS [4:0], the latch signal is L PMOS and L NMOS ; the latch signal L PMOS controls the control module Ctrl1 to latch the impedance matching control signal C PMOS [4:0], outputs CP[4:0], controls the data input DATA_IN to the PMOS impedance matching network, and the high potential in the data is driven and output through the PMOS impedance matching network; the latch signal L NMOS controls the control module Ctrl2 to latch the impedance matching control signal C NMOS [4:0], outputs CN[4:0], controls the data input DATA_IN to the NMOS impedance matching network, and the low potential in the data is driven and output through the NMOS impedance matching network, and finally adjusts the number of parallel resistors to achieve the effect of impedance matching.

[0031] A terminal impedance matching adjustment system provided by the present invention has the following beneficial effects:

[0032] (1) It can be realized by ordinary PMOS and NMOS transistors in the CMOS process and standard cells in the digital cell library, with a simple structure and easy to promote;

[0033] (2) Adopting a high-speed comparator, it can quickly obtain the comparison result, the impedance matching adjustment process is rapid, and the result is reliable;

[0034] (3) The data path parts used for the adjustment of PMOS and NMOS are partially multiplexed, which can save the layout area;

[0035] (4) The impedance matching control has two adjustment modes: automatic and manual, and impedance matching can be achieved in different hardware environments, with high flexibility and applicability, and can be widely applied to various transmission line terminal devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 is a schematic structural diagram of the terminal impedance matching adjustment system provided by the present invention.

[0037] Figure 2 is a schematic structural diagram of the NMOS impedance matching network provided by the present invention.

[0038] Figure 3 is a schematic structural diagram of the PMOS impedance matching network provided by the present invention.

[0039] Figure 4 is a schematic structural diagram of the voltage dividing module provided by the present invention.

[0040] Figure 5 is a schematic circuit diagram of the high-speed comparator provided by the present invention.

[0041] Figure 6 It is a schematic working process diagram of the impedance matching control signal generation module provided by the present invention.

[0042] Figure 7 It is a schematic structural diagram of the port drive output circuit provided by the present invention. Detailed implementation manners

[0043] The following further elaborates in detail on a terminal impedance matching adjustment system proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise scales, only for the purpose of conveniently and clearly assisting in explaining the embodiments of the present invention.

[0044] The present invention provides a terminal impedance matching adjustment system, as Figure 1As shown in the figure, it includes an impedance matching network, a voltage dividing module, a high-speed comparator, an impedance matching control signal generation module, and a port driving circuit. The impedance matching network includes a PMOS impedance matching network and an NMOS impedance matching network, and the high-speed comparator includes a PMOS high-speed comparator and an NMOS high-speed comparator. The PMOS impedance matching target value and the PMOS impedance matching control signal are input to the PMOS impedance matching network, and the NMOS impedance matching target value and the NMOS impedance matching control signal are input to the NMOS impedance matching network; the PMOS impedance matching network outputs the PMOS impedance matching state level to the PMOS high-speed comparator, and the NMOS impedance matching network outputs the NMOS impedance matching state level to the NMOS high-speed comparator. The voltage dividing module generates a fixed reference level through resistor voltage division and outputs it to the PMOS high-speed comparator and the NMOS high-speed comparator. The PMOS high-speed comparator is used to compare the PMOS impedance matching state level and the fixed reference level generated by the voltage dividing module, and the NMOS high-speed comparator is used to compare the NMOS impedance matching state level and the fixed reference level generated by the voltage dividing module; the PMOS high-speed comparator and the NMOS high-speed comparator output the comparison results to the impedance matching control signal generation module. The impedance matching control signal generation module generates a PMOS high-speed comparator control signal and an NMOS high-speed comparator control signal according to the comparison results and outputs them to the PMOS high-speed comparator and the NMOS high-speed comparator respectively to control their working states, and generates a PMOS impedance matching control signal and outputs it to the PMOS impedance matching network and the port driving circuit, generates an NMOS impedance matching control signal and outputs it to the NMOS impedance matching network and the port driving circuit, and synchronously generates a PMOS latch signal and an NMOS latch signal and outputs them to the port driving circuit after the adjustment is completed. The port driving circuit adjusts its own impedance according to the PMOS impedance matching control signal, the NMOS impedance matching control signal, the PMOS latch signal, and the NMOS latch signal, and finally achieves the expected impedance matching effect.

[0045] Analysis of the impedance matching network: Input the impedance matching target value and the 5-bit impedance matching control signal generated by the impedance matching control signal generation module. Adjust the size of the parallel resistors in the impedance matching network according to the 5-bit impedance matching control signal to match the target value, so as to achieve the impedance adjustment function.

[0046] Figure 2 is a schematic structural diagram of the NMOS impedance matching network. The NMOS impedance matching network consists of two parts, the upper part is an adjustable resistor network, which is configured by the user, and eight impedance selections can be realized through the three-bit control signal Q[2:0]; the lower part is an adaptive impedance adjustment network composed of 28 NMOS transistors (NM1~NM28) and 14 resistors R4. Each resistor R4 is connected to two NMOS transistors, such as Figure 2There are a total of five control signals C[4:0] generated by the impedance matching control signal generation module. Among them, control signal C[0] controls an NMOS transistor and a resistor, control signal C[1] controls two NMOS transistors and a resistor, control signal C[2] controls four NMOS transistors and a resistor, control signal C[3] controls seven NMOS transistors and a resistor, and control signal C[4] controls all NMOS transistors and a resistor. By controlling with different signals, stepless adjustment of 0 to 14 resistors in parallel can be achieved. For example, if 8 resistors are required to be in parallel, the control signal should be C[4:0]=01001. Figure 3 is a schematic diagram of the structure of the PMOS impedance matching network, and its circuit structure and principle are the same as those of the NMOS impedance matching network adjustment circuit.

[0047] Analysis of the voltage division module: As Figure 4 shown, a fixed level is generated through resistor voltage division and used as a reference level for judging whether the impedance matching adjustment is completed. Its voltage magnitude is half of the power supply voltage VDD.

[0048] Analysis of the comparator: As Figure 5 shown, this structure is a high-speed comparator, including a PMOS high-speed comparator and an NMOS high-speed comparator. The two have the same structure and are mainly composed of a comparison stage and a latch output stage. Among them, the gates of NMOS transistors NM29 and NM30 are the two input ports VP and VM of the comparator. The gates of NMOS transistors NM31 and NM32 are cross-connected to each other's drains. The sources of NMOS transistors NM31 and NM32 are respectively connected to the drains of input transistors NM29 and NM30; the gates of PMOS transistors PM30 and PM31 are cross-connected to each other's drains. The drains of PMOS transistors PM30 and PM31 are respectively connected to the drains of NMOS transistors NM31 and NM32 to form positive feedback, enabling the potentials at points A and B to change rapidly, thus enabling the function of high-speed comparison. PMOS transistors PM29 and PM32 are connected in diode configuration (drain connected to the gate, source connected to the power supply) to shunt current, making the voltage change range at points A and B larger. Capacitors C1 and C2 are filter capacitors. Two NAND gates NAND1 and NAND2 are cross-connected to form a latch structure and together with inverters INV1 and INV2 constitute the output stage of the comparator. The function of this comparator is to compare the magnitudes of the impedance matching state level and the reference level. If the two levels are different, the comparison result is determined to be high level; if the two levels are the same, the comparison result is determined to be low level.

[0049] Analysis of the impedance matching control signal generation module: The working process of this module is as Figure 6As shown: The impedance matching control signal has two modes: manual adjustment and automatic adjustment. When manually adjusting the impedance matching control signal, the relevant circuits for automatic impedance matching are bypassed. The latch signals of PMOS and NMOS need to be manually configured in sequence. After configuring the PMOS latch signal, manually configure the PMOS impedance matching control signal, and the port driver circuit can latch the current PMOS impedance matching control signal. Repeat the same operation process for the manual adjustment of NMOS impedance matching to complete the manual configuration of the impedance matching control signal.

[0050] The logic main body for automatically adjusting the impedance matching control signal is a presetable multi-bit counter. Specifically, assuming the number of bits of the counter is n, then there are a total of 2 n - 1 gears. It should be noted that the impedance matching control signal cannot be all 0, otherwise the port driver circuit cannot drive the output. Reuse this counter in the order of adjusting PMOS first and then NMOS, so as to save the layout area. When the automatic impedance matching adjustment starts, first manually set the impedance matching target values of PMOS and NMOS as the input signals of the impedance matching network. This target value is equivalent to the characteristic impedance value of the transmission line that can match the port driver circuit in this system. The counter starts counting from 1, and the initial value of the impedance matching control signal is 1. Then judge the level state of the comparator signal generated by the PMOS high-speed comparator in the analog circuit and sent to the impedance matching control signal generation module. If it is judged to be high level, it means that the adjustment result of the impedance network in the analog circuit has not been matched yet and needs to be adjusted continuously, so the counter increments by one. At the same time, generate a comparator control signal and feedback it to the PMOS high-speed comparator module to make it continue to work. Judge the updated PMOS high-speed comparator signal value again. Repeat the above operations until the comparator signal is judged to be low level, which indicates that the adjustment result of the impedance network in the analog circuit has been matched. At this time, generate a comparator control signal and feedback it to the PMOS high-speed comparator to make it stop working. In addition, generate a PMOS latch signal and send it together with the five-bit impedance matching control signal to the port driver circuit. The port driver circuit uses the PMOS latch signal to latch the current impedance matching control signal, thus realizing the configuration of the PMOS impedance matching network in the port driver circuit. After completing the PMOS impedance matching, start the NMOS impedance matching adjustment, and the counter is reset to 1. Then repeat the above-mentioned judgment and operation process to realize the configuration of the NMOS impedance network and complete the automatic configuration of the impedance matching control signal.

[0051] Analysis of the port driver circuit: The port driver circuit adjusts its own impedance according to the impedance matching control signal and the latch signal, and finally realizes the expected impedance matching effect. The structure of the port driver circuit is as Figure 7As shown. The PMOS network in the upper part is consistent with the above PMOS impedance matching network, and the NMOS network in the lower part is consistent with the N-type impedance matching network. The principle is that after the impedance matching control signal generation module completes impedance adjustment, it inputs the control signal and the latch signal into the control modules Ctrl1 and Ctrl2 of the port matching circuit at the same time. The control signal is C PMOS [4:0] and C NMOS [4:0], and the latch signal is L PMOS and L NMOS . L PMOS controls the Ctrl1 module to latch the C PMOS [4:0] control signal, outputs CP[4:0], controls the data input DATA_IN to the PMOS impedance matching network, and the high potential in the data is driven and output through the PMOS impedance matching network in the upper part. L NMOS controls the Ctrl2 module to latch the C NMOS [4:0] control signal, outputs CN[4:0], controls the data input DATA_IN to the NMOS impedance matching network, and the low potential in the data is driven and output through the NMOS impedance matching network in the lower part. Finally, the number of parallel resistors is adjusted to achieve the effect of impedance matching.

[0052] The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention according to the above disclosure are within the scope of protection of the claims.

Claims

1. A terminal impedance matching adjustment system, characterized in that: It includes an impedance matching network, a voltage divider module, a high-speed comparator, an impedance matching control signal generation module and a port driving circuit; The impedance matching network inputs an impedance matching target value and an impedance matching control signal, and adjusts the size of the parallel resistance in the impedance matching network according to the impedance matching control signal to match the impedance matching target value, thereby realizing an impedance adjustment function; The voltage division module generates a fixed reference level to the high-speed comparator through resistor voltage division; The high-speed comparator compares the impedance matching state level with the reference level, and outputs the comparison result to the impedance matching control signal generating module; The impedance matching control signal generating module generates a comparator control signal to the high-speed comparator according to the comparison result, generates an impedance matching control signal to the impedance matching network and the port driving circuit, and generates a latch signal to output to the port driving circuit; The port driving circuit adjusts its own impedance according to the impedance matching control signal and the latch signal generated by the impedance matching control signal generating module to achieve the expected impedance matching effect; The impedance matching network includes a PMOS impedance matching network and an NMOS impedance matching network; The PMOS impedance matching network includes PMOS tubes PM1-PM28, resistors R2, R3 and fourteen resistors R1; wherein the first end of the resistor R2 and the first end of the resistor R3 are connected to the output terminal OUT, and the second end of the resistor R2 and the second end of the resistor R3 are grounded; the source electrodes of the PMOS tubes PM1-PM28 are connected to the power supply VDD; the drain electrodes of every two adjacent PMOS tubes in the PMOS tubes PM1-PM28 are connected to the output terminal OUT through a resistor R1; the output terminal OUT is connected to the high-speed comparator; The NMOS impedance matching network includes NMOS tubes NM1~NM28, resistors R5, R6 and fourteen resistors R4; wherein the first end of the resistor R5 and the first end of the resistor R6 are commonly connected to VDD, and the second end of the resistor R5 and the second end of the resistor R6 are commonly connected to the output terminal OUT; the source electrodes of the NMOS tubes NM1~NM28 are all connected to the ground GND; the drain electrodes of every two adjacent NMOS tubes in the NMOS tubes NM1~NM28 are commonly connected to the output terminal OUT through a resistor R4; and the output terminal OUT is connected to a high-speed comparator.

2. The terminal impedance matching adjustment system according to claim 1, characterized in that: The high-speed comparator includes a PMOS high-speed comparator and an NMOS high-speed comparator, both of which have the same structure and are respectively composed of PMOS tubes PM29-PM32, NMOS tubes NM29-NM33, capacitors C1-C2, inverters INV1-INV2 and NAND gates NAND1-NAND2; The sources of PMOS tubes PM29 to PM32 are all connected to the power supply VDD, the gate of PMOS tube PM29 is connected to its own drain and to the drain of PMOS tube PM30; the gate of PMOS tube PM32 is connected to its own drain and to the drain of PMOS tube PM31; the gate of PMOS tube PM30 is connected to the drain of PMOS tube PM31, and the gate of PMOS tube PM31 is connected to the drain of PMOS tube PM30; the gate of NMOS tube NM31 is connected to the drain of NMOS tube NM32, and the gate of NMOS tube NM The source of NMOS tube NM31 is connected to the drain of NMOS tube NM29; the gate of NMOS tube NM32 is connected to the drain of NMOS tube NM31, and the source of NMOS tube NM32 is connected to the drain of NMOS tube NM30; the source of NMOS tube NM29 and the source of NMOS tube NM30 are connected to the drain of NMOS tube NM33; the gate of NMOS tube NM29 is connected to the input pin VM, and the gate of NMOS tube NM30 is connected to the input pin VP; the gate of NMOS tube NM33 is connected to the input pin VREF, and the drain is connected to the ground GND; The drain of the PMOS tube PM30 is connected to the first end of the capacitor C1, and the drain of the PMOS tube PM31 is connected to the first end of the capacitor C2; the second end of the capacitor C1 and the second end of the capacitor C2 are both connected to the drain of the NMOS tube NM33; the first end of the capacitor C1 is connected to the input end of the inverter INV1, and the first end of the capacitor C2 is connected to the input end of the inverter INV2; the output end of the inverter INV1 is connected to the first input end of the NAND gate NAND1, and the output end of the inverter INV2 is connected to the first input end of the NAND gate NAND2; the output end of the NAND gate NAND1 is connected to the second input end of the NAND gate NAND2, and the output end of the NAND gate NAND2 is connected to the second input end of NAND1; the output end of the NAND gate NAND1 is taken as the output of the high-speed comparator and sent to the impedance matching control signal generation module.

3. The terminal impedance matching adjustment system according to claim 2, characterized in that: The impedance matching control signal generation module includes two modes: manual adjustment and automatic adjustment; During manual adjustment, the relevant circuits for automatic impedance matching are bypassed, and the latch signal and impedance matching control signal are manually configured in sequence; During automatic adjustment, the relevant circuit is mainly composed of a multi-bit counter that can be set and control logic. The counter is reused in the order of adjusting the PMOS impedance matching network first and then adjusting the NMOS impedance matching network; the impedance matching control signal generation module generates an impedance matching control signal to the impedance matching network and the port drive circuit according to the output result of the high-speed comparator, generates a comparator control signal to the high-speed comparator, and synchronously outputs a latch signal to the port drive circuit after the adjustment is completed.

4. The terminal impedance matching adjustment system according to claim 3, characterized in that: The port driving circuit includes PMOS tubes PM33-PM60, NMOS tubes NM34-NM61, 14 resistors R7, and control modules Ctrl1 and Ctrl2; The sources of the PMOS tubes PM33 to PM60 are all connected to the power supply VDD; the sources of the NMOS tubes NM34 to NM60 are all connected to the ground GND; The drains of every two adjacent PMOS tubes in the PMOS tubes PM33 to PM60 and the drains of every two adjacent NMOS tubes in the NMOS tubes NM34 to NM60 are connected, and are connected to the output terminal DATA_OUT through a resistor R7; After the impedance matching control signal generation module completes the impedance adjustment, the impedance matching control signal and the latch signal are simultaneously input to the control modules Ctrl1 and Ctrl2. The impedance matching control signal is and , the latch signal is and ; Latch signal Control module Ctrl1 latches impedance matching control signal , output , control data input DATA_IN to the PMOS impedance matching network, the high potential in the data is driven output through the PMOS impedance matching network; latch signal Control module Ctrl2 latches impedance matching control signal , output , control the data input DATA_IN to the NMOS impedance matching network, the low potential in the data is driven output through the NMOS impedance matching network, and finally the number of resistors in parallel is adjusted to achieve the impedance matching effect.

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