Circuit device of digital filter

Abstract

The invention provides a digital filter circuit device. The circuit device comprises at least one storage circuit, at least one multiplication and addition circuit, at least one addition circuit, a first data selection circuit, a second data selection circuit and a third data selection circuit, the first data selection circuit inputs discrete digital signals; the storage circuit stores discrete digital signals and filter coefficients; the multiplication and addition circuit performs multiplication and addition operation on the discrete digital signal and the filter coefficient according to a preset corresponding relation, determines a multiplication and addition result and inputs the multiplication and addition result into the second data selection circuit; the second data selection circuit and the third data selection circuit gate corresponding data paths according to a configuration mode and perform input and output, and the addition circuit is used for adding an output signal of the second data selection circuit and an output signal of the third data selection circuit and outputting a filtering result corresponding to the configuration mode. According to the invention, different filter functions can be realized, and the application flexibility of the digital filter is improved.

Description

Technical Field

[0001] The present application belongs to the technical field of digital signal processing, and in particular, relates to a circuit device of a digital filter. Background Art

[0002] Since the 21st century, the information and communication industry has entered a new stage of development. Signal processing technology has become an important part of the communication field. Digital filtering technology, as an indispensable key technology, has been studied. Digital filters are devices that apply digital filtering technology. They process signals through mathematical operations to attenuate or amplify them. They are mainly used in the processing of digital signals. According to the characteristics of the impulse response of digital filters in the time domain, they can be divided into two categories, namely, finite impulse response filters (FIR) and infinite impulse response filters (IIR).

[0003] FIR digital filter is a basic filter element in the field of digital signal processing. Its characteristic is that it can ensure that the phase-frequency characteristics of the output digital signal still maintain a strict linear relationship after inputting a digital signal with arbitrary amplitude-frequency characteristics. FIR digital filter is a filter with strong stability, no feedback structure and easy hardware implementation. At the same time, it satisfies the coefficient symmetry, and the signal after filtering is not prone to phase distortion. Therefore, it has been widely used in the field of information transmission and digital image processing. However, the filtering process of FIR digital filter requires a long operation time, and only when the order of FIR digital filter reaches several to ten times that of IIR digital filter, its amplitude response characteristics can be comparable to IIR digital filter.

[0004] The characteristic of IIR digital filter is that the impulse response of the system is infinite, and its output depends not only on the input values ​​of the current and past signals, but also on the output values ​​of the past signals. According to the mathematical expression of IIR digital filter, it can be seen that IIR digital filter has a feedback structure, and the filtered signal will have phase distortion problem, but IIR digital filter has higher filtering efficiency and can achieve similar frequency response effect with a smaller order than FIR digital filter. The characteristic of IIR digital filter is that the amplitude-frequency characteristic is good, but the output signal is not strictly linear. Therefore, IIR digital filter is suitable for occasions where the signal phase requirement is not strict, such as voice calls, low-end video signal processing and other fields.

[0005] Therefore, it is extremely important for the development of digital filters to provide a circuit device that can simultaneously meet the functions of an FIR digital filter and an IIR digital filter to be suitable for different application scenarios. Summary of the invention

[0006] The present application discloses a circuit device of a digital filter, which can be configured with different filter types and select data paths of corresponding filters to realize corresponding filter functions and improve the flexibility of digital filter application.

[0007] Other purposes and advantages of the present application can be further understood from the technical features disclosed in the present application.

[0008] To achieve one or part or all of the above purposes or other purposes, the present application provides a digital filter circuit device, the circuit device comprising at least one storage circuit, at least one multiplication and addition circuit, at least one addition circuit, and a first data selection circuit, a second data selection circuit, and a third data selection circuit; the first data selection circuit is connected to the storage circuit and is used to input a discrete digital signal; the storage circuit is used to store the discrete digital signal and the filter coefficient; the multiplication and addition circuit is connected between the storage circuit and the second data selection circuit, and the multiplication and addition circuit is used to perform multiplication and addition operations on the discrete digital signal and the filter coefficient according to a preset corresponding relationship, determine the multiplication and addition result and input it into the second data selection circuit; The adding circuit is connected to the second data selection circuit and the third data selection circuit respectively. The second data selection circuit and the third data selection circuit are used to select the corresponding data path and perform input and output according to the configuration mode. The adding circuit is used to add the output signal of the second data selection circuit and the output signal of the third data selection circuit, and output the filtering result corresponding to the configuration mode.

[0009] In one implementation, the three data selection circuits each include an A terminal and a B terminal for inputting a signal and a Z terminal for outputting a signal, and when the configuration mode is the FIR mode, the three data selection circuits all select the A terminal signal; The input signal of the A terminal of the first data selection circuit is a discrete digital signal, the input signal of the A terminal of the second data selection circuit is a multiplication-addition result, and the input signal of the A terminal of the third data selection circuit is 0.

[0010] In one implementation, the expression of the filtering result in the FIR mode is: ; Among them, x(ni) is the discrete digital signal sequence of the sampled input, h(i) is the FIR filter coefficient, y(n) is the filter output signal sequence, L is the filter order, MUX2 Z The Z terminal output signal of the second data selection circuit, MUX3 Z The Z terminal of the third data selection circuit outputs a signal.

[0011] In one implementation, the three data selection circuits each include an A terminal and a B terminal for input signals and a Z terminal for output signals. When the configuration mode is the IIR mode, the circuit device is composed of a first circuit device and a second circuit device. The three data selection circuits of the first circuit device all select the A terminal signal, and the three data selection circuits of the second circuit device all select the B terminal signal.

[0012] In one implementation, the filtering result of the first circuit device is used as the B-end input signal of the third data selection circuit of the second circuit device, and the filtering result of the second circuit device is used as the B-end input signal of the first data selection circuit of the second circuit device.

[0013] In one implementation, the first circuit device is loaded with a first filter coefficient, and the second circuit device is loaded with a second filter coefficient, wherein the number of the second filter coefficient is one less than the number of the first filter coefficient.

[0014] In one implementation, the signal value at the B terminal of the second data selection circuit of the second circuit device is the inverse of the signal value at the A terminal of the second data selection circuit of the second circuit device, and the expression of the filtering result in the IIR mode is: ; Where x(n) is the discrete digital signal sequence of the sampled input, y(n) is the filter output signal sequence, a(i) is the filter coefficient related to the input signal sequence, b(i) is the filter coefficient related to the filtering result, L is the filter order, y nume(n) is the filtering result of the first circuit device, DENO MUX2B It is the signal value of the B terminal of the second data selection circuit of the second circuit device.

[0015] In one implementation, the circuit device switches different configuration modes through registers to achieve different filtering effects; in different configuration modes, a corresponding number of storage circuits, multiplication and addition circuits, and addition circuits are set according to the filter order corresponding to the configuration mode.

[0016] In one implementation, the storage circuit includes a signal storage circuit for storing the discrete digital signal and a coefficient storage circuit for storing the filter coefficient.

[0017] In one implementation, the multiplication and addition circuit includes a multiplier and an adder, the multiplier is connected to the signal storage circuit and the coefficient storage circuit, the multiplier multiplies the discrete digital signal and the filter coefficient according to a preset corresponding relationship to obtain a multiplication result, and the adder adds the multiplication results to obtain a multiplication and addition result.

[0018] The above-mentioned digital filter circuit device can switch different configuration modes, select the data path of the corresponding filter, load the corresponding filter coefficients, and can switch different filter types to achieve corresponding filtering functions, thereby meeting different application scenarios and improving the flexibility of digital filter applications.

[0019] In order to make the above and other purposes, features and advantages of the present application more obvious and understandable, preferred embodiments are specifically listed below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the specific embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0021] Figure 1 A schematic structural diagram of a digital filter circuit device provided in the present application.

[0022] Figure 2 A circuit diagram of a digital filter provided in this application.

[0023] Figure 3 A schematic diagram of a data path of a FIR digital filter circuit device provided in this application.

[0024] Figure 4 A data path diagram of an IIR digital filter circuit device provided in this application.

[0025] Figure 5 A 12th order FIR digital filter calculation provided for this application Schematic diagram of .

[0026] Figure 6 A 12th order FIR digital filter calculation provided for this application Schematic diagram of .

[0027] Figure 7 A 12th-order IIR digital filter calculation provided for this application Schematic diagram of .

[0028] Figure 8 A 12th-order IIR digital filter calculation provided for this application Schematic diagram of . DETAILED DESCRIPTION

[0029] The aforementioned and other technical contents, features and effects of the present application will be clearly presented in the following detailed description of a preferred embodiment with reference to the drawings. The terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances. This is just a way of distinguishing objects with the same attributes when describing the embodiments of the present application.

[0030] A digital filter is a component used to process digital signals. It uses multiplication and accumulation operations on the input digital signal to attenuate interference signals. It achieves signal filtering by changing the frequency characteristics of the signal. According to the time domain characteristics of the digital filter impulse response, digital filters can be divided into finite impulse response filters (FIR) and infinite impulse response filters (IIR). FIR digital filters are filters with strong stability, no feedback structure, and easy hardware implementation. At the same time, they meet the coefficient symmetry. The filtered signal is not prone to phase distortion, but the operation time is relatively long and the amplitude response characteristics are not as good as IIR digital filters. The characteristic of IIR digital filters is that the impulse response of the system is infinite, and its output depends not only on the input values ​​of the current and past signals, but also on the output values ​​of the past signals. Therefore, there is a feedback loop in its circuit structure, and the filtered signal will have phase distortion problems, but IIR digital filters have higher filtering efficiency and better amplitude-frequency characteristics. Based on the above characteristics, FIR digital filters are suitable for situations where high requirements for filtering accuracy are required in the fields of information transmission and digital image processing, while IIR digital filters are suitable for situations where low requirements for signal phase are required, such as voice calls and low-end video signal processing.

[0031] In order to enhance the versatility of filter application scenarios, the present application proposes a digital filter circuit device, such as Figure 1As shown, the circuit device includes at least one storage circuit, at least one multiplication and addition circuit, at least one addition circuit and a first data selection circuit, a second data selection circuit and a third data selection circuit; the first data selection circuit is connected to the storage circuit and is used to input a discrete digital signal; the storage circuit is used to store the discrete digital signal and the filter coefficient; the multiplication and addition circuit is connected between the storage circuit and the second data selection circuit, and the multiplication and addition circuit is used to multiply and add the discrete digital signal and the filter coefficient according to a preset corresponding relationship, determine the multiplication and addition result and input it into the second data selection circuit; the addition circuit is connected to the second data selection circuit and the third data selection circuit respectively, and the second data selection circuit and the third data selection circuit are used to select the corresponding data path and input and output according to the configuration mode, and the addition circuit is used to add the output signal of the second data selection circuit and the output signal of the third data selection circuit, and output the filtering result corresponding to the configuration mode.

[0032] This circuit device can simultaneously satisfy the functions of FIR digital filter and IIR digital filter. According to different application scenarios, different filter types can be switched. The user configures the type of digital filter (FIR or IIR) through the register and loads the corresponding filter coefficient. According to the filter type configured by the user, the circuit device selects the data path of the corresponding filter to realize the corresponding filter function. When the user configures the circuit device as an FIR digital filter, the circuit device selects a specific data path, the discrete digital signal enters the circuit device through the input end, and the filtering result is output at the output end to realize the filtering effect of the FIR digital filter; when the user configures the circuit device as an IIR digital filter, the two circuit devices of the present application are connected according to the specific data path, the discrete digital signal is input in the first circuit device, and the filtering result is output in the second circuit device, so as to realize the filtering effect of the IIR digital filter.

[0033] The present application is described in detail below with reference to the accompanying drawings.

[0034] Figure 2 A circuit diagram of a digital filter provided in the present application, the circuit device is composed of a plurality of storage circuits, a plurality of multiplication and addition circuits, a plurality of adder circuits and three data selection circuits. Hereinafter, the data selection circuit is referred to as a MUX circuit (Multiplexer, data selector), the first data selection circuit is referred to as MUX1, the second data selection circuit is referred to as MUX2, and the third data selection circuit is referred to as MUX3.

[0035] The storage circuit is a digital circuit that can store data. The storage circuit includes a signal storage circuit and a coefficient storage circuit. The signal storage circuit is responsible for storing the input discrete digital signal Z. -1The coefficient storage circuit is responsible for storing the filter coefficient coeff, and the storage circuit includes but is not limited to single-port and dual-port RAM, FIFO, and shift register.

[0036] The multiplication and addition circuit includes a multiplier and an adder. A multiplier is an electronic device circuit that performs the multiplication of two unrelated digital signals. It consists of a basic adder circuit. An adder is a digital circuit that can perform digital addition calculations to generate the sum of numbers. The multiplication and addition circuit is responsible for performing multiplication and addition operations on discrete digital signals and filter coefficients according to a specific corresponding relationship. The multiplication and addition circuit includes but is not limited to serial multiplication and accumulation multiplication and addition units and fully parallel multiplication and addition units and other forms of multiplication and addition unit structures.

[0037] The MUX circuit is a digital logic circuit that selects one of multiple input signals and outputs it. The MUX circuit is responsible for selecting a specific data path. The A and B terminals are input signals, and the Z terminal is the output signal. According to the selection signal value SEL, the MUX circuit selects to output the A terminal signal or the B terminal signal. The A terminal signal of MUX1 is a discrete digital signal, and the B terminal signal of MUX1 is the filtering result of the circuit device; the A terminal signal of MUX2 is the operation result of the multiplication and addition unit, and the B terminal signal of MUX2 is the negative result of the A terminal signal; the A terminal signal of MUX3 is 0, and the B terminal signal of MUX3 can be connected to other signals.

[0038] In some embodiments, when the configuration mode is FIR mode, the three data selection circuits all select the A-terminal signal to achieve the filtering effect of the FIR digital filter. Specifically, the mathematical expression of the FIR digital filter is: (Expression 1); Among them, x(ni) is the discrete digital signal sequence of the sampled input, h(i) is the FIR filter coefficient, and y(n) is the filter output signal sequence. is the filter order (length). From Expression 1, we can see that the FIR filter has no feedback structure, and the current filter result does not need to participate in subsequent filtering operations. The filtering result is only related to the filter coefficient and the input signal value.

[0039] When the user configures the circuit device as a FIR digital filter through registers, the circuit device data path is as follows Figure 3 As shown. MUX1, MUX2, and MUX3 all select the A-terminal signal, load the FIR filter coefficient h(i) into the coefficient storage circuit, and load the sampled input signal sequence into the signal storage circuit. After the circuit device is running, h(i) and x(ni) are multiplied according to a specific corresponding relationship, and then the product is added. The multiplication and addition result is , that is, the A-terminal signal of MUX2. From the circuit device structure diagram of the present application, it can be seen that the filtering result y(n) is obtained by adding the Z-terminal signal of MUX2. In the FIR filter, both MUX2 and MUX3 select the A-terminal signal, and the Z-terminal signal value of MUX2 is , the signal value at the Z end of MUX3 is 0, so the expression of the filtering result y(n) is: (Expression 2); It can be seen that expression 1 is consistent with expression 2, so, Figure 3 The circuit arrangement shown can realize a FIR digital filter function.

[0040] In some embodiments, when the configuration mode is the IIR mode, the circuit device is composed of a first circuit device and a second circuit device, and the three data selection circuits of the first circuit device all select the A-end signal, and the three data selection circuits of the second circuit device all select the B-end signal to achieve the filtering effect of the IIR digital filter. Specifically, the IIR digital filter is implemented as follows: (Expression 3); Among them, x(n) is the sampled input signal sequence, y(n) is the filter output signal sequence, a(i) is the filter coefficient related to the input signal sequence, b(i) is the filter coefficient related to the filtering result, and L is the filter order (length). From Expression 2, we can see that the IIR filter has a feedback structure. The current filtering result y(n) is not only related to the input signal value, but also to the previous filtering result, and the current filtering result will also participate in the subsequent filtering calculation.

[0041] When the user configures the circuit device as an IIR digital filter through registers, the circuit device data path is as follows Figure 4 As shown, the circuit device is composed of two circuit devices of the present application combined according to a specific signal connection relationship. The circuit device is divided into two parts, the first circuit device is the upper part, namely the NUME part, and the second circuit device is the lower part, namely the DENO part. Specifically, the output result y of the NUME part nume(n)Connected to the B-end signal of DENO_MUX3, the current output result y(n) of the entire IIR filter circuit device is fed back to the B-end signal of DENO_MUX1 as the input of the next beat of the DENO part. NUME_MUX1, NUME_MUX2, NUME_MUX3 all select the A-end signal, and DENO_MUX1, DENO_MUX2, DENO_MUX3 all select the B-end signal. The NUME part circuit device loads the first filter coefficient a(i), and the DENO part circuit device loads the second filter coefficient b(i). It can be obtained from Expression 3 that the number of b(i) is 1 less than a(i), so the coefficient storage circuit of the DENO part must be filled with 1 zero after loading b(L-1). By Figure 4 It can be seen that the NUME part of the IIR filter circuit device is the same as the FIR filter circuit structure, so we get: (Expression 4); From the data path of the IIR filter circuit device, it can be seen that the input signal of the DENO part is the filtering result y(n) of the IIR filter of the previous beat, so the signal value of the A terminal of DENO_MUX2 is: (Expression 5); The signal value at the B end of DENO_MUX2 is the negative form of the signal value at the A end, so, (Expression 6); Therefore, we obtain: (Expression 7); It can be seen that expression 7 is consistent with expression 3, so Figure 4 The circuit arrangement shown can realize an IIR digital filter function.

[0042] In a specific embodiment, the circuit device of the present application is configured as a 12th order FIR digital filter, and the data path of the circuit device is as follows: Figure 5 As shown, the first filtering result y(0) of the FIR digital filter is calculated. The sampled input signal sequence x(0) enters the circuit device and is multiplied by the corresponding coefficient h(0) according to the FIR mathematical expression to obtain y(0)=h(0)x(0). After that, x(1) enters the circuit device to calculate y(1), x(2) enters the circuit device to calculate y(2), and so on. Each time a sampled input signal sequence is input, a filtering result is obtained. To save space, the calculation process of y(1) to y(10) is omitted, and the calculation process of y(11) is as follows. Figure 6 As shown, the sampled input signal sequence and the filter coefficients are multiplied according to the corresponding relationship shown in the figure, and then the circuit device adds the multiplication results to obtain: (Expression 8); It can be seen from Expression 8 that the filtering operation process of the circuit device conforms to the mathematical expression of the FIR filter.

[0043] In another specific embodiment, the circuit device of the present application is configured as a 12th-order IIR digital filter, and the data path of the circuit device is as follows: Figure 7 As shown, the first filtering result y(0) of the IIR digital filter is calculated, and the sampled input signal sequence x(0) enters the NUME part of the circuit device. According to the IIR mathematical expression, y(0)=a(0)x(0) is obtained. After obtaining the y(0) value, it is fed back to the input end of the DENO part of the circuit device. The sampled input signal sequence x(1) enters the NUME part of the circuit device. According to x(0), x(1), y(0), y(1)=a(0)x(1)+a(1)x(0)+b(1)y(0) is calculated, and y(1) is fed back to the input end of the DENO part of the circuit device. And so on, each time a current filtering result is fed back, a sampled input signal sequence is input, and the next filtering result is calculated. In order to save space, the specific calculation process of y(1) to y(10) is omitted, and the calculation process of y(11) is as follows. Figure 8 As shown, y(11) is obtained by adding the opposites of y_nume(11) and y_deno(10): (Expression 9); It can be seen from Expression 9 that the filtering operation process of the circuit device conforms to the mathematical expression of the IIR filter.

[0044] In summary, the digital filter circuit device of the present application configures the filter type of the circuit device through a register, the circuit device selects the data path of the corresponding filter, loads the corresponding filter coefficients, and implements the corresponding filter function. The circuit device of the present application can be compatible with the implementation of FIR digital filter and IIR digital filter functions, and has the advantages of high flexibility and a wide range of application scenarios.

[0045] It should be noted that, for those of ordinary skill in the art, several improvements and modifications may be made to the present application without departing from the principles of the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application. It should be understood that certain features of the present disclosure described in the context of a separate embodiment for the sake of clarity may also be provided in a single embodiment by combination. Conversely, various features of the present disclosure described in the context of a single embodiment for the sake of clarity may also be provided individually or in any suitable combination or as any other described embodiment of the present disclosure.

Claims

1. A digital filter circuit device, characterized in that: The circuit device comprises at least one storage circuit, at least one multiplication and addition circuit, at least one addition circuit, and a first data selection circuit, a second data selection circuit, and a third data selection circuit; the first data selection circuit is connected to the storage circuit and is used to input a discrete digital signal; the storage circuit is used to store the discrete digital signal and the filter coefficient; the multiplication and addition circuit is connected between the storage circuit and the second data selection circuit, and the multiplication and addition circuit is used to perform multiplication and addition operations on the discrete digital signal and the filter coefficient according to a preset corresponding relationship, determine the multiplication and addition result, and input it into the second data selection circuit; The adding circuit is connected to the second data selection circuit and the third data selection circuit respectively. The second data selection circuit and the third data selection circuit are used to select the corresponding data path and perform input and output according to the configuration mode. The adding circuit is used to add the output signal of the second data selection circuit and the output signal of the third data selection circuit, and output the filtering result corresponding to the configuration mode.

2. A digital filter circuit device according to claim 1, characterized in that: The three data selection circuits all include an A terminal and a B terminal for inputting signals and a Z terminal for outputting signals. When the configuration mode is the FIR mode, the three data selection circuits all select the A terminal signal; The input signal of the A terminal of the first data selection circuit is a discrete digital signal, the input signal of the A terminal of the second data selection circuit is a multiplication-addition result, and the input signal of the A terminal of the third data selection circuit is 0.

3. A digital filter circuit device according to claim 2, characterized in that: The expression of the filtering result in the FIR mode is: ； Among them, x(ni) is the discrete digital signal sequence of the sampled input, h(i) is the FIR filter coefficient, y(n) is the filter output signal sequence, L is the filter order, MUX2 Z The Z terminal output signal of the second data selection circuit, MUX3 Z The Z terminal of the third data selection circuit outputs a signal.

4. A digital filter circuit device according to claim 1, characterized in that: The three data selection circuits each include an A terminal and a B terminal for input signals and a Z terminal for output signals. When the configuration mode is the IIR mode, the circuit device is composed of a first circuit device and a second circuit device. The three data selection circuits of the first circuit device each select the A terminal signal, and the three data selection circuits of the second circuit device each select the B terminal signal.

5. A digital filter circuit device according to claim 4, characterized in that: The filtering result of the first circuit device is used as the B-end input signal of the third data selection circuit of the second circuit device, and the filtering result of the second circuit device is used as the B-end input signal of the first data selection circuit of the second circuit device.

6. A digital filter circuit device according to claim 5, characterized in that: The first circuit device is loaded with a first filter coefficient, and the second circuit device is loaded with a second filter coefficient, the number of the second filter coefficient being one less than the number of the first filter coefficient.

7. A digital filter circuit device according to claim 6, characterized in that: The signal value at the B terminal of the second data selection circuit of the second circuit device is the inverse of the signal value at the A terminal of the second data selection circuit of the second circuit device, and the expression of the filtering result in the IIR mode is: ； Where x(n) is the discrete digital signal sequence of the sampled input, y(n) is the filter output signal sequence, a(i) is the filter coefficient related to the input signal sequence, b(i) is the filter coefficient related to the filtering result, L is the filter order, y nume(n) is the filtering result of the first circuit device, DENO MUX2B It is the signal value of the B terminal of the second data selection circuit of the second circuit device.

8. A digital filter circuit device according to claim 1, characterized in that: The circuit device switches different configuration modes through registers to achieve different filtering effects; in different configuration modes, corresponding numbers of storage circuits, multiplication and addition circuits and addition circuits are set according to the filter order corresponding to the configuration mode.

9. A digital filter circuit device according to claim 1, characterized in that: The storage circuit includes a signal storage circuit for storing the discrete digital signal and a coefficient storage circuit for storing the filter coefficient.

10. A digital filter circuit device according to claim 9, characterized in that: The multiplication and addition circuit includes a multiplier and an adder, the multiplier is connected to the signal storage circuit and the coefficient storage circuit, the multiplier performs multiplication operation on the discrete digital signal and the filter coefficient according to a preset corresponding relationship to obtain a multiplication result, and the adder adds the multiplication results to obtain a multiplication and addition result.

Images