Clock signal generation system, clock signal generation method and audio conversion chip

Abstract

The invention discloses a clock signal generation system, a clock signal generation method and an audio conversion chip, the system comprises a delay phase-locked loop, a clock edge acquisition module, a counter and at least one first clock generation module, and the first clock generation module is connected with the delay phase-locked loop and the counter. And the first screening module is used for screening pulse signals of the frequency-doubled clock signal and the reverse-phase frequency-doubled clock signal based on the count value to generate a first target clock signal. The frequency multiplication clock signal and the reverse-phase frequency multiplication clock signal are screened through the first clock generation module to generate the first target clock signal, multiple clock signals with different frequencies are generated at the same time under the condition of low cost, the requirement of a multi-input clock system is met, digital circuit logic processing is adopted, and the frequency multiplication clock signal generation circuit is simple in structure and convenient to operate. And the chip hardware circuit overhead is reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of audio conversion chips, and in particular relates to a clock signal generating system, a generating method and an audio conversion chip. Background Art

[0002] Taking the audio ADC (Analog-to-digital converter) chip using Delta-Sigma technology as an example, the analog front end generally generates sampled audio data through oversampling and Delta-Sigma noise shaping technology, and the digital back end converts the oversampled audio data into the final data at one times the audio sampling rate through a decimation algorithm.

[0003] There are many kinds of decimation algorithms, each with different characteristics: some decimation algorithms are simple to implement and consume less resources, but the frequency band flatness is poor and cannot be adjusted; some decimation algorithms are complex to implement and consume more resources, but the frequency band can be adjusted. In order to give full play to the advantages of various types of decimation filters, the audio ADC chip is usually composed of multiple cascades of decimation filters with different characteristics.

[0004] For example, audio ADC chips usually include comb CIC decimation filters, FIR decimation filters, etc. In practice, the input clock requirements of modules such as CIC filters, FIR filters, and ADC analog front ends are different. Most audio ADC chips use a PLL (Phase Lock Loop) as a frequency multiplier. According to the clock requirements of each module of the audio ADC chip, it generates an ideal multiplied clock through the frequency multiplication capability of the PLL, and then provides it to each module of the audio ADC chip through the corresponding clock division logic.

[0005] However, a PLL module itself is usually large in area, and occupies a relatively high proportion of the area of ​​the entire audio ADC chip. If we do not want to use a relatively large PLL as a clock multiplier, and use a clock multiplier with a weak multiplication capability but a very small hardware area, such as a DLL (Delay Lock Loop) clock multiplier, it is difficult to directly use the output clock of the multiplier or the divided clock of the output clock to meet the clock requirements of each module.

[0006] Therefore, in view of the above technical problems, it is necessary to provide a clock signal generating system, generating method and audio conversion chip. Summary of the invention

[0007] The object of the present invention is to provide a clock signal generating system, generating method and audio conversion chip, which can simultaneously generate multiple clock signals that meet different clock requirements and reduce circuit area overhead.

[0008] In order to achieve the above object, a technical solution provided by a specific embodiment of the present invention is as follows:

[0009] A clock signal generating system, the system comprising:

[0010] A delay locked loop, for generating a frequency-multiplied clock signal and an inverted frequency-multiplied clock signal based on an input clock signal and a frequency-multiplied configuration parameter;

[0011] A clock edge acquisition module, connected to the delay phase-locked loop, is used to delay the input clock signal according to the period of the multiplied clock signal to generate a delayed clock signal, and to generate a clock edge pulse signal based on the delayed clock signal and the input clock signal;

[0012] A counter, connected to the clock edge acquisition module, for generating a count value based on two adjacent pulses in the clock edge pulse signal;

[0013] At least one first clock generating module is connected to the delay locked loop and the counter, and is used to screen the pulse signals of the multiplied clock signal and the inverted multiplied clock signal based on the count value to generate a first target clock signal.

[0014] In one or more embodiments of the present invention, the system also includes a pre-division module, which is connected to a delay locked loop and is used to divide the input clock signal and generate an input clock division signal. The delay locked loop generates a multiplied clock signal based on the input clock division signal and the multiplication configuration parameters.

[0015] In one or more embodiments of the present invention, the first clock generation module includes a first register, a first clock screening unit and a first logic unit; wherein,

[0016] The first register is connected to the counter and is used to generate a first control word and a second control word based on a clock configuration parameter and a count value;

[0017] The first clock screening unit is connected to the first register and the delay locked loop, and is used to generate a first window signal based on the first control word and the frequency-multiplied clock signal, and to generate a second window signal based on the second control word and the inverted frequency-multiplied clock signal;

[0018] The first logic unit is connected to the counter, and is used to filter the pulse signal of the doubled clock signal based on the first window signal to generate a first output signal, filter the pulse signal of the inverted doubled clock signal based on the second window signal to generate a second output signal, and generate a first target clock signal based on the first output signal and the second output signal.

[0019] In one or more embodiments of the present invention, when the control bit of the first control word is 0, the first window signal is at a low level from the falling edge to the next adjacent falling edge within the period of the doubled frequency clock signal corresponding to the control bit; when the control bit of the first control word is 1, the first window signal is at a high level from the falling edge to the next adjacent falling edge within the period of the doubled frequency clock signal corresponding to the control bit;

[0020] When the control bit of the second control word is 0, the second window signal is at a low level during the period of the inverted multiplied clock signal corresponding to the control bit; when the control bit of the second control word is 1, the second window signal is at a high level during the period of the inverted multiplied clock signal corresponding to the control bit.

[0021] In one or more embodiments of the present invention, the clock generation system further includes a second clock generation module, the second clock generation module includes a second register, a second clock screening unit and a second logic unit; wherein,

[0022] The second register is connected to the counter and is used to generate a third control word based on the clock configuration parameter and the count value;

[0023] The second clock screening unit is connected to the second register and the delay locked loop, and is used to generate a third window signal based on the third control word and the multiplied clock signal;

[0024] The second logic unit is connected to the counter and is used to generate a second target clock signal based on the third window signal and the input clock signal.

[0025] Another specific embodiment of the present invention provides a technical solution as follows:

[0026] A method for generating a clock signal, the method comprising:

[0027] Get the input clock signal and frequency multiplication configuration parameters;

[0028] Generate a frequency-multiplied clock signal and an inverted frequency-multiplied clock signal based on an input clock signal and a frequency-multiplied configuration parameter through a delay-locked loop;

[0029] The clock edge acquisition module delays the input clock signal according to the period of the frequency-multiplied clock signal to generate a delayed clock signal, and generates a clock edge pulse signal based on the delayed clock signal and the input clock signal;

[0030] The counter generates a count value based on two adjacent pulses in the clock edge pulse signal;

[0031] At least one first clock generating module is used to screen the pulse signals of the frequency-multiplied clock signal and the frequency-inverted frequency-multiplied clock signal based on the count value to generate a first target clock signal.

[0032] In one or more embodiments of the present invention, the method further comprises:

[0033] The input clock signal is divided by a pre-dividing module to generate an input clock divided signal;

[0034] A multiplied clock signal is generated by a delay locked loop based on an input clock divided signal and a multiplied configuration parameter.

[0035] In one or more embodiments of the present invention, the method further comprises:

[0036] Generate a first control word and a second control word based on a clock configuration parameter and a count value through a first register;

[0037] Generate a first window signal based on a first control word and a frequency-multiplied clock signal by a first clock screening unit, and generate a second window signal based on a second control word and an inverted frequency-multiplied clock signal;

[0038] A first logic unit filters a pulse signal of a frequency-multiplied clock signal based on a first window signal to generate a first output signal, filters a pulse signal of an inverted frequency-multiplied clock signal based on a second window signal to generate a second output signal, and generates a first target clock signal based on the first output signal and the second output signal.

[0039] In one or more embodiments of the present invention, the clock generation method includes:

[0040] When the control bit of the first control word is 0, the first window signal is at a low level from the falling edge to the next adjacent falling edge within the period of the doubled frequency clock signal corresponding to the control bit; when the control bit of the first control word is 1, the first window signal is at a high level from the falling edge to the next adjacent falling edge within the period of the doubled frequency clock signal corresponding to the control bit;

[0041] When the control bit of the second control word is 0, the second window signal is at a low level during the period of the inverted multiplied clock signal corresponding to the control bit; when the control bit of the second control word is 1, the second window signal is at a high level during the period of the inverted multiplied clock signal corresponding to the control bit.

[0042] In one or more embodiments of the present invention, the method further comprises:

[0043] Generate a third control word based on the clock configuration parameter and the count value through the second register;

[0044] Generate a third window signal based on a third control word and a multiplied clock signal by a second clock screening unit;

[0045] A second target clock signal is generated by a second logic unit based on the third window signal and the input clock signal.

[0046] Another specific embodiment of the present invention provides a technical solution as follows:

[0047] An audio conversion chip, comprising the clock signal generation system, an analog front end and at least one first extraction filter according to any one of the embodiments; wherein:

[0048] The analog front end is connected to the clock signal generating system, and is used to receive the analog audio signal and oversample the analog audio signal based on the first target clock signal to generate a first sampling signal;

[0049] The first decimation filter is connected to the clock signal generating system and the analog front end, and is used to generate a second sampling signal based on the first sampling signal and the first target clock signal.

[0050] In one or more embodiments of the present invention, the audio conversion chip further includes a second decimation filter connected to the clock generation system and the first decimation filter for generating a digital audio signal based on the second sampling signal and the second target clock signal.

[0051] Compared with the prior art, the clock signal generating system, generating method and audio conversion chip of the present invention screen the frequency-multiplied clock signal and the frequency-multiplied clock signal by the first clock generating module to generate the first target clock signal, thereby realizing the simultaneous generation of multiple clock signals of different frequencies under low-cost conditions, and meeting the requirements of a multi-input clock system.

[0052] The use of digital circuit logic processing reduces the chip hardware circuit overhead. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0054] Figure 1 is a structural diagram of a clock signal generating system in Embodiment 1 of the present invention;

[0055] Figure 2 is a structural diagram of the first clock signal generating module in Embodiment 1 of the present invention;

[0056] Figure 3 is a timing diagram of a clock signal in Embodiment 1 of the present invention;

[0057] Figure 4 is a timing diagram of a clock signal in Embodiment 1 of the present invention;

[0058] Figure 5 is a structural diagram of a clock signal generating system in Embodiment 2 of the present invention;

[0059] Figure 6 is a structural diagram of a second clock signal generating module in Embodiment 2 of the present invention;

[0060] Figure 7 is a timing diagram of clock signals in Embodiment 2 of the present invention;

[0061] Figure 8 is a structural diagram of a clock signal generating system in Embodiment 3 of the present invention;

[0062] Fig. 9 This is a structural diagram of the audio conversion chip in Embodiment 4 of the present invention;

[0063] Fig.10 This is a flow chart of the clock signal generating method in Embodiment 5 of the present invention. DETAILED DESCRIPTION

[0064] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0065] Unless explicitly stated otherwise, throughout the specification and claims, the term “comprise” or variations such as “include” or “comprising”, etc., will be understood to include the stated elements or components but not to exclude other elements or components.

[0066] "Coupled" or "connected" or "connected" in the specification includes both direct connection and indirect connection. Indirect connection is a connection through an intermediate medium, such as a connection through an electrically conductive medium, which may have parasitic inductance or parasitic capacitance; indirect connection may also include connection through other active or passive devices on the basis of achieving the same or similar functional purposes, such as connection through circuits or components such as switches and follower circuits. In addition, in the present invention, words such as "first" and "second" are mainly used to distinguish one technical feature from another technical feature, and do not necessarily require or imply that there is a certain actual relationship, quantity or order between these technical features.

[0067] In the detailed description of the specification, reference is made to the accompanying drawings forming a part thereof, wherein like reference numerals refer to like parts throughout, and wherein are shown by way of exemplary embodiments that may be implemented. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description should not be considered in a limiting sense.

[0068] The various operations in the specification may be described in turn as multiple discrete actions or operations in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be interpreted as implying that these operations must be order-dependent. Specifically, these operations may not be performed in the order presented. The described operations may be performed in an order different from the described embodiments. Various additional operations may be performed and / or the described operations may be omitted in additional embodiments.

[0069] For purposes of this disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For purposes of this disclosure, the phrase "A, B and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0070] Various components and devices may be referred to or shown in the singular form in this document (for example, "MOS tube", "transistor", "switch", etc.), but this is only for convenience of discussion, and any element mentioned in the singular form may include multiple such elements according to the teachings of this document.

[0071] The specification describes the use of the phrases "in this embodiment" or "in other embodiments" or "in some embodiments", which can each refer to one or more of the same or different embodiments. In addition, the terms "including", "comprising", "having", etc. used in relation to the embodiments of the present disclosure are synonymous.

[0072] Embodiment 1:

[0073] like Figure 1 As shown, this embodiment provides a clock signal generating system, which includes a delay locked loop 10 , a clock edge acquisition module 20 , a counter 30 and at least one first clock generating module 40 .

[0074] A delay locked loop 10, for generating a frequency-multiplied clock signal Nx_clk and an inverted frequency-multiplied clock signal inv_Nx_clk based on an input clock signal in_clk and a frequency-multiplied configuration parameter;

[0075] The clock edge acquisition module 20 is connected to the delay locked loop 10, and is used to delay the input clock signal in_clk according to the period of the multiplied clock signal Nx_clk to generate a delayed clock signal dly_in_clk, and generate a clock edge pulse signal inclk_edge based on the delayed clock signal dly_in_clk and the input clock signal in_clk;

[0076] The counter 30 is connected to the clock edge acquisition module 20 and is used to generate a count value Nxclk_count based on two adjacent pulses in the clock edge pulse signal inclk_edge;

[0077] At least one first clock generating module 40 is connected to the delay locked loop 10 and the counter 30, and is used to screen the pulse signals of the multiplied clock signal Nx_clk and the inverted multiplied clock signal inv_Nx_clk based on the count value Nxclk_count to generate a first target clock signal out_clk.

[0078] like Figure 2 As shown, the first clock generating module 40 in this embodiment includes a first register 41 , a first clock screening unit 42 and a first logic unit 43 .

[0079] Specifically, the first register 41 is connected to the counter 30 and is used to generate the first control word CW1 and the second control word CW2 based on the clock configuration parameter and the count value Nxclk_count.

[0080] The first clock screening unit 42 is connected to the first register 41 and the delay locked loop 10, and is used to generate a first window signal Nx_clk_m based on the first control word CW1 and the multiplied clock signal Nx_clk, and to generate a second window signal inv_Nx_clk_m based on the second control word CW2 and the inverted multiplied clock signal inv_Nx_clk;

[0081] The first logic unit 43 is connected to the counter 30, and is used to filter the pulse signal of the multiplied clock signal Nx_clk based on the first window signal Nx_clk_m to generate a first output signal m_Nx_clk1, filter the pulse signal of the inverted multiplied clock signal inv_Nx_clk based on the second window signal inv_Nx_clk_m to generate a second output signal m_inv_Nx_clk1, and generate a first target clock signal out_clk based on the first output signal m_Nx_clk1 and the second output signal m_inv_Nx_clk1.

[0082] When the control bit of the first control word CW1 is 0, the first window signal Nx_clk_m is at a low level from the falling edge to the next adjacent falling edge within the period of the multiplied clock signal Nx_clk corresponding to the control bit; when the control bit of the first control word CW1 is 1, the first window signal Nx_clk_m is at a high level from the falling edge to the next adjacent falling edge within the period of the multiplied clock signal Nx_clk corresponding to the control bit;

[0083] When the control bit of the second control word CW2 is 0, the second window signal inv_Nx_clk_m is at a low level during the period of the inverted doubled frequency clock signal inv_Nx_clk corresponding to the control bit; when the control bit of the second control word CW2 is 1, the second window signal inv_Nx_clk_m is at a high level during the period of the inverted doubled frequency clock signal inv_Nx_clk corresponding to the control bit.

[0084] like Figure 3 As shown, the requirements for generating the first target clock signal out_clk1 based on the clock configuration parameters are: the first target clock signal out_clk1 is four times the frequency of the input clock signal in_clk, and the low level pulse width in a clock cycle of the first target clock signal out_clk1 is twice the high level pulse width.

[0085] Specifically, the input clock signal in_clk is a 1x clock signal, and the frequency multiplication configuration parameter is 6x. Therefore, the delay locked loop 10 generates a multiplied clock signal Nx_clk (6x) based on the input clock signal in_clk, and inverts the multiplied clock signal Nx_clk to obtain an inverted multiplied clock signal inv_Nx_clk.

[0086] The clock edge acquisition module 20 delays the input clock signal in_clk according to the period of the multiplied clock signal Nx_clk to generate a delayed clock signal dly_in_clk, wherein the delayed clock signal dly_in_clk is delayed by one period of the multiplied clock signal Nx_clk relative to the input clock signal in_clk, and generates a clock edge pulse signal inclk_edge based on the delayed clock signal dly_in_clk and the input clock signal in_clk. Specifically, when the input clock signal in_clk is high and the delayed clock signal dly_in_clk is low, the clock edge pulse signal inclk_edge is high; in other cases (i.e., when the input clock signal in_clk is low and the delayed clock signal dly_in_clk is low, or, when the input clock signal in_clk is high and the delayed clock signal dly_in_clk is high, or, when the input clock signal in_clk is high and the delayed clock signal dly_in_clk is high), the clock edge pulse signal inclk_edge is low.

[0087] It can be understood that at the falling edge of the high level pulse of the clock edge pulse signal inclk_edge, the counter 30 starts counting forward from 0, and the count value generated by the counter 30 is increased by 1 in each cycle of the multiplied clock signal Nx_clk. At the falling edge of the next adjacent high level pulse of the clock edge pulse signal inclk_edge, the current round of counting ends, and the counter 30 starts counting forward from 0 again. It can be understood that the count value generated by each round of counting corresponds to the preset multiplied frequency cycle. For example, in this embodiment, the multiplied clock signal Nx_clk is 6 times the frequency, that is, relative to the input clock signal in_clk, within one input clock signal in_clk cycle, the multiplied clock signal Nx_clk appears for a total of 6 cycles, then the counting cycle of the counter 30 is 6, that is, the counter 30 counts from 0 to 5, and starts counting again from 0 at the next falling edge of the clock edge pulse signal inclk_edge. It can be understood that the count value generated by the counter 30 corresponds to the frequency of the multiplied clock signal Nx_clk.

[0088] The first register 41 generates a first control word CW1 and a second control word CW2 based on the clock configuration parameters and the count value Nxclk_count. The number of bits of the first control word CW1 and the second control word CW2 is equal to the count value Nxclk_count generated by the counter 30. For example, if the count value is 8 (i.e., 0 to 7), the first register 41 generates an 8-bit first control word CW1 and a second control word CW2. In this embodiment, the count value is 6 (i.e., 0 to 5), and the first control word CW1 and the second control word CW2 are both 6 bits.

[0089] When the control bit of the first control word CW1 is 0, the first window signal Nx_clk_m is at a low level from the falling edge to the next adjacent falling edge within the period of the doubled clock signal Nx_clk corresponding to the control bit, and when the control bit of the first control word CW1 is 1, the first window signal Nx_clk_m is at a high level from the falling edge to the next adjacent falling edge within the period of the doubled clock signal Nx_clk corresponding to the control bit. It can also be understood here that: in this embodiment, when the control bit of the first control word CW1 is 0, the first window signal Nx_clk_m is at a low level within the period of the doubled clock signal Nx_clk corresponding to the control bit, and when the control bit of the first control word CW1 is 1, the first window signal Nx_clk_m is at a high level within the period of the doubled clock signal Nx_clk corresponding to the control bit, and the first window signal Nx_clk_m is delayed by half a period of the doubled clock signal Nx_clk relative to the doubled clock signal Nx_clk.

[0090] When the control bit of the second control word CW2 is 0, the second window signal inv_Nx_clk_m is at a low level during the period of the inverted doubled frequency clock signal inv_Nx_clk corresponding to the control bit; when the control bit of the second control word CW2 is 1, the second window signal inv_Nx_clk_m is at a high level during the period of the inverted doubled frequency clock signal inv_Nx_clk corresponding to the control bit.

[0091] like Figure 3 As shown, a 6-bit control word is used as an example: in this embodiment, the first control word CW1 is set to 010010 based on the clock configuration parameters, the 0th, 2nd, 3rd and 5th control bits are 0, the 1st and 4th control bits are 1, and the 0th, 1st, 2nd, 3rd, 4th and 5th control bits of the first control word CW1 correspond to count values ​​0, 1, 2, 3, 4 and 5 respectively.

[0092] The first window signal Nx_clk_m1 is at a low level between the falling edge of the multiplied clock signal Nx_clk period T0 corresponding to the count value Nxclk_count being 0 and the next adjacent falling edge (i.e., the falling edge of the multiplied clock signal Nx_clk period T1), the first window signal Nx_clk_m1 is at a high level between the falling edge of the multiplied clock signal Nx_clk period T1 corresponding to the count value Nxclk_count being 1 and the next adjacent falling edge (i.e., the falling edge of the multiplied clock signal Nx_clk period T2), the first window signal Nx_clk_m1 is at a low level between the falling edge of the multiplied clock signal Nx_clk period T1 corresponding to the count value Nxclk_count being 2 and the next adjacent falling edge (i.e., the falling edge of the multiplied clock signal Nx_clk period T2), and so on. Figure 3 The first window signal Nx_clk_m1 is shown.

[0093] It can be understood that since the first window signal Nx_clk_m1 is delayed relative to the count value Nxclk_count, that is, when the control bit of the first control word CW1 is 0, the first window signal Nx_clk_m1 is low level in the period of the multiplied clock signal Nx_clk corresponding to the control bit, and when the control bit of the first control word CW1 is 1, the first window signal Nx_clk_m1 is high level in the period of the multiplied clock signal Nx_clk corresponding to the control bit, and the first window signal Nx_clk_m1 is delayed by half the period of the multiplied clock signal Nx_clk relative to the multiplied clock signal Nx_clk, Figure 3 The first window signal Nx_clk_m1 is shown.

[0094] In this embodiment, based on the clock configuration parameters, the second control word CW2 is set to 001001, the 1st, 2nd, 4th and 5th control bits are 0, the 0th and 3rd control bits are 1, and the 0th, 1st, 2nd, 3rd, 4th and 5th control bits of the second control word CW2 correspond to count values ​​0, 1, 2, 3, 4 and 5 respectively.

[0095] The second window signal inv_Nx_clk_m1 is at a high level in the period T0 of the frequency-multiplied clock signal Nx_clk when the count value Nxclk_count is 0, and is at a low level in the period T1 of the frequency-multiplied clock signal Nx_clk when the count value Nxclk_count is 1, and so on. Figure 3 The second window signal inv_Nx_clk_m1 is shown.

[0096] The first logic unit 43 is connected to the counter 30, and is used to filter the pulse signal of the multiplied clock signal Nx_clk based on the first window signal Nx_clk_m1 to generate a first output signal m_Nx_clk1, filter the pulse signal of the inverted multiplied clock signal inv_Nx_clk based on the second window signal inv_Nx_clk_m1 to generate a second output signal m_inv_Nx_clk1, and generate a first target clock signal out_clk1 based on the first output signal m_Nx_clk1 and the second output signal m_inv_Nx_clk1.

[0097] Furthermore, in this embodiment, the first logic unit 43 performs an AND operation on the first window signal inv_Nx_clk_m1 and the multiplied clock signal Nx_clk to obtain a first output signal m_Nx_clk1, performs an AND operation on the second window signal inv_Nx_clk_m1 and the inverted multiplied clock signal inv_Nx_clk to obtain a second output signal m_inv_Nx_clk1, and performs an OR operation on the first output signal m_Nx_clk1 and the second output signal m_inv_Nx_clk1 to generate a first target clock signal out_clk1.

[0098] like Figure 4 As shown, a first target clock signal out_clk2 needs to be generated based on another clock configuration parameter: therefore, another first clock generating module 40 in this embodiment is connected to the delay locked loop 10 and the counter 30, and is used to screen the pulse signals of the multiplied clock signal Nx_clk and the inverted multiplied clock signal inv_Nx_clk based on the count value to generate another corresponding first target clock signal out_clk2.

[0099] Based on another clock configuration parameter, the first control word CW1 is set to 110110, the 0th and 3rd control bits are 0, the 1st, 2nd, 4th and 5th control bits are 1, and the first window signal Nx_clk_m2 is low level between the falling edge of the multiplied clock signal Nx_clk period T0 corresponding to the count value of 0 and the next adjacent falling edge (i.e., the falling edge of the multiplied clock signal Nx_clk period T1), and the first window signal Nx_clk_m2 is high level between the falling edge of the multiplied clock signal Nx_clk period T1 corresponding to the count value of 1 and the next adjacent falling edge (i.e., the falling edge of the multiplied clock signal Nx_clk period T2), and so on. Figure 4 It can be understood that, since the first window signal Nx_clk_m2 is delayed relative to the count value, that is, when the 0 control bit of the first control word CW1 is 0, the first window signal Nx_clk_m2 is at a low level in the period of the doubled-frequency clock signal Nx_clk corresponding to the control bit, and when the 1 control bit of the first control word CW1 is 1, the first window signal Nx_clk_m2 is at a high level in the period of the doubled-frequency clock signal Nx_clk corresponding to the control bit, and the first window signal Nx_clk_m2 is delayed relative to the doubled-frequency clock signal Nx_clk by half the period of the doubled-frequency clock signal Nx_clk, Figure 4 The first window signal Nx_clk_m2 is shown.

[0100] In this embodiment, the second control word CW2 is set to 000000 based on the clock configuration parameters, all control bits are 0, and the second window signal inv_Nx_clk_m2 is low level in the period T0 of the multiplied clock signal Nx_clk corresponding to the count value of 0. Figure 4 The second window signal inv_Nx_clk_m2 is shown.

[0101] The first logic unit 43 is connected to the counter 30, and is used to filter the pulse signal of the multiplied clock signal Nx_clk based on the first window signal Nx_clk_m2 to generate a corresponding first output signal m_Nx_clk2, filter the pulse signal of the inverted multiplied clock signal inv_Nx_clk based on the second window signal inv_Nx_clk_m2 to generate a corresponding second output signal m_inv_Nx_clk2, and generate a corresponding first target clock signal out_clk2 based on the first output signal m_Nx_clk2 and the second output signal m_inv_Nx_clk2.

[0102] Further, in this embodiment, the first logic unit 43 performs an AND operation on the first window signal Nx_clk_m2 and the multiplied clock signal Nx_clk to obtain a corresponding first output signal m_Nx_clk2, performs an AND operation on the second window signal inv_Nx_clk_m2 and the inverted multiplied clock signal inv_Nx_clk to obtain a corresponding second output signal m_inv_Nx_clk2, and performs an OR operation on the first output signal m_Nx_clk2 and the second output signal m_inv_Nx_clk2 to generate a corresponding first target clock signal out_clk2.

[0103] Understandably, Figure 3 and Figure 4 These are just two possible examples of this embodiment. In more optional embodiments, those skilled in the art can generate a first target clock signal out_clk that meets different clock signal requirements by setting one or more first clock generation modules 40 and based on the corresponding first control word CW1 and second control word CW2. The clock generation system proposed in this embodiment occupies a small hardware area and can generate a first target clock signal out_clk that meets the requirements of different modules of the audio conversion chip. In this embodiment, the number of first clock generation modules 40 can be freely adjusted based on the number of modules.

[0104] Embodiment 2:

[0105] like Figure 5 As shown, the difference from the embodiment 1 is that the clock generation system in this embodiment further includes a second clock generation module 50. The second clock generation module 50 is connected to the counter 30 and the delay locked loop 10.

[0106] like Figure 6 As shown, the second clock generating module 50 includes a second register 51 , a second clock screening unit 52 and a second logic unit 53 .

[0107] The second register 51 is connected to the counter 30 and is used to generate a third control word CW3 based on the clock configuration parameter and the count value Nxclk_count;

[0108] The second clock screening unit 52 is connected to the second register 51 and the delay locked loop 10, and is used to generate a third window signal clk_d based on the third control word CW3 and the multiplied clock signal Nx_clk.

[0109] like Figure 7 As shown, taking the generation of the second target clock signal OUT_clk with a frequency doubled relative to the input clock signal in_clk as an example:

[0110] Based on another clock configuration parameter, the third control word CW3 is set to 000111, the 3rd, 4th and 5th control bits are 0, the 0th, 1st and 2nd control bits are 1, and the third window signal clk_d is low level between the falling edge of the multiplied clock signal Nx_clk cycle T0 corresponding to the count value Nxclk_count being 0 and the next adjacent falling edge (i.e., the falling edge of the multiplied clock signal Nx_clk cycle T1), and the third window signal clk_d is low level between the falling edge of the multiplied clock signal Nx_clk cycle T1 corresponding to the count value Nxclk_count being 1 and the next adjacent falling edge (i.e., the falling edge of the multiplied clock signal Nx_clk cycle T2), and so on, to obtain Figure 7 It can be understood that, since the third window signal clk_d is delayed relative to the count value, that is, when the 0 control bit of the first control word CW1 is 1, the third window signal clk_d is high level in the multiplied clock signal Nx_clk period corresponding to the control bit, and when the 1 control bit of the first control word CW1 is 1, the third window signal clk_d is high level in the multiplied clock signal Nx_clk period corresponding to the control bit (and so on), and the third window signal clk_d is delayed relative to the multiplied clock signal Nx_clk by half the multiplied clock signal Nx_clk period, and the result is Figure 7 The third window signal clk_d is shown.

[0111] The second logic unit 53 is connected to the counter 30 and is used to generate the second target clock signal OUT_clk based on the third window signal clk_d and the input clock signal in_clk. Specifically, the second logic unit 53 performs an XOR operation on the third window signal clk_d and the input clock signal in_clk to generate the second target clock signal OUT_clk.

[0112] In this embodiment, the second target clock signal OUT_clk is indirectly generated by the frequency-multiplied clock signal Nx_clk, thereby effectively avoiding clock jitter.

[0113] Embodiment 3:

[0114] like Figure 8 As shown, the difference between this embodiment and embodiment 1 or embodiment 2 is that the clock signal generating system in this embodiment also includes a pre-division module 60, which is connected to the delay locked loop 10, and is used to divide the input clock signal in_clk and generate an input clock division signal div_in_clk. The delay locked loop 10 generates a multiplied clock signal Nx_clk based on the input clock division signal div_in_clk and the multiplication configuration parameters.

[0115] If the input clock signal in_clk is a multiple frequency (for example, 13 times the frequency), it is difficult to perform frequency multiplication processing on it. This embodiment proposes to divide the input clock signal in_clk to obtain a single-frequency input clock division signal div_in_clk, and then the delay locked loop 10 generates a multiplied clock signal Nx_clk based on the input clock division signal div_in_clk and the multiplication configuration parameters.

[0116] Embodiment 4:

[0117] like Fig. 9 As shown, this embodiment provides an audio conversion chip, which includes a clock signal generating system, an analog front end 70, a first decimation filter 80, and a second decimation filter 90 as in Embodiment 1, 2, or 3. In this embodiment, the first decimation filter 80 is illustrated by a CIC filter 80, and the second decimation filter 90 is illustrated by a FIR filter 90.

[0118] The analog front end 70 is connected to the first clock signal generating module 40 in the clock signal generating system, and is used to receive the analog audio signal and oversample the analog audio signal based on the first target clock signal out_clk1 to generate a first sampling signal S1. The first target clock signal out_clk1 in this embodiment is as follows: Figure 3 shown.

[0119] The CIC filter 80 is connected to the first clock signal generating module 40 and the analog front end 70 of the clock signal generating system, and is used to generate the second sampling signal S2 based on the first sampling signal S1 and the first target clock signal out_clk2. In this embodiment, the first target clock signal out_clk2 is as shown in FIG. Figure 4 shown.

[0120] The FIR filter 90 is connected to the second clock signal generating module 50 and the CIC filter 70 of the clock generating system, and is used to generate a digital audio signal based on the second sampling signal S2 and the second target clock signal OUT_clk. Figure 7 shown.

[0121] It can be understood that the analog front end 70, the first extraction filter 80 and the second extraction filter 90 in the audio conversion chip have different requirements for the input clock signal in_clk. This embodiment uses a clock signal generation system to simultaneously generate at least one first target clock signal out_clk and a second target clock signal OUT_clk to meet the clock requirements of the audio conversion chip and give full play to the advantages of various types of extraction filters.

[0122] Embodiment 5:

[0123] like Fig.10 As shown, this embodiment provides a clock signal generating method, the method comprising:

[0124] S1. Obtain input clock signal in_clk and frequency multiplication configuration parameters;

[0125] S2, generating a frequency-multiplied clock signal Nx_clk and an inverted frequency-multiplied clock signal inv_Nx_clk based on the input clock signal in_clk and the frequency-multiplied configuration parameters through the delay locked loop 10;

[0126] S3, delaying the input clock signal in_clk according to the period of the multiplied clock signal Nx_clk through the clock edge acquisition module 20 to generate a delayed clock signal dly_in_clk, and generating a clock edge pulse signal inclk_edge based on the delayed clock signal dly_in_clk and the input clock signal in_clk;

[0127] S4, generating a count value Nxclk_count based on two adjacent pulses in the clock edge pulse signal inclk_edge by the counter 30;

[0128] S5 , screening the pulse signals of the multiplied clock signal Nx_clk and the inverted multiplied clock signal inv_Nx_clk based on the count value Nxclk_count by at least one first clock generating module 40 to generate a first target clock signal out_clk.

[0129] Furthermore, the clock signal generating method in this embodiment also includes:

[0130] The pre-dividing module 60 divides the input clock signal in_clk and generates an input clock divided signal div_in_clk;

[0131] The delay locked loop 10 generates a multiplied clock signal Nx_clk based on the input clock division signal div_in_clk and the multiplication configuration parameters.

[0132] Furthermore, the clock signal generating method in this embodiment also includes:

[0133] Generate a first control word CW1 and a second control word CW2 based on a clock configuration parameter and a count value Nxclk_count through a first register 41;

[0134] Generate a first window signal Nx_clk_m based on the first control word CW1 and the frequency-multiplied clock signal Nx_clk through the first clock screening unit 42, and generate a second window signal inv_Nx_clk_m based on the second control word CW2 and the inverted frequency-multiplied clock signal inv_Nx_clk;

[0135] The first logic unit 43 filters the pulse signal of the multiplied clock signal Nx_clk based on the first window signal Nx_clk_m to generate a first output signal, filters the pulse signal of the inverted multiplied clock signal inv_Nx_clk based on the second window signal inv_Nx_clk_m to generate a second output signal, and generates a first target clock signal out_clk based on the first output signal and the second output signal.

[0136] Furthermore, the clock signal generating method in this embodiment also includes:

[0137] When the control bit of the first control word CW1 is 0, the first window signal Nx_clk_m is at a low level from the falling edge to the next adjacent falling edge within the period of the multiplied clock signal Nx_clk corresponding to the control bit; when the control bit of the first control word CW1 is 1, the first window signal Nx_clk_m is at a high level from the falling edge to the next adjacent falling edge within the period of the multiplied clock signal Nx_clk corresponding to the control bit;

[0138] When the control bit of the second control word CW2 is 0, the second window signal inv_Nx_clk_m is at a low level during the period of the inverted doubled frequency clock signal inv_Nx_clk corresponding to the control bit; when the control bit of the second control word CW2 is 1, the second window signal inv_Nx_clk_m is at a high level during the period of the inverted doubled frequency clock signal inv_Nx_clk corresponding to the control bit.

[0139] Furthermore, the clock signal generating method in this embodiment also includes:

[0140] Generate a third control word CW3 based on the clock configuration parameter and the count value Nxclk_count through the second register 51;

[0141] Generate a third window signal clk_d based on the third control word CW3 and the multiplied clock signal Nx_clk by the second clock screening unit 52;

[0142] The second target clock signal OUT_clk is generated by the second logic unit 53 based on the third window signal clk_d and the input clock signal in_clk.

[0143] It can be seen from the above technical solutions that the present invention has the following beneficial effects:

[0144] The present invention sets a first clock generating module and generates a first target clock signal that meets different clock signal requirements based on a count value, and realizes simultaneous generation of multiple clock signals of different frequencies under low cost conditions, thereby meeting the requirements of a multi-input clock system.

[0145] The clock generation system proposed in the present invention occupies a small hardware area and uses digital circuits for logic processing, which reduces the circuit area compared to analog circuits and reduces the chip hardware circuit overhead.

[0146] The present invention can generate a first target clock signal that meets the requirements of different modules of an audio conversion chip, and the number of first clock generation modules can be freely adjusted based on the clock signal requirements.

[0147] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0148] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A clock signal generating system, characterized in that: The system comprises: A delay locked loop, for generating a frequency-multiplied clock signal and an inverted frequency-multiplied clock signal based on an input clock signal and a frequency-multiplied configuration parameter; A clock edge acquisition module, connected to the delay phase-locked loop, is used to delay the input clock signal according to the period of the multiplied clock signal to generate a delayed clock signal, and to generate a clock edge pulse signal based on the delayed clock signal and the input clock signal; A counter, connected to the clock edge acquisition module, for generating a count value based on two adjacent pulses in the clock edge pulse signal; At least one first clock generating module is connected to the delay locked loop and the counter, and is used to screen the pulse signals of the multiplied clock signal and the inverted multiplied clock signal based on the count value to generate a first target clock signal.

2. The clock signal generating system according to claim 1, characterized in that: The system also includes a pre-division module, which is connected to a delay locked loop and is used to divide the input clock signal and generate an input clock division signal. The delay locked loop generates a multiplied clock signal based on the input clock division signal and a multiplication configuration parameter.

3. The clock signal generating system according to claim 1, characterized in that: The first clock generation module includes a first register, a first clock screening unit and a first logic unit; wherein, The first register is connected to the counter and is used to generate a first control word and a second control word based on a clock configuration parameter and a count value; The first clock screening unit is connected to the first register and the delay locked loop, and is used to generate a first window signal based on the first control word and the frequency-multiplied clock signal, and to generate a second window signal based on the second control word and the inverted frequency-multiplied clock signal; The first logic unit is connected to the counter, and is used to filter the pulse signal of the doubled clock signal based on the first window signal to generate a first output signal, filter the pulse signal of the inverted doubled clock signal based on the second window signal to generate a second output signal, and generate a first target clock signal based on the first output signal and the second output signal.

4. The clock signal generating system according to claim 3, characterized in that: When the control bit of the first control word is 0, the first window signal is at a low level from the falling edge to the next adjacent falling edge within the period of the doubled frequency clock signal corresponding to the control bit; when the control bit of the first control word is 1, the first window signal is at a high level from the falling edge to the next adjacent falling edge within the period of the doubled frequency clock signal corresponding to the control bit; When the control bit of the second control word is 0, the second window signal is at a low level during the period of the inverted multiplied clock signal corresponding to the control bit; when the control bit of the second control word is 1, the second window signal is at a high level during the period of the inverted multiplied clock signal corresponding to the control bit.

5. The clock signal generating system according to claim 1, characterized in that: The clock generation system further includes a second clock generation module, which includes a second register, a second clock screening unit and a second logic unit; wherein, The second register is connected to the counter and is used to generate a third control word based on the clock configuration parameter and the count value; The second clock screening unit is connected to the second register and the delay locked loop, and is used to generate a third window signal based on the third control word and the multiplied clock signal; The second logic unit is connected to the counter and is used to generate a second target clock signal based on the third window signal and the input clock signal.

6. A clock signal generating method, characterized in that: The method comprises: Get the input clock signal and frequency multiplication configuration parameters; Generate a frequency-multiplied clock signal and an inverted frequency-multiplied clock signal based on an input clock signal and a frequency-multiplied configuration parameter through a delay-locked loop; The clock edge acquisition module delays the input clock signal according to the period of the frequency-multiplied clock signal to generate a delayed clock signal, and generates a clock edge pulse signal based on the delayed clock signal and the input clock signal; The counter generates a count value based on two adjacent pulses in the clock edge pulse signal; At least one first clock generating module is used to screen the pulse signals of the frequency-multiplied clock signal and the frequency-inverted frequency-multiplied clock signal based on the count value to generate a first target clock signal.

7. The clock signal generating method according to claim 6, characterized in that: The method further comprises: The input clock signal is divided by a pre-dividing module to generate an input clock divided signal; A multiplied clock signal is generated by a delay locked loop based on an input clock divided signal and a multiplied configuration parameter.

8. The clock signal generating method according to claim 6, characterized in that: The method further comprises: Generate a first control word and a second control word based on a clock configuration parameter and a count value through a first register; Generate a first window signal based on a first control word and a frequency-multiplied clock signal by a first clock screening unit, and generate a second window signal based on a second control word and an inverted frequency-multiplied clock signal; A first logic unit filters a pulse signal of a frequency-multiplied clock signal based on a first window signal to generate a first output signal, filters a pulse signal of an inverted frequency-multiplied clock signal based on a second window signal to generate a second output signal, and generates a first target clock signal based on the first output signal and the second output signal.

9. The clock signal generating method according to claim 8, characterized in that: The clock generation method comprises: When the control bit of the first control word is 0, the first window signal is at a low level from the falling edge to the next adjacent falling edge within the period of the doubled frequency clock signal corresponding to the control bit; when the control bit of the first control word is 1, the first window signal is at a high level from the falling edge to the next adjacent falling edge within the period of the doubled frequency clock signal corresponding to the control bit; When the control bit of the second control word is 0, the second window signal is at a low level during the period of the inverted multiplied clock signal corresponding to the control bit; when the control bit of the second control word is 1, the second window signal is at a high level during the period of the inverted multiplied clock signal corresponding to the control bit.

10. The clock signal generating method according to claim 6, characterized in that: The method further comprises: Generate a third control word based on the clock configuration parameter and the count value through the second register; Generate a third window signal based on a third control word and a multiplied clock signal by a second clock screening unit; A second target clock signal is generated by a second logic unit based on the third window signal and the input clock signal.

11. An audio conversion chip, characterized in that: The audio conversion chip comprises a clock signal generating system, an analog front end and at least one first decimation filter as claimed in any one of claims 1 to 5; wherein: The analog front end is connected to the clock signal generating system, and is used to receive the analog audio signal and oversample the analog audio signal based on the first target clock signal to generate a first sampling signal; The first decimation filter is connected to the clock signal generating system and the analog front end, and is used to generate a second sampling signal based on the first sampling signal and the first target clock signal.

12. The audio conversion chip according to claim 11, characterized in that: The audio conversion chip also includes a second decimation filter, which is connected to the clock generation system and the first decimation filter and is used to generate a digital audio signal based on the second sampling signal and the second target clock signal.

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