An instrument forced shutdown circuit and instrument

Abstract

The application discloses an instrument forced shutdown circuit and an instrument, and relates to the field of circuit protection. Wherein, the first and second input pins of an OR gate chip U1 are connected with first and second buttons KEY1 and KEY2 respectively; the first and second input pins of an NOR gate chip U2 are connected with the output pin of the OR gate chip U1 and a third button KEY3 respectively; KEY1, KEY2 and KEY3 are three different buttons on the instrument; the output pin of the NOR gate chip U2 is connected with the base of a transistor Q1 through a resistor R1; the collector of the transistor Q1 is connected with the base of a transistor Q2; the collector of the transistor Q2 is connected with the gate of a PMOS tube U3 through a resistor R5; the source of the PMOS tube U3 is connected with the positive pole of a battery, and the drain thereof is connected with the power supply circuit of a microcontroller. The application can realize the function of power-off after pressing the button without changing the appearance structure of the instrument, and there is no risk of false touch.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of circuit protection, in particular to an instrument forced shutdown circuit and an instrument. BACKGROUND

[0002] The existing battery-powered instrument contains a microcontroller unit (MCU) working device inside. If the working program has a problem, there is a risk of working crash. At this time, only the battery power can be disconnected to restore normal operation. However, the battery in such an instrument is often not easy to disassemble, and the MCU crash software shutdown cannot respond at this time. At this time, it is impossible to realize the shutdown operation, and only the battery power can be self-shutdown or disassembled and powered off. This method is extremely unfriendly to users. The existing solution is to add an additional hardware switch to force power off. This method will change the appearance structure of the instrument, and it is easy to be accidentally touched. Another solution is to use a hardware circuit integral delay method. This method requires long-pressing the key for tens of seconds, which is not friendly to users. SUMMARY

[0003] In view of the problems existing in the prior art, the purpose of the present application is to provide an instrument forced shutdown circuit and an instrument, which can realize the power-off function by pressing the key without changing the appearance structure of the instrument, and there is no risk of accidental touch.

[0004] To achieve the above purpose, the present application provides the following solutions.

[0005] In one aspect, the present application provides an instrument forced shutdown circuit, which comprises an or gate chip U1, an or not gate chip U2, a resistor R1, a resistor R2, a transistor Q1, a transistor Q2, a PMOS tube U3, a resistor R3, a resistor R4, a resistor R5, a resistor R6 and a capacitor C1.

[0006] The first input pin of the OR gate chip U1 is connected with the first button KEY1; the second input pin of the OR gate chip U1 is connected with the second button KEY2; the output pin of the OR gate chip U1 is connected with the first input pin of the NOR gate chip U2; the second input pin of the NOR gate chip U2 is connected with the third button KEY3; the output pin of the NOR gate chip U2 is connected with one end of the resistor R1; the other end of the resistor R1 is connected with the base of the transistor Q1 and one end of the resistor R2 respectively; the other end of the resistor R2 and the emitter of the transistor Q1 are grounded; the collector of the transistor Q1 is connected with one end of the resistor R3, one end of the resistor R4 and the base of the transistor Q2 respectively; the other end of the resistor R3 and the emitter of the transistor Q2 are grounded; the collector of the transistor Q2 is connected with one end of the resistor R5; the other end of the resistor R5 is connected with one end of the resistor R6, one end of the capacitor C1 and the gate of the PMOS transistor U3 respectively; the other end of the resistor R4, the other end of the resistor R6, the other end of the capacitor C1 and the source of the PMOS transistor U3 are all connected with the positive pole of the battery in the instrument; the negative pole of the battery is grounded; the drain of the PMOS transistor U3 is connected with the power supply circuit of the microcontroller in the instrument; the first button KEY1, the second button KEY2 and the third button KEY3 are three different buttons provided on the instrument.

[0007] Optionally, the first button KEY1, the second button KEY2 or the third button KEY3 is at low level when being pressed.

[0008] Optionally, the output pin of the OR gate chip U1 outputs low level when the first button KEY1 and the second button KEY2 are pressed simultaneously; otherwise, the output pin of the OR gate chip U1 outputs high level.

[0009] Optionally, the output pin of the NOR gate chip U2 outputs high level when the first button KEY1, the second button KEY2 and the third button KEY3 are pressed simultaneously; otherwise, the output pin of the NOR gate chip U2 outputs low level.

[0010] Optionally, when the output pin of the NOR gate chip U2 outputs high level, the transistor Q1 is turned on, the transistor Q2 is turned off and the PMOS transistor U3 is turned off; otherwise, the PMOS transistor U3 is turned on.

[0011] Optionally, the forced shutdown circuit of the instrument further comprises a fuse F1; the other end of the resistor R4, the other end of the resistor R6, the other end of the capacitor C1 and the source of the PMOS transistor U3 are all connected with the positive pole of the battery through the fuse F1.

[0012] Optionally, the or gate chip U1 and the nor gate chip U2 are powered by 3.3V voltage.

[0013] Optionally, the instrument and meter forced shutdown circuit further comprises a capacitor C3; a power supply pin of the or gate chip U1 is grounded through the capacitor C3.

[0014] Optionally, the instrument and meter forced shutdown circuit further comprises a capacitor C2; a power supply pin of the nor gate chip U2 is grounded through the capacitor C2.

[0015] In another aspect, the application further provides an instrument and meter powered by a battery and comprising the instrument and meter forced shutdown circuit.

[0016] According to the specific embodiments provided by the application, the following technical effects are disclosed:

[0017] In the instrument and meter forced shutdown circuit provided by the application, the first key KEY1, the second key KEY2 and the third key KEY3 are three different keys on the instrument and meter, so that no additional keys need to be added to the instrument and meter, which is a hidden design of key combination and does not affect the weight and appearance of the original instrument and meter. The combination design of three keys requires that the three keys are pressed at the same time to complete the shutdown function, so there is no problem of accidental touch, and the use safety is improved. The three keys are pressed at the same time to realize immediate forced shutdown, which not only avoids the inconvenience of too many combination keys, but also avoids the problem that the user needs to wait for tens of seconds to shut down, greatly shortening the shutdown waiting time. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the application or the prior art, the following will briefly introduce the drawings needed in the embodiments. Obviously, the drawings described below are only some embodiments of the application, and for those skilled in the art, other drawings can also be obtained from these drawings without creative labor.

[0019] Figure 1 It is a circuit connection schematic diagram of the instrument and meter forced shutdown circuit. DETAILED DESCRIPTION

[0020] The technical solutions in the embodiments of the application will be described clearly and completely below with reference to the drawings in the embodiments of the application. Obviously, the described embodiments are only some of the embodiments of the application, not all the embodiments. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the application.

[0021] The application aims to provide an instrument forced shutdown circuit and an instrument, which can realize the function of power-off after pressing the button without changing the appearance structure of the instrument and without the risk of accidental touch.

[0022] In order to make the above-mentioned purposes, features and advantages of the application more obvious and easy to understand, the application will be further described in detail below with reference to the drawings and specific embodiments.

[0023] In an exemplary embodiment, the application provides an instrument forced shutdown circuit. Figure 1 As shown in the figure, the instrument forced shutdown circuit comprises an OR gate chip U1, an NOR gate chip U2, a resistor R1, a resistor R2, a transistor Q1, a transistor Q2, a PMOS tube U3, a resistor R3, a resistor R4, a resistor R5, a resistor R6 and a capacitor C1.

[0024] The first input pin of the OR gate chip U1 is connected with a first button KEY1. The second input pin of the OR gate chip U1 is connected with a second button KEY2. The output pin of the OR gate chip U1 is connected with the first input pin of the NOR gate chip U2. The second input pin of the NOR gate chip U2 is connected with a third button KEY3. The output pin of the NOR gate chip U2 is connected with one end of the resistor R1. The other end of the resistor R1 is connected with the base of the transistor Q1 and one end of the resistor R2 respectively. The other end of the resistor R2 and the emitter of the transistor Q1 are grounded. The collector of the transistor Q1 is connected with one end of the resistor R3, one end of the resistor R4 and the base of the transistor Q2 respectively. The other end of the resistor R3 and the emitter of the transistor Q2 are grounded. The collector of the transistor Q2 is connected with one end of the resistor R5. The other end of the resistor R5 is connected with one end of the resistor R6, one end of the capacitor C1 and the gate of the PMOS tube U3 respectively. The other end of the resistor R4, the other end of the resistor R6, the other end of the capacitor C1 and the source of the PMOS tube U3 are all connected with the positive electrode of the battery in the instrument. The negative electrode of the battery is grounded. The drain of the PMOS tube U3 is connected with the power supply circuit of the microcontroller in the instrument. The first button KEY1, the second button KEY2 and the third button KEY3 are three different buttons provided on the instrument.

[0025] When the first button KEY1, the second button KEY2 or the third button KEY3 is pressed, it is low.

[0026] When the first button KEY1 and the second button KEY2 are pressed at the same time, the output pin of the OR gate chip U1 outputs low; otherwise, the output pin of the OR gate chip U1 outputs high.

[0027] When the first key KEY1, the second key KEY2 and the third key KEY3 are pressed simultaneously, the output pin of the NOR chip U2 outputs high level; otherwise, the output pin of the NOR chip U2 outputs low level.

[0028] When the output pin of the NOR chip U2 outputs high level, the transistor Q1 is turned on, the transistor Q2 is turned off, and the PMOS U3 is turned off; otherwise, the PMOS U3 is turned on.

[0029] In an exemplary embodiment, the instrument forced shutdown circuit further comprises a fuse F1. In this exemplary embodiment, the other end of the resistor R4, the other end of the resistor R6, the other end of the capacitor C1 and the source of the PMOS U3 are connected to the positive pole of the battery through the fuse F1. The fuse F1 is used for short circuit protection of the subsequent circuit.

[0030] In an exemplary embodiment, the instrument forced shutdown circuit further comprises a battery connection terminal J1. The battery connection terminal J1 comprises three ports, the 1# port of which is connected to one end of the fuse F1, used to introduce the positive pole power supply signal VBAT of the battery. The 2# port of the battery connection terminal J1 is connected to the NTC port of the battery, used to introduce the temperature signal NTC of the battery. The 3# port of the battery connection terminal J1 is grounded.

[0031] In an exemplary embodiment, the battery can be a two-section lithium battery, and the positive pole power supply signal VBAT voltage is 8.4V.

[0032] The PMOS U3 can adopt an HSBB2627 chip, which comprises three electrodes and 8 pins, the 1#, 2# and 3# pins of which are source pins S, and the source pins S are connected to the other end of the fuse F1. The 4# pin of the HSBB2627 chip is a gate pin G, which is respectively connected to the other end of the resistor R5, one end of the resistor R6 and one end of the capacitor C1. The 5#, 6#, 7# and 8# pins of the HSBB2627 chip are all drain pins D, which are connected to the power supply circuit of the MCU. VBAT_PWR is the power supply signal of the MCU.

[0033] The or gate chip U1 can adopt SN74AHC1G32DBVR chip. The No. 1 pin of the SN74AHC1G32DBVR chip is used as the first input pin of the or gate chip U1, and is used for connecting the first button KEY1, and the input signal is recorded as A. The No. 2 pin of the SN74AHC1G32DBVR chip is used as the second input pin of the or gate chip U1, and is used for connecting the second button KEY2, and the input signal is recorded as B. The No. 3 pin of the SN74AHC1G32DBVR chip is a ground pin (recorded as GND) and is used for grounding. The No. 4 pin of the SN74AHC1G32DBVR chip is used as the output pin of the or gate chip U1, and the output signal is recorded as Y. The No. 5 pin of the or gate chip U1 is a power supply pin (recorded as VCC) and is used for connecting 3.3V voltage for power supply.

[0034] In an exemplary embodiment, the instrument forced shutdown circuit further comprises: a capacitor C3; the power supply pin of the or gate chip U1 is grounded through the capacitor C3.

[0035] The or gate chip U1 is used to take the logical or of the input signals A and B of the first button KEY1 and the second button KEY2, and outputs through the output signal Y. The or gate logic of the or gate chip U1 is shown in Table 1 as follows.

[0036] Table 1 Or gate logic of or gate chip U1

[0037]

[0038] The or gate chip U1 can adopt SN74AHC1G32DBVR chip. The No. 1 pin of the SN74AHC1G32DBVR chip is used as the first input pin of the or gate chip U1, and is used for connecting the first button KEY1, and the input signal is recorded as A. The No. 2 pin of the SN74AHC1G32DBVR chip is used as the second input pin of the or gate chip U1, and is used for connecting the second button KEY2, and the input signal is recorded as B. The No. 3 pin of the SN74AHC1G32DBVR chip is a ground pin (recorded as GND) and is used for grounding. The No. 4 pin of the SN74AHC1G32DBVR chip is used as the output pin of the or gate chip U1, and the output signal is recorded as Y. The No. 5 pin of the or gate chip U1 is a power supply pin (recorded as VCC) and is used for connecting 3.3V voltage for power supply.

[0039] In an exemplary embodiment, the instrument forced shutdown circuit further comprises: a capacitor C2; the power supply pin of the or gate chip U1 is grounded through the capacitor C2. The capacitor C2 and the capacitor C3 are filter capacitors of the device.

[0040] The NOR gate chip U2 is used to take logical NOR of the output signal of the OR gate chip U1 and the input signals A, B of the second button KEY2, and output through the output signal Y. The NOR gate logic of the NOR gate chip U2 is shown in Table 2 below.

[0041] Table 2 NOR gate logic of the NOR gate chip U2

[0042]

[0043] In an exemplary embodiment, the model of the triode Q1 and the triode Q2 can adopt 2N5551. The triode Q1 includes three pins, the base of which is connected to the other end of the resistor R1 and one end of the resistor R2, respectively, the emitter of which is connected to the power ground, and the collector of which is connected to one end of the resistor R3, one end of the resistor R4, and the base of the triode Q2. The triode Q1 is used to isolate the battery input and drive the subsequent triode Q2.

[0044] The triode Q2 also includes three pins, the base of which is connected to one end of the resistor R3, one end of the resistor R4, and the collector of the triode Q1, the emitter of which is connected to the power ground, and the collector of which is connected to one end of the resistor R5. The triode Q2 is used to drive the PMOS tube U3.

[0045] The resistors R3, R4, R5, R6, the triode Q1 and the triode Q2 are collectively used to ensure the gate-source (GS) voltage of the PMOS tube U3, so that it is in a conductive state in a normal state. At this time, the positive supply signal VBAT of the battery normally supplies power to the MCU via the fuse F1 and the PMOS tube U3.

[0046] The input signals of the first button KEY1, the second button KEY2 and the third button KEY3 are high level 1 when the corresponding button is not pressed, and low level 0 when the corresponding button is pressed.

[0047] The resistor R2 is used to ensure that the triode Q1 is in a default off state when powered on.

[0048] In the instrument and meter forced shutdown circuit of the present application, suitable three buttons are selected from the original buttons of the instrument and meter as the first button KEY1, the second button KEY2 and the third button KEY3, and the input signals of the three buttons are connected to the input terminals A, B and C of the OR gate chip U1, respectively. Figure 1The instrument and meter forced shutdown circuit is connected between the battery and the MCU power supply circuit. Pressing any of the keys KEY1, KEY2, and KEY3 will not trigger the shutdown function of the circuit. Only pressing the three keys KEY1, KEY2, and KEY3 connected with the instrument and meter forced shutdown circuit at the same time can trigger the shutdown function. When the user presses the three keys at the same time, KEY1, KEY2, and KEY3 are at low level, or the input signals A and B of the or gate chip U1 are at low level 0, so the output signal Y of the or gate chip U1 is at low level 0. Further, at this time, the input signals A and B of the nor gate chip U2 are both at low level 0, and the output signal Y of the nor gate chip U2 is at high level 1, so the transistor Q1 is turned on. The transistor Q1 is turned on, causing the transistor Q2 to be cut off. The transistor Q2 is cut off, causing the GS voltage of the PMOS tube U3 to be less than the conduction voltage, and the PMOS tube U3 is turned off. After the PMOS tube U3 is turned off, the MCU power supply circuit in the back stage is disconnected from the battery, becoming a state without power supply. At this time, the supply voltage VBAT_PWR of the MCU is less than the working voltage of the MCU, that is, the power supply of the MCU is disconnected, and the shutdown can be realized.

[0049] In one exemplary embodiment, the application also provides an instrument and meter powered by a battery, and provided with Figure 1 The instrument and meter forced shutdown circuit can realize the forced power-off shutdown function when the MCU crashes. This way uses the original keys of the instrument and meter to add the forced shutdown function without adding additional keys, which is a combination hidden design and does not affect the weight and appearance of the original instrument and meter. The application adopts a combination design of three keys, which requires the three keys to be pressed at the same time to complete the shutdown function, so there is no problem of accidental touch, improving the safety of use. Pressing the three keys at the same time can realize immediate forced shutdown, which will not be inconvenient to operate because of too many combination keys, and there is no problem that the user needs to wait for tens of seconds to shut down. In addition, the instrument and meter forced shutdown circuit of the application adopts a low-power gate circuit device, whose power consumption is in the order of uA, which almost does not affect the original battery usage time of the instrument and meter, so it has a wide application prospect.

[0050] The technical features of the above embodiments can be combined in any way. To make the description concise, not all possible combinations of the technical features in the above embodiments are described, but as long as the combinations of the technical features do not exist contradictions, they should be considered as the scope of the present application.

[0051] The principles and implementation manners of the present application are described herein by using specific examples, and the above examples are only used to help understand the method of the present application and its core idea; meanwhile, for those skilled in the art, according to the idea of the present application, the specific implementation manners and application ranges will have changes. In conclusion, the content of the specification should not be understood as a limitation of the present application.

Claims

1. An instrument forced shutdown circuit, characterized by, Comprise: or gate chip U1, or not gate chip U2, resistance R1, resistance R2, triode Q1, triode Q2, PMOS tube U3, resistance R3, resistance R4, resistance R5, resistance R6 and capacitor C1; The first input pin of the or gate chip U1 is connected with the first button KEY1; the second input pin of the or gate chip U1 is connected with the second button KEY2; the output pin of the or gate chip U1 is connected with the first input pin of the or not gate chip U2; the second input pin of the or not gate chip U2 is connected with the third button KEY3; the output pin of the or not gate chip U2 is connected with one end of the resistance R1; the other end of the resistance R1 is connected with the base of the triode Q1 and one end of the resistance R2 respectively; the other end of the resistance R2 and the emitter of the triode Q1 are grounded; the collector of the triode Q1 is connected with one end of the resistance R3, one end of the resistance R4 and the base of the triode Q2 respectively; the other end of the resistance R3 and the emitter of the triode Q2 are grounded; the collector of the triode Q2 is connected with one end of the resistance R5; the other end of the resistance R5 is connected with one end of the resistance R6, one end of the capacitor C1 and the gate of the PMOS tube U3 respectively; the other end of the resistance R4, the other end of the resistance R6, the other end of the capacitor C1 and the source of the PMOS tube U3 are all connected with the positive pole of the battery in the instrument; the negative pole of the battery is grounded; the drain of the PMOS tube U3 is connected with the power supply circuit of the microcontroller in the instrument; the first button KEY1, the second button KEY2 and the third button KEY3 are three different buttons on the instrument, which do not need to add extra buttons on the instrument, belonging to the hidden design of button combination; the combination design of three buttons is adopted, and the three buttons are pressed at the same time to complete the shutdown function; and the three buttons are pressed at the same time to realize immediate forced shutdown; When the first button KEY1, the second button KEY2 or the third button KEY3 is pressed, it is low level; When the first button KEY1 and the second button KEY2 are pressed at the same time, the output pin of the or gate chip U1 outputs low level; otherwise, the output pin of the or gate chip U1 outputs high level; When the first button KEY1, the second button KEY2 and the third button KEY3 are pressed at the same time, the output pin of the or not gate chip U2 outputs high level; otherwise, the output pin of the or not gate chip U2 outputs low level; When the output pin of the or not gate chip U2 outputs high level, the triode Q1 is turned on, the triode Q2 is cut off, and the PMOS tube U3 is turned off; otherwise, the PMOS tube U3 is turned on.

2. An instrument forced shutdown circuit according to claim 1, wherein, Further comprise: Fuse F1; the other end of the resistance R4, the other end of the resistance R6, the other end of the capacitor C1 and the source of the PMOS tube U3 are all connected to the positive pole of the battery through the fuse F1.

3. The instrument forced shutdown circuit of claim 1, wherein, The or gate chip U1 and the nor gate chip U2 are powered by 3.3V voltage.

4. The instrument forced shutdown circuit of claim 1, wherein, Further comprising: A capacitor C3; the power supply pin of the or gate chip U1 is grounded through the capacitor C3.

5. The instrument forced shutdown circuit of claim 1, wherein, Further comprising: A capacitor C2; the power supply pin of the nor gate chip U2 is grounded through the capacitor C2.

6. An instrument powered by a battery, characterized in that The instrument and apparatus forced shutdown circuit of any one of claims 1 to 5.

Images