Neural network predicts wireless signal quality

Abstract

The present invention discloses a neural network predicting the quality of a wireless signal, and specifically discloses an apparatus, system, and technology for using one or more neural networks to generate a prediction of the quality of one or more wireless signals to be transmitted, wherein the prediction is based at least in part on one or more reference signals. In at least one embodiment, a measurement report is generated by one or more neural networks.

Description

Technical Field

[0001] At least one embodiment relates to using a neural network for measurement reporting of wireless signals. For example, at least one embodiment relates to a processor or computing system for generating a prediction of the quality of one or more wireless signals to be transmitted, wherein the prediction is based at least in part on one or more reference signals. Background Art

[0002] When a user equipment (UE) is connected to a radio access network (RAN), it can monitor the connection between the UE and the RAN (e.g., the connection to the radio unit and / or base station). This process is often referred to as measurement and reporting, which can present some challenges. For example, if RLM typically involves periodically measuring and reporting radio link measurements from the UE to the RAN (e.g., base station), which involves the use of computing resources, bandwidth, and power, there is a need to improve radio link measurement and reporting. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Figure 1 is a block diagram illustrating a computing system of a user device according to at least one embodiment;

[0004] Figure 2 is a diagram illustrating measurement report initialization by prediction according to at least one embodiment;

[0005] Figure 3 is a flow chart illustrating measurement report initialization by predicting a triggering event according to at least one embodiment;

[0006] Figure 4 is a diagram illustrating measurement report initialization by predicting trigger event entry and exit according to at least one embodiment;

[0007] Figure 5 is a flow chart illustrating measurement report initialization by predicting event entry and exit according to at least one embodiment;

[0008] Figure 6 is a flow chart illustrating identification and configuration for measurement report volume prediction according to at least one embodiment;

[0009] Figure 7 is a block diagram illustrating a beam-specific model for predicting beam measurements according to at least one embodiment;

[0010] Figure 8 is a flow chart illustrating fusion of predicted beam measurements according to at least one embodiment;

[0011] Figure 9is a block diagram illustrating a cell-specific model for predicting cell measurement quantities according to at least one embodiment;

[0012] Figure 10 is an exemplary system illustrating measurement reporting in accordance with at least one embodiment;

[0013] Figure 11 is a block diagram illustrating a driver and / or runtime including one or more libraries to provide one or more application programming interfaces (APIs) according to at least one embodiment;

[0014] Figure 12 An example data center system is shown in accordance with at least one embodiment;

[0015] Figure 13A An example of an autonomous vehicle according to at least one embodiment is shown;

[0016] Figure 13B According to at least one embodiment, Figure 13A Examples of camera positions and fields of view for autonomous vehicles;

[0017] Figure 13C According to at least one embodiment Figure 13A A block diagram of an example system architecture for an autonomous vehicle;

[0018] Figure 13D is a diagram illustrating a method for one or more cloud-based servers and Figure 13A A diagram of a system for communicating between autonomous vehicles;

[0019] Figure 14 is a block diagram illustrating a computer system according to at least one embodiment;

[0020] Figure 15 is a block diagram illustrating a computer system according to at least one embodiment;

[0021] Figure 16 A computer system according to at least one embodiment is shown;

[0022] Figure 17 A computer system according to at least one embodiment is shown;

[0023] Figure 18A A computer system according to at least one embodiment is shown;

[0024] Figure 18B A computer system according to at least one embodiment is shown;

[0025] Figure 18C A computer system according to at least one embodiment is shown;

[0026] Figure 18D A computer system according to at least one embodiment is shown;

[0027] Figure 18E and Figure 18F illustrates a shared programming model according to at least one embodiment;

[0028] Figure 19 An exemplary integrated circuit and associated graphics processor are shown in accordance with at least one embodiment;

[0029] Figure 20A and Figure 20B An exemplary integrated circuit and associated graphics processor are shown in accordance with at least one embodiment;

[0030] Figure 21A and Figure 21B Additional exemplary graphics processor logic is shown in accordance with at least one embodiment;

[0031] Figure 22 A computer system according to at least one embodiment is shown;

[0032] Figure 23A A parallel processor according to at least one embodiment is shown;

[0033] Figure 23B shows a partition unit according to at least one embodiment;

[0034] Figure 23C illustrates a processing cluster according to at least one embodiment;

[0035] Figure 23D A graphics multiprocessor is shown in accordance with at least one embodiment;

[0036] Figure 24 A multi-graphics processing unit (GPU) system is shown in accordance with at least one embodiment;

[0037] Figure 25 A graphics processor according to at least one embodiment is shown;

[0038] Figure 26 is a block diagram illustrating a processor microarchitecture for a processor according to at least one embodiment;

[0039] Figure 27 illustrates at least a portion of a graphics processor according to one or more embodiments;

[0040] Figure 28 illustrates at least a portion of a graphics processor according to one or more embodiments;

[0041] Figure 29illustrates at least a portion of a graphics processor according to one or more embodiments;

[0042] Figure 30 is a block diagram of a graphics processing engine of a graphics processor according to at least one embodiment;

[0043] Figure 31 is a block diagram of at least a portion of a graphics processor core according to at least one embodiment;

[0044] Figure 32A and Figure 32B Thread execution logic including an array of processing elements of a graphics processor core is shown in accordance with at least one embodiment;

[0045] Figure 33 illustrates a parallel processing unit ("PPU") in accordance with at least one embodiment;

[0046] Figure 34 illustrates a general processing cluster ("GPC") in accordance with at least one embodiment;

[0047] Figure 35 illustrates a memory partitioning unit of a parallel processing unit ("PPU") according to at least one embodiment;

[0048] Figure 36 A streaming multiprocessor is shown in accordance with at least one embodiment;

[0049] Figure 37 A network for communicating data within a 5G wireless communication network is shown in accordance with at least one embodiment;

[0050] Figure 38 illustrates a network architecture for a 5G LTE wireless network according to at least one embodiment;

[0051] Figure 39 is a diagram illustrating some basic functionality of a mobile telecommunications network / system operating according to LTE and 5G principles, according to at least one embodiment;

[0052] Figure 40 illustrates a radio access network that may be part of a 5G network architecture in accordance with at least one embodiment;

[0053] Figure 41 An example illustration of a 5G mobile communication system in which multiple different types of devices are used is provided according to at least one embodiment;

[0054] Figure 42 An example high-level system according to at least one embodiment is shown;

[0055] Figure 43shows the architecture of a network system according to at least one embodiment;

[0056] Figure 44 illustrates example components of a device according to at least one embodiment;

[0057] Figure 45 illustrates an example interface for a baseband circuit according to at least one embodiment;

[0058] Figure 46 An example of an uplink channel according to at least one embodiment is shown;

[0059] Figure 47 shows the architecture of a network system according to at least one embodiment;

[0060] Figure 48 illustrates a control plane protocol stack according to at least one embodiment;

[0061] Figure 49 illustrates a user plane protocol stack according to at least one embodiment;

[0062] Figure 50 illustrates components of a core network according to at least one embodiment;

[0063] Figure 51 Components of a system supporting network function virtualization (NFV) according to at least one embodiment are shown; and

[0064] Figure 52 Components of a system for accessing large language models in accordance with at least one embodiment are shown. DETAILED DESCRIPTION

[0065] In the following description, numerous specific details are set forth to provide a more thorough understanding of at least one embodiment. However, it will be apparent to one skilled in the art that the concepts of the present invention may be practiced without one or more of these specific details.

[0066] In at least one embodiment, the algorithm for measuring and reporting the quality of fifth-generation (5G) radio links from user equipment (UE) devices to base stations has high latency. For example, this is because the current algorithm requires the UE to measure properties of the wireless signal over a period of time and then send reports of these properties to the base station. If the UE does not report measurements indicating poor signal quality quickly enough, there may not be enough time to mitigate the situation.

[0067] In at least one embodiment, the disclosed technology includes an apparatus, system, processor, circuit, process, computer-readable instructions, or other software for generating wireless signal reports using a neural network to predict measurement results of wireless signals based on a reference signal. In at least one embodiment, a processor including circuitry uses one or more neural networks to generate a measurement report based at least in part on one or more predictions of one or more measurement results of one or more wireless signals generated by the one or more neural networks. In at least one embodiment, the measurement report is a data structure that includes measurement results of wireless signals received by a UE device, wherein the measurement report may include information such as power, detected frequency, signal-to-noise ratio, or other parameters defined by a third generation partnership project (e.g., 5G). In at least one embodiment, the base station uses the measurement report to generate instructions for the UE. For example, if the measurement report indicates low power, the base station may instruct the UE to use a different base station.

[0068] In at least one embodiment, the processor executes software to detect a trigger event (e.g., low signal quality or low power in a signal) and accordingly provides a recently received reference signal to a neural network that predicts what future measurements of the signal will be. In at least one embodiment, this allows the use of a neural network to generate a measurement report without having to perform measurements for a period of time prior to the report.

[0069] Figure 1 is a block diagram illustrating a computing system 100 for a user device 110 according to at least one embodiment. In at least one embodiment, the computing system 100 is a set of computing components configured to execute one or more software programs and / or other operations to cause one or more computing components in the set of computing components to perform one or more computing operations. In at least one embodiment, the computing system 100 performs radio resource control (RRC) measurements to identify a radio link condition with the user device. In at least one embodiment, the processor 120 includes one or more circuits configured to use a neural network 140 to generate a prediction of the quality of one or more wireless signals to be transmitted, wherein the prediction is based at least in part on one or more reference signals. In at least one embodiment, the computing system 100 includes one or more processors 120 configured to use a neural network 140 to generate a prediction of the quality of one or more wireless signals to be transmitted, wherein the prediction is based at least in part on one or more reference signals.

[0070] In at least one embodiment, the UE 110 and the base station 160 communicate using a radio link 180. In at least one embodiment, the base station 160 is connected to the network 170 (e.g., wired, wireless, or a combination thereof). In at least one embodiment, the computing system 100 predicts a measurement report amount for one or more wireless signals. In at least one embodiment, the computing system 100 generates a measurement report based on the predicted measurement results. In at least one embodiment, the measurement report can be a data structure that includes measurement results of wireless signals received by the UE device. In at least one embodiment, the measurement report can include information such as power, detected frequency, reference signal received power (RSRP), reference signal received quality (RSRQ), and signal-to-interference-plus-noise ratio (SINR). In at least one embodiment, the base station 160 can use the measurement report to generate instructions for the UE 110. In at least one embodiment, the base station 160 performs mitigation measures based on the measurement report.

[0071] In at least one embodiment, UE 110 is any device used by an end user to communicate. In at least one embodiment, UE 110 may include a cellular phone, a laptop, a server, a computer, and any other hardware device capable of communication. In at least one embodiment, UE 110 includes any device capable of communicating via 3GPP-LTE, 4G, 5G New Radio (5G-NewRadio) wireless network, sixth generation (6G) wireless network, or other wireless communication standards from the Third Generation Partnership Project. In at least one embodiment, UE 110 includes one or more processors 120, a measurement module 130, one or more neural networks 140, and one or more memories 150. In at least one embodiment, UE 110 may be a device that provides a user with access to network services. In at least one embodiment, UE 110 is any component (or collection of components) capable of establishing a wireless connection with a base station 160.

[0072] In at least one embodiment, the processor 120 is a set of circuits for performing one or more operations in response to one or more instructions. In at least one embodiment, the one or more processors 110 are one or more x86-based CPUs. In at least one embodiment, the processor 120 (e.g., a CPU) includes one or more CPU circuits for performing one or more computing operations. In at least one embodiment, the processor 120 is a CPU. In at least one embodiment, the processor 120 is any other processor further described herein. In at least one embodiment, the processor 120 includes any circuit configuration for performing one or more computing operations further described herein. In at least one embodiment, the processor 120 may include several processors (e.g., 10 CPUs), including different types of processors (CPU, GPU, ASIC, data processing unit, FPGA) and different types of processing cores.

[0073] In at least one embodiment, processor 120 includes instructions for executing, using, or implementing measurement module 130. In at least one embodiment, measurement module 130 is a set of instructions that, if executed by one or more processors, causes the one or more processors to measure downlink reference signals. In at least one embodiment, downlink reference signals may include synchronization signal blocks (SSBs) and channel state information reference signals (CSI-RSs). In at least one embodiment, the measured one or more reference signals are input to neural network 140.

[0074] In at least one embodiment, the processor 120 includes instructions for executing, using, or implementing one or more neural networks 140. In at least one embodiment, the neural network 140 is any combination of any type of logic (e.g., software, hardware, firmware) and / or circuitry configured to perform training, learning, or inference of reference signals. In at least one embodiment, the processor 120 uses the neural network 140 to predict RRC measurement report quantities. In at least one embodiment, the processor 120 trains the neural network 140 to predict measurement report quantities. In at least one embodiment, the measurement report quantities include reference signal received power (RSRP), reference signal received quality (RSRQ), and signal to interference plus noise ratio (SINR). In at least one embodiment, the neural network 140 predicts the quality of one or more reference signals based at least in part on one or more reference signals. In at least one embodiment, the neural network 140 can be used for 3G, 4G, 5G, 6G, and other wireless communication protocols.

[0075] In at least one embodiment, the measurement report amount is predicted when the trigger event condition is met. In at least one embodiment, the trigger event may include event A1 (e.g., service becomes better than a threshold), event A2 (e.g., service becomes worse than a threshold), event A3 (e.g., neighbor becomes offset better than SpCell), event A4 (neighbor becomes better than a threshold), event A5 (e.g., SpCell becomes worse than threshold 1 and the neighbor becomes better than threshold 2), and event A6 (e.g., neighbor becomes offset better than SCell). In at least one embodiment, the trigger event has an entry condition and an exit condition. In at least one embodiment, by way of example, the entry condition is that the power measurement result of the signal is lower than a threshold, and the exit condition is that the power measurement result of the signal is higher than a threshold. In at least one embodiment, the event occurs when the entry condition is met. In at least one embodiment, the event ends when the exit condition is met. In at least one embodiment, the neural network 140 performs predictions based on the trigger event.

[0076] In at least one embodiment, the neural network 140 includes a convolutional neural network (CNN), a transform, an encoder, a decoder, a recurrent neural network (RNN), a long short-term memory (LSTM), a radial basis network (RBN), an autoencoder (AE), a Boltzmann machine (BM), a restricted Boltzmann machine (RBM), a deep belief network (DBN), a deep convolutional network (DCN), an extreme learning machine (ELM), a deep residual network (DRN), and / or any combination thereof. In at least one embodiment, one or more reference signals are one or more inputs to the neural network 140, and predicted measurement results of one or more wireless signals are one or more outputs of the neural network 140. In at least one embodiment, the processor 120 may execute, use, or train the neural network 140 to predict measurement results of the one or more wireless signals based at least in part on the one or more reference signals. In at least one embodiment, the processor 120 may execute, use, or train the neural network 140 to generate a measurement report based at least in part on the one or more predicted measurement results of the one or more wireless signals. In at least one embodiment, processor 120 may execute, use, or train neural network 140 to predict the quality of one or more wireless signals based at least in part on one or more reference signals.

[0077] In at least one embodiment, processor 120 includes memory 150. In at least one embodiment, memory 150 is hardware that includes circuitry for storing data. In at least one embodiment, memory 150 is a dynamic random access memory ("DRAM") device, a static random access memory ("SRAM") device, a flash memory device, a phase change memory device, or some other memory device with suitable performance for use as processor memory. In at least one embodiment, memory 150 stores one or more reference signals, one or more predicted measurement results, and one or more measurement reports.

[0078] In at least one embodiment, as shown, base station 160 establishes an uplink connection and / or a downlink connection with UE 110 for transporting data from UE 110 to base station 160 and vice versa. In at least one embodiment, the data transported via the uplink / downlink connection may include data transmitted between UEs 110, as well as data transmitted to / from a remote end (not shown) via network 170. In at least one embodiment, base station 160 is any component (or collection of components) configured to provide wireless access to network 170, such as an enhanced base station (eNB), a macro cell, a femto cell, a Wi-Fi access point (AP), or other wireless-enabled device. In at least one embodiment, base station 160 may provide wireless access according to one or more wireless communication protocols, such as Long Term Evolution (LTE), LTE-Advanced (LTE-A), High Speed ​​Packet Access (HSPA), Wi-Fi 802.11a / b / g / n / ac, etc. In at least one embodiment, base station 160 transmits a reference signal to UE 110 in a downlink manner.

[0079] In at least one embodiment, base station 160 is a transceiver that serves as a communication point for one or more UEs 110. In at least one embodiment, base station 160 can transmit and receive wireless signals. In at least one embodiment, base station 160 includes one or more radio frequency (RF) antennas to transmit and receive RF signals for other devices (e.g., UE 110). In at least one embodiment, base station 160 can transmit and receive fifth generation new radio (5G-NR) signals, including reference signals. In at least one embodiment, the disclosed technology can be used for 3G, 4G, LTE, 6G, and other wireless standards generated by IEEE or 3GPP.

[0080] In at least one embodiment, base station 160 wirelessly communicates with UE 110 using radio link 180 to transmit, receive, or otherwise share information, such as data packets, reference signals, or other communications. In at least one embodiment, UE 110 transmits a prediction of the quality of one or more wireless signals. In at least one embodiment, the prediction is based at least in part on one or more reference signals. In at least one embodiment, the prediction is a measurement report. In at least one embodiment, UE 110 receives the reference signal and transmits it to base station 160. In at least one embodiment, UE 110 predicts the measurement results and transmits them to base station 160. In at least one embodiment, base station 160 provides mitigation measures based on the predicted measurement results from UE 110. In at least one embodiment, UE 110 predicts the quality of one or more wireless signals and transmits them to base station 160. In at least one embodiment, base station 160 provides mitigation measures based on the quality of one or more wireless signals. In at least one embodiment, base station 160 uses neural network 140 to predict the measurement results of one or more wireless signals. In at least one embodiment, if the predicted measurement result indicates low power, base station 160 may instruct UE 110 to use a different base station. In at least one embodiment, UE 110 and base station 160 may generate a measurement report. In at least one embodiment, if the measurement report indicates low power, base station 160 may instruct UE 110 to use a different base station. In at least one embodiment, base station 160 may use or execute each component of UE 110.

[0081] Figure 2 is a diagram illustrating measurement report initialization by prediction according to at least one embodiment. In at least one embodiment, example 200 illustrates radio resource control (RRC) measurements and predicted future RRC measurement report amounts. In at least one embodiment, Figure 1 The measurement module 130 measures, monitors, receives, and / or analyzes one or more reference signals 201a-201n. In at least one embodiment, the UE 110 performs RRC measurements based on the downlink reference signals and predicts future RRC measurement report quantities. In at least one embodiment, the reference signals used to predict future RRC measurement report quantities may be all SSBs, all CSI-RSs, or a mixture of SSBs and CSI-RSs. In at least one embodiment, the predicted RRC measurement report quantities may be RSRP, RSRQ, SINR, or a combination thereof.

[0082] In at least one embodiment, reference signals 201a-201n are collected at respective past times t[-P]-t[0]. In at least one embodiment, reference signals 201a-201n are collected and / or measured during measurement window 210. In at least one embodiment, at past time t[-P], measurement module 130 collects and / or measures respective reference signal 201a. In at least one embodiment, while only three time instances are depicted, measurement module 130 may collect and / or measure any number of reference signals. In at least one embodiment, measurement module 130 sends each reference signal to neural network 140.

[0083] In at least one embodiment, when a triggering event condition is met, UE 110 initiates a procedure for predicting future RRC measurement report quantities. In at least one embodiment, the triggering event condition can be an event entry condition or an event exit condition. In at least one embodiment, a Layer 3 filtered measurement result must meet the triggering event condition. In at least one embodiment, UE 110 predicts whether all Layer 3 filtered measurement results meet the triggering event condition. In at least one embodiment, neural network 140 is used to predict Layer 3 filtered measurement results 211-213 during a future time duration 220.

[0084] In at least one embodiment, when the triggering event condition is met, UE 110 predicts whether all Layer 3 measurement results meet the triggering event condition. In at least one embodiment, if UE 110 predicts that all Layer 3 measurement results meet the triggering event condition, UE 110 initiates a measurement reporting procedure. In at least one embodiment, if UE 110 predicts that one or more Layer 3 measurement results do not meet the triggering event condition, UE 110 does not initiate a measurement reporting procedure. In at least one embodiment, a measurement reporting procedure is an instruction to generate a measurement report.

[0085] Figure 3 FIG. 3 is a process 300 illustrating measurement report initialization by predicting a triggering event according to at least one embodiment. In at least one embodiment, the process 300 is used by the UE 110 Figure 1 In at least one embodiment, the process 300 is described as above. Figure 2 In at least one embodiment, Figure 12-52 The system and processor disclosed in

[0045] performs all or part of process 300. In at least one embodiment, process 300 includes one or more steps of performing a method comprising using one or more neural networks to generate a prediction of the quality of one or more wireless signals to be transmitted, wherein the prediction is based at least in part on one or more reference signals.

[0086] In at least one embodiment, in step 310, a reference signal is measured to perform an RRC measurement report. In at least one embodiment, step 310 is performed by Figure 1 In at least one embodiment, the reference signal is executed as described above. Figure 1-2 . In at least one embodiment, the measurement module 130 receives and / or measures reference signals during the measurement window 210. In at least one embodiment, in the measure reference signals step 310, the processor 120 in the UE 110 receives one or more reference signals. In at least one embodiment, the one or more reference signals are measured during the measurement window 210 at each time instance 201a-201n.

[0087] In at least one embodiment, in step 320, UE 110 determines whether a triggering event condition is satisfied at the current time T0. In at least one embodiment, step 320 is performed by Figure 1 Processor 120 executes. In at least one embodiment, if UE 110 determines in step 320 that the trigger event condition is not met, process 300 proceeds to step 360. In at least one embodiment, if UE 110 determines in step 320 that the trigger event condition is met, process 300 proceeds to step 330. In at least one embodiment, the entry condition of the event and the exit condition of the event are configured as equal values. In at least one embodiment, the entry condition and the exit condition of the event are configured as different values. In at least one embodiment, a first parameter value, timeToTriggerForEntering, is defined for the entry condition of the event. In at least one embodiment, a second parameter value, timeToTriggerForLeaving, is defined for the exit condition of the event.

[0088] In at least one embodiment, in step 330, UE 110 predicts a future time duration (e.g., Figure 2 In at least one embodiment, step 330 is performed by Figure 1 The processor 120 and the neural network 140 are executed by the UE 110. In at least one embodiment, the UE 110 uses the neural network 140 to predict the measurement report quantity, such as 211-213, within the future time duration 220. In at least one embodiment, the measurement report quantity may include reference signal received power (RSRP), reference signal received quality (RSRQ), and signal to interference plus noise ratio (SINR).

[0089] In at least one embodiment, in step 340, UE 110 determines whether all predicted measurement report quantities satisfy the triggering event condition. In at least one embodiment, step 340 is performed by Figure 1In at least one embodiment, if UE 110 determines at step 340 that the predicted measurement result does not satisfy the triggering event, process 300 proceeds to step 360. In at least one embodiment, if UE 110 determines at step 340 that the predicted measurement result satisfies the triggering event, process 300 proceeds to step 350.

[0090] In at least one embodiment, in step 350, UE 110 initiates a measurement reporting procedure. In at least one embodiment, step 350 is performed by Figure 1 The processor 120 is executed. In at least one embodiment, if all predicted measurement report quantities meet the triggering event, the measurement reporting procedure is initiated. In at least one embodiment, when the first measurement reporting procedure is initiated, the UE 110 does not initialize the second measurement reporting procedure until a specific time duration reportIntervalMin has passed after the time when the first measurement reporting procedure is initiated. In at least one embodiment, reportIntervalMin is the minimum time interval between two measurement reporting initialization procedures. In at least one embodiment, the minimum time interval is user-configurable. In at least one embodiment, at the current time when the measurement reporting procedure is about to be triggered, the UE 110 predicts a future time when a subsequent measurement reporting procedure will be triggered. In at least one embodiment, if the time interval between the future time and the current time is less than a time duration equal to reportIntervalMin, the UE 110 does not initiate the first measurement reporting procedure at the current time.

[0091] In at least one embodiment, UE 110 does not initiate a measurement reporting procedure in step 360. In at least one embodiment, step 360 is performed by Figure 1 In at least one embodiment, if the reference signal does not satisfy the triggering event condition in step 320, the measurement reporting procedure is not initiated. In at least one embodiment, if the predicted measurement report amount does not satisfy the triggering event condition in step 340, the measurement reporting procedure is not initiated.

[0092] Figure 4 is a diagram illustrating measurement report initialization by predicting trigger event entry and exit according to at least one embodiment. In at least one embodiment, example 400 illustrates radio resource control (RRC) measurement and predicted trigger event entry and exit. In at least one embodiment, Figure 1 The measurement module 130 measures, monitors, receives and / or analyzes one or more reference signals 401a-401n. In at least one embodiment, the UE 110 performs RRC measurements based on the downlink reference signals and predicts future RRC measurement report quantities.

[0093] In at least one embodiment, reference signals 401a - 401n are collected at corresponding past times t[-P] - t[0]. In at least one embodiment, reference signals 401a - 401n are collected and / or measured during measurement window 410. In at least one embodiment, at past time t[-P], measurement module 130 collects and / or measures corresponding reference signal 401a. In at least one embodiment, although only three time instances are depicted, measurement module 130 can collect and / or measure any number of reference signals. In at least one embodiment, measurement module 130 sends each reference signal to neural network 140.

[0094] In at least one embodiment, neural network 140 is used to predict the layer-3 filtered measurement results 411 - 414 and 421 - 423 within a future time duration. In at least one embodiment, the layer-3 filtered measurement results 411 - 413 are predicted at 420. In at least one embodiment, the layer-3 filtered measurement results 421 - 423 are predicted at 430. In at least one embodiment, 440 shows the event entry condition that is first satisfied at time T0. In at least one embodiment, 460 shows the event exit condition that is first satisfied at time T1. In at least one embodiment, 460 and 470 show the potential times for measurement report initialization.

[0095] In at least one embodiment, after the event entry condition is satisfied at time T0, if UE 110 predicts that all layer-3 filtered measurements will satisfy the event entry condition, then UE 110 predicts a future time T1 when the event exit condition is satisfied at time T1. In at least one embodiment, if (T1 + timeToTriggerForLeaving) – (T0 + timeToTriggerForEntering) ≥ reportIntervalMin, then UE 110 initiates a measurement reporting procedure at the current time T0. In at least one embodiment, if (T1 + timeToTriggerForLeaving) – (T0 + timeToTriggerForEntering) < reportIntervalMin, then UE 110 predicts whether all layer-3 filtered measurement results 421 - 423 obtained during 430 will satisfy the event exit condition. In at least one embodiment, if the event exit condition is satisfied, then UE 110 does not initiate a measurement reporting procedure at the current time T0. In at least one embodiment, if the event exit condition is not satisfied, then UE 110 initiates a measurement reporting procedure at the current time T0.

[0096] Figure 5FIG. 5 is a process 500 illustrating measurement report initialization by predicting event entry and exit according to at least one embodiment. In at least one embodiment, UE 110 uses Figure 1 The processor 120 and the neural network 140 perform the process 500. In at least one embodiment, Figure 12-52 The system and processor disclosed in

[0066] performs all or part of process 500. In at least one embodiment, process 500 includes one or more steps for performing a method comprising using one or more neural networks to generate a prediction of the quality of one or more wireless signals to be transmitted, wherein the prediction is based at least in part on one or more reference signals.

[0097] In at least one embodiment, in step 502, a reference signal is measured to perform an RRC measurement report. In at least one embodiment, step 502 is performed by Figure 1 In at least one embodiment, as described above, Figure 1-4 In at least one embodiment, the measurement module 130 receives and / or measures the reference signal during the measurement window 410. In at least one embodiment, in the measure reference signal step 502, the processor 120 in the UE 110 receives one or more reference signals. In at least one embodiment, the one or more reference signals are measured during the measurement window 410 at each time instance 401a-401n.

[0098] In at least one embodiment, in step 504, UE 110 determines whether a trigger event entry condition is satisfied at the current time T0. In at least one embodiment, step 504 is performed by Figure 1 Processor 120 executes. In at least one embodiment, if UE 110 determines at step 504 that the trigger event entry condition is not met, process 500 proceeds to step 520. In at least one embodiment, if UE 110 determines at step 504 that the trigger event entry condition is met, process 500 proceeds to step 506. In at least one embodiment, the event entry condition and the event exit condition are configured as equal values. In at least one embodiment, the event entry condition and the event exit condition are configured as different values. In at least one embodiment, a first parameter value, timeToTriggerForEntering, is defined for the event entry condition. In at least one embodiment, a second parameter value, timeToTriggerForLeaving, is defined for the event exit condition.

[0099] In at least one embodiment, in step 506, UE 110 predicts a future time duration (e.g., Figure 4All measurement report quantities obtained within (420). In at least one embodiment, step 506 is performed by Figure 1 processor 120 and neural network 140. In at least one embodiment, UE 110 uses neural network 140 to predict the measurement report quantities (such as 411 - 413) within the future time duration 420 of the entry condition. In at least one embodiment, the measurement report quantities may include reference signal received power (RSRP), reference signal received quality (RSRQ), and signal-to-interference plus noise ratio (SINR).

[0100] In at least one embodiment, in step 508, UE 110 determines whether all predicted measurement report quantities satisfy the trigger event entry condition. In at least one embodiment, step 508 is performed by Figure 1 processor 120. In at least one embodiment, if UE 110 determines at step 508 that the predicted measurement results do not satisfy the trigger event entry condition, then process 500 proceeds to step 520. In at least one embodiment, if UE 110 determines at step 308 that the predicted measurement results satisfy the trigger event entry condition, then process 500 proceeds to step 510.

[0101] In at least one embodiment, in step 510, UE 110 predicts the future time T1 at which the trigger event exit condition will be satisfied. In at least one embodiment, step 510 is performed by Figure 1 processor 120.

[0102] In at least one embodiment, in step 512, UE 110 determines whether the time measurement results satisfy the condition. In at least one embodiment, step 512 is performed by Figure 1 processor 120. In at least one embodiment, UE 110 determines whether (T1 + timeToTriggerForLeaving) – (T0 + timeToTriggerForEntering) ≥ reportIntervalMin. In at least one embodiment, if (T1 + timeToTriggerForLeaving) – (T0 + timeToTriggerForEntering) ≥ reportIntervalMin, then process 500 continues to step 518. In at least one embodiment, if (T1 + timeToTriggerForLeaving) – (T0 + timeToTriggerForEntering) < reportIntervalMin, then UE 110 proceeds to step 514.

[0103] In at least one embodiment, in step 514, UE 110 predicts all measurement report quantities that are in the future time duration ( Figure 4 In at least one embodiment, step 514 is performed by Figure 1 The processor 120 and the neural network 140 in the UE 110 are executed. In at least one embodiment, the UE 110 uses the neural network 140 to predict the measurement report amount, such as 421-423, within the future time duration 430 of the departure condition. In at least one embodiment, the measurement report amount may include reference signal received power (RSRP), reference signal received quality (RSRQ), and signal to interference plus noise ratio (SINR).

[0104] In at least one embodiment, in step 516, UE 110 determines whether the predicted measurement result meets the condition. In at least one embodiment, step 516 is performed by Figure 1 Processor 120 executes. In at least one embodiment, UE 110 determines whether all predicted measurement results 421-423 meet the trigger event leaving condition. In at least one embodiment, if UE 110 determines in step 516 that the predicted measurement results do not meet the trigger event leaving condition, process 500 proceeds to step 518. In at least one embodiment, if UE 110 determines in step 516 that the predicted measurement results meet the trigger event leaving condition, process 500 proceeds to step 520.

[0105] In at least one embodiment, in step 518, UE 110 initiates a measurement reporting procedure. In at least one embodiment, step 518 is performed by Figure 1 In at least one embodiment, if one or more predicted measurement report quantities 421-423 do not satisfy the trigger event leaving condition, a measurement reporting procedure is initiated by UE 110. In at least one embodiment, if UE 110 determines in step 512 that (T1+timeToTriggerForLeaving)−(T0+timeToTriggerForEntering)≥reportIntervalMin, UE 110 initiates the measurement reporting procedure in step 518.

[0106] In at least one embodiment, UE 110 does not initiate a measurement reporting procedure in step 520. In at least one embodiment, step 520 is performed by Figure 1is executed by the processor 120. In at least one embodiment, if the UE 110 determines in step 504 that the trigger event entry condition is not satisfied at the current time T0, the measurement reporting procedure is not started. In at least one embodiment, if the UE 110 determines in step 508 that one or more predicted measurement results 411-413 do not satisfy the trigger event entry condition, the measurement reporting procedure is not started. In at least one embodiment, if the UE 110 determines in step 516 that one or more predicted measurement results 421-423 do not satisfy the trigger event exit condition, the measurement reporting procedure is not started.

[0107] In at least one embodiment, the predicted event for RRC measurement report initialization is event A1 (the serving becomes better than the threshold). In at least one embodiment, the entry condition for event A1 is Ms–Hys>Thresh, and the exit condition for event A1 is Ms+Hys<Thresh, where Ms is the measurement result of the serving cell (without considering any offset), Hys is the hysteresis parameter of event A1, and Thresh is the threshold parameter of event A1.

[0108] In at least one embodiment, the predicted event for RRC measurement report initialization is event A2 (the serving becomes worse than the threshold). In at least one embodiment, the entry condition for event A2 is Ms+Hys<Thresh, and the exit condition for event A2 is Ms–Hys>Thresh, where Ms is the measurement result of the serving cell (without considering any offset), Hys is the hysteresis parameter of event A2, and Thresh is the threshold parameter of event A2.

[0109] In at least one embodiment, the predicted event for RRC measurement report initialization is event A3 (a neighbor becomes offset better than the SpCell). In at least one embodiment, the entry condition for event A3 is Mn+Ofn+Ocn-Hys>Mp+Ofp+Ocp+Off, and the exit condition for event A3 is Mn+Ofn+Ocn+Hys<Mp+Ofp+Ocp+Off, where Mn is the measurement result of the neighboring cell (without considering any offset), Ofn is the measurement object specific offset of the reference signal of the neighboring cell, Ocn is the cell specific offset of the neighboring cell, Mp is the measurement result of the SpCell (without considering any offset), Ofp is the measurement object specific offset of the SpCell, Ocp is the cell specific offset of the SpCell, Hys is the hysteresis parameter of event A3, and Off is the offset parameter of event A3.

[0110] In at least one embodiment, the event for prediction in RRC measurement report initialization is event A4 (the neighbor becomes better than the threshold). In at least one embodiment, the entry condition for event A4 is Mn + Ofn + Ocn – Hys > Thresh, and the exit condition for event A4 is Mn + Ofn + Ocn + Hys < Thresh, where Mn is the measurement result of the neighboring cell (without considering any offset), Ofn is the measurement object specific offset of the neighboring cell, Ocn is the cell specific offset of the neighboring cell, Hys is the hysteresis parameter of event A4, and Thresh is the threshold parameter of event A4.

[0111] In at least one embodiment, the event for prediction in RRC measurement report initialization is event A5 (the SpCell becomes worse than threshold 1 (threshold1) and the neighbor becomes better than threshold 2 (threshold2)). In at least one embodiment, the entry condition for event A5 is Mp + Hys < Thresh1 and Mn + Ofn + Ocn - Hys > Thresh2, and the exit condition for event A5 is Mp - Hys > Thresh1 and Mn + Ofn + Ocn + Hys < Thresh2, where Mp is the measurement result of the NR SpCell (without considering any offset), Mn is the measurement result of the neighboring cell (without considering any offset), Ofn is the measurement object specific offset of the neighboring cell, Ocn is the cell specific offset of the neighboring cell, Hys is the hysteresis parameter of event A5, Thresh1 is the threshold parameter of event A5, and Thresh2 is the threshold parameter of event A5.

[0112] In at least one embodiment, the event for prediction in RRC measurement report initialization is event A6 (the neighbor becomes offset better than the SCell). In at least one embodiment, the entry condition for event A6 is Mn + Ocn - Hys > Ms + Ocs + Off, and the exit condition for event A6 is Mn + Ocn + Hys < Ms + Ocs + Off, where Mn is the measurement result of the neighboring cell (without considering any offset), Ocn is the cell specific offset of the neighboring cell, Ms is the measurement result of the serving cell (without considering any offset), Ocs is the cell specific offset of the serving cell, Hys is the hysteresis parameter of event A6, and Off is the offset parameter of event A6.

[0113] Figure 6 is a process 600 for identifying and configuring the prediction of the measurement report quantity shown according to at least one embodiment. In at least one embodiment, the process 600 is executed by the processor 120 of the UE 110 Figure 1 In at least one embodiment, Figure 12-52 the systems and processors disclosed in

[0114] In at least one embodiment, in step 610, UE 110 reports its supported RRC measurement report quantity prediction function capabilities. In at least one embodiment, step 610 is performed by Figure 1 The processor 120 of the UE 110 is executed. In at least one embodiment, the UE 110 indicates whether it supports the RRC measurement report amount prediction function. In at least one embodiment, the prediction capability includes but is not limited to: a) whether the UE can predict the future RRC measurement report amount of its serving cell, b) whether the UE can predict the future RRC measurement report amount of its (one or more) neighbor cells, and if so, what the (one or more) neighbor cells are, c) the type of RRC measurement report amount that the UE can predict, such as RSRP, RSRQ, SINR or a combination thereof, d) the processing / response time of the UE's predicted RRC measurement report amount, e) the UE's confidence level in its predicted RRC measurement report amount, f) the accuracy level of the UE's predicted RRC measurement report amount, and g) how far in advance the UE can predict its future RRC measurement report amount.

[0115] In at least one embodiment, in step 620, UE 110 reports a dynamic update of the applicable functionality regarding the RRC measurement report quantity prediction. In at least one embodiment, step 620 is performed by Figure 1 The processor 120 of the UE 110 executes.

[0116] In at least one embodiment, the applicable functions for RRC measurement report quantity prediction are a subset of the supported RRC measurement report quantity prediction functions. In at least one embodiment, by way of example, the supported RRC measurement report quantity prediction functions include predictions of RSRP, RSRQ, SINR, and combinations thereof. In at least one embodiment, when UE 110 transitions between different states (e.g., different locations, different power states), UE 110 reports dynamic updates regarding the applicable functions for RRC measurement report quantity prediction, indicating which one or more of RSRP, RSRQ, and SINR is the currently applicable function.

[0117] In at least one embodiment, the applicable functionality for RRC measurement report quantity prediction is a superset of the supported RRC measurement report quantity prediction functionality. In at least one embodiment, for example, the supported RRC measurement report quantity prediction functionality includes predictions of RSRP, RSRQ, SINR, and combinations thereof for its serving cell. In at least one embodiment, when UE 110 transitions between different states (e.g., different locations, different power states), UE 110 reports dynamic updates about the applicable RRC measurement report quantity prediction functionality, indicating when it can or cannot predict RSRP, RSRQ, SINR, and combinations thereof for its (one or more) neighboring cells in addition to its serving cell.

[0118] In at least one embodiment, the applicable RRC measurement report amount prediction function is a set different from the set of supported RRC measurement report amount prediction functions. In at least one embodiment, by way of example, the supported RRC measurement report amount prediction functions include predicting A1 events, A2 events, and combinations thereof. In at least one embodiment, when UE 110 transitions between different states (e.g., different locations, different power states), UE 110 reports dynamic updates about the applicable RRC measurement report amount prediction function, indicating when it can or cannot predict A3 events, A4 events, A5 events, A6 events, and combinations thereof.

[0119] In at least one embodiment, in step 630, the network configures the RRC measurement report quantity prediction functionality. In at least one embodiment, step 630 is performed by Figure 1 The processor 120 of the UE 110 executes.

[0120] Figure 7 is a block diagram 700 illustrating a beam-specific model for predicting beam measurements according to at least one embodiment. In at least one embodiment, block diagram 700 uses Figure 1 In at least one embodiment, the UE 110 trains beam-specific neural networks for RRC measurement report quantity prediction at future times and uses them for inference.

[0121] In at least one embodiment, for each beam n, there is a corresponding neural network n. In at least one embodiment, 701a-701n illustrate measurement windows for each reference cell of the corresponding beam. In at least one embodiment, 701a illustrates a reference signal for a cell of a first beam (e.g., Figure 4 401a-401n) of the measurement window (eg Figure 4410 in ). In at least one embodiment, 701n shows a measurement window for the reference signal of the cell of the nth beam. In at least one embodiment, the prediction horizon and the measurement results are inputs to each neural network 702a-702n. In at least one embodiment, the inputs to neural network 702a are 711a, the prediction horizon t[x], and 701a, the measurement results based on the reference signal associated with beam 1 at time {t[-P], ..., t[0]}. In at least one embodiment, the inputs to neural network 702n are 711n, the prediction horizon t[x], and 701n, the measurement results based on the reference signal associated with beam n at time {t[-P], ..., t[0]}.

[0122] In at least one embodiment, each neural network 702a-702n outputs a measurement quantity 703a-703n. In at least one embodiment, the processor 120 executes the neural networks 702a-702n. In at least one embodiment, the output of each neural network 702a-702n is a prediction of the measurement quantity for the corresponding beam t[x] ahead. In at least one embodiment, the measurement quantity 703a-703n is a predicted measurement quantity for the corresponding beam at a future time t[x]. In at least one embodiment, the predicted measurement quantities 703a-703n from the neural networks 702a-702n are fused to generate a single-cell measurement quantity prediction.

[0123] In at least one embodiment, the predicted measurements are fused in the selection output 704. In at least one embodiment, the predicted measurements are fused as described herein and in Figure 8 In at least one embodiment, processor 120 performs select output 704.

[0124] In at least one embodiment, UE 110 may be configured via network 170 to derive a fusion result of cell measurement quantity predictions by selecting the highest beam measurement quantity prediction value as output 704, where each predicted beam measurement quantity is provided by an output of a corresponding neural network 702a-702n.

[0125] In at least one embodiment, the UE 110 may be configured with a threshold for fusing predicted beam measurement quantities via the network 170. In at least one embodiment, the UE 110 first selects beam measurement quantity prediction values ​​above the threshold, and then averages the selected beam measurement quantity prediction values ​​to generate an output 704, where each predicted beam measurement quantity is provided by an output of a corresponding neural network 702a-702n.

[0126] In at least one embodiment, if none of the beam measurement quantity prediction values ​​are higher than the threshold, the UE 110 selects the highest beam measurement quantity prediction value as the output of 704 .

[0127] In at least one embodiment, UE 110 may be configured by network 170 with a parameter K that determines the number of beams for fusion of predicted beam measurement quantities. In at least one embodiment, UE 110 first selects the K highest beam measurement quantity prediction values ​​and then averages the selected beam measurement quantity prediction values ​​to generate an output at 704, where each predicted beam measurement quantity is provided by the output of a corresponding neural network 702a-702n.

[0128] In at least one embodiment, UE 110 may be configured by network 170 with a threshold for merging predicted beam measurement quantities and a parameter K that determines the maximum number of beams for merging predicted beam measurement quantities. In at least one embodiment, UE 110 first selects beam measurement quantity prediction values ​​above the threshold. In at least one embodiment, if the number of beam measurement quantity prediction values ​​above the threshold is greater than K, UE 110 selects the K highest beam measurement quantity prediction values ​​and then averages the selected beam measurement quantity prediction values ​​to generate an output at 704. In at least one embodiment, if the number of beam measurement quantity prediction values ​​above the threshold is less than or equal to K and greater than zero, UE 110 averages all selected beam measurement quantity prediction values ​​to generate an output at 704. In at least one embodiment, if the number of beam measurement quantity prediction values ​​above the threshold is equal to zero, UE 110 selects the highest beam measurement quantity prediction value as the output at 704.

[0129] In at least one embodiment, the single cell measurement quantity is further filtered by layer 3 filtering 705. In at least one embodiment, the processor 120 performs layer 3 filtering 705. In at least one embodiment, the layer 3 filtering 705 is performed by Figure 1 In at least one embodiment, the processor 120 executes the s =(1-a)*F n-1 +a*M n Perform layer 3 filtering 705, where M n is the latest value of the output from the fusion of the predicted beam measurements, F n is the filtered cell measurement result used to evaluate the reporting criteria or for updating the measurement report, F n-1 is the old filtered cell measurement result, where the first result from the output of the predicted beam measurement fusion is received and is a–1 / 2 (k / 4)When , F0 is set to M1, where k is the configured filter coefficient value. In at least one embodiment, the layer 3 filtered measurement is used to evaluate reporting criteria or for measurement reporting in 706. In at least one embodiment, processor 120 executes measurement reporting 706. In at least one embodiment, layer 3 is the network layer that determines how data is sent to the receiving device. In at least one embodiment, layer 3 transmits data segments between networks. In at least one embodiment, layer 2 is the data link layer that converts binary to signals and allows upper layers to access the media. In at least one embodiment, layer 2 identifies network protocols and connects devices to transmit and receive data. In at least one embodiment, layer 1 is the physical layer that includes physical hardware and transmits signals over the media. In at least one embodiment, layer 1 defines the wired or wireless components that connect devices. In at least one embodiment, layers 1-3 are part of the Open Systems Interconnection (OSI) model.

[0130] In at least one embodiment, the processor 120 may be used, alone or in combination, to perform Layer 3, Layer 2, or Layer 1 functions. In at least one embodiment, the processor 120 may utilize data received from these layers (e.g., packet data) and further perform Layer 4 functions (e.g., Transport Communication Protocol (TCP) and User Datagram Protocol (UDP) layers). In at least one embodiment, Layer 3 may include a radio resource control (RRC) layer. In at least one embodiment, Layer 2 may include a medium access control (MAC) layer, a radio link control (RLC) layer, and a packet data convergence protocol (PDCP) layer. In at least one embodiment, Layer 1 may include a physical (PHY) layer of a UE / RAN node.

[0131] Figure 8 is a process 800 illustrating fusion of predicted beam measurements according to at least one embodiment. In at least one embodiment, Figure 1 The processor 120 performs the process 800. In at least one embodiment, Figure 12-52 The system and processor disclosed in the embodiment of the present invention perform all or part of the process 800. In at least one embodiment, the process 800 describes Figure 7 The selected output is 704.

[0132] In at least one embodiment, in step 802, a beam measurement quantity prediction value is obtained. In at least one embodiment, step 802 is performed by Figure 1In at least one embodiment, in step 804, a determination is made as to whether a threshold for fusion is configured. In at least one embodiment, step 804 is performed by Figure 1 In at least one embodiment, if a threshold is configured, process 800 proceeds to step 808. In at least one embodiment, if a threshold is not configured, process 800 proceeds to step 806.

[0133] In at least one embodiment, in step 806, a determination is made whether the number of beams K for averaging is configured. In at least one embodiment, step 806 is performed by Figure 1 In at least one embodiment, if the number of beams for averaging is configured, process 800 proceeds to step 812. In at least one embodiment, if the number of beams for averaging is not configured, process 800 proceeds to step 810.

[0134] In at least one embodiment, in step 808, a determination is made whether a maximum number of beams K for averaging is configured. In at least one embodiment, step 808 is performed by Figure 1 In at least one embodiment, if the maximum number of beams for averaging is configured, process 800 proceeds to step 816. In at least one embodiment, if the maximum number of beams for averaging is not configured, process 800 proceeds to step 814.

[0135] In at least one embodiment, in step 816, a determination is made whether the number of beam measurement quantity prediction values ​​is above a threshold value K. In at least one embodiment, step 816 is performed by Figure 1 In at least one embodiment, if the number of beam measurement quantity prediction values ​​is greater than K, process 800 proceeds to step 812. In at least one embodiment, if the number of beam measurement quantity prediction values ​​is less than or equal to K, process 800 proceeds to step 818.

[0136] In at least one embodiment, in step 818, a determination is made whether the number of beam measurement quantity prediction values ​​is above a threshold of 0. In at least one embodiment, step 818 is performed by Figure 1 In at least one embodiment, if the number of beam measurement quantity prediction values ​​is greater than 0, process 800 proceeds to step 814. In at least one embodiment, if the number of beam measurement quantity prediction values ​​is less than or equal to 0, process 800 proceeds to step 810.

[0137] In at least one embodiment, in step 810, UE 110 selects the highest beam measurement quantity prediction value as the fusion output of 704. In at least one embodiment, step 810 is performed by Figure 1 The processor 120 of FIG. 110 is executed. In at least one embodiment, if the UE 110 determines in step 806 that the number of beams for averaging is not configured, the UE 110 selects the highest beam measurement quantity prediction value as the fusion output 704. In at least one embodiment, if the UE 110 determines in step 818 that the number of beam measurement quantity prediction values ​​is ≤ 0, the UE 110 selects the highest beam measurement quantity prediction value as the fusion output 704.

[0138] In at least one embodiment, in step 812, UE 110 averages the K highest beam measurement quantity predictions to generate the fused output of 704. In at least one embodiment, step 812 is performed by Figure 1 The processor 120 is executed. In at least one embodiment, if the UE 110 determines that the number of beams for averaging is configured in step 806, the UE 110 averages the K highest beam measurement quantity prediction values ​​to generate the fusion output of 704. In at least one embodiment, if the UE 110 determines that the number of beam measurement quantity prediction values ​​is greater than K in step 816, the UE 110 averages the K highest beam measurement quantity prediction values ​​to generate the fusion output of 704.

[0139] In at least one embodiment, in step 814, UE 110 averages the beam measurement quantity prediction values ​​above the threshold to generate the fusion output of 704. In at least one embodiment, step 814 is performed by Figure 1 The processor 120 is executed. In at least one embodiment, if the UE 110 determines in step 806 that the maximum number of beams for averaging is not configured, the UE 110 averages the beam measurement quantity prediction values ​​above the threshold to generate the fusion output of 704. In at least one embodiment, if the UE 110 determines in step 818 that the number of beam measurement quantity prediction values ​​is greater than 0, the UE 110 averages the beam measurement quantity prediction values ​​above the threshold to generate the fusion output of 704.

[0140] Figure 9 is a block diagram 900 illustrating a cell-specific model for predicting cell measurement quantities according to at least one embodiment. In at least one embodiment, block diagram 900 is a block diagram illustrating a cell-specific model for predicting cell measurement quantities using Figure 1 In at least one embodiment, the UE 110 trains cell-specific neural networks for RRC measurement report quantity predictions at future times and uses them for reasoning.

[0141] In at least one embodiment, 905a-905n illustrate measurement windows for each reference cell of the corresponding beam. In at least one embodiment, 905a illustrates a reference signal for a cell of a first beam (e.g., Figure 4 401a-401n) of the measurement window (eg Figure 4 410 in FIG. In at least one embodiment, 905n illustrates a measurement window for a reference signal of a cell for the nth beam. In at least one embodiment, the predicted ranges and measurements based on the reference signals associated with all beams are inputs to the neural network 920. In at least one embodiment, the inputs to the neural network 920 are the predicted range t[x] 902 and a set of measurement results for beams a through n 901.

[0142] In at least one embodiment, the neural network 920 outputs a predicted measurement quantity for each beam 930a-930n. In at least one embodiment, the processor 120 executes the neural network 920. In at least one embodiment, the output of the neural network 920 is a prediction of the measurement quantity t[x] ahead for all corresponding beams. In at least one embodiment, the measurement quantities 930a-930n are predicted measurement quantities for the corresponding beams at a future time t[x].

[0143] In at least one embodiment, the predicted beam measurements 930a-930n from the neural network 920 are fused to generate a single cell measurement prediction in the selection output 940. In at least one embodiment, the predicted measurement is fused in the selection output 940. In at least one embodiment, the predicted measurement is fused and / or selected as described above. Figures 7 and 8 In at least one embodiment, the processor 120 executes the selection output 940 to generate a single-cell measurement quantity prediction.

[0144] In at least one embodiment, the single cell measurement quantity is further filtered by layer 3 filtering 950. In at least one embodiment, the processor 120 performs layer 3 filtering 950. In at least one embodiment, the layer 3 filtering 950 is performed by Figure 1 In at least one embodiment, the above is combined with the processor 120 to execute. Figure 7 The described techniques perform layer 3 filtering 950. In at least one embodiment, layer 3 filtered measurements are used to evaluate reporting criteria or for measurement reporting in 706. In at least one embodiment, processor 120 performs measurement reporting 706.

[0145] Figure 10 An exemplary system for measurement reporting in accordance with at least one embodiment is shown.

[0146] Block diagram 1000 illustrates a software program executed by one or more processors according to at least one embodiment. In at least one embodiment, software program 1010 is a set of instructions that, if executed, causes one or more processors 1001 (e.g., Figure 1 In at least one embodiment, block diagram 1000 illustrates a software program 1010 executed by a processor (e.g., processor 1001). In at least one embodiment, processor 1001 is a processor such as processor 120, in conjunction with at least Figure 1 As described herein. In at least one embodiment, processor 1001 is any general-purpose processor having any architecture further described herein. In at least one embodiment, a processor (e.g., processor 1001) includes one or more circuits for performing one or more computing operations. In at least one embodiment, a processor (e.g., processor 1001) includes any circuit configuration for performing one or more computing operations further described herein.

[0147] In at least one embodiment, block diagram 1000 is composed of modules such that a processor, in conjunction with the modules, performs a series of operations. In at least one embodiment, processor 1001 includes a measurement module 1020, a prediction module 1030, a fusion and filtering module 1040, and an evaluation module 1050. In at least one embodiment, block diagram 1000 includes one or more modules to generate a prediction of the quality of one or more wireless signals to be transmitted, wherein the prediction is based at least in part on one or more reference signals.

[0148] In at least one embodiment, the module includes any combination of any type of logic (e.g., software, hardware, firmware) and / or circuitry configured to perform the described functions. In at least one embodiment, the module includes one or more circuits that form part of a larger system (e.g., an integrated circuit (IC), a system on a chip (SoC), a central processing unit (CPU), a graphics processing unit (GPU), a data processing unit (DPU), etc.). In at least one embodiment, the controller includes any combination of any type of logic (e.g., software, hardware, firmware) and / or circuitry configured to perform the described functions. In at least one embodiment, the software includes a software package, code, a programming language, a driver, instructions, an instruction set, or some combination thereof. In at least one embodiment, the hardware includes hardwired circuits, programmable circuits, state machine circuits, fixed-function circuits, firmware with stored instructions executed by programmable circuits, or some combination thereof.

[0149] In at least one embodiment, the logic unit includes firmware logic, hardware logic, or some combination thereof, configured to provide any of the functionality further described herein. In at least one embodiment, the logic unit includes circuitry that forms part of a larger system (e.g., an IC, SoC, CPU, GPU, DPU). In at least one embodiment, the logic unit includes logic circuitry for implementing firmware and / or hardware.

[0150] In at least one embodiment, the engine comprises modules and / or logic units as further described herein. In at least one embodiment, the component comprises modules and / or logic units as further described herein. In at least one embodiment, the engine comprises software logic, firmware logic, hardware logic, or some combination thereof configured to provide any functionality as further described herein. In at least one embodiment, the component comprises software logic, firmware logic, hardware logic, or some combination thereof configured to provide any functionality as further described herein. In at least one embodiment, the operations performed by hardware and / or firmware may alternatively be implemented by a software module embodied as a software package, code, and / or instruction set. In at least one embodiment, the logic unit also utilizes a portion of software to implement its functionality.

[0151] In at least one embodiment, a processor (eg, processor 1001 and processor 120) includes a measurement module 1020 that performs one or more processes, such as in conjunction with Figure 1 In at least one embodiment, the measurement module 1020 includes instructions for performing RRC measurements based on downlink reference signals, which are at least in combination with Figure 1-9 In at least one embodiment, the measurement module 1020 is a set of instructions that, if executed by one or more processors, causes the one or more processors to receive or perform measurements of a reference signal, as described above. Figure 1 In at least one embodiment, the processor 1001 includes a prediction module 1030 that performs one or more processes, such as combining Figure 1-9 In at least one embodiment, the prediction module 1030 includes instructions for determining whether a trigger event condition is satisfied and using the neural network 140 to predict the future RRC measurement report amount, which is at least in combination with Figure 1-9 In at least one embodiment, the prediction module 1030 is a set of instructions that, if executed by one or more processors, causes the one or more processors to perform a prediction of wireless signal quality, as described above. Figure 1-9 In at least one embodiment, the processor includes a fusion and filtering module 1040 that performs one or more processes, such as combining Figure 7-9 In at least one embodiment, the fusion and filtering module 1040 includes instructions for performing the fusion and layer 3 filtering 705 and 950 process 800, which is described in at least one embodiment. Figure 7-9 In at least one embodiment, the fusion and filtering module 1040 is a set of instructions that, if executed by one or more processors, causes the one or more processors to generate a fused output and apply layer 3 filtering to the fused output, as described above. Figure 7-9 In at least one embodiment, the processor includes an evaluation module 1050 that performs one or more processes, such as combining Figure 1-9 In at least one embodiment, the evaluation module 1050 includes instructions for executing the measurement reports 706 and 960, which are described in conjunction with at least Figure 7 and Figure 9 In at least one embodiment, the evaluation module 1050 is a set of instructions that, if executed by one or more processors, causes the one or more processors to evaluate reporting criteria or initiate a measurement reporting procedure, as described above. Figure 7-9 As described in .

[0152] Figure 11 1 is a block diagram illustrating a driver and / or runtime including one or more libraries for providing one or more application programming interfaces (APIs) according to at least one embodiment. In at least one embodiment, software program 1102 is a software module. In at least one embodiment, software program 1102 includes one or more software modules. In at least one embodiment, one or more software modules such as Figure 101102. In at least one embodiment, one or more APIs 1110 are software instruction sets that, if executed, cause one or more processors to perform one or more computing operations. In at least one embodiment, one or more APIs 1110 are distributed or otherwise provided as part of one or more libraries 1106, runtimes 1104, drivers 1104, and / or any other software and / or executable code groupings described further herein. In at least one embodiment, one or more APIs 1110 perform one or more computing operations in response to a call by a software program 1102. In at least one embodiment, a software program 1102 is a collection of software code, commands, instructions, or other text sequences that instructs a computing device to perform one or more computing operations and / or call one or more other instruction sets, such as APIs 1110 or API functions 1112, to be executed. In at least one embodiment, the functionality provided by one or more APIs 1110 includes software functions 1112, such as software functions that can be used to accelerate one or more portions of a software program 1102 using one or more parallel processing units (PPUs), such as a graphics processing unit (GPU).

[0153] In at least one embodiment, the API 1110 is a hardware interface to one or more circuits for performing one or more computing operations. In at least one embodiment, the one or more software APIs 1110 described herein are implemented to perform the following operations in conjunction with Figure 1-10 In at least one embodiment, one or more software programs 1102 include instructions that, if executed, cause one or more hardware devices and / or circuits to perform the following operations in conjunction with Figure 1-10 One or more techniques further described.

[0154] In at least one embodiment, software program 1102 (e.g., a user-implemented software program) utilizes one or more application programming interfaces (APIs) 1110 to perform various computational operations, such as memory reservations, matrix multiplications, arithmetic operations, or any computational operations performed by a parallel processing unit (PPU) (e.g., a graphics processing unit (GPU)), as further described herein. In at least one embodiment, one or more APIs 1110 provide a set of callable functions 1112, referred to herein as APIs, API functions, and / or functions, that each perform one or more computational operations, such as computational operations associated with parallel computing. For example, in an embodiment, one or more APIs 1110 provide functions 1112 to cause neural network 140 to predict measurements of one or more wireless signals.

[0155] In at least one embodiment, one or more software programs 1102 interact with or otherwise communicate with one or more APIs 1110 to perform one or more computing operations using one or more PPUs (e.g., GPUs). In at least one embodiment, the one or more computing operations using the one or more PPUs include at least one or more groups of computing operations that are accelerated by being executed at least in part by the one or more PPUs. In at least one embodiment, the one or more software programs 1102 interact with the one or more APIs 1110 to facilitate parallel computing using remote or local interfaces.

[0156] In at least one embodiment, the interface is software instructions that, if executed, provide access to one or more functions 1112 provided by one or more APIs 1110. In at least one embodiment, the software programs 1102 use native interfaces when a software developer compiles one or more software programs 1102 in conjunction with one or more libraries 1106 that include or otherwise provide access to one or more APIs 1110. In at least one embodiment, the one or more software programs 1102 are statically compiled with precompiled libraries 1106 or uncompiled source code that include instructions for executing the one or more APIs 1110. In at least one embodiment, the one or more software programs 1102 are dynamically compiled and linked to the one or more precompiled libraries 1106 that include the one or more APIs 1110 using a linker.

[0157] In at least one embodiment, when a software developer executes a software program, the software program 1102 uses a remote interface that utilizes or otherwise communicates with a library 1106 containing one or more APIs 1110 over a network or other remote communication medium. In at least one embodiment, the one or more libraries 1106 containing one or more APIs 1110 are executed by a remote computing service (e.g., a computing resource service provider). In another embodiment, the one or more libraries 1106 containing one or more APIs 1110 are executed by any other computing host that provides the one or more APIs 1110 to the one or more software programs 1102.

[0158] In at least one embodiment, a processor executing or using one or more software programs 1102 calls, uses, executes, or otherwise implements one or more APIs 1110 to allocate and otherwise manage memory used by the software programs 1102. In at least one embodiment, one or more software programs 1102 utilize one or more APIs 1110 to allocate and otherwise manage memory used by one or more portions of the software programs 1102 for acceleration using one or more PPUs (e.g., GPUs or any other accelerators or processors described further herein). These software programs 1102 request the neural network to perform measurement generation, prediction generation, and / or signal information generation using functionality 1112 provided by the one or more APIs 1110, in embodiments.

[0159] In at least one embodiment, API 1110 is an API for facilitating parallel computing. In at least one embodiment, API 1110 is any other API described further herein. In at least one embodiment, API 1110 is provided by a driver and / or runtime 1104. In at least one embodiment, API 1110 is provided by a CUDA user-mode driver. In at least one embodiment, API 1110 is provided by a CUDA runtime. In at least one embodiment, driver 1104 is data values ​​and software instructions that, if executed, perform or otherwise facilitate the operation of one or more functions 1112 of API 1110 during the loading and execution of one or more portions of software program 1102. In at least one embodiment, runtime 1104 is data values ​​and software instructions that, if executed, perform or otherwise facilitate the operation of one or more functions 1112 of API 1110 during the execution of software program 1102. In at least one embodiment, one or more software programs 1102 utilize one or more APIs 1110 implemented or otherwise provided by a driver and / or runtime 1104 to perform combined arithmetic operations by the one or more software programs 1102 during execution by one or more PPUs (e.g., GPUs).

[0160] In at least one embodiment, one or more software programs 1102 utilize one or more APIs 1110 provided by a driver and / or runtime 1104 to perform combined arithmetic operations for one or more PPUs (e.g., GPUs). In at least one embodiment, the one or more APIs 1110 provide combined arithmetic operations through the driver and / or runtime 704, as described above. In at least one embodiment, one or more software programs 1102 utilize one or more APIs 1110 provided by a driver and / or runtime 1104 to allocate or otherwise reserve one or more memory blocks 1114 for one or more PPUs (e.g., GPUs). In at least one embodiment, one or more software programs 1102 utilize one or more APIs 1110 provided by a driver and / or runtime 1104 to allocate or otherwise reserve memory blocks. In at least one embodiment, the one or more APIs 1110 are used to perform combined arithmetic operations, as described below in conjunction with Figure 1-10 Any of the ones described.

[0161] To improve the usability of the software program 1102 and / or optimize one or more portions of the software program 1102 for acceleration by one or more PPUs (e.g., GPUs), in one embodiment, one or more APIs 1110 provide one or more API functions 1112 for executing a neural network that can be used by or by one or more computing devices, as described above, and in conjunction with Figure 1-10 Further described below. In at least one embodiment, exemplary block diagram 1100 depicts a processor comprising one or more circuits to execute one or more software programs to combine two or more application programming interfaces (APIs) into a single API. In at least one embodiment, exemplary block diagram 1100 depicts a system comprising one or more processors to execute one or more software programs to combine two or more application programming interfaces (APIs) into a single API. In at least one embodiment, the processor uses the API to cause a neural network to generate measurement reports and / or otherwise perform the operations described herein. In at least one embodiment, exemplary block diagram 1100 illustrates an API for invoking a neural network to implement signal information generation and measurement report generation.

[0162] In at least one embodiment, a processor uses an exemplary API to call one or more neural networks, wherein the processor includes circuitry for using the one or more neural networks to generate a prediction of the quality of one or more wireless signals to be transmitted, wherein the prediction is based at least in part on one or more reference signals and / or otherwise perform the operations described herein. In at least one embodiment, a processor uses an exemplary API to call one or more neural networks, wherein the processor includes circuitry for using the one or more neural networks to generate a measurement report based at least in part on one or more predicted measurements of the wireless signals and / or otherwise perform the operations described herein. In at least one embodiment, in conjunction with Figure 11 The components, methods and / or systems described herein are as described in Figure 1-10 Any one of which is further non-exclusively shown.

[0163] Data Center

[0164] Figure 12 An example data center 1200 is shown in which at least one embodiment may be used. In at least one embodiment, the data center 1200 includes a data center infrastructure layer 1210, a framework layer 1220, a software layer 1230, and an application layer 1240.

[0165] In at least one embodiment, Figure 12 As shown, the data center infrastructure layer 1210 may include a resource coordinator 1212, grouped computing resources 1214, and node computing resources ("node CRs") 1216(1)-1216(N), where "N" represents any integer, positive integer. In at least one embodiment, the node CRs 1216(1)-1216(N) may include, but are not limited to, any number of central processing units ("CPUs") or other processors (including accelerators, field programmable gate arrays (FPGAs), graphics processors, etc.), memory devices (e.g., dynamic read-only memories), storage devices (e.g., solid-state drives or disk drives), network input / output ("NW I / O") devices, network switches, virtual machines ("VMs"), power modules, and cooling modules, etc. In at least one embodiment, one or more of the node CRs 1216(1)-1216(N) may be a server having one or more of the above-mentioned computing resources.

[0166] In at least one embodiment, the grouped computing resources 1214 may include separate groups of node CRs housed in one or more racks (not shown), or many racks (also not shown) housed in data centers at various geographic locations. In at least one embodiment, the separate groups of node CRs within the grouped computing resources 1214 may include computing, networking, memory, or storage resources that can be configured or allocated to support groupings of one or more workloads. In at least one embodiment, several node CRs including CPUs or processors may be grouped in one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches, in any combination.

[0167] In at least one embodiment, resource coordinator 1212 may configure or otherwise control one or more nodes CR 1216(1)-1216(N) and / or grouped computing resources 1214. In at least one embodiment, resource coordinator 1212 may comprise a software design infrastructure ("SDI") management entity for data center 1200. In at least one embodiment, resource coordinator 1212 may comprise hardware, software, or some combination thereof.

[0168] In at least one embodiment, Figure 12As shown, framework layer 1220 includes a job scheduler 1222, a configuration manager 1224, a resource manager 1226, and a distributed file system 1228. In at least one embodiment, framework layer 1220 may include a framework that supports software 1232 of software layer 1230 and / or one or more applications 1242 of application layer 1240. In at least one embodiment, software 1232 or applications 1242 may include web-based service software or applications, such as those provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, framework layer 1220 may include, but is not limited to, a free and open source software web application framework, such as Apache Spark™ (hereinafter referred to as "Spark"), which may utilize distributed file system 1228 for large-scale data processing (e.g., "big data"). In at least one embodiment, job scheduler 1222 may include a Spark driver to facilitate scheduling workloads supported by various layers of data center 1200. In at least one embodiment, the configuration manager 1224 can be capable of configuring different layers, such as the software layer 1230 and the framework layer 1220 including Spark and a distributed file system 1228 for supporting large-scale data processing. In at least one embodiment, the resource manager 1226 can manage the cluster or group computing resources mapped to or allocated to support the distributed file system 1228 and the job scheduler 1222. In at least one embodiment, the cluster or group computing resources can include the group computing resources 1214 on the data center infrastructure layer 1210. In at least one embodiment, the resource manager 1226 can coordinate with the resource coordinator 1212 to manage these mapped or allocated computing resources.

[0169] In at least one embodiment, the software 1232 included in the software layer 1230 may include software used by at least a portion of the node CRs 1216(1)-1216(N), the grouped computing resources 1214, and / or the distributed file system 1228 of the framework layer 1220. In at least one embodiment, the one or more types of software may include, but are not limited to, Internet web page search software, email virus scanning software, database software, and streaming video content software.

[0170] In at least one embodiment, the one or more applications 1242 included in the application layer 1240 may include one or more types of applications used by at least a portion of the node CRs 1216(1)-1216(N), the grouped computing resources 1214, and / or the distributed file system 1228 of the framework layer 1220. In at least one embodiment, the one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive computing, and machine learning applications, including training or inference software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments.

[0171] In at least one embodiment, any of configuration manager 1224, resource manager 1226, and resource coordinator 1212 can implement any number and type of self-modification actions based on any number and type of data obtained in any technically feasible manner. In at least one embodiment, the self-modification actions can relieve a data center operator of data center 1200 from making potentially poor configuration decisions and can avoid underutilized and / or poorly performing portions of the data center.

[0172] In at least one embodiment, data center 1200 may include tools, services, software, or other resources to train one or more machine learning models or use one or more machine learning models to predict or infer information according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model can be trained by calculating weight parameters according to a neural network architecture using the software and computing resources described above with respect to data center 1200. In at least one embodiment, using the weight parameters calculated using one or more training techniques described herein, a trained machine learning model corresponding to one or more neural networks can be used to infer or predict information using the resources described above with respect to data center 1200.

[0173] In at least one embodiment, data center 1200 can use a CPU, application-specific integrated circuit (ASIC), GPU, FPGA, or other hardware to use the above resources to perform training and / or reasoning. In addition, one or more of the above software and / or hardware resources can be configured as a service to allow users to train or perform information reasoning, such as image recognition, speech recognition, or other artificial intelligence services.

[0174] In at least one embodiment, data center 1200 is integrated into Figure 1-11In at least one embodiment, nodes CR1216(1)-1216(N) include one or more circuits for performing operations such as those described above in conjunction with Figure 1-11 Describes the operation.

[0175] Figure 13A An example of an autonomous vehicle 1300 is shown, according to at least one embodiment. In at least one embodiment, autonomous vehicle 1300 (alternatively referred to herein as "vehicle 1300") can be, but is not limited to, a passenger vehicle, such as a car, truck, bus, and / or another type of vehicle that can accommodate one or more passengers. In at least one embodiment, vehicle 1300 can be a semi-tractor-trailer for hauling cargo. In at least one embodiment, vehicle 1300 can be an aircraft, a robotic vehicle, or another type of vehicle.

[0176] Automated driving vehicles may be described according to the levels of automation defined by the National Highway Traffic Safety Administration ("NHTSA") and the Society of Automotive Engineers ("SAE") of the U.S. Department of Transportation, "Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles" (e.g., Standard No. J3016-201806, dated June 15, 2018, Standard No. J3016-201609, dated September 30, 2016, and previous and future versions of this standard). In one or more embodiments, the vehicle 1300 may be capable of functioning according to one or more of the levels 1 to 5 of automated driving. For example, in at least one embodiment, the vehicle 1300 may be capable of conditional automation (Level 3), high automation (Level 4), and / or full automation (Level 5), depending on the embodiment.

[0177] In at least one embodiment, the vehicle 1300 may include, but is not limited to, components such as a chassis, a body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other components of the vehicle. In at least one embodiment, the vehicle 1300 may include, but is not limited to, a propulsion system 1350, such as an internal combustion engine, a hybrid power plant, an all-electric engine, and / or another type of propulsion system. In at least one embodiment, the propulsion system 1350 may be connected to a drive train of the vehicle 1300, which may include, but is not limited to, a transmission, to enable propulsion of the vehicle 1300. In at least one embodiment, the propulsion system 1350 may be controlled in response to receiving a signal from a throttle / accelerator 1352.

[0178] In at least one embodiment, when propulsion system 1350 is operating (e.g., when the vehicle is traveling), a steering system 1354 (which may include, but is not limited to, a steering wheel) is used to steer vehicle 1300 (e.g., along a desired path or route). In at least one embodiment, steering system 1354 may receive signals from steering actuator 1356. In at least one embodiment, a steering wheel may be optional for fully automated (Level 5) functionality. In at least one embodiment, brake sensor system 1346 may be used to operate the vehicle brakes in response to signals received from brake actuator 1348 and / or brake sensors.

[0179] In at least one embodiment, the controller 1336 may include, but is not limited to, one or more system-on-chips ("SoCs") ( Figure 13A ) and / or a graphics processing unit (“GPU”) provides signals (e.g., representing commands) to one or more components and / or systems of vehicle 1300. For example, in at least one embodiment, controller 1336 can send signals to operate vehicle brakes via brake actuator 1348, operate steering system 1354 via one or more steering actuators 1356, and operate propulsion system 1350 via one or more throttles / accelerators 1352. In at least one embodiment, one or more controllers 1336 can include one or more onboard (e.g., integrated) computing devices (e.g., supercomputers) that process sensor signals and output operational commands (e.g., signals representing commands) to implement autonomous driving and / or assist a driver in driving vehicle 1300. In at least one embodiment, the one or more controllers 1336 may include a first controller 1336 for autonomous driving functionality, a second controller 1336 for functional safety functionality, a third controller 1336 for artificial intelligence functionality (e.g., computer vision), a fourth controller 1336 for infotainment functionality, a fifth controller 1336 for redundancy in emergency situations, and / or other controllers. In at least one embodiment, a single controller 1336 may handle two or more of the aforementioned functions, two or more controllers 1336 may handle a single function, and / or any combination thereof.

[0180] In at least one embodiment, one or more controllers 1336 provide signals for controlling one or more components and / or systems of the vehicle 1300 in response to sensor data received from one or more sensors (e.g., sensor inputs). In at least one embodiment, the sensor data can be received from sensors such as, but not limited to, one or more global navigation satellite system ("GNSS") sensors 1358 (e.g., one or more global positioning system sensors), one or more RADAR sensors 1360, one or more ultrasonic sensors 1362, one or more LIDAR sensors 1364, one or more inertial measurement unit (IMU) sensors 1366 (e.g., one or more accelerometers, one or more gyroscopes, one or more magnetic compasses, one or more magnetometers, etc.), one or more microphones 1396, one or more stereo cameras 1368, one or more wide angle cameras 1370 (e.g., fisheye cameras), one or more infrared cameras 1372, one or more surround cameras 1374 (e.g., 360 degree cameras), telemetry cameras (e.g., gyroscopes), and the like. Figure 13A Not shown), mid-range camera ( Figure 13A ), one or more speed sensors 1344 (e.g., for measuring the speed of the vehicle 1300), one or more vibration sensors 1342, one or more steering sensors 1340, one or more brake sensors (e.g., as part of a brake sensor system 1346), and / or other sensor types are received.

[0181] In at least one embodiment, one or more controllers 1336 may receive input (e.g., represented by input data) from a dashboard 1332 of the vehicle 1300 and provide output (e.g., represented by output data, display data, etc.) via a human machine interface ("HMI") display 1334, an audible annunciator, a speaker, and / or other components of the vehicle 1300. In at least one embodiment, the output may include information such as vehicle speed, velocity, time, map data (e.g., high definition map ( Figure 13A ), location data (e.g., the location of the vehicle 1300, such as on a map), directions, the locations of other vehicles (e.g., occupancy barriers), information about objects and the states of objects sensed by the one or more controllers 1336, etc. For example, in at least one embodiment, the HMI display 1334 can display information about the presence of one or more objects (e.g., road signs, warning signs, traffic light changes, etc.) and / or information about the driving maneuvers the vehicle has made, is making, or will make (e.g., changing lanes now, taking exit 34B in two miles, etc.).

[0182] In at least one embodiment, the vehicle 1300 further includes a network interface 1324 that can communicate over one or more networks using one or more wireless antennas 1326 and / or one or more modems. For example, in at least one embodiment, the network interface 1324 may be capable of communicating over Long Term Evolution ("LTE"), Wideband Code Division Multiple Access ("WCDMA"), Universal Mobile Telecommunications System ("UMTS"), Global System for Mobile Communications ("GSM"), IMT-CDMA Multi-Carrier ("CDMA2000") networks, etc. In at least one embodiment, the one or more wireless antennas 1326 can also use one or more local area networks (e.g., Bluetooth, Bluetooth Low Energy (LE), Z-Wave, ZigBee, etc.) and / or one or more low power wide area networks (hereinafter referred to as "LPWAN") (e.g., protocols such as LoRaWAN and SigFox) to enable communication between objects in the environment (e.g., vehicles, mobile devices).

[0183] In at least one embodiment, the vehicle 1300 is integrated into Figure 1-11 In at least one embodiment, the vehicle 1300 includes one or more circuits for performing operations such as those described above in conjunction with Figure 1-11 Describes the operation.

[0184] Figure 13B According to at least one embodiment, Figure 13A 1300. In at least one embodiment, the cameras and respective fields of view are an example embodiment and are not intended to be limiting. For example, in at least one embodiment, additional and / or alternative cameras may be included and / or the cameras may be located in different locations on vehicle 1300.

[0185] In at least one embodiment, the camera type used for the camera may include, but is not limited to, a digital camera that may be suitable for use with components and / or systems of the vehicle 1300. In at least one embodiment, one or more cameras may operate at Automotive Safety Integrity Level ("ASIL") B and / or other ASILs. In at least one embodiment, the camera type may have any image capture rate, such as 60 frames per second (fps), 120fps, 240fps, etc., depending on the embodiment. In at least one embodiment, the camera may be capable of using a rolling shutter, a global shutter, another type of shutter, or a combination thereof. In at least one embodiment, the color filter array may include a red-clear-clear ("RCCC") filter array, a red-clear-clear-blue ("RCCB") filter array, a red-blue-green-clear ("RBGC") filter array, a Foveon X3 filter array, a Bayer sensor ("RGGB") filter array, a monochrome sensor filter array, and / or other types of filter arrays. In at least one embodiment, a clear pixel camera, such as one having an RCCC, RCCB, and / or RBGC color filter array, may be used in an effort to increase photosensitivity.

[0186] In at least one embodiment, one or more cameras can be used to perform advanced driver assistance system ("ADAS") functions (e.g., as part of a redundant or fail-safe design). For example, in at least one embodiment, a multi-function mono camera can be installed to provide functions including lane departure warning, traffic sign assistance, and intelligent headlight control. In at least one embodiment, one or more cameras (e.g., all cameras) can simultaneously record and provide image data (e.g., video).

[0187] In at least one embodiment, one or more cameras can be mounted in a mounting assembly, such as a custom designed (three-dimensional ("3D") printed) assembly, so as to cut out stray light and reflections from within the car (e.g., reflections from the dashboard reflecting in the windshield mirror) that may interfere with the camera's ability to capture image data. With respect to the rearview mirror mounting assembly, in at least one embodiment, the rearview mirror assembly can be 3D printed custom so that the camera mounting plate matches the shape of the rearview mirror. In at least one embodiment, one or more cameras can be integrated into the rearview mirror. In at least one embodiment, for side-view cameras, one or more cameras can also be integrated into the four pillars at each corner of the car.

[0188] In at least one embodiment, a camera (e.g., a forward-facing camera) having a field of view that includes a portion of the environment in front of the vehicle 1300 can be used for surround vision, as well as to help identify the forward path and obstacles with the assistance of one or more controllers 1336 and / or control SoCs, thereby providing information that is critical for generating an occupancy grid and / or determining a preferred vehicle path. In at least one embodiment, the forward-facing camera can be used to perform many of the same ADAS functions as LIDAR, including but not limited to emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, the forward-facing camera can also be used for ADAS functions and systems, including but not limited to lane departure warning ("LDW"), automatic cruise control ("ACC"), and / or other functions (e.g., traffic sign recognition).

[0189] In at least one embodiment, various cameras can be used in a forward-facing configuration, including, for example, a monocular camera platform including a CMOS ("Complementary Metal Oxide Semiconductor") color imager. In at least one embodiment, a wide-angle camera 1370 can be used to sense objects entering from the periphery (e.g., pedestrians, people crossing the road, or bicycles). Although Figure 13B Only one wide-angle camera 1370 is shown in FIG. 1 , however, in other embodiments, any number (including zero) of wide-angle cameras may be present on vehicle 1300. In at least one embodiment, any number of remote cameras 1398 (e.g., a remote stereo camera pair) may be used for depth-based object detection, particularly for objects for which a neural network has not yet been trained. In at least one embodiment, remote cameras 1398 may also be used for object detection and classification, as well as basic object tracking.

[0190] In at least one embodiment, any number of stereo cameras 1368 may also be included in the forward configuration. In at least one embodiment, one or more stereo cameras 1368 may include an integrated control unit including a scalable processing unit that may provide programmable logic ("FPGA") and a multi-core microprocessor with a controller area network ("CAN") or Ethernet interface integrated on a single chip. In at least one embodiment, such a unit may be used to generate a 3D map of the vehicle's 1300 environment, including distance estimates for all points in the image. In at least one embodiment, one or more stereo cameras 1368 may include, but are not limited to, a compact stereo vision sensor, which may include, but are not limited to, two camera lenses (one on each side) and an image processing chip that may measure the distance from the vehicle 1300 to the target object and use the generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning functions. In at least one embodiment, other types of stereo cameras 1368 may be used in addition to those described herein.

[0191] In at least one embodiment, a camera having a field of view of a portion of the environment including the sides of the vehicle 1300 (e.g., a side-view camera) can be used for surround viewing to provide information for creating and updating occupancy grids and generating side collision warnings. For example, in at least one embodiment, the surround camera 1374 (e.g., Figure 13B Four surround cameras 1374 (shown) can be positioned on the vehicle 1300. In at least one embodiment, the one or more surround cameras 1374 can include, but are not limited to, any number and combination of wide-angle cameras 1370, one or more fish-eye lenses, one or more 360-degree cameras, and / or the like. For example, in at least one embodiment, four fish-eye lens cameras can be located on the front, rear, and sides of the vehicle 1300. In at least one embodiment, the vehicle 1300 can use three surround cameras 1374 (e.g., left, right, and rear), and can utilize one or more other cameras (e.g., a forward-facing camera) as a fourth surround-view camera.

[0192] In at least one embodiment, a camera having a field of view that includes a portion of the environment behind the vehicle 1300 (e.g., a rearview camera) can be used for parking assistance, surround view, rear collision warning, and creating and updating occupancy grids. In at least one embodiment, a variety of cameras can be used, including but not limited to cameras that are also suitable as one or more forward-facing cameras (e.g., long-range camera 1398 and / or one or more mid-range cameras 1376, one or more stereo cameras 1368, one or more infrared cameras 1372, etc.), as described herein.

[0193] In at least one embodiment, the vehicle 1300 is integrated into Figure 1-11 In at least one embodiment, the vehicle 1300 includes one or more circuits for performing operations such as those described above in conjunction with Figure 1-11 Describes the operation.

[0194] Figure 13C According to at least one embodiment, Figure 13A A block diagram of an example system architecture for an autonomous vehicle 1300 is provided. In at least one embodiment, Figure 13CEach of one or more components, one or more features, and one or more systems of vehicle 1300 is shown as being connected via bus 1302. In at least one embodiment, bus 1302 may include, but is not limited to, a CAN data interface (alternatively referred to herein as a "CAN bus"). In at least one embodiment, CAN may be a network internal to vehicle 1300 that facilitates control of various features and functions of vehicle 1300, such as brake actuation, acceleration, braking, steering, wipers, and the like. In one embodiment, bus 1302 may be configured with dozens or even hundreds of nodes, each with its own unique identifier (e.g., a CAN ID). In at least one embodiment, bus 1302 may be read to find steering wheel angle, ground speed, engine revolutions per minute ("RPM"), button positions, and / or other vehicle status indicators. In at least one embodiment, bus 1302 may be an ASIL B compliant CAN bus.

[0195] In at least one embodiment, FlexRay and / or Ethernet may be used in addition to or in addition to CAN. In at least one embodiment, there may be any number of buses 1302, which may include, but are not limited to, zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses using other protocols. In at least one embodiment, two or more buses 1302 may be used to perform different functions and / or may be used for redundancy. For example, a first bus 1302 may be used for collision avoidance functionality, and a second bus 1302 may be used for actuation control. In at least one embodiment, each bus 1302 may communicate with any component of the vehicle 1300, and two or more buses 1302 may communicate with the same component. In at least one embodiment, each of any number of system-on-chips ("SoCs") 1304, each of one or more controllers 1336, and / or each computer within the vehicle may have access to the same input data (e.g., input from sensors in the vehicle 1300) and may be connected to a common bus, such as a CAN bus.

[0196] In at least one embodiment, the vehicle 1300 may include one or more controllers 1336, such as those described herein with respect to Figure 13A In at least one embodiment, the controller 1336 can be used for a variety of functions. In at least one embodiment, the controller 1336 can be coupled to any of the various other components and systems of the vehicle 1300 and can be used to control the vehicle 1300, the artificial intelligence of the vehicle 1300, the infotainment and / or other functions of the vehicle 1300.

[0197] In at least one embodiment, the vehicle 1300 may include any number of SoCs 1304. Each of the SoCs 1304 may include, but is not limited to, a central processing unit ("CPU(s)") 1306, a graphics processing unit ("GPU(s")) 1308, one or more processors 1310, one or more caches 1312, one or more accelerators 1314, one or more data stores 1316, and / or other components and features not shown. In at least one embodiment, the one or more SoCs 1304 may be used to control the vehicle 1300 in various platforms and systems. For example, in at least one embodiment, the one or more SoCs 1304 may be combined in a system (e.g., a system of the vehicle 1300) with a high-definition ("HD") map 1322 that may be downloaded from one or more servers (e.g., a system of the vehicle 1300) via a network interface 1324. Figure 13C ) to obtain map refreshes and / or updates.

[0198] In at least one embodiment, one or more CPUs 1306 may include a CPU cluster or CPU complex (alternatively referred to herein as a "CCPLEX"). In at least one embodiment, one or more CPUs 1306 may include multiple cores and / or a second level ("L2") cache. For example, in at least one embodiment, one or more CPUs 1306 may include eight cores in a mutually coupled multiprocessor configuration. In at least one embodiment, one or more CPUs 1306 may include four dual-core clusters, each with a dedicated L2 cache (e.g., a 2MB L2 cache). In at least one embodiment, one or more CPUs 1306 (e.g., CCPLEX) may be configured to support simultaneous cluster operations such that any combination of clusters of one or more CPUs 1306 may be active at any given time.

[0199] In at least one embodiment, one or more CPUs 1306 can implement power management functionality including, but not limited to, one or more of the following features: automatic clock gating of various hardware modules when idle to conserve dynamic power; clock gating of each core when the core is not actively executing instructions due to executing a wait for interrupt ("WFI") / wait for event ("WFE") instruction; each core can be independently powered; each core cluster can be independently clock gated when all cores are clock gated or power gated; and / or each core cluster can be independently power gated when all cores are power gated. In at least one embodiment, one or more CPUs 1306 can further implement an enhanced algorithm for managing power states, where allowed power states and expected wakeup times are specified, and hardware / microcode determines the optimal power state for the core, cluster, and CCPLEX input. In at least one embodiment, the processing core can support a simplified power state entry sequence in software, where the work is offloaded to the microcode. In at least one embodiment, the processing core is referred to as a compute unit or arithmetic unit.

[0200] In at least one embodiment, one or more GPUs 1308 may include an integrated GPU (or alternatively referred to herein as an "iGPU"). In at least one embodiment, one or more GPUs 1308 may be programmable and may be efficient for parallel workloads. In at least one embodiment, one or more GPUs 1308 may utilize an enhanced tensor instruction set. In one embodiment, one or more GPUs 1308 may include one or more streaming microprocessors, wherein each streaming microprocessor may include a level 1 ("L1") cache (e.g., an L1 cache having at least 96KB of storage capacity), and two or more streaming microprocessors may share an L2 cache (e.g., an L2 cache having 512KB of storage capacity). In at least one embodiment, one or more GPUs 1308 may include at least eight streaming microprocessors. In at least one embodiment, one or more GPUs 1308 may utilize a computing application programming interface (API). In at least one embodiment, one or more GPUs 1308 may utilize one or more parallel computing platforms and / or programming models (e.g., NVIDIA's CUDA).

[0201] In at least one embodiment, one or more GPUs 1308 can be power-optimized for optimal performance in automotive and embedded use cases. For example, in one embodiment, one or more GPUs 1308 can be fabricated on fin field-effect transistors (“FinFETs”). In at least one embodiment, each streaming microprocessor can include multiple mixed-precision processing cores partitioned into multiple blocks. For example, but not limited to, 64 PF32 cores and 32 PF64 cores can be partitioned into four processing blocks. In at least one embodiment, each processing block can be allocated 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed-precision NVIDIA Tensor Cores for deep learning matrix arithmetic, a level zero (“L0”) instruction cache, a warp scheduler, a dispatch unit, and / or a 64KB register file. In at least one embodiment, the streaming microprocessor can include independent parallel integer and floating-point data paths to provide efficient execution of workloads that mix compute and addressing operations. In at least one embodiment, the streaming microprocessor can include independent thread scheduling capabilities to enable finer-grained synchronization and collaboration between parallel threads. In at least one embodiment, a streaming microprocessor may include a combined L1 data cache and shared memory unit to improve performance while simplifying programming.

[0202] In at least one embodiment, one or more GPUs 1308 may include high bandwidth memory ("HBM") and / or a 16GB HBM2 memory subsystem to provide a peak memory bandwidth of approximately 900 GB / s in some examples. In at least one embodiment, synchronous graphics random access memory ("SGRAM"), such as graphics double data rate type five synchronous random access memory ("GDDR5"), may be used in addition to or in lieu of HBM memory.

[0203] In at least one embodiment, the one or more GPUs 1308 may include unified memory technology. In at least one embodiment, address translation services ("ATS") support may be used to allow the one or more GPUs 1308 to directly access the one or more CPUs 1306 page tables. In at least one embodiment, when the one or more GPUs 1308 memory management units ("MMUs") experience a miss, an address translation request may be sent to the one or more CPUs 1306. In response, in at least one embodiment, the one or more CPUs 1306 may look up the virtual-to-physical mapping of the address in its page table and transmit the translation back to the one or more GPUs 1308. In at least one embodiment, unified memory technology may allow a single unified virtual address space to be used for memory for both the one or more CPUs 1306 and the one or more GPUs 1308, thereby simplifying programming the one or more GPUs 1308 and porting applications to the one or more GPUs 1308.

[0204] In at least one embodiment, one or more GPUs 1308 may include any number of access counters that can track the frequency with which one or more GPUs 1308 access the memory of other processors. In at least one embodiment, the one or more access counters can help ensure that memory pages are moved to the physical memory of the processor that accesses the page most frequently, thereby improving the efficiency of memory ranges shared between processors.

[0205] In at least one embodiment, one or more SoCs 1304 may include any number of caches 1312, including those described herein. For example, in at least one embodiment, one or more caches 1312 may include a level 3 ("L3") cache available to one or more CPUs 1306 and one or more GPUs 1308 (e.g., connected to CPUs 1306 and GPUs 1308). In at least one embodiment, one or more caches 1312 may include a write-back cache that can track the state of a line, for example, by using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, the L3 cache may include 4MB or more, depending on the embodiment, although smaller cache sizes may be used.

[0206] In at least one embodiment, one or more SoCs 1304 may include one or more accelerators 1314 (e.g., hardware accelerators, software accelerators, or a combination thereof). In at least one embodiment, one or more SoCs 1304 may include a hardware acceleration cluster that may include optimized hardware accelerators and / or large on-chip memory. In at least one embodiment, large on-chip memory (e.g., 4MB of SRAM) may enable the hardware acceleration cluster to accelerate neural networks and other computations. In at least one embodiment, the hardware acceleration cluster may be used to supplement one or more GPUs 1308 and offload some tasks of one or more GPUs 1308 (e.g., freeing up more cycles of one or more GPUs 1308 to perform other tasks). In at least one embodiment, one or more accelerators 1314 may be used for target workloads that are sufficiently stable to withstand acceleration testing (e.g., perception, convolutional neural networks (“CNNs”), recurrent neural networks (“RNNs”), etc.). In at least one embodiment, CNNs may include region-based or region-based convolutional neural networks (“RCNNs”) and fast RCNNs (e.g., as used for object detection) or other types of CNNs.

[0207] In at least one embodiment, one or more accelerators 1314 (e.g., a hardware acceleration cluster) may include one or more deep learning accelerators ("DLAs"). One or more DLAs may include, but are not limited to, one or more Tensor Processing Units ("TPUs"), which may be configured to provide an additional 10 trillion operations per second for deep learning applications and reasoning. In at least one embodiment, a TPU may be an accelerator configured and optimized to perform image processing functions (e.g., for CNN, RCNN, etc.). One or more DLAs may be further optimized for a specific set of neural network types and floating-point operations and reasoning. In at least one embodiment, the design of one or more DLAs may provide higher performance per millimeter than a typical general-purpose GPU, and generally significantly exceeds the performance of a CPU. In at least one embodiment, one or more TPUs may perform several functions, including single-instance convolution functions that support, for example, INT8, INT16, and FP16 data types for features and weights, as well as post-processor functions. In at least one embodiment, one or more DLAs can quickly and efficiently execute neural networks, particularly CNNs, on processed or unprocessed data for any of a variety of functions, including, for example, but not limited to: a CNN for object recognition and detection using data from a camera sensor; a CNN for distance estimation using data from a camera sensor; a CNN for emergency vehicle detection and identification and detection using data from a microphone 1396; a CNN for face recognition and vehicle owner recognition using data from a camera sensor; and / or a CNN for safety and / or security-related events.

[0208] In at least one embodiment, a DLA can perform any function of one or more GPUs 1308, and by using an inference accelerator, for example, a designer can target any function to either one or more DLAs or one or more GPUs 1308. For example, in at least one embodiment, a designer can focus CNN processing and floating-point operations on one or more DLAs and leave other functions to one or more GPUs 1308 and / or other one or more accelerators 1314.

[0209] In at least one embodiment, one or more accelerators 1314 (e.g., a hardware acceleration cluster) may include a programmable vision accelerator ("PVA"), which may be referred to herein alternatively as a computer vision accelerator. In at least one embodiment, one or more PVAs may be designed and configured to accelerate computer vision algorithms for advanced driver assistance systems ("ADAS") 1338, autonomous driving, augmented reality ("AR") applications, and / or virtual reality ("VR") applications. In at least one embodiment, one or more PVAs may strike a balance between performance and flexibility. For example, in at least one embodiment, each of the one or more PVAs may include, for example, but not limited to, any number of reduced instruction set computer ("RISC") cores, direct memory access ("DMA"), and / or any number of vector processors.

[0210] In at least one embodiment, the RISC core can interact with an image sensor (e.g., an image sensor of any camera described herein), an image signal processor, and the like. In at least one embodiment, each RISC core can include any amount of memory. In at least one embodiment, the RISC core can use any of a variety of protocols, depending on the embodiment. In at least one embodiment, the RISC core can execute a real-time operating system ("RTOS"). In at least one embodiment, the RISC core can be implemented using one or more integrated circuit devices, application specific integrated circuits ("ASICs"), and / or memory devices. For example, in at least one embodiment, the RISC core can include an instruction cache and / or tightly coupled RAM.

[0211] In at least one embodiment, the DMA can enable components of the PVA to access system memory independently of the one or more CPUs 1306. In at least one embodiment, the DMA can support any number of features for providing optimizations to the PVA, including, but not limited to, support for multi-dimensional addressing and / or circular addressing. In at least one embodiment, the DMA can support up to six or more dimensions of addressing, which can include, but are not limited to, block width, block height, block depth, horizontal block stride, vertical block stride, and / or depth stride.

[0212] In at least one embodiment, the vector processor can be a programmable processor that can be designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing capabilities. In at least one embodiment, the PVA can include a PVA core and two vector processing subsystem partitions. In at least one embodiment, the PVA core can include a processor subsystem, a DMA engine (e.g., two DMA engines), and / or other peripherals. In at least one embodiment, the vector processing subsystem can serve as the main processing engine of the PVA and can include a vector processing unit ("VPU"), an instruction cache, and / or a vector memory (e.g., "VMEM"). In at least one embodiment, the VPU core can include a digital signal processor, such as a single instruction multiple data ("SIMD"), a very long instruction word ("VLIW") digital signal processor. In at least one embodiment, the combination of SIMD and VLIW can increase throughput and speed.

[0213] In at least one embodiment, each vector processor may include an instruction cache and may be coupled to a dedicated memory. As a result, in at least one embodiment, each vector processor may be configured to execute independently of the other vector processors. In at least one embodiment, the vector processors included in a particular PVA may be configured to exploit data parallelism. For example, in at least one embodiment, multiple vector processors included in a single PVA may execute the same computer vision algorithm, but on different regions of an image. In at least one embodiment, the vector processors included in a particular PVA may execute different computer vision algorithms simultaneously on the same image, or even execute different algorithms on sequenced images or portions of images. In at least one embodiment, any number of PVAs may be included in the hardware acceleration cluster, and any number of vector processors may be included in each PVA, among other things. In at least one embodiment, the PVAs may include additional error correction code ("ECC") memory to enhance overall system security.

[0214] In at least one embodiment, one or more accelerators 1314 (e.g., a hardware acceleration cluster) may include an on-chip computer vision network and static random access memory ("SRAM") to provide high bandwidth, low latency SRAM to one or more accelerators 1314. In at least one embodiment, the on-chip memory may include at least 4MB of SRAM, including, for example, but not limited to, eight field-configurable memory blocks that can be accessed by both the PVA and the DLA. In at least one embodiment, each pair of memory blocks may include an advanced peripheral bus ("APB") interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used. In at least one embodiment, the PVA and the DLA may access the memory via a backbone network that provides high-speed access to the memory to the PVA and the DLA. In at least one embodiment, the backbone network may include an on-chip computer vision network that interconnects the PVA and the DLA to the memory (e.g., using APB).

[0215] In at least one embodiment, the on-chip computer vision network may include an interface that determines that both the PVA and DLA provide ready and valid signals before transmitting any control signals / addresses / data. In at least one embodiment, the interface may provide separate phases and separate channels for sending control signals / addresses / data, as well as burst-type communication for continuous data transmission. In at least one embodiment, the interface may conform to the International Organization for Standardization ("ISO") 26262 or the International Electrotechnical Commission ("IEC") 61408 standards, although other standards and protocols may be used.

[0216] In at least one embodiment, one or more SoCs 1304 may include a real-time gaze tracking hardware accelerator. In at least one embodiment, the real-time gaze tracking hardware accelerator may be used to quickly and efficiently determine the position and range of objects (e.g., within a world model) to generate real-time visual simulations for use in RADAR signal interpretation, for sound propagation synthesis and / or analysis, for simulation of SONAR systems, for general wave propagation simulations, for comparison with LIDAR data for positioning and / or other functions, and / or for other uses.

[0217] In at least one embodiment, one or more accelerators 1314 (e.g., a hardware acceleration cluster) have a wide range of uses for autonomous driving. In at least one embodiment, the PVA can be a programmable vision accelerator that is used in key processing stages in ADAS and autonomous vehicles. In at least one embodiment, the capabilities of the PVA at low power and low latency are well matched to the algorithmic domain that requires predictable processing. In other words, the PVA performs well in semi-intensive or intensive conventional computations, even on small data sets, which may require predictable runtimes with low latency and low power. In at least one embodiment, an autonomous vehicle, such as in vehicle 1300, may be designed to run classic computer vision algorithms because they can be efficient at object detection and integer math operations.

[0218] For example, according to at least one embodiment of the technology, PVA is used to perform computer stereo vision. In at least one embodiment, a semi-global matching-based algorithm can be used in some examples, although this is not meant to be limiting. In at least one embodiment, applications for Level 3-5 autonomous driving use dynamic estimation / stereo matching on the fly (e.g., structure from motion, pedestrian recognition, lane detection, etc.). In at least one embodiment, PVA can perform computer stereo vision functions on input from two monocular cameras.

[0219] In at least one embodiment, the PVA can be used to perform dense optical flow. For example, in at least one embodiment, the PVA can process raw RADAR data (e.g., using a 4D Fast Fourier Transform) to provide processed RADAR data. In at least one embodiment, the PVA is used for time-of-flight depth processing, for example, by processing raw time-of-flight data to provide processed time-of-flight data.

[0220] In at least one embodiment, the DLA can be used to run any type of network to enhance control and driving safety, including, for example, but not limited to, a neural network that outputs a confidence score for each object detection. In at least one embodiment, the confidence score can be expressed or interpreted as a probability, or as providing a relative "weight" of each detection relative to other detections. In at least one embodiment, the confidence score enables the system to make further decisions about which detections should be considered true positive detections rather than false positive detections. In at least one embodiment, the system can set a threshold for the confidence score and only consider detections that exceed the threshold as true positive detections. In embodiments using an automatic emergency braking ("AEB") system, a false positive detection will cause the vehicle to automatically perform emergency braking, which is obviously undesirable. In at least one embodiment, a highly confident detection can be considered a trigger for AEB. In at least one embodiment, the DLA can run a neural network for regressing the confidence score. In at least one embodiment, the neural network may take as its input at least some subset of parameters, such as bounding box dimensions, a ground plane estimate obtained (e.g., from another subsystem), outputs of one or more IMU sensors 1366 associated with vehicle 1300 heading, distance, 3D position estimates of objects obtained from the neural network and / or other sensors (e.g., one or more LIDAR sensors 1364 or one or more RADAR sensors 1360), etc.

[0221] In at least one embodiment, one or more SoCs 1304 (e.g., a hardware acceleration cluster) may include one or more data stores 1316 (e.g., memory). In at least one embodiment, one or more data stores 1316 may be on-chip memory of one or more SoCs 1304 that may store neural networks to be executed on one or more GPUs 1308 and / or DLAs. In at least one embodiment, one or more data stores 1316 may have a capacity large enough to store multiple instances of a neural network for redundancy and safety. In at least one embodiment, one or more data stores 1312 may include an L2 or L3 cache.

[0222] In at least one embodiment, one or more SoCs 1304 may include any number of processors 1310 (e.g., embedded processors). In at least one embodiment, one or more processors 1310 may include a boot and power management processor, which may be a dedicated processor and subsystem to handle boot power and management functions and related security implementations. In at least one embodiment, the boot and power management processor may be part of the boot sequence of one or more SoCs 1304 and may provide runtime power management services. In at least one embodiment, the boot power and management processor may provide clock and voltage programming, assist in system low-power state transitions, one or more SoCs 1304 thermal and temperature sensor management, and / or one or more SoCs 1304 power state management. In at least one embodiment, each temperature sensor may be implemented as a ring oscillator whose output frequency is proportional to temperature, and one or more SoCs 1304 may use the ring oscillator to detect the temperature of one or more CPUs 1306, one or more GPUs 1308, and / or one or more accelerators 1314. In at least one embodiment, if the temperature is determined to exceed a threshold, the boot and power management processor may enter a temperature fault routine and place one or more SoCs 1304 into a lower power consumption state and / or place the vehicle 1300 into a driver's safe parking pattern (e.g., bringing the vehicle 1300 to a safe stop).

[0223] In at least one embodiment, one or more processors 1310 may further include a set of embedded processors that can be used as an audio processing engine. In at least one embodiment, the audio processing engine can be an audio subsystem that can provide hardware with full hardware support for multi-channel audio through multiple interfaces and a wide and flexible range of audio I / O interfaces. In at least one embodiment, the audio processing engine is a dedicated processor core that has a digital signal processor with dedicated RAM.

[0224] In at least one embodiment, one or more processors 1310 may further include an always-on processor engine. In at least one embodiment, the automatic processing engine may provide the necessary hardware features to support low-power sensor management and wake-up use cases. In at least one embodiment, the processors on the always-on processor engine may include, but are not limited to, a processor core, tightly coupled RAM, supporting peripherals (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0225] In at least one embodiment, one or more processors 1310 may further include a safety cluster engine, which may include but is not limited to a dedicated processor subsystem for handling safety management of automotive applications. In at least one embodiment, the safety cluster engine may include but is not limited to two or more processor cores, tightly coupled RAM, supporting peripherals (e.g., timers, interrupt controllers, etc.) and / or routing logic. In safety mode, in at least one embodiment, the two or more cores may operate in lockstep mode and may function as a single core with comparison logic to detect any differences between their operations. In at least one embodiment, one or more processors 1310 may further include a real-time camera engine, which may include but is not limited to a dedicated processor subsystem for handling real-time camera management. In at least one embodiment, one or more processors 1310 may further include a high dynamic range signal processor, which may include but is not limited to an image signal processor, which is a hardware engine that is part of the camera processing pipeline.

[0226] In at least one embodiment, one or more processors 1310 may include a video image synthesizer, which may be a processing block (e.g., implemented on a microprocessor) that implements the video post-processing functions required by a video playback application to produce the final video, thereby generating the final image for the player window. In at least one embodiment, the video image synthesizer may perform lens distortion correction on one or more wide-angle cameras 1370, one or more surround cameras 1374, and / or one or more in-cabin monitoring camera sensors. In at least one embodiment, the in-cabin monitoring camera sensors are preferably monitored by a neural network running on another instance of SoC 1304, the neural network being configured to identify cabin events and respond accordingly. In at least one embodiment, the in-cabin system may perform, but is not limited to, lip reading to activate cellular service and place calls, dictate emails, change the vehicle's destination, activate or change the vehicle's infotainment system and settings, or provide voice-activated web surfing. In at least one embodiment, certain features are available to the driver when the vehicle is operating in autonomous mode, but are otherwise disabled.

[0227] In at least one embodiment, the video image compositor may include enhanced temporal noise reduction for simultaneous spatial and temporal noise reduction. For example, in at least one embodiment, where motion occurs in the video, the noise reduction appropriately weights the spatial information, thereby reducing the weight of information provided by adjacent frames. In at least one embodiment, where an image or portion of an image does not include motion, the temporal noise reduction performed by the video image compositor may use information from previous images to reduce noise in the current image.

[0228] In at least one embodiment, the video image compositor can also be configured to perform stereoscopic rectification on the input stereoscopic lens frames. In at least one embodiment, the video image compositor can also be used for user interface composition when using an operating system desktop, without requiring one or more GPUs 1308 to continuously render new surfaces. In at least one embodiment, when one or more GPUs 1308 are powered and actively performing 3D rendering, the video image compositor can be used to offload one or more GPUs 1308 to improve performance and responsiveness.

[0229] In at least one embodiment, one or more of the SoCs 1304 may further include a Mobile Industry Processor Interface ("MIPI") camera serial interface for receiving video and input from a camera, a high-speed interface, and / or a video input block that may be used for a camera and associated pixel input functionality. In at least one embodiment, one or more of the SoCs 1304 may further include an input / output controller that may be controlled by software and may be used to receive I / O signals that are not assigned to a specific role.

[0230] In at least one embodiment, one or more of the SoCs 1304 may further include a wide range of peripheral interfaces to enable communication with peripheral devices, audio encoders / decoders (“codecs”), power management, and / or other devices. The one or more SoCs 1304 may be configured to process data from cameras (e.g., via Gigabit multimedia serial links and Ethernet connections), sensors (e.g., one or more LIDAR sensors 1364, one or more RADAR sensors 1360, etc., which may be connected via Ethernet), data from the bus 1302 (e.g., vehicle 1300 speed, steering wheel position, etc.), data from one or more GNSS sensors 1358 (e.g., via Ethernet bus or CAN bus connections), and the like. In at least one embodiment, one or more of the SoCs 1304 may further include dedicated high-performance mass storage controllers, which may include their own DMA engines and may be used to offload the one or more CPUs 1306 from routine data management tasks.

[0231] In at least one embodiment, one or more SoCs 1304 can be an end-to-end platform with a flexible architecture that spans automation levels 3-5, thereby providing a comprehensive functional safety architecture that leverages and effectively uses computer vision and ADAS technologies to achieve diversity and redundancy, providing a platform that can provide a flexible and reliable driving software stack and deep learning tools. In at least one embodiment, one or more SoCs 1304 can be faster and more reliable than conventional systems, and even more energy and space efficient. For example, in at least one embodiment, one or more accelerators 1314, when combined with one or more CPUs 1306, one or more GPUs 1308, and one or more data stores 1316, can provide a fast and efficient platform for Level 3-5 autonomous driving vehicles.

[0232] In at least one embodiment, computer vision algorithms can be executed on a CPU, which can be configured using a high-level programming language (e.g., the C programming language) to execute a variety of processing algorithms on a variety of visual data. However, in at least one embodiment, CPUs generally cannot meet the performance requirements of many computer vision applications, such as those related to execution time and power consumption. In at least one embodiment, many CPUs are unable to execute complex object detection algorithms in real time, which are used in in-vehicle ADAS applications and actual Level 3-5 autonomous driving vehicles.

[0233] The embodiments described herein allow for the execution of multiple neural networks simultaneously and / or sequentially, and for the results to be combined together to achieve Level 3-5 autonomous driving functionality. For example, in at least one embodiment, a CNN executed on a DLA or a discrete GPU (e.g., one or more GPUs 1320) may include text and word recognition, thereby allowing the supercomputer to read and understand traffic signs, including signs for which the neural network has not been specifically trained. In at least one embodiment, the DLA may also include a neural network that can recognize, interpret, and provide semantic understanding of the signs and pass this semantic understanding to a path planning module running on the CPU Complex.

[0234] In at least one embodiment, for Level 3, 4, or 5 driving, multiple neural networks can be run simultaneously. For example, in at least one embodiment, a warning sign consisting of "Caution: flashing lights indicate icy conditions" along with connected lights can be interpreted independently or collectively by multiple neural networks. In at least one embodiment, the sign itself can be identified as a traffic sign by a first deployed neural network (e.g., a trained neural network), and the text "flashing lights indicate icy conditions" can be interpreted by a second deployed neural network, which notifies the vehicle's path planning software (preferably executing on a CPU Complex) that icy conditions exist when flashing lights are detected. In at least one embodiment, flashing lights can be identified by operating a third deployed neural network over multiple frames, notifying the vehicle's path planning software of the presence (or absence) of flashing lights. In at least one embodiment, all three neural networks can run simultaneously, for example within the DLA and / or on one or more GPUs 1308.

[0235] In at least one embodiment, a CNN for facial recognition and vehicle owner identification can use data from the camera sensor to identify the presence of an authorized driver and / or owner of the vehicle 1300. In at least one embodiment, an always-on sensor processor engine can be used to unlock the vehicle when the owner approaches the driver's door and turns on the lights, and, in security mode, can be used to disable the vehicle when the owner leaves the vehicle. In this way, one or more SoCs 1304 provide protection against theft and / or carjacking.

[0236] In at least one embodiment, a CNN for emergency vehicle detection and identification can use data from microphone 1396 to detect and identify emergency vehicle sirens. In at least one embodiment, one or more SoCs 1304 use the CNN to classify environmental and urban sounds, as well as classify visual data. In at least one embodiment, the CNN running on the DLA is trained to identify the relative approaching speed of the emergency vehicle (e.g., by using the Doppler effect). In at least one embodiment, the CNN can also be trained to identify emergency vehicles for the area in which the vehicle is operating, as identified by one or more GNSS sensors 1358. In at least one embodiment, when operating in Europe, the CNN will seek to detect European sirens, while when operating in the United States, the CNN will seek to identify only North American sirens. In at least one embodiment, once an emergency vehicle is detected, a control program can be used with the assistance of one or more ultrasonic sensors 1362 to execute emergency vehicle safety routines, slow the vehicle, pull over, stop the vehicle, and / or idle the vehicle until the emergency vehicle passes.

[0237] In at least one embodiment, the vehicle 1300 may include one or more CPUs 1318 (e.g., one or more discrete CPUs or one or more dCPUs) that may be coupled to the one or more SoCs 1304 via a high-speed interconnect (e.g., PCIe). In at least one embodiment, the one or more CPUs 1318 may include an X86 processor, for example, and the one or more CPUs 1318 may be used to perform any of a variety of functions, including, for example, arbitrating potential inconsistent results between ADAS sensors and the one or more SoCs 1304, and / or monitoring the status and health of one or more controllers 1336 and / or an information system on a chip ("information SoC") 1330.

[0238] In at least one embodiment, the vehicle 1300 may include one or more GPUs 1320 (e.g., one or more discrete GPUs or one or more dGPUs) that may be coupled to the one or more SoCs 1304 via a high-speed interconnect (e.g., NVIDIA's NVLINK). In at least one embodiment, the one or more GPUs 1320 may provide additional artificial intelligence functionality, such as by executing redundant and / or different neural networks, and may be used to train and / or update the neural networks based at least in part on input (e.g., sensor data) from sensors of the vehicle 1300.

[0239] In at least one embodiment, vehicle 1300 may further include a network interface 1324, which may include, but is not limited to, one or more wireless antennas 1326 (e.g., one or more wireless antennas 1326 for different communication protocols, such as cellular antennas, Bluetooth antennas, etc.). In at least one embodiment, network interface 1324 may be used to enable wireless connectivity with other vehicles and / or computing devices (e.g., a passenger's client device) via the internet with a cloud (e.g., using a server and / or other network devices). In at least one embodiment, to communicate with other vehicles, a direct link may be established between vehicle 1300 and the other vehicle, and / or an indirect link may be established (e.g., via a network and the internet). In at least one embodiment, a vehicle-to-vehicle communication link may be used to provide the direct link. In at least one embodiment, the vehicle-to-vehicle communication link may provide vehicle 1300 with information about vehicles in its vicinity (e.g., vehicles in front of, to the sides of, and / or behind vehicle 1300). In at least one embodiment, this functionality may be part of the cooperative adaptive cruise control functionality of vehicle 1300.

[0240] In at least one embodiment, the network interface 1324 may include a SoC that provides modulation and demodulation functionality and enables one or more controllers 1336 to communicate over a wireless network. In at least one embodiment, the network interface 1324 may include a radio frequency front end for up-conversion from baseband to radio frequency and down-conversion from radio frequency to baseband. In at least one embodiment, frequency conversion may be performed in any technically feasible manner. For example, frequency conversion may be performed by well-known processes and / or using a superheterodyne process. In at least one embodiment, the radio frequency front end functionality may be provided by a separate chip. In at least one embodiment, the network interface may include wireless functionality for communicating over LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0241] In at least one embodiment, the vehicle 1300 may further include one or more data stores 1328, which may include, but are not limited to, off-chip (e.g., one or more SoCs 1304) storage. In at least one embodiment, the one or more data stores 1328 may include, but are not limited to, one or more storage elements including RAM, SRAM, dynamic random access memory ("DRAM"), video random access memory ("VRAM"), flash memory, a hard disk, and / or other components and / or devices that can store at least one bit of data.

[0242] In at least one embodiment, the vehicle 1300 may further include one or more GNSS sensors 1358 (e.g., GPS and / or assisted GPS sensors) to assist with mapping, perception, occupancy raster generation, and / or path planning functions. In at least one embodiment, any number of GNSS sensors 1358 may be used, including, for example, but not limited to, GPS connected to a serial interface (e.g., RS-232) bridge using a USB connector with Ethernet.

[0243] In at least one embodiment, the vehicle 1300 may further include one or more RADAR sensors 1360. One or more RADAR sensors 1360 may be used by the vehicle 1300 for remote vehicle detection, even in darkness and / or in adverse weather conditions. In at least one embodiment, the RADAR functional safety level may be ASIL B. One or more RADAR sensors 1360 may use a CAN bus and / or bus 1302 (e.g., to transmit data generated by one or more RADAR sensors 1360) for control and access to object tracking data, and in some examples may access an Ethernet channel to access raw data. In at least one embodiment, a variety of RADAR sensor types may be used. For example, but not limited to, one or more of the RADAR sensors 1360 may be suitable for front, rear, and side RADAR use. In at least one embodiment, one or more RADAR sensors 1360 are pulse Doppler RADAR sensors.

[0244] In at least one embodiment, one or more RADAR sensors 1360 may include different configurations, such as long-range with a narrow field of view, short-range with a wide field of view, short-range side coverage, etc. In at least one embodiment, long-range RADAR can be used for adaptive cruise control functionality. In at least one embodiment, a long-range RADAR system can provide a wide field of view achieved through two or more independent scans (e.g., within a range of 250 meters). In at least one embodiment, one or more RADAR sensors 1360 can help distinguish between static and moving objects and can be used by the ADAS system 1338 for emergency brake assistance and forward collision warning. In at least one embodiment, the one or more sensors 1360 included in the long-range RADAR system may include, but are not limited to, a monostatic multi-mode RADAR with multiple (e.g., six or more) fixed RADAR antennas and high-speed CAN and FlexRay interfaces. In at least one embodiment, having six antennas, with the four central antennas, can create a focused beam pattern designed to record the surroundings of the vehicle 1300 at higher speeds with minimal interference from traffic in adjacent lanes. In at least one embodiment, the additional two antennas may provide an expanded field of view, allowing for quick detection of vehicles entering or exiting the vehicle's 1300 lane.

[0245] In at least one embodiment, as an example, a medium-range RADAR system may include, for example, a range of up to 160m (front) or 80m (rear), and a field of view of up to 42 degrees (front) or 150 degrees (rear). In at least one embodiment, a short-range RADAR system may include, but is not limited to, any number of RADAR sensors 1360 designed to be mounted on both ends of the rear bumper. When mounted on both ends of the rear bumper, in at least one embodiment, the RADAR sensor system can generate two light beams that continuously monitor the rear of the vehicle and nearby blind spots. In at least one embodiment, the short-range RADAR system can be used in an ADAS system 1338 for blind spot detection and / or lane change assistance.

[0246] In at least one embodiment, the vehicle 1300 may further include one or more ultrasonic sensors 1362. In at least one embodiment, one or more ultrasonic sensors 1362, which may be positioned on the front, rear, and / or sides of the vehicle 1300, may be used for parking assistance and / or for creating and updating occupancy barriers. In at least one embodiment, a variety of ultrasonic sensors 1362 may be used, and different ultrasonic sensors 1362 may be used for different detection ranges (e.g., 2.5 m, 4 m). In at least one embodiment, the ultrasonic sensors 1362 may operate at an ASIL B functional safety level.

[0247] In at least one embodiment, the vehicle 1300 can include one or more LIDAR sensors 1364. The one or more LIDAR sensors 1364 can be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, the one or more LIDAR sensors 1364 can be functional safety level ASIL B. In at least one embodiment, the vehicle 1300 can include multiple (e.g., two, four, six, etc.) LIDAR sensors 1364 that can use Ethernet (e.g., provide data to a Gigabit Ethernet switch).

[0248] In at least one embodiment, one or more LIDAR sensors 1364 may be capable of providing a list of objects and their distances for a 360-degree field of view. In at least one embodiment, commercially available one or more LIDAR sensors 1364 may, for example, have an advertised range of approximately 100 meters, an accuracy of 2-3 cm, and support a 100 Mbps Ethernet connection. In at least one embodiment, one or more non-obtrusive LIDAR sensors 1364 may be used. In such an embodiment, one or more LIDAR sensors 1364 may be implemented as small devices embedded in the front, rear, sides, and / or corners of vehicle 1300. In at least one embodiment, one or more LIDAR sensors 1364 may provide a horizontal field of view of up to 120 degrees and a vertical field of view of 35 degrees, even for low-reflectivity objects, and a range of 200 meters. In at least one embodiment, the forward-facing one or more LIDAR sensors 1364 may be configured for a horizontal field of view between 45 and 135 degrees.

[0249] In at least one embodiment, LIDAR technology (such as 3D flash LIDAR) may also be used. 3D flash LIDAR uses a laser flash as a transmission source to illuminate approximately 200 meters around vehicle 1300. In at least one embodiment, the flash LIDAR unit includes, but is not limited to, a receiver that records the laser pulse propagation time and the reflected light at each pixel, which in turn corresponds to the range from vehicle 1300 to the object. In at least one embodiment, flash LIDAR can enable the generation of a highly accurate and distortion-free image of the surrounding environment with each laser flash. In at least one embodiment, four flash LIDAR sensors can be deployed, one on each side of vehicle 1300. In at least one embodiment, the 3D flash LIDAR system includes, but is not limited to, a solid-state 3D line-of-sight array LIDAR camera with no moving components other than a fan (e.g., a non-scanning LIDAR device). In at least one embodiment, the flash LIDAR device can use 5 nanosecond Class I (eye-safe) laser pulses per frame and can capture the reflected laser light in the form of a 3D range point cloud and co-registered intensity data.

[0250] In at least one embodiment, the vehicle 1300 may also include one or more IMU sensors 1366. In at least one embodiment, the one or more IMU sensors 1366 may be located at the center of the rear axle of the vehicle 1300. In at least one embodiment, the one or more IMU sensors 1366 may include, for example, but not limited to, one or more accelerometers, one or more magnetometers, one or more gyroscopes, one or more magnetic compasses, and / or other sensor types. In at least one embodiment, for example, in a six-axis application, the one or more IMU sensors 1366 may include, but not limited to, accelerometers and gyroscopes. In at least one embodiment, for example, in a nine-axis application, the one or more IMU sensors 1366 may include, but not limited to, accelerometers, gyroscopes, and magnetometers.

[0251] In at least one embodiment, one or more IMU sensors 1366 can be implemented as a miniature, high-performance GPS-aided inertial navigation system ("GPS / INS") that combines microelectromechanical system ("MEMS") inertial sensors, a high-sensitivity GPS receiver, and advanced Kalman filtering algorithms to provide estimates of position, velocity, and attitude; in at least one embodiment, one or more IMU sensors 1366 can enable vehicle 1300 to estimate heading without input from a magnetic sensor by directly observing and correlating velocity changes from GPS to one or more IMU sensors 1366. In at least one embodiment, one or more IMU sensors 1366 and one or more GNSS sensors 1358 can be combined in a single integrated unit.

[0252] In at least one embodiment, the vehicle 1300 can include one or more microphones 1396 positioned within and / or around the vehicle 1300. In at least one embodiment, the one or more microphones 1396 can be used for emergency vehicle detection and identification, among other things.

[0253] In at least one embodiment, the vehicle 1300 may further include any number of camera types, including one or more stereo cameras 1368, one or more wide angle cameras 1370, one or more infrared cameras 1372, one or more surround cameras 1374, one or more long range cameras 1398, one or more mid range cameras 1376, and / or other camera types. In at least one embodiment, the cameras may be used to capture image data around the entire periphery of the vehicle 1300. In at least one embodiment, the type of camera used depends on the vehicle 1300. In at least one embodiment, any combination of camera types may be used to provide the necessary coverage around the vehicle 1300. In at least one embodiment, the number of cameras deployed may vary depending on the embodiment. For example, in at least one embodiment, the vehicle 1300 may include six cameras, seven cameras, ten cameras, twelve cameras, or another number of cameras. In at least one embodiment, the cameras may, by way of example but not limitation, support Gigabit Multimedia Serial Link ("GMSL") and / or Gigabit Ethernet. In at least one embodiment, the present disclosure previously referred to herein may provide a plurality of cameras. Figure 13A and Figure 13B Each camera can be described in more detail.

[0254] In at least one embodiment, vehicle 1300 may further include one or more vibration sensors 1342. In at least one embodiment, one or more vibration sensors 1342 may measure vibration of a component (e.g., an axle) of vehicle 1300. For example, in at least one embodiment, a change in vibration may indicate a change in the road surface. In at least one embodiment, when two or more vibration sensors 1342 are used, the difference between the vibrations may be used to determine friction or slippage in the road surface (e.g., when there is a vibration difference between a powered drive shaft and a freely rotating shaft).

[0255] In at least one embodiment, the vehicle 1300 may include an ADAS system 1338. The ADAS system 1338 may include, but is not limited to, an SoC. In at least one embodiment, the ADAS system 1338 may include, but is not limited to, any number of autonomous / adaptive / automatic cruise control ("ACC") systems, cooperative adaptive cruise control ("CACC") systems, forward collision warning ("FCW") systems, automatic emergency braking ("AEB") systems, lane departure warning ("LDW") systems, lane keeping assist ("LKA") systems, blind spot alert ("BSW") systems, rear cross traffic alert ("RCTW") systems, collision warning ("CW") systems, lane centering ("LC") systems, and / or other systems, features, and / or functions, and combinations thereof.

[0256] In at least one embodiment, the ACC system may utilize one or more RADAR sensors 1360, one or more LIDAR sensors 1364, and / or any number of cameras. In at least one embodiment, the ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, the longitudinal ACC system monitors and controls the distance to the vehicle immediately ahead of the vehicle 1300 and automatically adjusts the speed of the vehicle 1300 to maintain a safe distance from the vehicle ahead. In at least one embodiment, the lateral ACC system performs distance keeping and recommends that the vehicle 1300 change lanes when necessary. In at least one embodiment, lateral ACC is associated with other ADAS applications, such as LC and CW.

[0257] In at least one embodiment, the CACC system uses information from other vehicles, which may be received from the other vehicles via a wireless link or indirectly via a network connection (e.g., via the Internet) via a network interface 1324 and / or one or more wireless antennas 1326. In at least one embodiment, the direct link may be provided by a vehicle-to-vehicle ("V2V") communication link, while the indirect link may be provided by an infrastructure-to-vehicle ("I2V") communication link. Typically, the V2V communication concept provides information about the vehicle immediately ahead (e.g., the vehicle immediately ahead of vehicle 1300 and in the same lane as it), while the I2V communication concept provides information about traffic further ahead. In at least one embodiment, the CACC system may include one or both of the I2V and V2V information sources. In at least one embodiment, given information about vehicles ahead of vehicle 1300, the CACC system may be more reliable and have the potential to improve the smoothness of traffic flow and reduce road congestion.

[0258] In at least one embodiment, the FCW system is designed to warn the driver of hazards so that the driver can take corrective action. In at least one embodiment, the FCW system uses a forward-facing camera and / or one or more RADAR sensors 1360, which are coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to driver feedback, such as a display, speaker, and / or vibration component. In at least one embodiment, the FCW system can provide warnings, such as in the form of audible, visual warnings, vibrations, and / or rapid brake pulses.

[0259] In at least one embodiment, an AEB system detects an impending forward collision with another vehicle or other object and can automatically apply the brakes if the driver does not take corrective action within specified time or distance parameters. In at least one embodiment, the AEB system can utilize one or more forward-facing cameras and / or one or more RADAR sensors 1360 coupled to a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when the AEB system detects a hazard, the AEB system typically first warns the driver to take corrective action to avoid the collision, and, if the driver does not take corrective action, the AEB system can automatically apply the brakes to attempt to prevent or at least mitigate the effects of the predicted collision. In at least one embodiment, the AEB system can include technologies such as dynamic brake support and / or braking on impending collisions.

[0260] In at least one embodiment, the LDW system provides visual, audible, and / or tactile warnings, such as steering wheel or seat vibrations, to alert the driver when vehicle 1300 crosses a lane marking. In at least one embodiment, the LDW system is inactive when the driver indicates an intentional lane departure, such as by activating a turn signal. In at least one embodiment, the LDW system may utilize a front-facing camera coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to driver feedback such as a display, speaker, and / or vibration assembly. In at least one embodiment, a LKA system is a variation of the LDW system. If vehicle 1300 begins to leave its lane, the LKA system provides steering input or braking to correct vehicle 1300.

[0261] In at least one embodiment, the BSW system detects and warns the driver of vehicles in the car's blind spot. In at least one embodiment, the BSW system can provide visual, audible, and / or tactile alerts to indicate that merging or changing lanes is unsafe. In at least one embodiment, the BSW system can provide additional warnings when the driver uses a turn signal. In at least one embodiment, the BSW system can use one or more rear-facing cameras and / or one or more RADAR sensors 1360 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to driver feedback, such as a display, speaker, and / or vibration component.

[0262] In at least one embodiment, the RCTW system can provide visual, audible, and / or tactile notifications when an object is detected outside the rear camera range while the vehicle 1300 is in reverse. In at least one embodiment, the RCTW system includes an AEB system to ensure application of vehicle brakes to avoid a collision. In at least one embodiment, the RCTW system can use one or more rear-facing RADAR sensors 1360 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to driver feedback such as a display, speaker, and / or vibration component.

[0263] In at least one embodiment, conventional ADAS systems can be prone to generating false positive results, which can be annoying and distracting to the driver, but are generally not catastrophic because conventional ADAS systems alert the driver and allow the driver to decide whether a safe condition truly exists and take appropriate action. In at least one embodiment, in the event of conflicting results, the vehicle 1300 itself decides whether to follow the results of the primary or secondary computer (e.g., the first controller 1336 or the second controller 1336). For example, in at least one embodiment, the ADAS system 1338 can be a backup and / or secondary computer that provides perception information to a backup computer rationality module. In at least one embodiment, the backup computer rationality monitor can run redundant software on hardware components to detect failures in perception and dynamic driving tasks. In at least one embodiment, the output from the ADAS system 1338 can be provided to a supervisory MCU. In at least one embodiment, if the outputs from the primary and secondary computers conflict, the supervisory MCU determines how to reconcile the conflict to ensure safe operation.

[0264] In at least one embodiment, the primary computer can be configured to provide a confidence score to the supervisory MCU to indicate the primary computer's confidence in the selected result. In at least one embodiment, if the confidence score exceeds a threshold, the supervisory MCU can follow the primary computer's instructions regardless of whether the secondary computer provides conflicting or inconsistent results. In at least one embodiment, if the confidence score does not meet the threshold, and if the primary and secondary computers indicate different results (e.g., a conflict), the supervisory MCU can arbitrate between the computers to determine the appropriate result.

[0265] In at least one embodiment, the supervisory MCU can be configured to run a neural network that is trained and configured to determine, based at least in part on outputs from the primary and secondary computers, conditions under which the secondary computer provides a false alarm. In at least one embodiment, the neural network in the supervisory MCU can learn when the output of the secondary computer can be trusted and when it cannot be trusted. For example, in at least one embodiment, when the secondary computer is a RADAR-based FCW system, the neural network in the supervisory MCU can learn when the FCW system identifies a metal object that is not actually a danger, such as a drain grate or manhole cover, that would trigger an alarm. In at least one embodiment, when the secondary computer is a camera-based LDW system, the neural network in the supervisory MCU can learn to override the LDW when a cyclist or pedestrian is present and lane departure is actually the safest maneuver. In at least one embodiment, the supervisory MCU can include at least one of a DLA or a GPU suitable for running a neural network with associated memory. In at least one embodiment, the supervisory MCU can include and / or be included as a component of one or more SoCs 1304.

[0266] In at least one embodiment, the ADAS system 1338 may include an auxiliary computer that uses traditional computer vision rules to perform ADAS functions. In at least one embodiment, the auxiliary computer may use classical computer vision rules (if-then), and the presence of a neural network in the supervisory MCU may improve reliability, safety, and performance. For example, in at least one embodiment, the diverse implementations and intentional non-identity make the entire system more fault-tolerant, especially for failures caused by software (or software-hardware interface) functions. For example, in at least one embodiment, if there is a software vulnerability or bug in the software running on the main computer, and a different software code running on the auxiliary computer provides the same overall result, the supervisory MCU can be more confident that the overall result is correct and that the vulnerability in the software or hardware on the main computer did not cause a significant error.

[0267] In at least one embodiment, the output of the ADAS system 1338 can be input into the primary computer's perception module and / or the primary computer's dynamic driving task module. For example, in at least one embodiment, if the ADAS system 1338 indicates a forward collision warning due to an object directly ahead, the perception module can use this information when identifying the object. In at least one embodiment, as described herein, the secondary computer can have its own neural network that has been trained to reduce the risk of false positives.

[0268] In at least one embodiment, the vehicle 1300 may further include an infotainment SoC 1330 (e.g., an in-vehicle infotainment system (IVI)). Although shown and described as an SoC, in at least one embodiment, the infotainment system 1330 may not be a SoC and may include, but is not limited to, two or more discrete components. In at least one embodiment, the infotainment SoC 1330 may include, but is not limited to, a combination of hardware and software that can be used to provide audio (e.g., music, personal digital assistant, navigation instructions, news, radio, etc.), video (e.g., TV, movies, streaming, etc.), phone (e.g., hands-free calling), network connectivity (e.g., LTE, WiFi, etc.), and / or information services (e.g., a navigation system, rear parking assist, radio data system, vehicle-related information such as fuel level, total distance covered, brake fuel level, oil level, door open / closed, air filter information, etc.) to the vehicle 1300. For example, the infotainment SoC 1330 may include a radio, a disk player, a navigation system, a video player, USB and Bluetooth connectivity, a car, an in-vehicle entertainment system, WiFi, steering wheel audio controls, hands-free voice control, a heads-up display ("HUD"), an HMI display 1334, a telematics device, a control panel (e.g., for controlling and / or interacting with various components, features, and / or systems), and / or other components. In at least one embodiment, the infotainment SoC 1330 may be further configured to provide information (e.g., visual and / or auditory) to a user of the vehicle, such as information from an ADAS system 1338, autonomous driving information (such as planned vehicle maneuvers), trajectory, surrounding environment information (e.g., intersection information, vehicle information, road information, etc.), and / or other information.

[0269] In at least one embodiment, the infotainment SoC 1330 can include any number and type of GPU functionality. In at least one embodiment, the infotainment SoC 1330 can communicate with other devices, systems, and / or components of the vehicle 1300 via a bus 1302 (e.g., a CAN bus, Ethernet, etc.). In at least one embodiment, the infotainment SoC 1330 can be coupled to a supervisory MCU so that the infotainment system's GPU can perform some autonomous driving functions in the event of a failure of the main controller 1336 (e.g., the vehicle's 1300 main computer and / or backup computer). In at least one embodiment, the infotainment SoC 1330 can cause the vehicle 1300 to enter a driver-to-safety stop mode, as described herein.

[0270] In at least one embodiment, the vehicle 1300 may further include an instrument panel 1332 (e.g., a digital instrument panel, an electronic instrument panel, a digital instrument panel, etc.). In at least one embodiment, the instrument panel 1332 may include, but is not limited to, a controller and / or a supercomputer (e.g., a discrete controller or a supercomputer). In at least one embodiment, the instrument panel 1332 may include, but is not limited to, any number and combination of a set of instruments, such as a speedometer, fuel level, oil pressure, a tachometer, an odometer, a turn indicator, a gear position indicator, one or more seat belt warning lights, one or more parking brake warning lights, one or more engine check lights, supplemental restraint system (e.g., airbag) information, lighting controls, safety system controls, navigation information, etc. In some examples, information may be displayed and / or shared between the infotainment SoC 1330 and the instrument panel 1332. In at least one embodiment, the instrument panel 1332 may be included as part of the infotainment SoC 1330, or vice versa.

[0271] In at least one embodiment, the vehicle 1300 is integrated into Figure 1-11 In at least one embodiment, the CPU 1318 includes one or more circuits for performing operations such as those described above in conjunction with Figure 1-11 Describes the operation.

[0272] Figure 13D In accordance with at least one embodiment, a cloud-based server and Figure 13A13. A diagram of a system 1377 for communicating between autonomous vehicles 1300. In at least one embodiment, system 1377 may include, but is not limited to, one or more servers 1378, one or more networks 1390, and any number and type of vehicles, including vehicle 1300. One or more servers 1378 may include, but is not limited to, multiple GPUs 1384(A)-1384(H) (collectively referred to herein as GPUs 1384), PCIe switches 1382(A)-1382(D) (collectively referred to herein as PCIe switches 1382), and / or CPUs 1380(A)-1380(B) (collectively referred to herein as CPUs 1380). GPUs 1384, CPUs 1380, and PCIe switches 1382 may be interconnected with high-speed connections, such as, but not limited to, NVLink interface 1388 developed by NVIDIA and / or PCIe connections 1386. The GPUs 1384 are connected via NVLink and / or NVSwitch SoCs, and the GPUs 1384 and PCIe switches 1382 are connected via a PCIe interconnect. In at least one embodiment, although eight GPUs 1384, two CPUs 1380, and four PCIe switches 1382 are shown, this is not intended to be limiting. In at least one embodiment, each of the one or more servers 1378 may include, but is not limited to, any number of GPUs 1384, CPUs 1380, and / or PCIe switches 1382 in any combination. For example, in at least one embodiment, one or more servers 1378 may each include eight, sixteen, thirty-two, and / or more GPUs 1384.

[0273] In at least one embodiment, one or more servers 1378 may receive image data representing an image from a vehicle via one or more networks 1390 that depicts unexpected or altered road conditions, such as recently begun road construction. In at least one embodiment, one or more servers 1378 may transmit a neural network 1392, an updated neural network 1392, and / or map information 1394, including, but not limited to, information regarding traffic and road conditions, to the vehicle via one or more networks 1390. In at least one embodiment, updates to the map information 1394 may include, but not limited to, updates to the HD map 1322, such as information regarding construction sites, potholes, access roads, flooding, and / or other obstacles. In at least one embodiment, the neural network 1392, the updated neural network 1392, and / or the map information 1394 may be generated by new training and / or experience represented by data received from any number of vehicles in the environment, and / or may be based at least on training performed at a data center (e.g., using one or more servers 1378 and / or other servers).

[0274] In at least one embodiment, one or more servers 1378 can be used to train a machine learning model (e.g., a neural network) based at least in part on the training data. In at least one embodiment, the training data can be generated by the vehicle and / or can be generated in simulation (e.g., using a game engine). In at least one embodiment, any amount of the training data is labeled (e.g., where the associated neural network benefits from supervised learning) and / or undergoes other pre-processing. In at least one embodiment, no amount of the training data is labeled and / or pre-processed (e.g., where the associated neural network does not require supervised learning). In at least one embodiment, once the machine learning model is trained, the machine learning model can be used by the vehicle (e.g., transmitted to the vehicle via one or more networks 1390, and / or the machine learning model can be used by one or more servers 1378 to remotely monitor the vehicle.

[0275] In at least one embodiment, one or more servers 1378 can receive data from the vehicle and apply the data to the latest real-time neural networks for real-time intelligent reasoning. In at least one embodiment, one or more servers 1378 can include a deep learning supercomputer and / or a dedicated AI computer powered by one or more GPUs 1384, such as the DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, one or more servers 1378 can include the deep learning infrastructure of a data center using CPU power.

[0276] In at least one embodiment, the deep learning infrastructure of one or more servers 1378 may be capable of fast, real-time inference and may use this capability to assess and verify the health of the processors, software, and / or related hardware in the vehicle 1300. For example, in at least one embodiment, the deep learning infrastructure may receive periodic updates from the vehicle 1300, such as an image sequence and / or objects that the vehicle 1300 has located within that image sequence (e.g., via computer vision and / or other machine learning object classification techniques). In at least one embodiment, the deep learning infrastructure may run its own neural network to identify objects and compare them to those identified by the vehicle 1300, and if the results do not match and the deep learning infrastructure concludes that the AI ​​in the vehicle 1300 is malfunctioning, the one or more servers 1378 may send a signal to the vehicle 1300 instructing the vehicle's 1300 fail-safe computer to take control, notify passengers, and complete a safe parking maneuver.

[0277] In at least one embodiment, one or more servers 1378 may include one or more GPUs 1384 and one or more programmable inference accelerators (e.g., NVIDIA's TensorRT 3). In at least one embodiment, the combination of GPU-powered servers and inference acceleration can enable real-time responses. In at least one embodiment, for example, in situations where performance is less critical, servers powered by CPUs, FPGAs, and other processors can be used for inference.

[0278] In at least one embodiment, the vehicle 1300 is integrated into Figure 1-11 In at least one embodiment, CPUs 1380(A)-1380(B) include one or more circuits for performing operations such as those described above in conjunction with Figure 1-11 Describes the operation.

[0279] Computer system

[0280] Figure 14 1400 is a block diagram illustrating an exemplary computer system according to at least one embodiment, which may be a system of interconnected devices and components, a system on a chip (SOC), or some combination thereof formed with a processor that may include execution units to execute instructions. In at least one embodiment, according to the present disclosure, such as the embodiments described herein, computer system 1400 may include, but is not limited to, components such as processor 1402, whose execution units include logic to execute algorithms for processing data. In at least one embodiment, computer system 1400 may include a processor such as the Intel® processor 1402 available from Intel Corporation of Santa Clara, California. Processor family, XeonTM, XScaleTM and / or StrongARMTM, Core TM or Intel microprocessor, although other systems (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.) may also be used. In at least one embodiment, computer system 1400 may execute a version of the WINDOWS operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (e.g., UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0281] Embodiments may be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol (IP) devices, digital cameras, personal digital assistants ("PDAs"), and handheld PCs. In at least one embodiment, the embedded application may include a microcontroller, a digital signal processor ("DSP"), a system on a chip, a network computer ("NetPC"), a set-top box, a network hub, a wide area network ("WAN") switch, or any other system that can execute one or more instructions according to at least one embodiment.

[0282] In at least one embodiment, computer system 1400 may include, but is not limited to, a processor 1402, which may include, but is not limited to, one or more execution units 1408 to perform machine learning model training and / or inference according to the techniques described herein. In at least one embodiment, system 1400 is a single-processor desktop or server system, but in another embodiment, system 1400 may be a multi-processor system. In at least one embodiment, processor 1402 may include, but is not limited to, a complex instruction set computer ("CISC") microprocessor, a reduced instruction set computing ("RISC") microprocessor, a very long instruction word ("VLIW") microprocessor, a processor that implements a combination of instruction sets, or any other processor device, such as a digital signal processor. In at least one embodiment, processor 1402 may be coupled to a processor bus 1410, which may transmit data signals between processor 1402 and other components in computer system 1400.

[0283] In at least one embodiment, processor 1402 may include, but is not limited to, a level 1 ("L1") internal cache memory ("cache") 1404. In at least one embodiment, processor 1402 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory may reside external to processor 1402. Other embodiments may include a combination of internal and external caches, depending on the specific implementation and requirements. In at least one embodiment, register file 1406 may store different types of data in various registers, including, but not limited to, integer registers, floating point registers, status registers, and an instruction pointer register.

[0284] In at least one embodiment, an execution unit 1408, including but not limited to logic for performing integer and floating point operations, is also located in the processor 1402. In at least one embodiment, the processor 1402 may also include a microcode ("ucode") read-only memory ("ROM") for storing microcode for certain macroinstructions. In at least one embodiment, the execution unit 1408 may include logic for processing a packed instruction set 1409. In at least one embodiment, by including the packed instruction set 1409 in the instruction set of the general-purpose processor 1402, and the associated circuitry to execute the instructions, operations used by many multimedia applications may be performed using packed data in the general-purpose processor 1402. In one or more embodiments, many multimedia applications may be accelerated and executed more efficiently by using the full width of the processor's data bus to perform operations on the packed data, which may not require transferring smaller units of data across the processor's data bus to perform one or more operations one data element at a time.

[0285] In at least one embodiment, execution unit 1408 may also be used in a microcontroller, an embedded processor, a graphics device, a DSP, and other types of logic circuits. In at least one embodiment, computer system 1400 may include, but is not limited to, memory 1420. In at least one embodiment, memory 1420 may be implemented as a dynamic random access memory ("DRAM") device, a static random access memory ("SRAM") device, a flash memory device, or other storage device. In at least one embodiment, memory 1420 may store instructions 1419 and / or data 1421 represented by data signals that may be executed by processor 1402.

[0286] In at least one embodiment, a system logic chip can be coupled to the processor bus 1410 and the memory 1420. In at least one embodiment, the system logic chip can include, but is not limited to, a memory controller hub ("MCH") 1416, and the processor 1402 can communicate with the MCH 1416 via the processor bus 1410. In at least one embodiment, the MCH 1416 can provide a high-bandwidth memory path 1418 to the memory 1420 for instruction and data storage, as well as for storage of graphics commands, data, and textures. In at least one embodiment, the MCH 1416 can initiate data signals between the processor 1402, the memory 1420, and other components in the computer system 1400, and bridge data signals between the processor bus 1410, the memory 1420, and the system I / O 1422. In at least one embodiment, the system logic chip can provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 1416 may be coupled to the memory 1420 via a high-bandwidth memory path 1418 , and the graphics / video card 1412 may be coupled to the MCH 1416 via an Accelerated Graphics Port (“AGP”) interconnect 1414 .

[0287] In at least one embodiment, computer system 1400 may use system I / O 1422, which is a proprietary hub interface bus, to couple MCH 1416 to I / O controller hub ("ICH") 1430. In at least one embodiment, ICH 1430 may provide direct connection to certain I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus for connecting peripheral devices to memory 1420, chipset, and processor 1402. Examples may include, but are not limited to, an audio controller 1429, a firmware hub ("Flash BIOS") 1428, a wireless transceiver 1426, a data store 1424, a traditional I / O controller 1423 including a user input and keyboard interface, a serial expansion port 1427 (e.g., a universal serial bus (USB)), and a network controller 1434. In at least one embodiment, data store 1424 may include a hard drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0288] In at least one embodiment, Figure 14 The system is shown as comprising interconnected hardware devices or "chips", while in other embodiments, Figure 14 A system on a chip (SoC) may be shown. In at least one embodiment, Figure 14The devices shown in can be interconnected with a proprietary interconnect, a standardized interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of system 1400 are interconnected using a Compute Express Link (CXL) interconnect.

[0289] In at least one embodiment, the computer system 1400 is integrated into Figure 1-11 In at least one embodiment, the processor 1402 includes one or more circuits for performing operations such as those described above in conjunction with Figure 1-11 Describes the operation.

[0290] Figure 15 1 is a block diagram illustrating an electronic device 1500 for utilizing a processor 1510 in accordance with at least one embodiment. In at least one embodiment, the electronic device 1500 may be, for example, but not limited to, a notebook computer, a tower server, a rack server, a blade server, a laptop computer, a desktop computer, a tablet computer, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0291] In at least one embodiment, system 1500 may include, but is not limited to, a processor 1510 communicatively coupled to any suitable number or kind of components, peripherals, modules, or devices. In at least one embodiment, processor 1510 is coupled using a bus or interface, such as an IC bus, a system management bus ("SMBus"), a low pin count (LPC) bus, a serial peripheral interface ("SPI"), a high-definition audio ("HDA") bus, a serial advanced technology attachment ("SATA") bus, a universal serial bus ("USB") (versions 1, 2, 3, etc.), or a universal asynchronous receiver / transmitter ("UART") bus. In at least one embodiment, Figure 15 shows a system comprising interconnected hardware devices or "chips", while in other embodiments, Figure 15 An exemplary system on a chip (SoC) may be shown. In at least one embodiment, Figure 15 The devices shown in can be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, Figure 15 One or more components of the system are interconnected using Compute Express Link (CXL) interconnect lines.

[0292] In at least one embodiment, Figure 15It may include a display 1524, a touch screen 1525, a touchpad 1530, a near field communication unit (“NFC”) 1545, a sensor hub 1540, a thermal sensor 1539, a fast chipset (“EC”) 1535, a trusted platform module (“TPM”) 1538, a BIOS / firmware / flash memory (“BIOS, FW Flash”) 1522, a DSP 1560, a drive “SSD or HDD” 1520 (e.g., a solid state disk (“SSD”) or a hard disk drive (“HDD”)), a wireless local area network unit (“WLAN”) 1550, a Bluetooth unit 1552, a wireless wide area network unit (“WWAN”) 1556, a global positioning system (GPS) 1555, a camera (“USB 3.0 camera”) 1554 (e.g., a USB 3.0 camera), or a low power double data rate (“LPDDR”) memory unit (“LPDDR3”) 1515 implemented with, for example, the LPDDR3 standard. These components may each be implemented in any suitable manner.

[0293] In at least one embodiment, other components may be communicatively coupled to processor 1510 via the components described above. In at least one embodiment, accelerometer 1541, ambient light sensor (“ALS”) 1542, compass 1543, and gyroscope 1544 may be communicatively coupled to sensor hub 1540. In at least one embodiment, thermal sensor 1539, fan 1537, keyboard 1536, and touchpad 1530 may be communicatively coupled to EC 1535. In at least one embodiment, speaker 1563, earphone 1564, and microphone (“mic”) 1565 may be communicatively coupled to audio unit (“audio codec and class-D amplifier”) 1564, which in turn may be communicatively coupled to DSP 1560. In at least one embodiment, audio unit 1564 may include, for example, but not limited to, an audio codec / decoder (“codec”) and a class-D amplifier. In at least one embodiment, SIM card (“SIM”) 1557 may be communicatively coupled to WWAN unit 1556. In at least one embodiment, components such as the WLAN unit 1550 and the Bluetooth unit 1552 and the WWAN unit 1556 may be implemented as a next generation form factor (NGFF).

[0294] In at least one embodiment, the electronic device 1500 is integrated into Figure 1-11 In at least one embodiment, the processor 1510 includes one or more circuits for performing operations such as those described above in conjunction with Figure 1-11 Describes the operation.

[0295] Figure 16Illustrated is a computer system 1600 in accordance with at least one embodiment. In at least one embodiment, the computer system 1600 is configured to implement the various processes and methods described throughout this disclosure.

[0296] In at least one embodiment, computer system 1600 includes, but is not limited to, at least one central processing unit ("CPU") 1602 connected to a communication bus 1610 implemented using any suitable protocol, such as PCI ("Peripheral Component Interconnect"), Peripheral Component Interconnect Express ("PCI-Express"), AGP ("Accelerated Graphics Port"), HyperTransport, or any other bus or point-to-point communication protocol. In at least one embodiment, computer system 1600 includes, but is not limited to, main memory 1604 and control logic (e.g., implemented as hardware, software, or a combination thereof), and data may be stored in main memory 1604 in the form of random access memory ("RAM"). In at least one embodiment, a network interface subsystem ("network interface") 1622 provides an interface to other computing devices and networks for receiving data from computer system 1600 and transmitting data to other systems.

[0297] In at least one embodiment, computer system 1600 includes, but is not limited to, input device 1608, parallel processing system 1612, and display device 1606, which can be implemented using conventional cathode ray tubes ("CRTs"), liquid crystal displays ("LCDs"), light emitting diodes ("LEDs"), plasma displays, or other suitable display technologies. In at least one embodiment, user input is received from input device 1608 (such as a keyboard, mouse, touchpad, microphone, etc.). In at least one embodiment, each of the aforementioned modules can be located on a single semiconductor platform to form a processing system.

[0298] In at least one embodiment, computer system 1600 is integrated into Figure 1-11 In at least one embodiment, the CPU 1602 includes one or more circuits for performing operations such as those described above in conjunction with Figure 1-11 Describes the operation.

[0299] Figure 17A computer system 1700 is shown in accordance with at least one embodiment. In at least one embodiment, computer system 1700 includes, but is not limited to, a computer 1710 and a USB stick 1720. In at least one embodiment, computer 1710 may include, but is not limited to, any number and type of processors (not shown) and memory (not shown). In at least one embodiment, computer 1710 includes, but is not limited to, a server, a cloud instance, a laptop computer, and a desktop computer.

[0300] In at least one embodiment, the USB stick 1720 includes, but is not limited to, a processing unit 1730, a USB interface 1740, and USB interface logic 1750. In at least one embodiment, the processing unit 1730 can be any instruction execution system, apparatus, or device capable of executing instructions. In at least one embodiment, the processing unit 1730 can include, but is not limited to, any number and type of processing cores (not shown). In at least one embodiment, the processing core 1730 includes an application specific integrated circuit ("ASIC") that is optimized to perform any number and type of operations associated with machine learning. For example, in at least one embodiment, the processing core 1730 is a tensor processing unit ("TPC") that is optimized to perform machine learning inference operations. In at least one embodiment, the processing core 1730 is a vision processing unit ("VPU") that is optimized to perform machine vision and machine learning inference operations.

[0301] In at least one embodiment, USB interface 1740 can be any type of USB connector or USB receptacle. For example, in at least one embodiment, USB interface 1740 is a USB 3.0 Type-C receptacle for data and power. In at least one embodiment, USB interface 1740 is a USB 3.0 Type-A connector. In at least one embodiment, USB interface logic 1750 can include any number and type of logic that enables processing unit 1730 to connect to a device (e.g., computer 1710) via USB connector 1740.

[0302] In at least one embodiment, computer system 1700 is integrated into Figure 1-11 In at least one embodiment, the computer 1710 includes one or more circuits to perform the following operations: Figure 1-11 Describes the operation.

[0303] Figure 18AAn exemplary architecture is shown in which multiple GPUs 1810-1813 are communicatively coupled to multiple multi-core processors 1805-1806 via high-speed links 1840-1843 (e.g., buses / point-to-point interconnects, etc.). In one embodiment, the high-speed links 1840-1843 support 4 GB / s, 30 GB / s, 80 GB / s, or higher communication throughput. Various interconnect protocols can be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0.

[0304] Furthermore, in one embodiment, two or more GPUs 1810-1813 are interconnected via high-speed links 1829-1830, which may be implemented using the same or different protocols / links as used for high-speed links 1840-1843. Similarly, two or more multi-core processors 1805-1806 may be connected via high-speed link 1828, which may be a symmetric multiprocessor (SMP) bus running at 20 GB / s, 30 GB / s, 120 GB / s, or higher. Alternatively, the same protocol / links may be used (e.g., via a common interconnect fabric) to accomplish this. Figure 18A All communications between the various system components shown in .

[0305] In one embodiment, each multi-core processor 1805-1806 is communicatively coupled to processor memory 1801-1802 via memory interconnects 1826-1827, respectively, and each GPU 1810-1813 is communicatively coupled to GPU memory 1820-1823 via GPU memory interconnects 1850-1853, respectively. Memory interconnects 1826-1827 and 1850-1853 can utilize the same or different memory access technologies. By way of example and not limitation, processor memory 1801-1802 and GPU memory 1820-1823 can be volatile memory, such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or can be non-volatile memory, such as 3D XPoint or Nano-Ram. In one embodiment, some portion of the processor memory 1801-1802 may be volatile memory, while another portion may be non-volatile memory (eg, using a two-level memory (2LM) hierarchy).

[0306] As described herein, although the various processors 1805-1806 and GPUs 1810-1813 may each be physically coupled to a specific memory 1801-1802, 1820-1823, a unified memory architecture may be implemented in which the same virtual system address space (also referred to as an "effective address" space) is distributed across the various physical memories. For example, the processor memories 1801-1802 may each contain 64GB of system memory address space, and the GPU memories 1820-1823 may each contain 32GB of system memory address space (resulting in a total addressable memory size of 256GB in this example).

[0307] Figure 18B 1807 and a graphics acceleration module 1846. The graphics acceleration module 1846 may include one or more GPU chips integrated on a line card that is coupled to the processor 1807 via a high-speed link 1840. Alternatively, the graphics acceleration module 1846 may be integrated on the same package or chip as the processor 1807.

[0308] In at least one embodiment, the illustrated processor 1807 includes a plurality of cores 1860A-1860D, each having a translation lookaside buffer 1861A-1861D and one or more caches 1862A-1862D. In at least one embodiment, the cores 1860A-1860D may include various other components, not shown, for executing instructions and processing data. In at least one embodiment, the caches 1862A-1862D may include level 1 (L1) and level 2 (L2) caches. In addition, one or more shared caches 1856 may be included in the caches 1862A-1862D and shared by each group of cores 1860A-1860D. For example, one embodiment of the processor 1807 includes 24 cores, each having its own L1 cache, twelve shared L2 caches, and twelve shared L3 caches. In this embodiment, two adjacent cores share one or more L2 and L3 caches. The processor 1807 and the graphics acceleration module 1846 are connected to the system memory 1814, which may include Figure 18A Processor memory 1801-1802 in.

[0309] Coherence is maintained for data and instructions stored in the various caches 1862A-1862D, 1856, and system memory 1814 via inter-core communication over a coherence bus 1864. For example, each cache may have cache coherence logic / circuitry associated therewith to communicate over the coherence bus 1864 in response to detecting a read or write to a particular cache line. In one implementation, a cache snooping protocol is implemented over the coherence bus 1864 to snoop cache accesses.

[0310] In one embodiment, proxy circuitry 1825 communicatively couples graphics acceleration module 1846 to coherence bus 1864, thereby allowing graphics acceleration module 1846 to participate in a cache coherence protocol as a peer of cores 1860A-1860D. In particular, in at least one embodiment, interface 1835 provides connectivity to proxy circuitry 1825 via high-speed link 1840 (e.g., a PCIe bus, NVLink, etc.), and interface 1837 connects graphics acceleration module 1846 to link 1840.

[0311] In one implementation, the accelerator integrated circuit 1836 provides cache management, memory access, context management, and interrupt management services on behalf of the multiple graphics processing engines 1831, 1832, N of the graphics acceleration module. The graphics processing engines 1831, 1832, N may each comprise a separate graphics processing unit (GPU). Alternatively, the graphics processing engines 1831, 1832, N may selectively comprise different types of graphics processing engines within the GPU, such as a graphics execution unit, a media processing engine (e.g., a video encoder / decoder), a sampler, and a blit engine. In at least one embodiment, the graphics acceleration module 1846 may be a GPU having multiple graphics processing engines 1831-1832, N, or the graphics processing engines 1831-1832, N may be individual GPUs integrated into a common package, line card, or chip.

[0312] In one embodiment, the accelerator integrated circuit 1836 includes a memory management unit (MMU) 1839 for performing various memory management functions, such as virtual-to-physical memory translation (also known as effective-to-real memory translation), and a memory access protocol for accessing system memory 1814. The MMU 1839 may also include a translation lookaside buffer ("TLB") (not shown) for caching virtual / effective-to-physical / real address translations. In one implementation, cache 1838 may store commands and data for efficient access by the graphics processing engines 1831-1832, N. In at least one embodiment, data stored in cache 1838 and graphics memory 1833-1834, M is kept consistent with the core caches 1862A-1862D, 1856, and system memory 1814. As previously described, this task may be accomplished via proxy circuitry 1825 acting on behalf of cache 1838 and graphics memory 1833-1834, M (e.g., sending updates related to modifications / accesses of cache lines on processor caches 1862A-1862D, 1856 to cache 1838 and receiving updates from cache 1838).

[0313] A set of registers 1845 stores context data for threads executed by graphics processing engines 1831-1832, N, and context management circuitry 1848 manages thread contexts. For example, context management circuitry 1848 can perform save and restore operations to save and restore the context of various threads during context switches (e.g., where a first thread is saved and a second thread is stored so that the second thread can be executed by the graphics processing engine). For example, context management circuitry 1848 can store current register values ​​to a designated area in memory (e.g., identified by a context pointer) upon context switching. The register values ​​can then be restored upon returning to context. In one embodiment, interrupt management circuitry 1847 receives and processes interrupts received from system devices.

[0314] In one implementation, the MMU 1839 converts virtual / effective addresses from the graphics processing engine 1831 into real / physical addresses in the system memory 1814. One embodiment of the accelerator integrated circuit 1836 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 1846 and / or other accelerator devices. The graphics accelerator module 1846 can be dedicated to a single application executing on the processor 1807, or can be shared among multiple applications. In one embodiment, a virtualized graphics execution environment is presented in which the resources of the graphics processing engines 1831-1832, N are shared with multiple applications or virtual machines (VMs). In at least one embodiment, the resources can be subdivided into "slices" that are allocated to different VMs and / or applications based on processing requirements and priorities associated with the VMs and / or applications.

[0315] In at least one embodiment, the accelerator integrated circuit 1836 acts as a bridge to the system for the graphics acceleration module 1846 and provides address translation and system memory caching services. In addition, the accelerator integrated circuit 1836 can provide virtualization facilities for the host processor to manage virtualization, interrupts, and memory management for the graphics processing engines 1831-1832.

[0316] Because the hardware resources of graphics processing engines 1831-1832, N are explicitly mapped into the real address space seen by host processor 1807, any host processor can directly address these resources using effective address values. In at least one embodiment, one function of accelerator integrated circuit 1836 is to physically separate graphics processing engines 1831-1832, N so that they appear as independent units to the system.

[0317] In at least one embodiment, one or more graphics memories 1833-1834, M are respectively coupled to each graphics processing engine 1831-1832, N. Graphics memories 1833-1834, M store instructions and data, which are processed by each graphics processing engine 1831-1832, N. Graphics memories 1833-1834, M can be volatile memory, such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or can be non-volatile memory, such as 3D XPoint or Nano-Ram.

[0318] In one embodiment, to reduce data traffic on link 1840, biasing techniques can be used to ensure that the data stored in graphics memory 1833-1834, M is the data most frequently used by graphics processing engines 1831-1832, N, and preferably not used (at least not frequently) by cores 1860A-1860D. Similarly, in at least one embodiment, the biasing mechanism attempts to keep data needed by the core (and preferably not graphics processing engines 1831-1832, N) in the core's cache 1862A-1862D, 1856 and system memory 1814.

[0319] Figure 18C Another exemplary embodiment is shown in which an accelerator integrated circuit 1836 is integrated into the processor 1807. In this embodiment, the graphics processing engines 1831-1832, N communicate directly with the accelerator integrated circuit 1836 via interfaces 1837 and 1835 (which may also utilize any form of bus or interface protocol) over a high-speed link 1840. The accelerator integrated circuit 1836 can perform operations related to Figure 18B The operations described above are identical to those described above. However, due to its close proximity to the coherence bus 1864 and caches 1862A-1862D, 1856, higher throughput is possible. One embodiment supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization), which can include a programming model controlled by the accelerator integrated circuit 1836 and a programming model controlled by the graphics acceleration module 1846.

[0320] In at least one embodiment, the graphics processing engines 1831-1832, N are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application can funnel other application requests to the graphics processing engines 1831-1832, N, thereby providing virtualization within a VM / partition.

[0321] In at least one embodiment, graphics processing engines 1831-1832,N can be shared by multiple VM / application partitions. In at least one embodiment, the sharing model can use a hypervisor to virtualize graphics processing engines 1831-1832,N to allow each operating system to access them. For a single-partition system without a hypervisor, the operating system owns graphics processing engines 1831-1832,N. In at least one embodiment, the operating system can virtualize graphics processing engines 1831-1832,N to provide access to each process or application.

[0322] In at least one embodiment, the graphics acceleration module 1846 or individual graphics processing engines 1831-1832,N use a process handle to select a process element. In one embodiment, the process element is stored in the system memory 1814 and can be addressed using the effective address to real address translation techniques described herein. In at least one embodiment, the process handle can be an implementation-specific value that is provided to the host process when registering its context with the graphics processing engine 1831-1832,N (i.e., calling system software to add the process element to the process element linked list). In at least one embodiment, the lower 16 bits of the process handle can be the offset of the process element in the process element linked list.

[0323] Figure 18D An exemplary accelerator integrated slice 1890 is shown. As used herein, a "slice" comprises a designated portion of the processing resources of an accelerator integrated circuit 1836. An application is an effective address space 1882 in system memory 1814 that stores process elements 1883. In one embodiment, process elements 1883 are stored in response to a GPU call 1881 from an application 1880 executing on processor 1807. Process elements 1883 contain the process state of the corresponding application 1880. A work descriptor (WD) 1884 contained in process element 1883 may be a single job requested by the application, or may contain a pointer to a job queue. In at least one embodiment, WD 1884 is a pointer to a job request queue in the application's address space 1882.

[0324] The graphics acceleration module 1846 and / or the individual graphics processing engines 1831-1832, N can be shared by all processes or a subset of processes in the system. In at least one embodiment, an infrastructure for setting process state and sending WD 1884 to the graphics acceleration module 1846 to start a job in a virtualized environment can be included.

[0325] In at least one embodiment, a dedicated process programming model is implementation-specific. In this model, a single process owns either a graphics acceleration module 1846 or an individual graphics processing engine 1831. Since the hypervisor initializes the accelerator integrated circuit for the owning partition when the graphics acceleration module 1846 is owned by a single process, the operating system initializes the accelerator integrated circuit 1836 for the owning process when the graphics acceleration module 1846 is assigned.

[0326] In operation, the WD fetch unit 1891 in the accelerator integrated slice 1890 fetches the next WD 1884, which includes an indication of work to be completed by one or more graphics processing engines of the graphics acceleration module 1846. Data from WD 1884 can be stored in registers 1845 and used by the MMU 1839, interrupt management circuitry 1847, and / or context management circuitry 1848, as shown. For example, one embodiment of the MMU 1839 includes segment / page roaming circuitry for accessing segment / page tables 1886 within the OS virtual address space 1885. The interrupt management circuitry 1847 can process interrupt events 1892 received from the graphics acceleration module 1846. When executing graphics operations, effective addresses 1893 generated by the graphics processing engines 1831-1832, N are converted into real addresses by the MMU 1839.

[0327] In one embodiment, the same set of registers 1845 is replicated for each graphics processing engine 1831-1832, N, and / or graphics acceleration module 1846, and the registers 1845 can be initialized by the hypervisor or operating system. Each of these replicated registers can be included in the accelerator integration slice 1890. Example registers that can be initialized by the hypervisor are shown in Table 1.

[0328]

[0329] Example registers that may be initialized by the operating system are shown in Table 2.

[0330]

[0331]

[0332] In one embodiment, each WD 1884 is specific to a particular graphics acceleration module 1846 and / or graphics processing engine 1831-1832, N. It contains all the information needed by the graphics processing engine 1831-1832, N to complete the work, or it can be a pointer to a memory location where the application has set up a command queue for the work to be done.

[0333] Figure 18E 1896 , which virtualizes the graphics acceleration module engine for the operating system 1895.

[0334] In at least one embodiment, the shared programming model allows all processes or a subset of processes from all partitions or a subset of partitions in the system to use the graphics acceleration module 1846. There are two programming models in which the graphics acceleration module 1846 is shared by multiple processes and partitions: time-sliced ​​sharing and graphics-directed sharing.

[0335] In this model, the hypervisor 1896 owns the graphics acceleration module 1846 and makes its functionality available to all operating systems 1895. For the graphics acceleration module 1846 to support virtualization through the hypervisor 1896, the graphics acceleration module 1846 may adhere to the following: (1) the application's job requests must be autonomous (i.e., no state needs to be maintained between jobs), or the graphics acceleration module 1846 must provide a context save and restore mechanism, (2) the graphics acceleration module 1846 guarantees that the application's job requests are completed within a specified amount of time, including any transition errors, or the graphics acceleration module 1846 provides the ability to preempt job processing, and (3) fairness between graphics acceleration module 1846 processes must be ensured when operating in a directed shared programming model.

[0336] In at least one embodiment, an application 1880 is required to make an operating system 1895 system call using a graphics acceleration module 1846 type, a work descriptor (WD), an authority mask register (AMR) value, and a context save / restore region pointer (CSRP). In at least one embodiment, the graphics acceleration module 1846 type describes the target acceleration function for the system call. In at least one embodiment, the graphics acceleration module 1846 type can be a system-specific value. In at least one embodiment, the WD is formatted specifically for the graphics acceleration module 1846 and can take the form of a graphics acceleration module 1846 command, an effective address pointer to a user-defined structure, an effective address pointer to a command queue, or any other data structure describing work to be performed by the graphics acceleration module 1846. In one embodiment, the AMR value is the AMR state for the current process. In at least one embodiment, the value passed to the operating system is similar to that of an application setting the AMR. If the implementation of the accelerator integrated circuit 1836 and graphics acceleration module 1846 does not support the User Authority Mask Override Register (UAMOR), the operating system can apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. Hypervisor 1896 can optionally apply the current privilege mask overwrite register (AMOR) value before placing the AMR into process element 1883. In at least one embodiment, CSRP is one of registers 1845 that contains the effective address of an area in the application's address space 1882 for graphics acceleration module 1846 to save and restore context state. This pointer is optional if state does not need to be saved between jobs or when a job is preempted. In at least one embodiment, the context save / restore area can be fixed system memory.

[0337] Upon receiving the system call, the operating system 1895 may verify that the application 1880 has been registered and granted permission to use the graphics acceleration module 1846. The operating system 1895 then uses

[0338] The information shown in Table 3 is used to call the management program 1896.

[0339]

[0340] Upon receiving the hypervisor call, the hypervisor 1896 verifies that the operating system 1895 has registered and been granted permission to use the graphics acceleration module 1846. The hypervisor 1896 then places the process element 1883 into a linked list of process elements of the corresponding graphics acceleration module 1846 type. The process element may include the information shown in Table 4.

[0341]

[0342]

[0343] In at least one embodiment, the hypervisor initializes the plurality of accelerator integrated slice 1890 registers 1845 .

[0344] like Figure 18F As shown, in at least one embodiment, a unified memory is used that is addressable via a common virtual memory address space for accessing physical processor memories 1801-1802 and GPU memories 1820-1823. In this implementation, operations executed on GPUs 1810-1813 utilize the same virtual / effective memory address space to access processor memories 1801-1802, and vice versa, thereby simplifying programmability. In at least one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 1801, a second portion is allocated to second processor memory 1802, a third portion is allocated to GPU memory 1820, and so on. In at least one embodiment, the entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each of processor memories 1801-1802 and GPU memories 1820-1823, thereby allowing any processor or GPU to access that memory using a virtual address mapped to any physical memory.

[0345] In one embodiment, bias / coherency management circuitry 1894A-1894E within one or more MMUs 1839A-1839E ensures cache coherency between the caches of one or more host processors (e.g., 1805) and GPUs 1810-1813 and implements biasing techniques that indicate the physical memory where certain types of data should be stored. Figure 18F Multiple instances of bias / coherence management circuits 1894A- 1894E are shown in , but bias / coherence circuits may be implemented within an MMU of one or more host processors 1805 and / or within an accelerator integrated circuit 1836 .

[0346] One embodiment allows GPU attached memory 1820-1823 to be mapped as part of system memory and accessed using shared virtual memory (SVM) technology, but without suffering the performance drawbacks associated with full system cache coherence. In at least one embodiment, the ability to access GPU attached memory 1820-1823 as system memory without the heavy cache coherence overhead provides a favorable operating environment for GPU offloading. This arrangement allows software of the host processor 1805 to set operands and access calculation results without the overhead of traditional I / O DMA data copies. Such traditional copies include driver calls, interrupts, and memory mapped I / O (MMIO) accesses, which are all less efficient than simple memory accesses. In at least one embodiment, the ability to access GPU attached memory 1820-1823 without cache coherence overhead can be critical to the execution time of the offloaded calculation. For example, in situations with large amounts of streaming write memory traffic, cache coherence overhead can significantly reduce the effective write bandwidth seen by the GPUs 1810-1813. In at least one embodiment, efficiency of operand setup, efficiency of result access, and efficiency of GPU computation may play a role in determining the effectiveness of GPU offloading.

[0347] In at least one embodiment, the selection of GPU bias and host processor bias is driven by a bias tracker data structure. For example, a bias table can be used, which can be a page-granular structure (e.g., controlled at the granularity of a memory page) that includes 1 or 2 bits per GPU-attached memory page. In at least one embodiment, the bias table can be implemented in the stolen memory range of one or more GPU-attached memories 1820-1823, with or without a bias cache in GPUs 1810-1813 (e.g., to cache frequently / recently used entries in the bias table). Alternatively, the entire bias table can be maintained within the GPU.

[0348] In at least one embodiment, before actually accessing the GPU memory, the bias table entry associated with each access to the GPU attached memory 1820-1823 is accessed, resulting in the following operations. First, local requests from GPUs 1810-1813 whose pages are found in the GPU bias are forwarded directly to the corresponding GPU memory 1820-1823. Local requests from the GPU whose pages are found in the host bias are forwarded to processor 1805 (e.g., via a high-speed link as described above). In one embodiment, a request from processor 1805 to find the requested page in the host processor bias completes a request similar to a normal memory read. Alternatively, a request to a GPU biased page can be forwarded to GPUs 1810-1813. In at least one embodiment, if the GPU is not currently using the page, the GPU can subsequently migrate the page to the host processor bias. In at least one embodiment, the bias state of a page can be changed via a software-based mechanism, a hardware-assisted software-based mechanism, or, in limited cases, a purely hardware-based mechanism.

[0349] One mechanism for changing the bias state employs an API call (e.g., OpenCL), which in turn calls the GPU's device driver, which in turn sends a message (or queues a command descriptor) to the GPU, directing the GPU to change the bias state and, in some migrations, to perform a cache flush operation in the host. In at least one embodiment, the cache flush operation is used for migrations from host processor 1805 bias to GPU bias, but not for the reverse migration.

[0350] In one embodiment, cache coherence is maintained by temporarily rendering GPU-biased pages that cannot be cached by host processor 1805. To access these pages, processor 1805 may request access from GPU 1810, which may or may not immediately grant access. Therefore, to reduce communication between processor 1805 and GPU 1810, it is beneficial to ensure that GPU-biased pages are the pages required by the GPU and not the host processor 1805, and vice versa.

[0351] Figure 19 An exemplary integrated circuit and associated graphics processor according to various embodiments described herein are shown, which can be manufactured using one or more IP cores. In addition to the illustrations, other logic and circuits may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0352] Figure 19is a block diagram illustrating an exemplary system on a chip integrated circuit 1900 that can be fabricated using one or more IP cores according to at least one embodiment. In at least one embodiment, integrated circuit 1900 includes one or more application processors 1905 (e.g., CPUs), at least one graphics processor 1910, and may additionally include an image processor 1915 and / or a video processor 1920, any of which may be modular IP cores. In at least one embodiment, integrated circuit 1900 includes peripheral or bus logic, including a USB controller 1925, a UART controller 1930, an SPI / SDIO controller 1935, and an I.sup.2S / I.sup.2C controller 1940. In at least one embodiment, integrated circuit 1900 may include a display device 1945 coupled to one or more of a High-Definition Multimedia Interface (HDMI) controller 1950 and a Mobile Industry Processor Interface (MIPI) display interface 1955. In at least one embodiment, storage may be provided by a flash memory subsystem 1960, including flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 1965 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits also include an embedded security engine 1970 .

[0353] In at least one embodiment, integrated circuit 1900 is integrated into Figure 1-11 In at least one embodiment, the application processor 1905 includes one or more circuits for performing operations such as those described above in conjunction with Figure 1-11 Describes the operation.

[0354] Figures 20A-20B An exemplary integrated circuit and associated graphics processor according to various embodiments described herein are shown, which can be manufactured using one or more IP cores. In addition to the illustrations, other logic and circuits may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0355] Figures 20A-20B is a block diagram illustrating an exemplary graphics processor for use within a SoC according to embodiments described herein. Figure 20A An exemplary graphics processor 2010 of a system-on-chip integrated circuit that can be fabricated using one or more IP cores in accordance with at least one embodiment is shown. Figure 20B Another exemplary graphics processor 2040 of a system-on-chip integrated circuit is shown, which may be manufactured using one or more IP cores, in accordance with at least one embodiment. Figure 20AThe graphics processor 2010 is a low power graphics processor core. In at least one embodiment, Figure 20B The graphics processor 2040 is a higher performance graphics processor core. In at least one embodiment, each graphics processor 2010, 2040 can be Figure 19 A variant of the graphics processor 1910.

[0356] In at least one embodiment, the graphics processor 2010 includes a vertex processor 2005 and one or more fragment processors 2015A-2015N (e.g., 2015A, 2015B, 2015C, 2015D through 2015N-1 and 2015N). In at least one embodiment, the graphics processor 2010 can execute different shader programs via separate logic, such that the vertex processor 2005 is optimized to perform operations for the vertex shader program, while the one or more fragment processors 2015A-2015N perform fragment (e.g., pixel) shading operations for the fragment or pixel or shader program. In at least one embodiment, the vertex processor 2005 performs the vertex processing stage of the 3D graphics pipeline and generates primitives and vertex data. In at least one embodiment, the one or more fragment processors 2015A-2015N use the primitives and vertex data generated by the vertex processor 2005 to generate a frame buffer for display on a display device. In at least one embodiment, one or more fragment processors 2015A-2015N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform similar operations as pixel shader programs provided in the Direct 3D API.

[0357] In at least one embodiment, the graphics processor 2010 additionally includes one or more memory management units (MMUs) 2020A-2020B, one or more caches 2025A-2025B, and one or more circuit interconnects 2030A-2030B. In at least one embodiment, the one or more MMUs 2020A-2020B provide a mapping of virtual to physical addresses for the graphics processor 2010, including for the vertex processor 2005 and / or the fragment processors 2015A-2015N, which may reference vertex or image / texture data stored in memory, in addition to vertex or image / texture data stored in the one or more caches 2025A-2025B. In at least one embodiment, the one or more MMUs 2020A-2020B may synchronize with other MMUs within the system, including with other MMUs. Figure 19One or more MMUs associated with one or more application processors 1905, graphics processor 1915, and / or video processor 1920 enable each processor 1905-1920 to participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 2030A-2030B enable graphics processor 2010 to connect to other IP cores within the SoC via an internal bus of the SoC or via a direct connection.

[0358] In at least one embodiment, graphics processor 2040 includes Figure 20A One or more MMUs 2020A-2020B, caches 2025A-2025B, and circuit interconnects 2030A-2030B of the graphics processor 2010. In at least one embodiment, the graphics processor 2040 includes one or more shader cores 2055A-2055N (e.g., 2055A, 2055B, 2055C, 2055D, 2055E, 2055F through 2055N-1 and 2055N) that provide a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, the graphics processor 2040 includes an inter-core task manager 2045 that acts as a thread dispatcher to dispatch execution threads to one or more shader cores 2055A-2055N and a tiling unit 2058 to accelerate tile-based rendering operations in which rendering operations of a scene are subdivided in image space, for example, to exploit local spatial coherence within a scene or to optimize the use of internal caches.

[0359] In at least one embodiment, graphics processors 2010 and 2040 are integrated into Figure 1-11 In at least one embodiment, graphics processors 2010 and 2040 include one or more circuits for performing operations such as those described above in conjunction with Figure 1-11 Describes the operation.

[0360] Figures 21A-21B Additional exemplary graphics processor logic according to embodiments described herein is shown. In at least one embodiment, Figure 21A Shows that can be included in Figure 19 Graphics core 2100 within graphics processor 1910, and in at least one embodiment, may be such as Figure 20B Unified shader cores 2055A-2055N are shown. Figure 21BA highly parallel, general-purpose graphics processing unit 2130 suitable for deployment on a multi-chip module in at least one embodiment is shown.

[0361] In at least one embodiment, graphics core 2100 includes a shared instruction cache 2102, texture units 2118, and cache / shared memory 2120, which are common to execution resources within graphics core 2100. In at least one embodiment, graphics core 2100 may include multiple slices 2101A-2101N, or partitions of each core, and the graphics processor may include multiple instances of graphics core 2100. Slices 2101A-2101N may include support logic including local instruction caches 2104A-2104N, thread schedulers 2106A-2106N, thread dispatchers 2108A-2108N, and a set of registers 2110A-2110N. In at least one embodiment, slices 2101A-2101N may include a set of additional function units (AFUs 2112A-2112N), floating point units (FPUs 2114A-2114N), integer arithmetic logic units (ALUs 2116A-2116N), address calculation units (ACUs 2113A-2113N), double-precision floating point units (DPFPUs 2115A-2115N), and matrix processing units (MPUs 2117A-2117N).

[0362] In at least one embodiment, the FPUs 2114A-2114N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the DPFPUs 2115A-2115N perform double-precision (64-bit) floating-point operations. In at least one embodiment, the ALUs 2116A-2116N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed-precision operations. In at least one embodiment, the MPUs 2117A-2117N can also be configured for mixed-precision matrix operations, including half-precision floating-point operations and 8-bit integer operations. In at least one embodiment, the MPUs 2117-2117N can perform various matrix operations to accelerate machine learning application frameworks, including enabling support for accelerated general matrix-to-matrix multiplication (GEMM). In at least one embodiment, the AFUs 2112A-2112N can perform additional logical operations not supported by the floating-point or integer units, including trigonometric operations (e.g., sine, cosine, etc.).

[0363] In at least one embodiment, the graphics processor 2100 is integrated into Figure 1-11 In at least one embodiment, the graphics processor 2100 includes one or more circuits for performing operations such as those described above in conjunction with Figure 1-11 Describes the operation.

[0364] Figure 21B A general purpose processing unit (GPGPU) 2130 is shown in at least one embodiment, which can be configured to enable highly parallel computing operations to be performed by a group of graphics processing units. In at least one embodiment, GPGPU 2130 can be directly linked to other instances of GPGPU 2130 to create a multi-GPU cluster to increase the training speed for deep neural networks. In at least one embodiment, GPGPU 2130 includes a host interface 2132 to enable connection to a host processor. In at least one embodiment, host interface 2132 is a PCI Express interface. In at least one embodiment, host interface 2132 can be a vendor-specific communication interface or communication structure. In at least one embodiment, GPGPU 2130 receives commands from the host processor and uses a global scheduler 2134 to assign execution threads associated with those commands to a group of compute clusters 2136A-2136H. In at least one embodiment, compute clusters 2136A-2136H share a cache memory 2138. In at least one embodiment, cache memory 2138 may serve as a higher level of cache for cache memory within compute clusters 2136A-2136H.

[0365] In at least one embodiment, the GPGPU 2130 includes memory 2144A-2144B coupled to the compute cluster 2136A-2136H via a set of memory controllers 2142A-2142B. In at least one embodiment, the memory 2144A-2144B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), which includes graphics double data rate (GDDR) memory.

[0366] In at least one embodiment, the computing clusters 2136A-2136H each include a set of graphics cores, e.g. Figure 21A The graphics core 2100 may include multiple types of integer and floating-point logic units that can perform computational operations at various precision ranges, including precision suitable for machine learning computations. For example, in at least one embodiment, at least a subset of the floating-point units in each compute cluster 2136A-2136H may be configured to perform 16-bit or 32-bit floating-point operations, while a different subset of the floating-point units may be configured to perform 64-bit floating-point operations.

[0367] In at least one embodiment, multiple instances of GPGPU 2130 can be configured to function as a compute cluster. In at least one embodiment, the communication used by compute clusters 2136A-2136H for synchronization and data exchange varies between embodiments. In at least one embodiment, multiple instances of GPGPU 2130 communicate via a host interface 2132. In at least one embodiment, GPGPU 2130 includes an I / O hub 2139 that couples GPGPU 2130 to a GPU link 2140, enabling direct connections to other instances of GPGPU 2130. In at least one embodiment, GPU link 2140 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 2130. In at least one embodiment, GPU link 2140 is coupled to a high-speed interconnect to send and receive data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 2130 reside in separate data processing systems and communicate via a network device accessible through host interface 2132. In at least one embodiment, GPU link 2140 may be configured to enable connection to a host processor in addition to or as an alternative to host interface 2132 .

[0368] In at least one embodiment, the GPGPU 2130 can be configured to train a neural network. In at least one embodiment, the GPGPU 2130 can be used within an inference platform. In at least one embodiment, where the GPGPU 2130 is used for inference, the GPGPU can include fewer compute clusters 2136A-2136H than when the GPGPU is used to train a neural network. In at least one embodiment, the memory technology associated with the memories 2144A-2144B can differ between the inference and training configurations, with higher-bandwidth memory technology being dedicated to the training configuration. In at least one embodiment, the inference configuration of the GPGPU 2130 can support inference-specific instructions. For example, in at least one embodiment, the inference configuration can provide support for one or more 8-bit integer dot product instructions, which can be used during inference operations of a deployed neural network.

[0369] In at least one embodiment, GPGPU 2130 is integrated into Figure 1-11 In at least one embodiment, the GPGPU 2130 includes one or more circuits to perform operations such as those described above in conjunction with Figure 1-11 Describes the operation.

[0370] Figure 22A block diagram of a computer system 2200 is shown, according to at least one embodiment. In at least one embodiment, computer system 2200 includes a processing subsystem 2201 having one or more processors 2202 and a system memory 2204, which communicates via an interconnect path that may include a memory hub 2205. In at least one embodiment, memory hub 2205 may be a separate component within a chipset assembly or may be integrated within one or more processors 2202. In at least one embodiment, memory hub 2205 is coupled to an I / O subsystem 2211 via a communication link 2206. In one embodiment, I / O subsystem 2211 includes an I / O hub 2207, which may enable computer system 2200 to receive input from one or more input devices 2208. In at least one embodiment, I / O hub 2207 may enable a display controller, which may be included in one or more processors 2202, to provide output to one or more display devices 2210A. In at least one embodiment, the one or more display devices 2210A coupled to the I / O hub 2207 may include local, internal, or embedded display devices.

[0371] In at least one embodiment, the processing subsystem 2201 includes one or more parallel processors 2212 coupled to the memory hub 2205 via a bus or other communication link 2213. In at least one embodiment, the communication link 2213 can be any of a number of standard-based communication link technologies or protocols, such as, but not limited to, PCI Express, or can be a vendor-specific communication interface or communication structure. In at least one embodiment, the one or more parallel processors 2212 form a parallel or vector processing system in a computational cluster, which can include a large number of processing cores and / or processing clusters, such as a multi-integrated core (MIC) processor. In at least one embodiment, the one or more parallel processors 2212 form a graphics processing subsystem that can output pixels to one of one or more display devices 2210A coupled via the I / O hub 2207. In at least one embodiment, the one or more parallel processors 2212 can also include a display controller and display interface (not shown) to enable direct connection to the one or more display devices 2210B.

[0372] In at least one embodiment, a system storage unit 2214 can be connected to the I / O hub 2207 to provide a storage mechanism for the computer system 2200. In at least one embodiment, an I / O switch 2216 can be used to provide an interface mechanism to enable connections between the I / O hub 2207 and other components, such as a network adapter 2218 and / or a wireless network adapter 2217 that can be integrated into the platform, as well as various other devices that can be added via one or more add-on devices 2220. In at least one embodiment, the network adapter 2218 can be an Ethernet adapter or another wired network adapter. In at least one embodiment, the wireless network adapter 2219 can include one or more of Wi-Fi, Bluetooth, near field communication (NFC), or other network devices including one or more radio devices.

[0373] In at least one embodiment, the computer system 2200 may include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to the I / O hub 2207. In at least one embodiment, the interconnection may be implemented using any suitable protocol, such as a PCI (Peripheral Component Interconnect) based protocol (e.g., PCI-Express) or other bus or point-to-point communication interface and / or protocol. Figure 22 Communication paths for various components in a chip, such as NV-Link high-speed interconnect or interconnect protocol.

[0374] In at least one embodiment, one or more parallel processors 2212 include circuits optimized for graphics and video processing, including, for example, video output circuits, and constitute a graphics processing unit (GPU). In at least one embodiment, one or more parallel processors 2212 include circuits optimized for general-purpose processing. In at least one embodiment, the components of the computer system 2200 can be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processors 2212, memory hub 2205, processor 2202, and I / O hub 2207 can be integrated into a system-on-chip (SoC) integrated circuit. In at least one embodiment, the components of the computer system 2200 can be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of the computer system 2200 can be integrated into a multi-chip module (MCM), which can be interconnected with other multi-chip modules into a modular computer system.

[0375] In at least one embodiment, the computing system 2200 is integrated into Figure 1-11In at least one embodiment, the processor 2202 includes one or more circuits for performing operations such as those described above in conjunction with Figure 1-11 Describes the operation.

[0376] processor

[0377] Figure 23A 2300 in accordance with at least one embodiment. In at least one embodiment, the various components of the parallel processor 2300 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA). In at least one embodiment, the parallel processor 2300 is shown as a processor according to an exemplary embodiment. Figure 22 A variation of the one or more parallel processors 2212 shown.

[0378] In at least one embodiment, parallel processor 2300 includes parallel processing unit 2302. In at least one embodiment, parallel processing unit 2302 includes an I / O unit 2304 that enables communication with other devices, including other instances of parallel processing unit 2302. In at least one embodiment, I / O unit 2304 can be directly connected to other devices. In at least one embodiment, I / O unit 2304 connects to other devices using a hub or switch interface (e.g., memory hub 2305). In at least one embodiment, the connection between memory hub 2305 and I / O unit 2304 forms a communication link. In at least one embodiment, I / O unit 2304 is connected to a host interface 2306 and a memory crossbar switch 2316, where host interface 2306 receives commands for performing processing operations and memory crossbar switch 2316 receives commands for performing memory operations.

[0379] In at least one embodiment, when host interface 2306 receives command buffers via I / O unit 2304, host interface 2306 can direct work operations to execute those commands to front end 2308. In at least one embodiment, front end 2308 is coupled to scheduler 2310, which is configured to distribute commands or other work items to processing cluster array 2312. In at least one embodiment, scheduler 2310 ensures that processing cluster array 2312 is properly configured and in a valid state before distributing tasks to processing cluster array 2312. In at least one embodiment, scheduler 2310 is implemented by firmware logic executing on a microcontroller. In at least one embodiment, the microcontroller-implemented scheduler 2310 can be configured to perform complex scheduling and work distribution operations at both coarse and fine granularity, thereby enabling fast preemption and context switching of threads executing on processing array 2312. In at least one embodiment, host software can authenticate workloads for scheduling on processing array 2312 through one of multiple graphics processing doorbells. In at least one embodiment, the workload may then be automatically distributed across the processing array 2312 by scheduler 2310 logic within a microcontroller that includes scheduler 2310 .

[0380] In at least one embodiment, processing cluster array 2312 can include up to "N" processing clusters (e.g., cluster 2314A, cluster 2314B, through cluster 2314N). In at least one embodiment, each cluster 2314A-2314N of processing cluster array 2312 can execute a large number of concurrent threads. In at least one embodiment, scheduler 2310 can assign work to clusters 2314A-2314N of processing cluster array 2312 using various scheduling and / or work distribution algorithms, which can vary depending on the workload generated by each program or computation type. In at least one embodiment, scheduling can be handled dynamically by scheduler 2310 or can be partially assisted by compiler logic during the compilation of program logic configured to be executed by processing cluster array 2312. In at least one embodiment, different clusters 2314A-2314N of processing cluster array 2312 can be assigned to process different types of programs or to perform different types of computations.

[0381] In at least one embodiment, processing cluster array 2312 can be configured to perform various types of parallel processing operations. In at least one embodiment, processing cluster array 2312 can be configured to perform general-purpose parallel computing operations. For example, in at least one embodiment, processing cluster array 2312 can include logic to perform processing tasks including filtering video and / or audio data, performing modeling operations including physics operations, and performing data transformations.

[0382] In at least one embodiment, processing cluster array 2312 is configured to perform parallel graphics processing operations. In at least one embodiment, processing cluster array 2312 may include additional logic to support the execution of such graphics processing operations, including but not limited to texture sampling logic to perform texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, processing cluster array 2312 may be configured to execute shader programs related to graphics processing, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, parallel processing units 2302 may transfer data from system memory via I / O units 2304 for processing. In at least one embodiment, during processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 2322) during processing and then written back to system memory.

[0383] In at least one embodiment, when parallel processing unit 2302 is used to perform graphics processing, scheduler 2310 can be configured to divide the processing workload into tasks of approximately equal size to better distribute graphics processing operations to multiple clusters 2314A-2314N of processing cluster array 2312. In at least one embodiment, portions of processing cluster array 2312 can be configured to perform different types of processing. For example, in at least one embodiment, a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform tessellation and geometry shading, and a third portion can be configured to perform pixel shading or other screen-space operations to generate a rendered image for display. In at least one embodiment, intermediate data generated by one or more of clusters 2314A-2314N can be stored in a buffer to allow the intermediate data to be transferred between clusters 2314A-2314N for further processing.

[0384] In at least one embodiment, the processing cluster array 2312 can receive processing tasks to be executed via the scheduler 2310, which receives commands defining the processing tasks from the front end 2308. In at least one embodiment, the processing tasks can include an index of data to be processed, such as surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands defining how to process the data (e.g., what program to execute). In at least one embodiment, the scheduler 2310 can be configured to obtain an index corresponding to a task, or can receive the index from the front end 2308. In at least one embodiment, the front end 2308 can be configured to ensure that the processing cluster array 2312 is configured in a valid state before starting a workload specified by an incoming command buffer (e.g., a batch buffer, a push buffer, etc.).

[0385] In at least one embodiment, each of the one or more instances of parallel processing unit 2302 can be coupled to parallel processor memory 2322. In at least one embodiment, parallel processor memory 2322 can be accessed via memory crossbar 2316, which can receive memory requests from processing cluster array 2312 and I / O unit 2304. In at least one embodiment, memory crossbar 2316 can access parallel processor memory 2322 via memory interface 2318. In at least one embodiment, memory interface 2318 can include multiple partition units (e.g., partition unit 2320A, partition unit 2320B, through partition unit 2320N), which can each be coupled to a portion of parallel processor memory 2322 (e.g., a memory unit). In at least one embodiment, the plurality of partition units 2320A-2320N are configured to be equal to the number of memory cells, such that the first partition unit 2320A has a corresponding first memory cell 2324A, the second partition unit 2320B has a corresponding memory cell 2324B, and the Nth partition unit 2320N has a corresponding Nth memory cell 2324N. In at least one embodiment, the number of partition units 2320A-2320N may not be equal to the number of memory devices.

[0386] In at least one embodiment, memory units 2324A-2324N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, memory units 2324A-2324N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). In at least one embodiment, render targets such as frame buffers or texture maps may be stored across memory units 2324A-2324N, allowing partition units 2320A-2320N to write portions of each render target in parallel to efficiently use the available bandwidth of parallel processor memory 2322. In at least one embodiment, local instances of parallel processor memory 2322 may be eliminated in favor of a unified memory design utilizing system memory in combination with local cache memory.

[0387] In at least one embodiment, any of the clusters 2314A-2314N in the processing cluster array 2312 can process data to be written to any memory unit 2324A-2324N within the parallel processor memory 2322. In at least one embodiment, the memory crossbar 2316 can be configured to transmit the output of each cluster 2314A-2314N to any partition unit 2320A-2320N or another cluster 2314A-2314N, which can perform other processing operations on the output. In at least one embodiment, each cluster 2314A-2314N can communicate with a memory interface 2318 via the memory crossbar 2316 to read from or write to various external storage devices. In at least one embodiment, memory crossbar switch 2316 has connections to memory interface 2318 for communicating with I / O unit 2304, as well as connections to local instances of parallel processor memory 2322, thereby enabling processing units within different processing clusters 2314A-2314N to communicate with system memory or other memory that is not local to parallel processing unit 2302. In at least one embodiment, memory crossbar switch 2316 can use virtual channels to separate traffic flows between clusters 2314A-2314N and partition units 2320A-2320N.

[0388] In at least one embodiment, multiple instances of parallel processing unit 2302 can be provided on a single plug-in card, or multiple plug-in cards can be interconnected. In at least one embodiment, different instances of parallel processing unit 2302 can be configured to interoperate with each other, even if the different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences. For example, in at least one embodiment, some instances of parallel processing unit 2302 can include higher precision floating point units relative to other instances. In at least one embodiment, a system incorporating one or more instances of parallel processing unit 2302 or parallel processor 2300 can be implemented in a variety of configurations and form factors, including but not limited to desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0389] Figure 23B is a block diagram of a partition unit 2320 according to at least one embodiment. In at least one embodiment, the partition unit 2320 is Figure 23A2320N。In at least one embodiment, the partition unit 2320 includes an L2 cache 2321, a frame buffer interface 2325 and an ROP 2326 (raster operation unit). The L2 cache 2321 is a read / write cache that is configured to perform load and store operations received from the memory crossbar switch 2316 and the ROP 2326. In at least one embodiment, the L2 cache 2321 outputs read misses and urgent write-back requests to the frame buffer interface 2325 for processing. In at least one embodiment, updates can also be sent to the frame buffer via the frame buffer interface 2325 for processing. In at least one embodiment, the frame buffer interface 2325 communicates with memory units in the parallel processor memory (such as Figure 23A interacts with one of the memory units 2324A-2324N (e.g., within parallel processor memory 2322).

[0390] In at least one embodiment, ROP 2326 is a processing unit that performs raster operations such as stenciling, z-testing, blending, etc. In at least one embodiment, ROP 2326 then outputs processed graphics data that is stored in graphics memory. In at least one embodiment, ROP 2326 includes compression logic to compress depth or color data written to memory and decompress depth or color data read from memory. In at least one embodiment, the compression logic can be lossless compression logic that utilizes one or more of a variety of compression algorithms. In at least one embodiment, the type of compression performed by ROP 2326 can vary based on the statistical characteristics of the data to be compressed. For example, in at least one embodiment, incremental color compression is performed based on depth and color data on a per-tile basis.

[0391] In at least one embodiment, ROP 2326 is included within each processing cluster (e.g., Figure 23A In at least one embodiment, read and write requests for pixel data are transmitted through the memory crossbar 2316 rather than through the pixel fragment data transfer. In at least one embodiment, the processed graphics data can be displayed on a display device such as a Figure 22 2202 for further processing, or by Figure 23A One of the processing entities within parallel processor 2300 is routed for further processing.

[0392] Figure 23C is a block diagram of a processing cluster 2314 within a parallel processing unit according to at least one embodiment. In at least one embodiment, a processing cluster is Figure 23AIn at least one embodiment, processing cluster 2314 can be configured to execute many threads in parallel, where the term "thread" refers to an instance of a particular program executed on a particular set of input data. In at least one embodiment, single instruction multiple data (SIMD) instruction issuance technology is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, single instruction multiple thread (SIMT) technology is used to support the parallel execution of a large number of generally synchronized threads, which uses a common instruction unit that is configured to issue instructions to a group of processing engines within each processing cluster.

[0393] In at least one embodiment, the operation of the processing cluster 2314 can be controlled by a pipeline manager 2332 that assigns processing tasks to SIMT parallel processors. In at least one embodiment, the pipeline manager 2332 Figure 23A Scheduler 2310 receives instructions and manages the execution of these instructions via graphics multiprocessor 2334 and / or texture unit 2336. In at least one embodiment, graphics multiprocessor 2334 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors with different architectures may be included within processing cluster 2314. In at least one embodiment, one or more instances of graphics multiprocessor 2334 may be included within processing cluster 2314. In at least one embodiment, graphics multiprocessor 2334 may process data, and data crossbar 2340 may be used to distribute the processed data to one of multiple possible destinations (including other shader units). In at least one embodiment, pipeline manager 2332 may facilitate the distribution of processed data by specifying a destination for the processed data to be distributed via data crossbar 2340.

[0394] In at least one embodiment, each graphics multiprocessor 2334 within a processing cluster 2314 may include the same set of function execution logic (e.g., arithmetic logic unit, load-store unit, etc.). In at least one embodiment, the function execution logic may be configured in a pipelined manner, where new instructions may be issued before previous instructions have completed. In at least one embodiment, the function execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, shifts, and calculations of various algebraic functions. In at least one embodiment, the same functional unit hardware may be utilized to perform different operations, and any combination of functional units may be present.

[0395] In at least one embodiment, instructions transmitted to the processing cluster 2314 constitute threads. In at least one embodiment, a group of threads executed across a set of parallel processing engines is a thread group. In at least one embodiment, a thread group executes a program on different input data. In at least one embodiment, each thread within a thread group can be assigned to a different processing engine within the graphics multiprocessor 2334. In at least one embodiment, a thread group can include fewer threads than the number of processing engines within the graphics multiprocessor 2334. In at least one embodiment, when a thread group includes fewer threads than the number of processing engines, one or more processing engines may be idle during the processing of a loop of the thread group. In at least one embodiment, a thread group can also include more threads than the number of processing engines within the graphics multiprocessor 2334. In at least one embodiment, when a thread group includes more threads than the number of processing engines within the graphics multiprocessor 2334, processing can be performed in consecutive clock cycles. In at least one embodiment, multiple thread groups can be executed simultaneously on the graphics multiprocessor 2334.

[0396] In at least one embodiment, the graphics multiprocessor 2334 includes internal cache memory to perform load and store operations. In at least one embodiment, the graphics multiprocessor 2334 can abandon the internal cache and use cache memory within the processing cluster 2314 (e.g., L1 cache 2348). In at least one embodiment, each graphics multiprocessor 2334 can also access a partition unit (e.g., Figure 23A L2 cache within partition units 2320A-2320N) of the graphics multiprocessor 2302 is shared across all processing clusters 2314 and can be used to transfer data between threads. In at least one embodiment, graphics multiprocessor 2334 can also access off-chip global memory, which can include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory external to parallel processing unit 2302 can be used as global memory. In at least one embodiment, processing cluster 2314 includes multiple instances of graphics multiprocessor 2334, which can share common instructions and data, which can be stored in L1 cache 2348.

[0397] In at least one embodiment, each processing cluster 2314 may include a memory management unit ("MMU") 2345 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of the MMU 2345 may reside in Figure 23A2318. In at least one embodiment, the MMU 2345 includes a set of page table entries (PTEs) that are used to map virtual addresses to physical addresses of tiles (more on tiling) and optionally to cache line indices. In at least one embodiment, the MMU 2345 may include an address translation lookaside buffer (TLB) or cache that may reside within the graphics multiprocessor 2334 or L1 cache or processing cluster 2314. In at least one embodiment, the physical addresses are processed to assign surface data access locality for efficient request interleaving between partition units. In at least one embodiment, the cache line index may be used to determine whether a request for a cache line is a hit or a miss.

[0398] In at least one embodiment, the processing clusters 2314 can be configured such that each graphics multiprocessor 2334 is coupled to a texture unit 2336 to perform texture mapping operations, which determine texture sample locations, read texture data, and filter texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within the graphics multiprocessor 2334, and retrieved from an L2 cache, local parallel processor memory, or system memory as needed. In at least one embodiment, each graphics multiprocessor 2334 outputs processed tasks to a data crossbar 2340 to provide the processed tasks to another processing cluster 2314 for further processing or to store the processed tasks in an L2 cache, local parallel processor memory, or system memory via the memory crossbar 2316. In at least one embodiment, a PreROP 2342 (pre-raster operations unit) is configured to receive data from the graphics multiprocessor 2334 and direct the data to a ROP unit, which can communicate with a partition unit (e.g., a partition unit) as described herein. Figure 23A In at least one embodiment, the PreROP 2342 unit can perform optimizations for color blending, organize pixel color data, and perform address translation.

[0399] In at least one embodiment, the parallel processor 2300 is integrated into Figure 1-11 In at least one embodiment, the parallel processor 2300 includes one or more circuits for performing operations such as those described above in conjunction with Figure 1-11 Describes the operation.

[0400] Figure 23DA graphics multiprocessor 2334 is shown in accordance with at least one embodiment. In at least one embodiment, the graphics multiprocessor 2334 is coupled to a pipeline manager 2332 of a processing cluster 2314. In at least one embodiment, the graphics multiprocessor 2334 has an execution pipeline that includes, but is not limited to, an instruction cache 2352, an instruction unit 2354, an address mapping unit 2356, a register file 2358, one or more general purpose graphics processing unit (GPGPU) cores 2362, and one or more load / store units 2366. The GPGPU cores 2362 and the load / store units 2366 are coupled to a cache memory 2372 and a shared memory 2370 via a memory and cache interconnect 2368.

[0401] In at least one embodiment, the instruction cache 2352 receives a stream of instructions to be executed from the pipeline manager 2332. In at least one embodiment, the instructions are cached in the instruction cache 2352 and dispatched for execution by the instruction unit 2354. In one embodiment, the instruction unit 2354 can dispatch instructions as thread groups (e.g., warps), assigning each thread of the thread group to a different execution unit within the GPGPU core 2362. In at least one embodiment, the instructions can access any local, shared, or global address space by specifying an address within the unified address space. In at least one embodiment, the address mapping unit 2356 can be used to convert addresses in the unified address space into different memory addresses that can be accessed by the load / store unit 2366.

[0402] In at least one embodiment, register file 2358 provides a set of registers for the functional units of graphics multiprocessor 2334. In at least one embodiment, register file 2358 provides temporary storage for operands for the data paths of the functional units (e.g., GPGPU core 2362, load / store unit 2366) connected to graphics multiprocessor 2334. In at least one embodiment, register file 2358 is divided between each functional unit such that a dedicated portion of register file 2358 is allocated to each functional unit. In at least one embodiment, register file 2358 is divided between the different warps being executed by graphics multiprocessor 2334.

[0403] In at least one embodiment, the GPGPU cores 2362 may each include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing instructions of the graphics multiprocessor 2334. The GPGPU cores 2362 may be architecturally similar or may differ in architecture. In at least one embodiment, a first portion of the GPGPU core 2362 includes a single-precision FPU and integer ALU, while a second portion of the GPGPU core includes a double-precision FPU. In at least one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point arithmetic or enable variable-precision floating-point arithmetic. In at least one embodiment, the graphics multiprocessor 2334 may additionally include one or more fixed-function or special-function units to perform specific functions, such as copying rectangles or pixel blending operations. In at least one embodiment, one or more of the GPGPU cores may also include fixed-function or special-function logic.

[0404] In at least one embodiment, the GPGPU core 2362 includes SIMD logic capable of executing a single instruction on multiple sets of data. In one embodiment, the GPGPU core 2362 can physically execute SIMD4, SIMD8, and SIMD16 instructions, and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, the SIMD instructions for the GPGPU core can be generated by a shader compiler at compile time, or automatically generated when executing a program written and compiled for a single program multiple data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for a SIMT execution model can be executed by a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads performing the same or similar operations can be executed in parallel by a single SIMD8 logic unit.

[0405] In at least one embodiment, the memory and cache interconnect 2368 is an interconnect network that connects each functional unit of the graphics multiprocessor 2334 to the register file 2358 and the shared memory 2370. In at least one embodiment, the memory and cache interconnect 2368 is a crossbar interconnect that allows the load / store unit 2366 to perform load and store operations between the shared memory 2370 and the register file 2358. In at least one embodiment, the register file 2358 can operate at the same frequency as the GPGPU core 2362, resulting in very low latency for data transfers between the GPGPU core 2362 and the register file 2358. In at least one embodiment, the shared memory 2370 can be used to enable communication between threads executing on the functional units within the graphics multiprocessor 2334. In at least one embodiment, the cache memory 2372 can be used, for example, as a data cache to cache texture data communicated between the functional units and the texture unit 2336. In at least one embodiment, the shared memory 2370 can also be used as a program-managed cache. In at least one embodiment, in addition to automatically cached data stored in cache memory 2372, threads executing on GPGPU core 2362 may also programmatically store data in shared memory.

[0406] In at least one embodiment, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU can be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In at least one embodiment, the GPU can be integrated on the same package or chip as the core and communicatively coupled to the core via an internal processor bus / interconnect (i.e., internal to the package or chip). In at least one embodiment, regardless of the manner in which the GPU is connected, the processor core can assign work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. In at least one embodiment, the GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0407] In at least one embodiment, the graphics multiprocessor 2334 is integrated into Figure 1-11 In at least one embodiment, the graphics multiprocessor 2334 includes one or more circuits for performing operations such as those described above in conjunction with Figure 1-11 Describes the operation.

[0408] Figure 24A multi-GPU computing system 2400 is shown in accordance with at least one embodiment. In at least one embodiment, multi-GPU computing system 2400 may include a processor 2402 coupled to a plurality of general-purpose graphics processing units (GPGPUs) 2406A-D via a host interface switch 2404. In at least one embodiment, host interface switch 2404 is a PCI Express switch device that couples processor 2402 to a PCI Express bus, over which processor 2402 can communicate with GPGPUs 2406A-D. GPGPUs 2406A-D may be interconnected via a set of high-speed P2P GPU-to-GPU links 2416. In at least one embodiment, GPU-to-GPU links 2416 connect to each of GPGPUs 2406A-D via a dedicated GPU link. In at least one embodiment, P2P GPU links 2416 enable direct communication between each GPGPU 2406A-D without requiring communication through host interface bus 2404 to which processor 2402 is connected. In at least one embodiment, with GPU-to-GPU traffic directed to P2P GPU link 2416, host interface bus 2404 remains available for system memory access or communication with other instances of multi-GPU computing system 2400, e.g., via one or more network devices. While in at least one embodiment, GPGPUs 2406A-D are connected to processor 2402 via host interface switch 2404, in at least one embodiment, processor 2402 includes direct support for P2P GPU link 2416 and can connect directly to GPGPUs 2406A-D.

[0409] In at least one embodiment, the multi-GPU computing system 2400 is integrated into Figure 1-11 In at least one embodiment, the processor 2402 includes one or more circuits for performing the operations described above in conjunction with Figure 1-11 The operation described.

[0410] Figure 25 FIG2 is a block diagram of a graphics processor 2500 according to at least one embodiment. In at least one embodiment, graphics processor 2500 includes a ring interconnect 2502, a pipeline front end 2504, a media engine 2537, and graphics cores 2580A-2580N. In at least one embodiment, ring interconnect 2502 couples graphics processor 2500 to other processing units, including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, graphics processor 2500 is one of many processors integrated within a multi-core processing system.

[0411] In at least one embodiment, the graphics processor 2500 receives batches of commands via a ring interconnect 2502. In at least one embodiment, the incoming commands are interpreted by a command streamer 2503 in a pipeline front end 2504. In at least one embodiment, the graphics processor 2500 includes scalable execution logic for performing 3D geometry processing and media processing via graphics cores 2580A-2580N. In at least one embodiment, for 3D geometry processing commands, the command streamer 2503 provides the commands to a geometry pipeline 2536. In at least one embodiment, for at least some media processing commands, the command streamer 2503 provides the commands to a video front end 2534, which is coupled to a media engine 2537. In at least one embodiment, the media engine 2537 includes a video quality engine (VQE) 2530 for video and image post-processing, and a multi-format encoding / decoding (MFX) 2533 engine for providing hardware-accelerated media data encoding and decoding. In at least one embodiment, the geometry pipeline 2536 and the media engine 2537 each generate execution threads for thread execution resources provided by at least one graphics core 2580A.

[0412] In at least one embodiment, the graphics processor 2500 includes scalable thread execution resources featuring modular cores 2580A-2580N (sometimes referred to as core slices), each of which has multiple sub-cores 2550A-2550N, 2560A-2560N (sometimes referred to as core sub-slices). In at least one embodiment, the graphics processor 2500 can have any number of graphics cores 2580A-2580N. In at least one embodiment, the graphics processor 2500 includes a graphics core 2580A having at least a first sub-core 2550A and a second sub-core 2560A. In at least one embodiment, the graphics processor 2500 is a low-power processor having a single sub-core (e.g., 2550A). In at least one embodiment, the graphics processor 2500 includes multiple graphics cores 2580A-2580N, each of which includes a set of first sub-cores 2550A-2550N and a set of second sub-cores 2560A-2560N. In at least one embodiment, each of the first sub-cores 2550A-2550N includes at least a first set of execution units 2552A-2552N and media / texture samplers 2554A-2554N. In at least one embodiment, each of the second sub-cores 2560A-2560N includes at least a second set of execution units 2562A-2562N and samplers 2564A-2564N. In at least one embodiment, each of the sub-cores 2550A-2550N, 2560A-2560N shares a set of shared resources 2570A-2570N. In at least one embodiment, the shared resources include shared cache memory and pixel operation logic.

[0413] In at least one embodiment, the graphics processor 2500 is integrated into Figure 1-11 In at least one embodiment, the graphics processor 2500 includes one or more circuits for performing operations such as those described above in conjunction with Figure 1-11 Describes the operation.

[0414] Figure 26 is a block diagram illustrating a microarchitecture for a processor 2600 that may include logic circuitry for executing instructions, according to at least one embodiment. In at least one embodiment, the processor 2600 may execute instructions including x86 instructions, ARM instructions, specialized instructions for an application-specific integrated circuit (ASIC), and the like. In at least one embodiment, the processor 2600 may include registers for storing packed data, such as the 64-bit wide MMX registers in microprocessors enabled with MMX technology from Intel Corporation of Santa Clara, California. TMRegisters. In at least one embodiment, MMX registers available in integer and floating point form can operate with packed data elements that accompany single instruction multiple data (“SIMD”) and streaming SIMD extensions (“SSE”) instructions. In at least one embodiment, 128-bit wide XMM registers associated with SSE2, SSE3, SSE4, AVX, or higher (generally referred to as “SSEx”) technology can hold such packed data operands. In at least one embodiment, processor 2610 can execute instructions to accelerate machine learning or deep learning algorithms, training, or inference.

[0415] In at least one embodiment, the processor 2600 includes an in-order front end ("front end") 2601 to fetch instructions to be executed and prepare the instructions for later use in the processor pipeline. In at least one embodiment, the front end 2601 may include several units. In at least one embodiment, an instruction prefetcher 2626 retrieves instructions from memory and provides the instructions to an instruction decoder 2628, which in turn decodes or interprets the instructions. For example, in at least one embodiment, the instruction decoder 2628 decodes the received instructions into one or more operations called "microinstructions" or "micro-operations" (also referred to as "micro-ops" or "micro-instructions") that the machine can execute. In at least one embodiment, the instruction decoder 2628 parses the instructions into an opcode and corresponding data and control fields, which can be used by the microarchitecture to perform the operations according to at least one embodiment. In at least one embodiment, the trace cache 2630 can assemble the decoded microinstructions into a program-ordered sequence or trace in the microinstruction queue 2634 for execution. In at least one embodiment, when trace cache 2630 encounters a complex instruction, microcode ROM 2632 provides the microinstructions necessary to complete the operation.

[0416] In at least one embodiment, some instructions may be converted into a single micro-op, while other instructions may require several micro-ops to complete the entire operation. In at least one embodiment, if more than four micro-ops are required to complete an instruction, the instruction decoder 2628 may access the microcode ROM 2632 to execute the instruction. In at least one embodiment, an instruction may be decoded into a smaller number of micro-ops for processing at the instruction decoder 2628. In at least one embodiment, if multiple micro-ops are required to complete the operation, the instruction may be stored in the microcode ROM 2632. In at least one embodiment, the trace cache 2630 references the entry point programmable logic array ("PLA") to determine the correct micro-op pointer for reading the microcode sequence from the microcode ROM 2632 to complete one or more instructions in accordance with at least one embodiment. In at least one embodiment, after the microcode ROM 2632 completes the micro-op sequencing for the instruction, the front end 2601 of the machine may resume fetching micro-ops from the trace cache 2630.

[0417] In at least one embodiment, an out-of-order execution engine ("OOO engine") 2603 can prepare instructions for execution. In at least one embodiment, the OOO logic has multiple buffers to smooth and reorder the instruction flow to optimize performance as instructions go down the pipeline and are scheduled for execution. The OOO engine 2603 includes, but is not limited to, an allocator / register renamer 2640, a memory microinstruction queue 2642, an integer / floating-point microinstruction queue 2644, a memory scheduler 2646, a fast scheduler 2602, a slow / general purpose floating-point scheduler ("slow / general purpose FP scheduler") 2604, and a simple floating-point scheduler ("simple FP scheduler") 2606. In at least one embodiment, the fast scheduler 2602, the slow / general purpose floating-point scheduler 2604, and the simple floating-point scheduler 2606 are also collectively referred to as "microinstruction schedulers 2602, 2604, 2606." In at least one embodiment, the allocator / register renamer 2640 allocates the machine buffers and resources required for each microinstruction to execute in sequence. In at least one embodiment, the allocator / register renamer 2640 renames logical registers into entries in the register file. In at least one embodiment, the allocator / register renamer 2640 also allocates an entry for each microinstruction in one of two microinstruction queues: a memory microinstruction queue 2642 for memory operations and an integer / floating-point microinstruction queue 2644 for non-memory operations, preceding the memory scheduler 2646 and the microinstruction schedulers 2602, 2604, and 2606. In at least one embodiment, the microinstruction schedulers 2602, 2604, and 2606 determine when a microinstruction is ready to execute based on the readiness of their dependent input register operand sources and the availability of the execution resource microinstructions that need to be completed. The fast scheduler 2602 of at least one embodiment can schedule every half of the main clock cycle, while the slow / general floating-point scheduler 2604 and the simple floating-point scheduler 2606 can schedule once per main processor clock cycle. In at least one embodiment, microinstruction schedulers 2602, 2604, 2606 arbitrate on dispatch ports to schedule microinstructions for execution.

[0418] In at least one embodiment, execution block 2611 includes, but is not limited to, integer register file / branch network 2608, floating point register file / branch network ("FP register file / branch network") 2610, address generation units ("AGUs") 2612 and 2614, fast arithmetic logic units ("fast ALUs") 2616 and 2618, slow arithmetic logic unit ("slow ALU") 2620, floating point ALU ("FP") 2622, and floating point move unit ("FP move") 2624. In at least one embodiment, integer register file / branch network 2608 and floating point register file / bypass network 2610 are also referred to herein as "register files 2608, 2610." In at least one embodiment, AGUs 2612 and 2614, fast ALUs 2616 and 2618, slow ALU 2620, floating-point ALU 2622, and floating-point move unit 2624 are also referred to herein as "execution units 2612, 2614, 2616, 2618, 2620, 2622, and 2624." In at least one embodiment, execution block 2611 may include, but is not limited to, any number (including zero) and type of register files, branch networks, address generation units, and execution units (in any combination).

[0419] In at least one embodiment, register files 2608 and 2610 may be arranged between microinstruction schedulers 2602, 2604, and 2606 and execution units 2612, 2614, 2616, 2618, 2620, 2622, and 2624. In at least one embodiment, integer register file / branch network 2608 performs integer operations. In at least one embodiment, floating-point register file / branch network 2610 performs floating-point operations. In at least one embodiment, each of register files 2608 and 2610 may include, but is not limited to, a branch network that can bypass or forward recently completed results that have not yet been written to the register file to new dependent objects. In at least one embodiment, register files 2608 and 2610 can communicate data with each other. In at least one embodiment, integer register file / branch network 2608 may include, but is not limited to, two separate register files: one register file for low-order 32-bit data and a second register file for high-order 32-bit data. In at least one embodiment, floating point register file / branch network 2610 may include, but is not limited to, 128-bit wide entries, as floating point instructions typically have operands that are 64 to 128 bits wide.

[0420] In at least one embodiment, execution units 2612, 2614, 2616, 2618, 2620, 2622, and 2624 can execute instructions. In at least one embodiment, register files 2608 and 2610 store integer and floating-point data operand values ​​required for microinstructions to execute. In at least one embodiment, processor 2600 can include, but is not limited to, any number of execution units 2612, 2614, 2616, 2618, 2620, 2622, and 2624, and any combination thereof. In at least one embodiment, floating-point ALU 2622 and floating-point move unit 2624 can execute floating-point, MMX, SIMD, AVX, SSE, or other operations, including specialized machine learning instructions. In at least one embodiment, floating-point ALU 2622 can include, but is not limited to, a 64-bit by 64-bit floating-point divider to perform division, square root, and remainder micro-operations. In at least one embodiment, floating-point hardware can be used to process instructions involving floating-point values. In at least one embodiment, ALU operations can be passed to fast ALUs 2616 and 2618. In at least one embodiment, fast ALUs 2616 and 2618 can perform fast operations with an effective latency of half a clock cycle. In at least one embodiment, most complex integer operations go to slow ALU 2620, as slow ALU 2620 may include, but is not limited to, integer execution hardware for long-latency operations, such as multipliers, shifts, flag logic, and branch processing. In at least one embodiment, memory load / store operations can be performed by ALUs 2612 and 2614. In at least one embodiment, fast ALU 2616, fast ALU 2618, and slow ALU 2620 can perform integer operations on 64-bit data operands. In at least one embodiment, fast ALU 2616, fast ALU 2618, and slow ALU 2620 can be implemented to support various data bit sizes, including 16, 32, 128, 256, and the like. In at least one embodiment, the floating point ALU 2622 and floating point shift unit 2624 can be implemented to support a range of operands having bits of various widths. In at least one embodiment, the floating point ALU 2622 and floating point shift unit 2624 can operate on 128-bit wide packed data operands in conjunction with SIMD and multimedia instructions.

[0421] In at least one embodiment, microinstruction schedulers 2602, 2604, 2606 schedule dependent operations before the parent load completes execution. In at least one embodiment, because microinstructions can be speculatively scheduled and executed in processor 2600, processor 2600 can also include logic for handling memory misses. In at least one embodiment, if a data load misses in the data cache, there may be dependent operations running in the pipeline that temporarily prevent the scheduler from having the correct data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use incorrect data. In at least one embodiment, it may be necessary to replay dependent operations and allow independent operations to complete. In at least one embodiment, the scheduler and replay mechanism of at least one embodiment of the processor can also be designed to capture instruction sequences for text string comparison operations.

[0422] In at least one embodiment, the term "register" may refer to an on-board processor storage location that can be used as part of an instruction to identify an operand. In at least one embodiment, registers may be those that can be used from outside the processor (from a programmer's perspective). In at least one embodiment, registers may not be limited to a particular type of circuit. Instead, in at least one embodiment, registers can store data, provide data, and perform the functions described herein. In at least one embodiment, the registers described herein can be implemented by circuitry within the processor using a variety of different techniques, such as dedicated physical registers, physical registers dynamically allocated using register renaming, a combination of dedicated and dynamically allocated physical registers, and the like. In at least one embodiment, integer registers store 32-bit integer data. The register file of at least one embodiment also includes eight multimedia SIMD registers for packing data.

[0423] In at least one embodiment, processor 2600 is integrated into Figure 1-11 In at least one embodiment, the processor 2600 includes one or more circuits for performing operations such as those described above in conjunction with Figure 1-11 Describes the operation.

[0424] Figure 27 A block diagram of a processing system according to at least one embodiment is shown. In at least one embodiment, system 2700 includes one or more processors 2702 and one or more graphics processors 2708, and can be a single-processor desktop system, a multi-processor workstation system, or a server system with a large number of processors 2702 or processor cores 2707. In at least one embodiment, system 2700 is a processing platform incorporated within a system-on-chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices.

[0425] In at least one embodiment, the system 2700 may include or be incorporated into a server-based gaming platform, including a gaming console, a mobile gaming console, a handheld gaming console, or an online gaming console, including a gaming and media console. In at least one embodiment, the system 2700 is a mobile phone, a smart phone, a tablet computing device, or a mobile internet device. In at least one embodiment, the processing system 2700 may also include a device coupled to or integrated into a wearable device, such as a smartwatch wearable device, a smart glasses device, an augmented reality device, or a virtual reality device. In at least one embodiment, the processing system 2700 is a television or set-top box device having one or more processors 2702 and a graphical interface generated by one or more graphics processors 2708.

[0426] In at least one embodiment, one or more processors 2702 each include one or more processor cores 2707 to process instructions that, when executed, perform operations for system and user software. In at least one embodiment, each of the one or more processor cores 2707 is configured to process a specific instruction set 2709. In at least one embodiment, the instruction set 2709 can facilitate complex instruction set computing (CISC), reduced instruction set computing (RISC), or computing via very long instruction words (VLIW). In at least one embodiment, the processor cores 2707 can each process a different instruction set 2709, which can include instructions that facilitate emulation of other instruction sets. In at least one embodiment, the processor cores 2707 can also include other processing devices, such as a digital signal processor (DSP).

[0427] In at least one embodiment, the processor 2702 includes a cache memory 2704. In at least one embodiment, the processor 2702 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory is shared among various components of the processor 2702. In at least one embodiment, the processor 2702 also uses an external cache (e.g., a level 3 (L3) cache or a last level cache (LLC)) (not shown), which may be shared among the processor cores 2707 using known cache coherence techniques. In at least one embodiment, the processor 2702 further includes a register file 2706. The processor may include different types of registers (e.g., integer registers, floating point registers, status registers, and an instruction pointer register) for storing different types of data. In at least one embodiment, the register file 2706 may include general purpose registers or other registers.

[0428] In at least one embodiment, one or more processors 2702 are coupled to one or more interface buses 2710 to transmit communication signals, such as address, data, or control signals, between the processors 2702 and other components in the system 2700. In at least one embodiment, the interface bus 2710 can be a processor bus, such as a version of a Direct Media Interface (DMI) bus. In at least one embodiment, the interface 2710 is not limited to a DMI bus and can include one or more peripheral component interconnect buses (e.g., PCI, PCI Express), a memory bus, or other types of interface buses. In at least one embodiment, the processor 2702 includes an integrated memory controller 2716 and a platform controller hub 2730. In at least one embodiment, the memory controller 2716 facilitates communication between memory devices and other components of the processing system 2700, while the platform controller hub (PCH) 2730 provides connections to input / output (I / O) devices via a local I / O bus.

[0429] In at least one embodiment, the memory device 2720 can be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or other suitable memory device for use as processor memory. In at least one embodiment, the memory device 2720 can be used as system memory for the processing system 2700 to store data 2722 and instructions 2721 for use when one or more processors 2702 execute applications or processes. In at least one embodiment, the memory controller 2716 is also coupled to an optional external graphics processor 2712, which can communicate with one or more graphics processors 2708 in the processor 2702 to perform graphics and media operations. In at least one embodiment, a display device 2711 can be connected to the processor 2702. In at least one embodiment, the display device 2711 can include one or more internal display devices, such as in a mobile electronic device or laptop device, or an external display device connected via a display interface (e.g., DisplayPort, etc.). In at least one embodiment, the display device 2711 may include a head-mounted display (HMD), such as a stereoscopic display device used in virtual reality (VR) applications or augmented reality (AR) applications.

[0430] In at least one embodiment, the platform controller hub 2730 enables peripheral devices to connect to the storage device 2720 and the processor 2702 via a high-speed I / O bus. In at least one embodiment, the I / O peripherals include, but are not limited to, an audio controller 2746, a network controller 2734, a firmware interface 2728, a wireless transceiver 2726, a touch sensor 2725, and a data storage device 2724 (e.g., a hard drive, flash memory, etc.). In at least one embodiment, the data storage device 2724 can be connected via a storage interface (e.g., SATA) or via a peripheral bus, such as a peripheral component interconnect bus (e.g., PCI, PCIe). In at least one embodiment, the touch sensor 2725 can include a touch screen sensor, a pressure sensor, or a fingerprint sensor. In at least one embodiment, the wireless transceiver 2726 can be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver, such as a 3G, 4G, or Long Term Evolution (LTE) transceiver. In at least one embodiment, the firmware interface 2728 enables communication with the system firmware and can be, for example, a Unified Extensible Firmware Interface (UEFI). In at least one embodiment, a network controller 2734 can enable network connectivity to a wired network. In at least one embodiment, a high-performance network controller (not shown) is coupled to the interface bus 2710. In at least one embodiment, the audio controller 2746 is a multi-channel high-definition audio controller. In at least one embodiment, the processing system 2700 includes an optional legacy I / O controller 2840 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to the system 2700. In at least one embodiment, the platform controller hub 2730 can also be connected to one or more universal serial bus (USB) controllers 2742 that connect input devices such as a keyboard and mouse 2743 combination, a camera 2744, or other USB input devices.

[0431] In at least one embodiment, instances of the memory controller 2716 and the platform controller hub 2730 may be integrated into a discrete external graphics processor, such as the external graphics processor 2712. In at least one embodiment, the platform controller hub 2730 and / or the memory controller 2716 may be external to one or more processors 2702. For example, in at least one embodiment, the system 2700 may include an external memory controller 2716 and a platform controller hub 2730, which may be configured as a memory controller hub and a peripheral controller hub in a system chipset that communicates with the processor 2702.

[0432] In at least one embodiment, system 2700 is integrated into Figure 1-11In at least one embodiment, the processor 2702 includes one or more circuits for performing operations such as those described above in conjunction with Figure 1-11 Describes the operation.

[0433] Figure 28 is a block diagram of a processor 2800 having one or more processor cores 2802A-2802N, an integrated memory controller 2814, and an integrated graphics processor 2808, in accordance with at least one embodiment. In at least one embodiment, the processor 2800 may include additional cores, up to and including the additional core 2802N represented by the dashed box. In at least one embodiment, each processor core 2802A-2802N includes one or more internal cache units 2804A-2804N. In at least one embodiment, each proce...

Claims

1. A processor, comprising: One or more circuits for using one or more neural networks to generate a prediction of the quality of one or more wireless signals to be transmitted, wherein the prediction is based at least in part on one or more reference signals. 2 . The processor of claim 1 , wherein the one or more circuits are configured to generate a measurement report using the prediction of the quality of the one or more wireless signals.

3. The processor of claim 1 , wherein the one or more reference signals are one or more inputs to the one or more neural networks and the prediction of the quality of the one or more wireless signals is one or more outputs of the one or more neural networks. 4 . The processor of claim 1 , wherein the prediction of the quality of the one or more wireless signals is to be transmitted by a user device.

5. The processor of claim 1, wherein the one or more reference signals comprises a synchronization signal block (SSB) signal. 6 . The processor of claim 1 , wherein the one or more reference signals comprise a channel state information reference signal (CSI-RS).

7. The processor of claim 1, wherein the prediction of the quality of the one or more wireless signals comprises at least one or more of a reference signal received power (RSRP), a reference signal received quality (RSRQ), and a signal to interference plus noise ratio (SINR).

8. A system comprising: One or more processors for using one or more neural networks to generate a prediction of the quality of one or more wireless signals to be transmitted, wherein the prediction is based at least in part on one or more reference signals.

9. The system of claim 8, wherein the one or more processors are configured to generate a measurement report using the prediction of the quality of the one or more wireless signals.

10. The system of claim 8, wherein the one or more reference signals are one or more inputs to the one or more neural networks and the prediction of the quality of the one or more wireless signals is one or more outputs of the one or more neural networks.

11. The system of claim 8, wherein the prediction of the quality of the one or more wireless signals is transmitted over a radio link.

12. The system of claim 8, wherein the prediction of the quality of the one or more wireless signals is filtered through a layer 3 filter.

13. The system of claim 8, wherein the prediction of the quality of the one or more wireless signals is further based on a triggering event condition.

14. The system according to claim 8, wherein the trigger event condition further comprises an entry condition of the event and an exit condition of the event.

15. A method comprising: One or more neural networks are used to generate predictions of the quality of one or more wireless signals to be transmitted, wherein the predictions are based at least in part on one or more reference signals.

16. The method of claim 15, generating a measurement report using the prediction of the quality of the one or more wireless signals.

17. The method of claim 15, wherein the one or more reference signals are one or more inputs to the one or more neural networks and the prediction of the quality of the one or more wireless signals is one or more outputs of the one or more neural networks.

18. The method according to claim 15, further comprising: A second prediction of the quality of the one or more wireless signals is generated after a defined time interval. The method of claim 15 , wherein the one or more reference signals are transmitted periodically.

20. The method of claim 15, further comprising: The prediction of the quality of the one or more wireless signals is transmitted by the user equipment to a base station in the fifth generation 5G network.

Images