Turbo code tail bit decoding device, decoding method and Beidou receiver

Abstract

The present invention relates to a tail bit decoding device, a decoding method and a Beidou receiver of a Turbo code, wherein the device comprises: a first decoder, which calculates first LLR information according to input check bit 1 soft information including tail bits, L21 information and first system bit soft information; a second decoder, which calculates second LLR information according to input check bit 2 soft information including tail bits, L12 information and second system bit soft information; an L12 calculation module, which performs external information calculation, interleaving and zero padding on the first LLR information and outputs L12 information; an L21 calculation module, which performs external information calculation, deinterleaving and zero padding on the second LLR information and outputs L21 information; and a decision output module, which is used to make a decision on the second LLR information after stopping iteration and deinterleave and output a Turbo code decoding result. The present invention uses the tail bit information of the Turbo code for decoding, thereby improving the performance of the decoder.

Description

Technical Field

[0001] The present invention relates to the fields of decoding technology and satellite navigation technology, and in particular to a Turbo code tail bit decoding device, decoding method and Beidou receiver. Background Art

[0002] Turbo code is a channel error correction coding scheme that can approach the Shannon limit. Many communication systems, such as 3G and 4G mobile communication systems supported by 3GPP, use Turbo code as their channel coding scheme. In recent years, with the popularity of LDPC code and Polar code, 5G NR uses LDPC code and Polar code as its channel coding scheme. However, many communication systems, especially some satellite communication systems, such as the RDSS subsystem in China's Beidou Satellite Navigation System BDS, still use the Turbo code coding scheme due to the good performance of the Turbo code scheme.

[0003] The bit sequence output by the Turbo code encoder includes soft information bits of length K and tail bits of length T. The role of the tail bits is to reset the encoder grid to zero, which is conducive to the correct decoding of the receiver. Therefore, the tail bit sequence also carries some useful information and cannot be ignored.

[0004] The tail bits are not used in the existing Turbo code decoder because the length of the interleaver is K and it is not possible to process an additional tail bit sequence of length T. Therefore, the external information can only be retained with a length of K, and then the sub-decoder can only receive and process a system bit soft information sequence or a check bit soft information sequence of length K, and the additional tail bit soft information sequence of length T is discarded.

[0005] The tail bits carry some useful information, and the existing Turbo code decoder that does not use the tail bits will cause a degradation in decoding performance. Summary of the invention

[0006] In view of the above analysis, the present invention aims to disclose a Turbo code tail bit decoding device, decoding method and Beidou receiver to solve the problem that the traditional Turbo code decoder cannot utilize the tail bits, resulting in reduced decoding performance.

[0007] The present invention discloses a Turbo code tail bit decoding device, comprising: a first decoder, a second decoder, an L12 calculation module, an L21 calculation module and a decision output module; wherein: A first decoder, configured to calculate first LLR information according to input parity bit 1 soft information including tail bits, L21 information, and first system bit soft information; A second decoder, configured to calculate second LLR information according to the input check bit 2 soft information including tail bits, L12 information, and second system bit soft information; The second system bit soft information is the soft information of the tail bits obtained by interleaving the information before the tail bits of the first system bit soft information and then concatenating the tail bits; An L12 calculation module, configured to perform external information calculation, interleave and zero padding on the first LLR information, and then output L12 information including tail bits; An L21 calculation module, configured to perform external information calculation, deinterleave and zero padding on the second LLR information, and then output L21 information including tail bits; The decision output module is used to make a decision and deinterleave the second LLR information that meets the iteration stop condition, and output the Turbo code decoding result.

[0008] Furthermore, the first and second decoders are both tail bit sub-decoders; the length of the input information of the tail bit sub-decoder is K+T; K is the length of the encoded input data block, and T is the data length of the tail bit; the tail bit sub-decoder adopts a decoding algorithm including a log-map algorithm and a max-log-map algorithm, and operates K+T times to obtain the LLR information of the decoded output; During the decoding process, the first decoder is first decoded to obtain L12 information; the L12 information is input to the second decoder for decoding to obtain L21 information; the first decoder is decoded again; and the process is repeated in this manner until the maximum number of iterations is met.

[0009] Furthermore, it also includes: a first interleaver and a splicer, which are used to generate second system bit soft information; The first interleaver is a K-bit interleaver; used to interleave the first K bits of the first system bit soft information, and output the interleaved data to the splicer; The splicer is used to splice the accessed interleaved data and the last T tail bit soft information of the first system bit soft information together to output the second system bit soft information.

[0010] Further, the L12 calculation module includes a first external information calculation module, a second interleaver and a first zero padding module; The first external information calculation module is used to access the first K data of the first LLR information with a length of K+T output by the first decoder, discard the last T data, use the first K data of the first LLR information for calculation, remove the influence of prior information and system bit soft information, and obtain pure external information with a length of K; The second interleaver is a K-bit interleaver, configured to interleave external data of length K output by the first external information calculation module; The first zero-padding module is used to perform a zero-padding operation with a length of T bits on the data output by the second interleaver, and output L12 information with a length of K+T as external information input by the second decoder.

[0011] Further, the L21 calculation module includes a second external information calculation module, a second deinterleaver and a second zero padding module; The second external information calculation module is used to access the first K data of the second LLR information with a length of K+T output by the second decoder, discard the last T data, use the first K data of the second LLR information for calculation, remove the influence of prior information and system bit soft information, so as to obtain pure external information with a length of K; The second deinterleaver is a K-bit deinterleaver, configured to deinterleave external data of length K output by the second external information calculation module; The second zero-padding module is used to perform a zero-padding operation with a length of T bits on the data output by the second deinterleaver, and output L21 information with a length of K+T as external information input by the first decoder.

[0012] Furthermore, the calculation method of the external information is: ; Among them, LLR ext1 , LLR ext2 are the external information calculated by the first and second external information calculation modules in the current time, LLR 1 , LLR 2 The first and second LLR information output by the first and second decoders are LLR sys1 , LLR sys2 The first and second system bit soft information of the first and second decoders are input respectively, LLR a1 , LLR a2 It is the external information input by the first and second decoders.

[0013] Further, the decision output module includes a decision device and a first deinterleaver; The input end of the decision device is connected to the output end of the second decoder, accesses the second LLR information output by the second decoder, and is used to make a hard decision on the second LLR information that meets the condition for stopping iteration; and outputs the decision result to the input end of the first deinterleaver; The first deinterleaver deinterleaves the decision result output by the decider and outputs a Turbo code decoding result.

[0014] The present invention also discloses a decoding method based on the tail bit decoding device of the Turbo code as described above, comprising the following steps: Step S1, obtaining the first system bit soft information of the length K+T of the system input, the check bit 1 soft information and the check bit 2 soft information of the length K+T; initializing the L21 information and L12 information of the length K+T; setting the number of decoding iterations; Step S2, interleave the first K data of the first system bit soft information, and then concatenate them with the last T tail bit soft information of the first system bit soft information to obtain soft information with a length of K+T as the second system bit soft information; Step S3, executing the operation of the first decoder, inputting the check bit 1 soft information, L21 information and the first system bit soft information into the first decoder to calculate the first LLR information; inputting the first LLR information into the L12 calculation module to perform external information calculation, interleaving and zero padding, and then outputting the L12 information including the tail bit; Step S4, executing the operation of the second decoder, inputting the check bit 2 soft information, L12 information and the second system bit soft information into the second decoder to calculate the second LLR information; inputting the second LLR information into the L21 calculation module to perform external information calculation, deinterleaving and zero padding, and then outputting the L21 information including the tail bit; Step S5, jump to step S3, execute the operation of the first sub-decoder, and then execute the operation of the second sub-decoder, and perform iteratively until a preset maximum number of iterations is reached; Step S6: Perform a hard decision on the second LLR information output by the second decoder, and then perform a deinterleaving operation to output a Turbo code decoding result.

[0015] Furthermore, the external information calculation method in the L12 calculation module and the L21 calculation module is: ; Among them, LLR ext1 , LLR ext2 They are the external information of L12 and L21 calculation modules in the current calculation, LLR 1 , LLR 2 The first and second LLR information output by the first and second decoders are LLR sys1 , LLR sys2 The first and second system bit soft information of the first and second decoders are input respectively, LLR a1 , LLR a2 It is the external information input by the first and second decoders.

[0016] The present invention also discloses a Beidou receiver, which receives the RDSS subsystem signal in the Beidou satellite navigation system BDS. When performing Turbo code decoding, the tail bit decoding device of the Turbo code as described above is adopted, and the tail bit information of the Turbo code is used for decoding, thereby improving the decoding performance.

[0017] The present invention can achieve one of the following beneficial effects: The tail bit decoding device and method of the Turbo code and the Beidou receiver disclosed in the present invention utilize the tail bit information of the Turbo code for decoding, thereby improving the performance of the decoder; the device and method are suitable for realizing reliable data transmission under low signal-to-noise ratio (SNR) conditions, and can gradually improve the accuracy of decoding through iteration; the device and method are applied to the RDSS subsystem in the Beidou satellite navigation system (BDS) to improve the performance of the Beidou receiver. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings are only used for the purpose of illustrating specific embodiments and are not to be considered as limiting the present invention. In the entire drawings, the same reference symbols represent the same components; Figure 1 A schematic block diagram of the components and connections of a tail bit decoding device for a Turbo code in an embodiment of the present invention; Figure 2 Schematic diagram of a coding scheme of a Turbo code in an embodiment of the present invention; Figure 3 A schematic diagram of coding of a Turbo code used in a CDMA2000 system in an embodiment of the present invention; Figure 4 is a schematic diagram of a signal processing structure of a sub-encoder in an embodiment of the present invention; Figure 5 The figure is a flow chart of a decoding method of a tail bit decoding device of a Turbo code in an embodiment of the present invention. DETAILED DESCRIPTION

[0019] The preferred embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings, wherein the accompanying drawings constitute a part of this application and are used to illustrate the principles of the present invention together with the embodiments of the present invention.

[0020] Embodiment 1 An embodiment of the present invention discloses a tail bit decoding device for a Turbo code; Figure 1 As shown, it includes: a first decoder, a second decoder, an L12 calculation module, an L21 calculation module and a decision output module; wherein the first and second decoders are tail bit sub-decoders, A first decoder, configured to calculate first LLR (log-likelihood ratio) information according to input parity bit 1 soft information including tail bits, L21 information and first system bit soft information; A second decoder, configured to calculate second LLR information according to the input check bit 2 soft information including tail bits, L12 information, and second system bit soft information; The second system bit soft information is the soft information of the tail bit obtained by interleaving the information before the tail bit of the first system bit soft information and then concatenating the tail bit; An L12 calculation module, configured to perform external information calculation, interleave and zero padding on the first LLR information, and then output L12 information including tail bits; An L21 calculation module, configured to perform external information calculation, deinterleave and zero padding on the second LLR information, and then output L21 information including tail bits; The decision output module is used to make a decision and deinterleave the second LLR information that meets the iteration stop condition, and output the Turbo code decoding result.

[0021] Specifically, the tail bit sub-decoders of the first and second decoders have an input information length of K+T due to the tail bit, where K is the length of the encoded input data block, and T is the data length of the tail bit; the tail bit sub-decoder adopts a decoding algorithm including a log-map algorithm and a max-log-map algorithm, and operates K+T times to obtain the LLR information of the decoded output; During the decoding process, the first decoder is first decoded to obtain L12 information; the L12 information is input to the second decoder for decoding to obtain L21 information; the first decoder is decoded again; and the process is repeated in this manner until the maximum number of iterations is met.

[0022] like Figure 2 As shown in the figure, the coding scheme of Turbo code mainly includes two sub-encoders, an interleaver, and a rate matching module. The rate matching module mainly performs the puncturing function, which removes certain check bits or repeated system bits to meet the requirements of the transmission data rate. We usually call the upper sub-encoder sub-encoder 1 and the lower sub-encoder sub-encoder 2. The structures of the two sub-encoders are the same, and they also output system bits and check bits, so the structures of their corresponding sub-decoders are also the same. The difference from sub-encoder 1 is that the input bits of sub-encoder 2 are interleaved.

[0023] It should be pointed out that in the tail bit decoding solution of the Turbo code in the embodiment of the present invention, rate matching is not the focus, and therefore, the rate matching solution submodule is not involved.

[0024] like Figure 3 The Turbo code used in the CDMA2000 system shown in the figure; for each information bit input, each sub-encoder of the encoder outputs 3 bits, X, Y, Z, where X is a systematic bit, and Y and Z are parity bits. The systematic bit is the same bit as the input bit of the sub-encoder; but the X bit sequence may include tail bits in addition to the bit sequence input by the sub-encoder.

[0025] The signal processing structure of the two sub-encoders is the same, please refer to Figure 4 .

[0026] like Figure 4 As shown, for each input bit I, the sub-encoder outputs three bits X, Y, and Z. Assuming that the length of each information data block, i.e., the sequence of the encoded input bit I, is K, then Figure 1 and Figure 2 The length of the interleaver in is also K, but due to the tail bit encoding mechanism, the lengths of the three output sequences X, Y and Z of the sub-encoder are all K+T. Here, the length of the tail bit sequence corresponding to each output bit sequence is T (e.g. Figure 2 T=3).

[0027] One more thing to note is that before each block of data is Turbo-coded, Figure 3 The initial values ​​of the three registers in are set to 0.

[0028] Specifically, Figure 4 For example, in the tail bit generation scheme, when a sequence of bit I is input, that is, when the first K bits are input, the switch branch is closed with the upper branch for encoding, and three output bit sequences X, Y and Z of length K are generated respectively; then, the switch branch is switched to the lower branch and closed with the lower branch, and the sub-encoder continues to operate, generating three tail bit sequences of length T (here T=3) respectively, and appending them to the X, Y and Z sequences respectively. In the end, the lengths of the X, Y and Z sequences are all K+T, that is, they are all K+3 bits. The role of the tail bit is to finally return the grid of the sub-encoder to zero, which is conducive to the correct decoding of the receiver. Therefore, the tail bit sequence also carries useful information that cannot be ignored.

[0029] Specifically, the input information of the first decoder in this embodiment is the parity bit 1 soft information including the tail bit, L21 information and the first system bit soft information of length K+T; Among them, the check bit 1 soft information and the first system bit soft information are information for decoding transmitted by the system; the L21 information is external information with a length of K+T calculated by the L21 calculation module; The input information of the second bit sub-decoder in this embodiment is K+T including the soft information of the check bit 2 of the tail bit, the L12 information; and the second system bit soft information of the tail bit soft information after the information before the tail bit is interleaved and spliced; Among them, the check bit 2 soft information is the information for decoding transmitted by the system; the L12 information is the external information with a length of K+T calculated by the L12 calculation module; The solution of this embodiment also includes: a first interleaver and a splicer, which are used to generate second system bit soft information; The first interleaver is a K-bit interleaver; used to interleave the first K bits of the first system bit soft information, and output the interleaved data to the splicer; The splicer is used to splice the accessed interleaved data and the last T tail bit soft information of the first system bit soft information together to output the second system bit soft information.

[0030] Specifically, the L12 calculation module includes a first external information calculation module, a second interleaver and a first zero padding module; The first external information calculation module is used to access the first K data of the first LLR information with a length of K+T output by the first decoder, discard the last T data, use the first K data of the first LLR information for calculation, remove the influence of prior information and system bit soft information, and obtain pure external information with a length of K; The calculation method of the external information is: ; Among them, LLR ext1 is the external information output by the first external information calculation module in the current calculation, LLR 1 is the first LLR information output by the first decoder, LLR sys1 is the first systematic bit soft information of the first decoder input, LLR a1 is the external information input by the first decoder; The second interleaver is a K-bit interleaver, configured to interleave external data of length K output by the first external information calculation module; The first zero-padding module is used to perform a zero-padding operation with a length of T bits on the data output by the second interleaver, and output L12 information with a length of K+T as external information input by the second decoder.

[0031] Specifically, the L21 calculation module includes a second external information calculation module, a second deinterleaver and a second zero padding module; The second external information calculation module is used to access the first K data of the second LLR information with a length of K+T output by the second decoder, discard the last T data, use the first K data of the second LLR information for calculation, remove the influence of prior information and system bit soft information, so as to obtain pure external information with a length of K; The calculation method of the external information is: ; Among them, LLR ext2 is the external information output by the second external information calculation module in the current calculation, LLR 2 is the second LLR information output by the second decoder, LLR sys2 is the second systematic bit soft information of the second decoder input, LLR a2 is the external information input by the second decoder; The second deinterleaver is a K-bit deinterleaver, configured to deinterleave external data of length K output by the second external information calculation module; The second zero-padding module is used to perform a zero-padding operation with a length of T bits on the data output by the second deinterleaver, and output L21 information with a length of K+T as external information input by the first decoder.

[0032] The purpose of the calculation formula of the external information is to remove the influence of the prior information and the system bit soft information in the LLR information output by the first and second decoders, so as to obtain pure external information. This part of information will be passed to the next sub-decoder to improve the performance of the entire Turbo decoding process.

[0033] The decision output module includes a decision device and a first deinterleaver; The input end of the decision device is connected to the output end of the second decoder, accesses the second LLR information output by the second decoder, and is used to make a hard decision on the second LLR information that meets the condition for stopping iteration; and outputs the decision result to the input end of the first deinterleaver; The condition for stopping iteration is that the iteration reaches a preset maximum number of iterations; The first deinterleaver deinterleaves the decision result output by the decider and outputs a Turbo code decoding result.

[0034] In the decoding operation of the tail bit sub-decoder of the present embodiment, the input data length is K+T, so the operation cycles in the tail bit sub-decoder are K+T times, instead of K cycles of the traditional sub-decoder; Referring to the max-log-map decoding algorithm, the tail bit decoder needs to perform the following operations: 1) Initialize variables; variables include branch metric values, forward state metric values, backward state metric values, and output LLR values, all of which are initialized to zero vectors; 2) Perform backward iteration: perform K+T bit-by-bit calculations on the input information from back to front to obtain the branch metric gamma and the backward state metric beta; Among them, the initial value of the backward state metric value utilizes the grid 0 state information brought by the tail bit; 3) Perform forward iteration; calculate the input information bit by bit from front to back to obtain the branch metric value gamma and the forward state metric value alpha; Among them, the initial value of the forward state metric value uses the state information that the initial value of the encoder register is 0; 4) Calculate the output LLR information; The LLR information is calculated using the forward state metric alpha and the backward state metric beta.

[0035] During the operation, the calculation methods of the branch metric value gamma, the backward state metric value beta, the forward state metric value alpha and the LLR information may all refer to the existing calculation methods.

[0036] In summary, the Turbo code tail bit decoding device disclosed in this embodiment uses the tail bit information of the Turbo code for decoding, thereby improving the performance of the decoder; it is suitable for achieving reliable data transmission under low signal-to-noise ratio (SNR) conditions, and can gradually improve the decoding accuracy through iteration.

[0037] Embodiment 2 Another embodiment of the present invention discloses a decoding method using the tail bit decoding device of the Turbo code disclosed in the first embodiment, such as Figure 5 As shown, the following steps are included: Step S1, obtaining the first system bit soft information of the length K+T of the system input, the check bit 1 soft information and the check bit 2 soft information of the length K+T; initializing the L21 information and L12 information of the length K+T; setting the number of decoding iterations; Step S2, interleave the first K data of the first system bit soft information, and then concatenate them with the last T tail bit soft information of the first system bit soft information to obtain soft information with a length of K+T as the second system bit soft information; Step S3, executing the operation of the first decoder, inputting the check bit 1 soft information, L21 information and the first system bit soft information into the first decoder to calculate the first LLR information; inputting the first LLR information into the L12 calculation module to perform external information calculation, interleaving and zero padding, and then outputting the L12 information including the tail bit; Step S4, executing the operation of the second decoder, inputting the check bit 2 soft information, L12 information and the second system bit soft information into the second decoder to calculate the second LLR information; inputting the second LLR information into the L21 calculation module to perform external information calculation, deinterleaving and zero padding, and then outputting the L21 information including the tail bit; Step S5, jump to step S3, execute the operation of the first sub-decoder, and then execute the operation of the second sub-decoder, and perform iteratively until a preset maximum number of iterations is reached; Step S6: Perform a hard decision on the second LLR information output by the second decoder, and then perform a deinterleaving operation to output a Turbo code decoding result.

[0038] Specifically, the external information calculation method in the L12 calculation module and the L21 calculation module is: ; Among them, LLR ext1 , LLR ext2 They are the external information of L12 and L21 calculation modules in the current calculation, LLR 1 , LLR 2 The first and second LLR information output by the first and second decoders are LLR sys1 , LLR sys2 The first and second system bit soft information of the first and second decoders are input respectively, LLR a1 , LLR a2 It is the external information input by the first and second decoders.

[0039] The specific technical details and beneficial effects of this embodiment are the same as those described in Embodiment 1. Please refer to them for details and will not be described in detail here.

[0040] Embodiment 3 Another embodiment of the present invention discloses a Beidou receiver; the Beidou receiver receives the RDSS subsystem signal in the Beidou satellite navigation system BDS, and when performing Turbo code decoding, the tail bit decoding device of the Turbo code in the first embodiment is adopted, and the tail bit information of the Turbo code is used for decoding, thereby improving the decoding performance.

[0041] The specific technical details and beneficial effects of this embodiment are the same as those described in Embodiment 1. Please refer to them for details and will not be described in detail here.

[0042] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by any technician familiar with the technical field within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

Claims

1. A Turbo code tail bit decoding device, characterized in that: include: A first decoder, a second decoder, an L12 calculation module, an L21 calculation module and a decision output module; wherein, A first decoder, configured to calculate first LLR information according to input parity bit 1 soft information including tail bits, L21 information, and first system bit soft information; A second decoder, configured to calculate second LLR information according to the input check bit 2 soft information including tail bits, L12 information, and second system bit soft information; The second system bit soft information is the soft information of the tail bits obtained by interleaving the information before the tail bits of the first system bit soft information and then concatenating the tail bits; An L12 calculation module, configured to perform external information calculation, interleave and zero padding on the first LLR information, and then output L12 information including tail bits; An L21 calculation module, configured to perform external information calculation, deinterleave and zero padding on the second LLR information, and then output L21 information including tail bits; The decision output module is used to make a decision and deinterleave the second LLR information that meets the iteration stop condition, and output the Turbo code decoding result.

2. The tail bit decoding device of Turbo code according to claim 1, characterized in that: The first and second decoders are both tail bit sub-decoders; the length of the input information of the tail bit sub-decoder is K+T; K is the length of the encoded input data block, and T is the data length of the tail bit; the tail bit sub-decoder adopts decoding algorithms including log-map algorithm and max-log-map algorithm, and operates K+T times to obtain the LLR information of the decoded output; In the decoding process, the decoding operation of the first decoder is first performed to obtain L12 information; Input the L12 information into the second decoder for decoding operation to obtain the L21 information; perform the decoding operation of the first decoder again; and iterate in this manner until the maximum number of iterations is met.

3. The tail bit decoding device of Turbo code according to claim 2, characterized in that: Also includes: A first interleaver and splicer, used for generating second system bit soft information; The first interleaver is a K-bit interleaver; used to interleave the first K bits of the first system bit soft information, and output the interleaved data to the splicer; The splicer is used to splice the accessed interleaved data and the last T tail bit soft information of the first system bit soft information together to output the second system bit soft information.

4. The tail bit decoding device of Turbo code according to claim 2, characterized in that: The L12 calculation module includes a first external information calculation module, a second interleaver and a first zero padding module; The first external information calculation module is used to access the first K data of the first LLR information with a length of K+T output by the first decoder, discard the last T data, use the first K data of the first LLR information for calculation, remove the influence of prior information and system bit soft information, and obtain pure external information with a length of K; The second interleaver is a K-bit interleaver, configured to interleave external data of length K output by the first external information calculation module; The first zero-padding module is used to perform a zero-padding operation with a length of T bits on the data output by the second interleaver, and output L12 information with a length of K+T as external information input by the second decoder.

5. The tail bit decoding device of Turbo code according to claim 2, characterized in that: The L21 calculation module includes a second external information calculation module, a second deinterleaver and a second zero padding module; The second external information calculation module is used to access the first K data of the second LLR information with a length of K+T output by the second decoder, discard the last T data, use the first K data of the second LLR information for calculation, remove the influence of prior information and system bit soft information, so as to obtain pure external information with a length of K; The second deinterleaver is a K-bit deinterleaver, configured to deinterleave external data of length K output by the second external information calculation module; The second zero-padding module is used to perform a zero-padding operation with a length of T bits on the data output by the second deinterleaver, and output L21 information with a length of K+T as external information input by the first decoder.

6. The tail bit decoding device of Turbo code according to claim 4 or 5, characterized in that: The calculation method of the external information is: ； Among them, LLR ext1 , LLR ext2 are the external information calculated by the first and second external information calculation modules at the current time, LLR1 and LLR2 are the first and second LLR information output by the first and second decoders, respectively. sys1 , LLR sys2 The first and second system bit soft information of the first and second decoders are input respectively, LLR a1 , LLR a2 It is the external information input by the first and second decoders.

7. The tail bit decoding device of Turbo code according to claim 6, characterized in that: The decision output module includes a decision device and a first deinterleaver; The input end of the decision device is connected to the output end of the second decoder, accesses the second LLR information output by the second decoder, and is used to make a hard decision on the second LLR information that meets the condition for stopping iteration; and outputs the decision result to the input end of the first deinterleaver; The first deinterleaver deinterleaves the decision result output by the decider and outputs a Turbo code decoding result.

8. A decoding method based on the tail bit decoding device of a Turbo code according to any one of claims 1 to 7, characterized in that: The following steps are involved: Step S1, obtaining the first system bit soft information of the length K+T of the system input, the check bit 1 soft information and the check bit 2 soft information of the length K+T; initializing the L21 information and L12 information of the length K+T; setting the number of decoding iterations; Step S2, interleave the first K data of the first system bit soft information, and then concatenate them with the last T tail bit soft information of the first system bit soft information to obtain soft information with a length of K+T as the second system bit soft information; Step S3, executing the operation of the first decoder, inputting the check bit 1 soft information, L21 information and the first system bit soft information into the first decoder to calculate the first LLR information; Input the first LLR information into the L12 calculation module to perform external information calculation, interleaving and zero padding, and then output the L12 information including the tail bits; Step S4, executing the operation of the second decoder, inputting the check bit 2 soft information, L12 information and the second system bit soft information into the second decoder to calculate the second LLR information; Input the second LLR information into the L21 calculation module to perform external information calculation, deinterleaving and zero padding, and then output the L21 information including the tail bits; Step S5, jump to step S3, execute the operation of the first sub-decoder, and then execute the operation of the second sub-decoder, and perform iteratively until a preset maximum number of iterations is reached; Step S6: Perform a hard decision on the second LLR information output by the second decoder, and then perform a deinterleaving operation to output a Turbo code decoding result.

9. The decoding method according to claim 8, characterized in that: The external information calculation method in the L12 calculation module and the L21 calculation module is: ； Among them, LLR ext1 , LLR ext2 LLR1 and LLR2 are the external information calculated by the L12 and L21 calculation modules in the current calculation respectively. LLR1 and LLR2 are the first and second LLR information output by the first and second decoders respectively. sys1 , LLR sys2 The first and second system bit soft information of the first and second decoders are input respectively, LLR a1 , LLR a2 It is the external information input by the first and second decoders.

10. A Beidou receiver, characterized in that: The Beidou receiver receives the RDSS subsystem signal in the Beidou satellite navigation system BDS, and when performing Turbo code decoding, adopts the Turbo code tail bit decoding device as described in any one of claims 1-7, and uses the tail bit information of the Turbo code for decoding, thereby improving the decoding performance.

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