Signal Processing Method, Apparatus, Device, Storage Medium and Program Product

Abstract

The present application provides a signal processing method, apparatus, device, storage medium and program product, relating to the field of wireless technologies. Among them, the method includes: turning on a first state of a phase-locked loop (PLL) in a radio frequency transceiver chip, where the radio frequency transceiver chip is a radio frequency transceiver chip in a time division duplex (TDD) transceiver system, the radio frequency transceiver chip includes a transmit link and a receive link, the PLL is connected to the local oscillator of the transmit link and is also connected to the local oscillator of the receive link; obtaining a first direct current (DC) offset of the signal of the receive link; and in the case where the first DC offset is greater than or equal to a preset value, switching the state of the PLL from the first state to a target state, where in the target state, the DC offset of the signal of the receive link is less than the preset value. In the embodiments of the present application, by configuring multiple states of the PLL for the radio frequency transceiver chip, the influence of the DC offset is reduced by switching the state of the PLL, and resource occupation can be reduced.

Description

Technical Field

[0001] This application relates to the field of wireless technologies, and in particular, to a signal processing method, apparatus, device, storage medium, and program product. Background Art

[0002] Currently, fifth-generation mobile networks (5G) base stations typically adopt a zero-intermediate frequency receiver architecture, which has low receiver hardware complexity, small size, and reduced power consumption. However, the zero-intermediate frequency receiver architecture generates a large DC offset at zero intermediate frequency, which is likely to interfere with the baseband signal.

[0003] Regarding the DC offset problem generated by the zero-intermediate frequency architecture receiver, currently, it is usually calibrated in different gain modes, and then the calibration values are made into a look-up table and stored in a memory, or the input end of the low-noise amplifier is terminated with a virtual load and the DC offset is evaluated and stored in the memory. In this way, in the working mode or in the burst time slot, the stored DC offset is subtracted from the received digital baseband signal, or fed to the analog baseband circuit through a digital-to-analog converter (DAC) for subtraction, so as to reduce the influence of the DC offset.

[0004] However, the above method of subtracting signals requires a large amount of storage resources, resulting in a large operating cost. Summary of the Invention

[0005] Embodiments of this application provide a signal processing method, apparatus, device, storage medium, and program product to solve the problem of high operating cost of the device when dealing with the influence of DC offset.

[0006] To solve the above technical problem, this application is implemented as follows:

[0007] In a first aspect, embodiments of this application provide a signal processing method, and the method includes:

[0008] Turn on the first state of the phase-locked loop (PLL) in the radio frequency transceiver chip, where the radio frequency transceiver chip is a radio frequency transceiver chip in a time division duplex (TDD) transceiver system, the radio frequency transceiver chip includes a transmit link and a receive link, the PLL is connected to the local oscillator of the transmit link and is also connected to the local oscillator of the receive link, and the first state is one of at least two states of the PLL;

[0009] Obtain a first DC offset amount of the signal of the receive link;

[0010] When the first DC offset is greater than or equal to a preset value, switch the state of the PLL from the first state to a target state, where the target state is one of the at least two states other than the first state, and in the target state, the DC offset of the signal of the receiving link is less than the preset value.

[0011] Optionally, when the first DC offset is greater than or equal to a preset value, switching the state of the PLL from the first state to a target state includes:

[0012] When the first DC offset is greater than or equal to a preset value, switch the state of the PLL from the first state to the second state among the at least two states during a reception time slot, where the PLL generates local oscillator signals with the same frequency for the transmission link and the receiving link in the first state, and the second state is a state of interrupting the transmission of the local oscillator signal of the transmission link;

[0013] Obtain a second DC offset of the signal of the receiving link;

[0014] Determine the target state of the PLL according to the second DC offset.

[0015] Optionally, determining the target state of the PLL according to the second DC offset includes:

[0016] When the second DC offset is greater than or equal to the preset value, switch the state of the PLL from the second state to the third state among the at least two states, and in the third state, the PLL generates a first local oscillator signal for the transmission link and a second local oscillator signal for the receiving link, and the frequencies of the first local oscillator signal and the second local oscillator signal are different;

[0017] Filter the DC signal of the receiving link through a baseband filter until the DC signal offset of the receiving link is less than the preset value.

[0018] Optionally, after switching the state of the PLL from the second state to the third state among the at least two states, the method further includes:

[0019] Obtain the adjacent channel leakage ratio (ACLR) of the transmission link;

[0020] When the ACLR is less than a preset threshold value, switch the state of the PLL from the third state to the fourth state among the at least two states during a transmission time slot, where in the fourth state, the PLL interrupts the transmission of the local oscillator signal of the receiving link;

[0021] Filtering the DC signal of the receiving link through a baseband filter until the DC signal offset of the receiving link is less than the preset value, includes:

[0022] When the ACLR is greater than or equal to the preset threshold value, filtering the DC signal of the receiving link through a baseband filter until the DC signal offset of the receiving link is less than the preset value.

[0023] Optionally, determining the target state of the PLL according to the second DC offset includes:

[0024] When the second DC offset is less than the preset value, determining the second state as the target state of the PLL.

[0025] Optionally, before the first state of the PLL in the radio frequency transceiver chip is turned on, the method further includes:

[0026] Obtaining a first temperature value inside the radio frequency transceiver chip;

[0027] After the first state of the PLL in the radio frequency transceiver chip is turned on, the method further includes:

[0028] Obtaining a second temperature value inside the radio frequency transceiver chip;

[0029] When the first DC offset is less than the preset value and the difference between the second temperature value and the first temperature value is greater than a preset threshold, updating the temperature of the radio frequency transceiver chip from the first temperature value to the second temperature value, and detecting the DC offset of the signal of the receiving link based on the updated temperature value.

[0030] Optionally, the local oscillator of the transmitting link is connected to the reference signal transmitting device through the PLL, and the local oscillator of the receiving link is connected to the PLL through a first switch;

[0031] The local oscillator of the transmitting link is connected to the mixer of the transmitting link through a second switch;

[0032] The local oscillator of the receiving link is connected to the mixer of the receiving link through a third switch;

[0033] In the first state, the first switch, the second switch, and the third switch are all in the closed state;

[0034] In the second state of the PLL, the first switch and the third switch are both in the closed state, and the second switch is in the open state.

[0035] Optionally, the PLL includes a first PLL and a second PLL;

[0036] The first ends of the first PLL and the second PLL are connected to the reference signal transmitting device, and the frequencies of the signals output by the first PLL and the second PLL are different;

[0037] The second end of the first PLL is connected to the local oscillator of the transmitting link, the second end of the second PLL is connected to the local oscillator of the receiving link through a fourth switch, and the second ends of the first PLL and the second PLL are connected through the first switch;

[0038] In the first state, the first switch, the second switch, and the third switch are all in the closed state, and the fourth switch is in the open state;

[0039] In the second state of the PLL, the first switch and the third switch are both in the closed state, and the second switch and the fourth switch are in the open state;

[0040] In the third state of the PLL, the first switch is in the open state, and the second switch, the third switch, and the fourth switch are all in the closed state;

[0041] In the fourth state of the PLL, the first switch and the third switch are both in the open state, and the second switch and the fourth switch are both in the closed state.

[0042] In a second aspect, an embodiment of the present application provides a signal processing device, the device includes:

[0043] An enabling module, configured to enable the first state of the phase-locked loop PLL in the radio frequency transceiver chip, where the radio frequency transceiver chip is a radio frequency transceiver chip in a time division duplex TDD transceiver system, the radio frequency transceiver chip includes a transmitting link and a receiving link, the PLL is connected to the local oscillator of the transmitting link and is also connected to the local oscillator of the receiving link, and the first state is one of at least two states of the PLL;

[0044] A first obtaining module, configured to obtain a first DC offset of the signal of the receiving link;

[0045] A switching module, configured to switch the state of the PLL from the first state to a target state when the first DC offset is greater than or equal to a preset value, where the target state is one of the at least two states other than the first state, and in the target state, the DC offset of the signal of the receiving link is less than the preset value.

[0046] Optionally, when the first DC offset is greater than or equal to the preset value, the switching module includes:

[0047] A switching sub-module, configured to, when the first DC offset is greater than or equal to a preset value, switch the state of the PLL from the first state to a second state among the at least two states during a reception time slot, wherein the PLL generates local oscillator signals with the same frequency for the transmit link and the receive link in the first state, and the second state is a state of interrupting the transmission of the local oscillator signal of the transmit link;

[0048] An acquisition sub-module, configured to acquire a second DC offset of the signal of the receive link;

[0049] A determination sub-module, configured to determine a target state of the PLL according to the second DC offset.

[0050] Optionally, the determination sub-module includes:

[0051] A first switching unit, configured to, when the second DC offset is greater than or equal to the preset value, switch the state of the PLL from the second state to a third state among the at least two states. In the third state, the PLL generates a first local oscillator signal for the transmit link and a second local oscillator signal for the receive link, and the frequencies of the first local oscillator signal and the second local oscillator signal are different;

[0052] A processing unit, configured to filter the DC signal of the receive link through a baseband filter until the DC signal offset of the receive link is less than the preset value.

[0053] Optionally, the determination sub-module further includes:

[0054] An acquisition unit, configured to acquire an adjacent channel leakage ratio (ACLR) of the transmit link;

[0055] A second switching unit, configured to, when the ACLR is less than a preset threshold, switch the state of the PLL from the third state to a fourth state among the at least two states during a transmit time slot, wherein in the fourth state, the PLL interrupts the transmission of the local oscillator signal of the receive link;

[0056] The processing unit is specifically configured to:

[0057] When the ACLR is greater than or equal to the preset threshold, filter the DC signal of the receive link through a baseband filter until the DC signal offset of the receive link is less than the preset value.

[0058] Optionally, the determination sub-module is specifically configured to:

[0059] When the second DC offset is less than the preset value, determine the second state as the target state of the PLL.

[0060] Optionally, the device further includes:

[0061] A second acquisition module, configured to acquire a first temperature value inside the RF transceiver chip;

[0062] The device further includes:

[0063] A third acquisition module, configured to acquire a second temperature value inside the RF transceiver chip;

[0064] An update module, configured to update the temperature of the RF transceiver chip from the first temperature value to the second temperature value when the first DC offset is less than the preset value and the difference between the second temperature value and the first temperature value is greater than a preset threshold, and detect the DC offset of the signal of the receiving link based on the updated temperature value.

[0065] Optionally, the local oscillator of the transmitting link is connected to the reference signal transmitting device through the PLL, and the local oscillator of the receiving link is connected to the PLL through a first switch;

[0066] The local oscillator of the transmitting link is connected to the mixer of the transmitting link through a second switch;

[0067] The local oscillator of the receiving link is connected to the mixer of the receiving link through a third switch;

[0068] In the first state, the first switch, the second switch, and the third switch are all in a closed state;

[0069] In the second state of the PLL, the first switch and the third switch are both in a closed state, and the second switch is in an open state.

[0070] Optionally, the PLL includes a first PLL and a second PLL;

[0071] The first ends of the first PLL and the second PLL are connected to the reference signal transmitting device, and the frequencies of the signals output by the first PLL and the second PLL are different;

[0072] The second end of the first PLL is connected to the local oscillator of the transmitting link, the second end of the second PLL is connected to the local oscillator of the receiving link through a fourth switch, and the second ends of the first PLL and the second PLL are connected through the first switch;

[0073] In the first state, the first switch, the second switch, and the third switch are all in the closed state, and the fourth switch is in the open state;

[0074] In the second state of the PLL, the first switch and the third switch are both in the closed state, and the second switch and the fourth switch are in the open state;

[0075] In the third state of the PLL, the first switch is in the open state, and the second switch, the third switch, and the fourth switch are all in the closed state;

[0076] In the fourth state of the PLL, the first switch and the third switch are both in the open state, and the second switch and the fourth switch are both in the closed state.

[0077] In a third aspect, an embodiment of the present application provides an electronic device, including: a processor, a memory, and a program stored on the memory and executable on the processor. When the program is executed by the processor, the steps of the signal processing method described in the first aspect are implemented.

[0078] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the signal processing method described in the first aspect are implemented.

[0079] In a fifth aspect, a computer program product is provided, including computer instructions, which when executed by a processor implement the steps of the signal processing method as described in the first aspect.

[0080] In the embodiment of the present application, by configuring multiple states of the PLL for the radio frequency transceiver chip, the influence of DC offset is reduced by switching the state of the PLL, resource occupation can be reduced, and the operation cost of the device can be lowered. Description of the Drawings

[0081] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments of the present application will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0082] Figure 1 is a zero-IF receiver architecture diagram provided by an embodiment of the present application;

[0083] Figure 2 is one of the flowcharts of a signal processing method provided by an embodiment of the present application;

[0084] Figure 3 It is a schematic structural diagram of a radio frequency transceiver chip provided by an embodiment of the present application;

[0085] Figure 4 It is a schematic diagram of the principle of a phase-locked loop provided by an embodiment of the present application;

[0086] Figure 5 It is the second flowchart of a signal processing method provided by an embodiment of the present application;

[0087] Figure 6 It is a schematic structural diagram of a signal processing device provided by an embodiment of the present application;

[0088] Figure 7 It is a schematic structural diagram of a communication device provided by an embodiment of the present application. Detailed implementation manners

[0089] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts shall fall within the protection scope of the present application.

[0090] For the convenience of understanding the content of the present application, the related technologies will be described.

[0091] As Figure 1 shown, Figure 1 It is a zero-IF receiver architecture diagram adopted by a 5G base station. Its working principle is as follows: A radio frequency signal with a frequency of F sig is received through an antenna, filtered by a radio frequency filter, and then amplified by a low-noise amplifier; the radio frequency signal is mixed to the baseband through a mixer (the local oscillator frequency is F lo ,F lo =F sig ); at the baseband, the baseband signal is amplified to an appropriate power and the out-of-band useless signals are filtered through a baseband filter and a baseband amplifier, etc.; after being converted into a digital baseband signal by an analog-to-digital converter (ADC), it is processed by a digital module, and finally a digital signal is output.

[0092] Due to the low hardware complexity, small size of the zero-IF architecture receiver, power consumption is also reduced. However, it generates a large DC offset at zero-IF, causing interference to the baseband signal and thus affecting performance. Generally speaking, the generation of DC offset can be divided into three aspects. One is the self-mixing of the local oscillator signal, that is, due to reasons such as poor isolation between the RF and local oscillator ports of the mixer, the local oscillator leaks to the previous stage and is reflected to the input of the mixer, and is mixed with the local oscillator to generate; the second is the self-mixing of the transmit leakage, that is, the transmit signal will leak to the RF port of the mixer through the receive link, and due to reasons such as the limited isolation between the RF and local oscillator ports of the mixer, the transmit signal self-mixes; the third is the self-mixing of the strong interference signal, that is, the strong interference outside the system is transmitted to the RF port of the mixer, and due to reasons such as the limited isolation between the RF and local oscillator ports of the mixer, the DC offset is caused.

[0093] To address the above problem of DC offset, a high-pass filter can be added after the mixer to filter out the DC offset. However, its cut-off frequency is related to the capacitance value. If you want to filter out the DC offset, the capacitance value needs to be very large, and the larger the capacitance volume, which is not conducive to the high integration requirements of the device. Moreover, it will cause the switching speed between the transmit mode and the receive mode to slow down, and at the same time, it will introduce too large a time delay, resulting in a decrease in the sensitivity of the receive link. Most importantly, this method may even filter out the received signal.

[0094] The embodiments of the present application provide a signal processing method, device, equipment, storage medium and program product to solve the problem of high operating cost of the device when dealing with the influence of DC offset.

[0095] See Figure 2 , Figure 2 is a flowchart of a signal processing method provided by the embodiments of the present application. As Figure 2 shown, the method includes the following steps:

[0096] Step 201, turn on the first state of the phase-locked loop (PLL) in the RF transceiver chip, where the RF transceiver chip is the RF transceiver chip in a time division duplexing (TDD) transceiver system, the RF transceiver chip includes a transmit link and a receive link, the PLL is connected to the local oscillator of the transmit link and is also connected to the local oscillator of the receive link, and the first state is one of at least two states of the PLL;

[0097] Step 202, obtain the first DC offset amount of the signal of the receive link;

[0098] Step 203: When the first DC offset is greater than or equal to a preset value, switch the state of the PLL from the first state to a target state, where the target state is one of the at least two states other than the first state, and in the target state, the DC offset of the signal of the receiving link is less than the preset value.

[0099] As Figure 3 shown, a radio frequency transceiver chip (TRX) includes a transmitting link (the upper part of the figure) and a receiving link (the lower part of the figure). By configuring a phase-locked loop (PLL) to be connected to the local oscillators of both the transmitting link and the receiving link, and by configuring different states of the PLL, it is possible to switch the PLL between different states, thereby achieving the purpose of reducing or eliminating the DC offset.

[0100] Among them, the PLL is a closed-loop feedback control system, and its schematic diagram can be seen in Figure 4 shown. The PLL can lock the phase and frequency of the input signal and generate an output signal synchronized with the input signal.

[0101] The phase-locked loop mainly consists of a phase detector, a low-pass filter, a voltage-controlled oscillator, and a frequency divider. The working principle of the phase-locked loop is based on feedback control. When the frequency F ref / M of the input signal after frequency division is different from the frequency F out / N of the output signal of the voltage-controlled oscillator after frequency division through the feedback loop, the phase detector will detect the phase difference and generate an error signal. This error signal is processed by the filter and used to adjust the frequency of the voltage-controlled oscillator until the frequencies and phases of F ref / M and F out / N are the same. At this time, the PLL enters the locked state, and finally an output signal with a stable frequency of F out =F ref ×N / M is achieved.

[0102] Based on the above principle, by connecting the PLL to the reference signal transmitting device, a signal with a corresponding frequency can be output by the PLL.

[0103] At the same time, in a TDD transceiver system, at least two states of the PLL configuration are stored in the register. For example, the following four states of the configuration switch, and the four switch states correspond to the four states of the PLL one by one.

[0104] Switch state 1: S1 is connected, S2 is connected, S3 is connected, S4 is disconnected;

[0105] Switch state 2: S1 is connected, S2 is disconnected, S3 is connected, S4 is disconnected;

[0106] Switch state 3: S1 is disconnected, S2 is connected, S3 is connected, S4 is connected;

[0107] Switch state 4: S1 is off, S2 is on, S3 is off, S4 is on.

[0108] By adjusting the switch state, the switching of the PLL state is achieved.

[0109] In at least two states of the PLL, a single state or a coordinated switch between multiple states can be used to reduce the DC offset of the signal in the receiving link.

[0110] The above at least two states of the PLL may include at least two of the following states:

[0111] The PLL generates a local oscillator signal with the same frequency for both the transmitting link and the receiving link;

[0112] The PLL generates a local oscillator signal with different frequencies for the transmitting link and the receiving link;

[0113] The PLL only generates a local oscillator signal for the receiving link;

[0114] The PLL only generates a local oscillator signal for the transmitting link.

[0115] When the PLL is in the first state, if the DC offset of the receiving link is greater than the preset value, the PLL can be switched to the second state. If, in the second state, the DC offset of the receiving link is less than the preset value, then the second state is the target state. If, in the second state, the DC offset of the receiving link is still greater than the preset value, it can be switched to the third state and / or the fourth state until the DC offset of the receiving link is less than the preset value, and the current state of the PLL is the target state.

[0116] The above multiple states of the PLL can be achieved by means of a switch combination as Figure 3 shown, and in addition, it can also be achieved by other means. For example, by configuring different PLLs to be connected to the transmitting link and the receiving link respectively, and each PLL corresponds to one of the above at least two states, and the state switching of the PLL is achieved by controlling the working state of each PLL.

[0117] Optionally, when the first DC offset is greater than or equal to the preset value, switching the state of the PLL from the first state to the target state includes:

[0118] When the first DC offset is greater than or equal to a preset value, the state of the PLL is switched from the first state to the second state among the at least two states during a reception time slot. Wherein, the PLL generates local oscillator signals with the same frequency for the transmit link and the receive link in the first state, and the second state is a state in which the local oscillator signal of the transmit link is interrupted from being transmitted;

[0119] Obtain a second DC offset of the signal of the receive link;

[0120] Determine the target state of the PLL according to the second DC offset.

[0121] When the PLL is in the first state, if the DC offset of the signal of the receive link is greater than the preset value, considering that in a TDD transceiver system, the transmit leakage self-mixing generated by the transmit local oscillator has a greater impact on the chip performance. In the TDD transceiver system, during the reception time slot, the local oscillator signal of the transmit link is turned off, that is, the state of the PLL is switched to the second state during the reception time slot, so that the receive link reduces the interference caused by the transmit signal leakage during the reception time slot.

[0122] As Figure 3 shown, when the PLL is in the first state, the first switch (S1), the second switch (S2), and the third switch (S3) are in the closed state, and the fourth switch (S4) is in the open state. The PLL1 generates local oscillator signals with the same power for the transmit link and the receive link; when in the second state, S1 and S3 are in the connected state, and S2 and S4 are in the open state, that is, during the reception time slot, the transmission of the local oscillator signal of the transmit link is interrupted, and the PLL1 only generates a local oscillator signal for the receive link.

[0123] By the above method, it is possible to reduce the transmit leakage generated by the transmit local oscillator and reduce the DC offset of the receive link by switching the state of the PLL during the reception time slot.

[0124] Optionally, the determining the target state of the PLL according to the second DC offset includes:

[0125] When the second DC offset is greater than or equal to the preset value, the state of the PLL is switched from the second state to the third state among the at least two states. In the third state, the PLL generates a first local oscillator signal for the transmit link and a second local oscillator signal for the receive link, and the frequencies of the first local oscillator signal and the second local oscillator signal are different;

[0126] Filter the DC signal of the receive link through a baseband filter until the DC signal offset of the receive link is less than the preset value.

[0127] When the PLL is in the second state, if the DC offset of the receiving link is still greater than or equal to the preset value, it indicates that there is still self-mixing of the received local oscillator signal or self-mixing of strong interference signals. Then, the mixer of the receiving link of the radio frequency transceiver chip adopts the baseband frequency translation function, and the PLL generates local oscillator signals with different frequencies for the transmitting link and the receiving link.

[0128] As Figure 3 shown, in the third state, S1 is disconnected, S2 is connected, S3 is connected, S4 is connected, and PLL1 and PLL2 respectively generate local oscillator signals with different frequencies for the transmitting link and the receiving link.

[0129] In the third state, when the signal of the receiving link is mixed to the frequency difference between the first local oscillator signal and the second local oscillator signal, the DC is filtered by the baseband filter until the DC signal offset of the received signal is less than the preset value.

[0130] By the above method, the DC offset generated by self-mixing of the received local oscillator signal or self-mixing of strong interference signals can be reduced.

[0131] Optionally, after switching the state of the PLL from the second state to the third state among the at least two states, the method further includes:

[0132] Obtaining the adjacent channel leakage ratio (ACLR) of the transmitting link;

[0133] When the ACLR is less than the preset threshold, switch the state of the PLL from the third state to the fourth state among the at least two states during the transmission time slot, where in the fourth state, the PLL interrupts the transmission of the local oscillator signal of the receiving link;

[0134] The filtering the DC signal of the receiving link by the baseband filter until the DC signal offset of the receiving link is less than the preset value includes:

[0135] When the ACLR is greater than or equal to the preset threshold, filter the DC signal of the receiving link by the baseband filter until the DC signal offset of the receiving link is less than the preset value.

[0136] When the PLL is in the third state, obtain the ACLR of the transmitting link. If the ACLR is less than the preset threshold, it means that the spectrum of the transmitting link is expanded, resulting in the deterioration of the ACLR value. Then, interrupt the transmission of the local oscillator signal of the receiving link during the transmission time slot, and filter the DC signal of the receiving link by the baseband filter.

[0137] If the ACLR is greater than a preset threshold value, it indicates that the spectrum of the transmitting link has not deteriorated the value of the ACLR. Then, the DC signal of the receiving link is filtered out by the baseband filter.

[0138] Through the above method, the interference to the transmitted signal can be reduced and the signal quality can be improved.

[0139] Optionally, determining the target state of the PLL according to the second DC offset includes:

[0140] When the second DC offset is less than the preset value, the second state is determined as the target state of the PLL.

[0141] When the PLL switches from the first state to the second state, if the DC offset of the receiving link is less than the preset value, the second state is determined as the target state of the PLL.

[0142] Optionally, before the first state of the PLL in the radio frequency transceiver chip is turned on, the method further includes:

[0143] Obtain the first temperature value inside the radio frequency transceiver chip;

[0144] After the first state of the PLL in the radio frequency transceiver chip is turned on, the method further includes:

[0145] Obtain the second temperature value inside the radio frequency transceiver chip;

[0146] When the first DC offset is less than the preset value and the difference between the second temperature value and the first temperature value is greater than a preset threshold, update the temperature of the radio frequency transceiver chip from the first temperature value to the second temperature value, and detect the DC offset of the signal of the receiving link based on the updated temperature value.

[0147] Since the performance of the radio frequency transceiver chip may be affected by the change of the system temperature, obtain the first temperature value inside the chip before turning on the first state of the PLL, obtain the second temperature value inside the chip after turning on the first state. When the first DC offset is less than the preset value, if the temperature change inside the chip is large (greater than the preset threshold), then update the temperature value, and re-detect the DC offset of the signal of the receiving link based on the updated temperature value, and judge whether the DC offset is greater than the preset value based on the re-detected DC offset.

[0148] Similarly, before the PLL switches to the second state, the first temperature value inside the chip can be obtained, and after switching to the second state, the second temperature value inside the chip can be obtained. If the temperature change is large, the DC offset of the signal of the receiving link can be detected again based on the changed temperature.

[0149] In the above manner, the influence of temperature change on the detection result of the DC offset can be reduced, and the detection accuracy of the DC offset can be improved.

[0150] Optionally, the local oscillator of the transmitting link is connected to the reference signal transmitting device through the PLL, and the local oscillator of the receiving link is connected to the PLL through a first switch;

[0151] The local oscillator of the transmitting link is connected to the mixer of the transmitting link through a second switch;

[0152] The local oscillator of the receiving link is connected to the mixer of the receiving link through a third switch;

[0153] In the first state, the first switch, the second switch, and the third switch are all in the closed state;

[0154] In the second state of the PLL, the first switch and the third switch are both in the closed state, and the second switch is in the open state.

[0155] As Figure 3 shown, the PLL is connected to the reference signal transmitting device and the local oscillator of the transmitting link. The PLL is connected to the local oscillator of the receiving link through a first switch S1.

[0156] The local oscillator of the transmitting link is connected to the mixer of the transmitting link through a second switch S2, and the local oscillator of the receiving link is connected to the mixer of the receiving link through a third switch S3.

[0157] Based on the above structure, when the PLL is in the first state, the first switch S1, the second switch S2, and the third switch S3 are closed, and the reference signal transmitting device transmits local oscillator signals with the same power for the transmitting link and the receiving link through the PLL1.

[0158] When the PLL is in the second state, the first switch S1 and the third switch S3 are closed, the second switch S2 is open, and the PLL1 generates a local oscillator signal for the receiving link.

[0159] By closing and opening multiple switches to achieve the switching of the PLL state, the DC offset of the receiving link can be reduced, the resource occupation can be reduced, and the operation cost of the device can be reduced.

[0160] Optionally, the PLL includes a first PLL and a second PLL;

[0161] The first ends of the first PLL and the second PLL are connected to the reference signal transmitting device, and the frequencies of the signals output by the first PLL and the second PLL are different;

[0162] The second end of the first PLL is connected to the local oscillator of the transmitting link. The second end of the second PLL is connected to the local oscillator of the receiving link through a fourth switch. The second ends of the first PLL and the second PLL are connected through the first switch;

[0163] In the first state, the first switch, the second switch, and the third switch are all in the closed state, and the fourth switch is in the open state;

[0164] In the second state of the PLL, the first switch and the third switch are both in the closed state, and the second switch and the fourth switch are in the open state;

[0165] In the third state of the PLL, the first switch is in the open state, and the second switch, the third switch, and the fourth switch are all in the closed state;

[0166] In the fourth state of the PLL, the first switch and the third switch are both in the open state, and the second switch and the fourth switch are both in the closed state.

[0167] As Figure 3 shown, the first PLL and the second PLL are respectively connected to the reference signal transmitting device. The first PLL and the second PLL process the signals transmitted by the reference signal transmitting device to obtain a first local oscillator signal and a second local oscillator signal with different frequencies.

[0168] In the first state, the first switch S1, the second switch S2, and the third switch S3 are all closed, and the fourth switch S4 is open. PLL1 generates local oscillator signals with the same frequency for the transmitting link and the receiving link;

[0169] In the second state, the first switch S1 and the third switch S3 are both closed, and the second switch S2 and the fourth switch S4 are open. PLL1 generates a local oscillator signal only for the receiving link;

[0170] In the third state, the first switch S1 is open, and the second switch S2, the third switch S3, and the fourth switch S4 are closed. Both PLL1 and PLLL2 are in the on state. PLL1 and PLL2 respectively generate local oscillator signals with different frequencies for the transmitting link and the receiving link;

[0171] In the fourth state, the first switch S1 and the third switch S3 are open, and the second switch S2 and the fourth switch S4 are closed. PLL1 generates a local oscillator signal only for the transmitting link.

[0172] By closing and opening multiple switches to achieve the switching of the PLL state, it is possible to reduce the DC offset of the receiving link, and can reduce the resource occupancy and the operating cost of the device.

[0173] In the embodiments of the present application, by switching the state of the PLL, the DC offset introduced in the zero-IF architecture can be reduced or eliminated, which helps to improve the performance of the system.

[0174] For the convenience of understanding this embodiment, the following takes the accompanying drawings as an example to illustrate the specific implementation manners of the present application.

[0175] As Figure 5 shown, the signal processing method includes the following steps:

[0176] Step 1: In the TDD transceiver system, store four states of the PLL configuration in the RF chip register: Switch state 1: S1 connected, S2 connected, S3 connected, S4 disconnected, address bits are 1011 (bits 1-4); Switch state 2: S1 connected, S2 disconnected, S3 connected, S4 disconnected, address bits are 1001 (bits 5-8); Switch state 3: S1 disconnected, S2 connected, S3 connected, S4 connected, address bits are 0111 (bits 9-12); Switch state 4: S1 disconnected, S2 connected, S3 disconnected, S4 connected, address bits are 0110 (bits 13-16).

[0177] Step 2: Set the clock reference signal frequency to F ref , set the RF signal frequency to F sig . The temperature sensor of the RF transceiver chip records the temperature as T at this time. The microcontroller (Microcontroller Unit, MCU) reads the address bits of switch state 1 in the memory, and the switch state at this time is switch state 1. Start PLL1 to generate a local oscillator signal with a frequency of F lo for the transmit link and the receive link respectively. In the zero-IF architecture, F sig =F lo .

[0178] Step 3: According to the digital signal processing result of the baseband, the chip internally determines whether a DC offset occurs in the receive link (that is, the DC offset amount is greater than the preset value).

[0179] If no DC offset occurs, it is necessary to consider that the performance of the RF transceiver chip may be affected by the system temperature change. That is, according to the temperature displayed by the temperature sensor at this time, the chip internally determines whether the temperature changes. If the temperature remains unchanged, the entire process ends. If the temperature changes, update T to the current temperature of the chip and re-determine whether a DC offset occurs in the receive link, and loop the process;

[0180] If there is a DC offset, considering in the TDD transceiver system, the self-mixing of the transmit leakage generated by the transmit local oscillator has a greater impact on the chip performance. Therefore, in the receive time slot, first turn off the local oscillator of the transmit link. The MCU of the RF transceiver chip reads the address bit of switch state 2 in the memory, and the switch state at this time is switch state 2.

[0181] Step 4: According to the digital signal processing of the baseband, the chip internally determines whether the DC offset is eliminated (i.e., the DC offset amount is less than the preset value).

[0182] If the DC offset is eliminated, the corresponding self-mixing of the transmit leakage is eliminated. Then, according to the temperature displayed by the temperature sensor at this time, the chip internally determines whether the temperature changes. If the temperature remains unchanged, the entire process ends; if the temperature changes, update T to the current temperature of the chip, and re-determine whether there is a DC offset in the receive link, and loop the process.

[0183] If the DC offset is not eliminated, it means that there is still self-mixing of the receive local oscillator signal or strong interference signal self-mixing. Then, the mixer in the receive link of the RF transceiver chip uses the baseband frequency translation function. PLL1 still generates the transmit local oscillator with a frequency of F lo and then start PLL2 to generate the receive local oscillator with a frequency of F lo1 where F sig -F lo1 =F if The MCU of the RF transceiver chip reads the address bit of switch state 3 in the memory, and the switch state at this time is switch state 3.

[0184] Step 5: According to the signal output by the mixer in the transmit link, the chip internally determines whether the spectrum in the transmit link is expanded, resulting in the deterioration of the adjacent channel leakage ratio (ACLR). If the value of ACLR is not lower than the threshold Th, then execute Step 6; if the value of ACLR is lower than the threshold, turn off the local oscillator of the receive link in the transmit time slot. The MCU of the RF transceiver chip reads the address bit of switch state 4 in the memory, and the switch state at this time is switch state 4.

[0185] Step 6: When the received signal is mixed to F if , filter out the DC through the baseband filter. At this time, the self-mixing of the local oscillator signal and the strong interference signal is eliminated, and continue to the next step to enter the temperature judgment unit. According to the temperature displayed by the temperature sensor at this time, the chip internally determines whether the temperature changes. If the temperature remains unchanged, the entire process ends; if the temperature changes, update T to the current temperature of the chip, and re-determine whether there is a DC offset in the receive link, and loop the process.

[0186] The above process of the present application is described below through two specific embodiments.

[0187] Example 1: Only transmit mixing self-leakage

[0188] Based on Figure 5 the above corresponding process, the signal processing method of this embodiment includes:

[0189] The same as steps 1 and 2 above;

[0190] Step 3: According to the digital signal processing of the baseband, the chip internally determines that there is a DC offset in the receiving link. During the receiving time slot, the local oscillator of the transmitting link is turned off. The MCU of the radio frequency transceiver chip reads the address bit of switch state 2 in the memory, and the switch state at this time is switch state 2;

[0191] Step 4: According to the digital signal processing of the baseband, the chip internally determines that the DC offset has been eliminated. Then, according to the temperature displayed by the temperature sensor at this time, the chip internally determines whether the temperature has changed. If the temperature remains unchanged, the entire process ends; if the temperature changes, update T to the temperature of the chip at this time and jump back to the first judgment unit for a loop process.

[0192] Example 2: There are simultaneously transmit mixing self-leakage, local oscillator signal self-mixing, and strong interference signal self-mixing

[0193] Based on Figure 5 the above corresponding process, the signal processing method of this embodiment includes:

[0194] The same as steps 1 and 2 above;

[0195] Step 3: According to the digital signal processing of the baseband, the chip internally determines that there is a DC offset in the receiving link. During the receiving time slot, the local oscillator of the transmitting link is turned off. The MCU of the radio frequency transceiver chip reads the address bit of switch state 2 in the memory, and the switch state at this time is switch state 2;

[0196] Step 4: According to the digital signal processing of the baseband, the chip internally determines that the DC offset has not been eliminated. The mixer in the receiving link of the radio frequency transceiver chip uses the baseband frequency shift function. PLL1 still generates the transmit local oscillator with a frequency of F lo Then start PLL2 to generate the receive local oscillator with a frequency of F lo1 F sig -F lo1 =F if The MCU of the radio frequency transceiver chip reads the address bit of switch state 3 in the memory, and the switch state at this time is switch state 3;

[0197] Step 5: Based on the signal output by the transmitter-link mixer, the chip internally determines whether the spectrum in the transmitter link has expanded, causing the value of ACLR to deteriorate. If the value of ACLR is not lower than the threshold Th, then proceed to Step 6; if it is lower than the threshold Th, during the transmission time slot, turn off the local oscillator of the receiver link, and the MCU of the RF transceiver chip reads the address bit of the switch state 4 in the memory. At this time, the switch state is the switch state 4.

[0198] Step 6: When the received signal is mixed to F if , filter out the direct current through the baseband filter. At this time, the self-mixing of the local oscillator signal and the strong interference signal is eliminated, and continue to the next step to enter the temperature judgment unit. According to the temperature displayed by the temperature sensor at this time, the chip internally determines whether the temperature has changed. If the temperature remains unchanged, then end the entire process; if the temperature has changed, update T to the current temperature of the chip and jump back to the first judgment unit for a loop process.

[0199] The RF transceiver chip is responsible for the high-speed conversion between digital and analog signals in a 5G base station and is a key device in 5G network equipment. In the embodiments of this application, by configuring multiple states of the PLL for the RF transceiver chip, the influence of local oscillator offset is reduced or eliminated by switching the state of the PLL. The above method occupies less resources and is more conducive to the integration of the whole machine.

[0200] See Figure 6 , Figure 6 is a schematic structural diagram of a signal processing device provided by the embodiments of this application. As Figure 6 shown, the signal processing device 600 includes:

[0201] An enabling module 601, configured to enable the first state of the phase-locked loop PLL in the RF transceiver chip, where the RF transceiver chip is the RF transceiver chip in a time-division duplex TDD transceiver system. The RF transceiver chip includes a transmitter link and a receiver link. The PLL is connected to the local oscillator of the transmitter link and is also connected to the local oscillator of the receiver link. The first state is one of at least two states of the PLL.

[0202] A first acquisition module 602, configured to acquire the first direct current offset of the signal of the receiver link.

[0203] A switching module 603, configured to switch the state of the PLL from the first state to a target state when the first direct current offset is greater than or equal to a preset value, where the target state is one of the at least two states other than the first state. In the target state, the direct current offset of the signal of the receiver link is less than the preset value.

[0204] Optionally, when the first DC offset is greater than or equal to a preset value, the switching module includes:

[0205] A switching sub-module, configured to switch the state of the PLL from the first state to the second state among the at least two states during a reception time slot when the first DC offset is greater than or equal to the preset value, where the PLL generates local oscillator signals with the same frequency for the transmit link and the receive link in the first state, and the second state is a state in which the local oscillator signal of the transmit link is interrupted from being transmitted;

[0206] An acquisition sub-module, configured to acquire a second DC offset of the signal of the receive link;

[0207] A determination sub-module, configured to determine a target state of the PLL according to the second DC offset.

[0208] Optionally, the determination sub-module includes:

[0209] A first switching unit, configured to switch the state of the PLL from the second state to the third state among the at least two states when the second DC offset is greater than or equal to the preset value. In the third state, the PLL generates a first local oscillator signal for the transmit link and a second local oscillator signal for the receive link, and the frequencies of the first local oscillator signal and the second local oscillator signal are different;

[0210] A processing unit, configured to filter the DC signal of the receive link through a baseband filter until the DC signal offset of the receive link is less than the preset value.

[0211] Optionally, the determination sub-module further includes:

[0212] An acquisition unit, configured to acquire an adjacent channel leakage ratio (ACLR) of the transmit link;

[0213] A second switching unit, configured to switch the state of the PLL from the third state to the fourth state among the at least two states during a transmit time slot when the ACLR is less than a preset threshold value. In the fourth state, the PLL interrupts the transmission of the local oscillator signal of the receive link;

[0214] The processing unit is specifically configured to:

[0215] When the ACLR is greater than or equal to the preset threshold value, filter the DC signal of the receive link through a baseband filter until the DC signal offset of the receive link is less than the preset value.

[0216] Optionally, the determining sub-module is specifically configured to:

[0217] When the second DC offset is less than the preset value, determine the second state as the target state of the PLL.

[0218] Optionally, the apparatus further includes:

[0219] A second acquisition module, configured to acquire a first temperature value inside the RF transceiver chip;

[0220] The apparatus further includes:

[0221] A third acquisition module, configured to acquire a second temperature value inside the RF transceiver chip;

[0222] An update module, configured to update the temperature of the RF transceiver chip from the first temperature value to the second temperature value when the first DC offset is less than the preset value and the difference between the second temperature value and the first temperature value is greater than a preset threshold, and detect the DC offset of the signal of the receiving link based on the updated temperature value.

[0223] Optionally, the local oscillator of the transmitting link is connected to the reference signal transmitting device through the PLL, and the local oscillator of the receiving link is connected to the PLL through a first switch;

[0224] The local oscillator of the transmitting link is connected to the mixer of the transmitting link through a second switch;

[0225] The local oscillator of the receiving link is connected to the mixer of the receiving link through a third switch;

[0226] In the first state, the first switch, the second switch, and the third switch are all in a closed state;

[0227] In the second state of the PLL, the first switch and the third switch are both in a closed state, and the second switch is in an open state.

[0228] Optionally, the PLL includes a first PLL and a second PLL;

[0229] The first ends of the first PLL and the second PLL are connected to the reference signal transmitting device, and the frequencies of the signals output by the first PLL and the second PLL are different;

[0230] The second end of the first PLL is connected to the local oscillator of the transmitting link, the second end of the second PLL is connected to the local oscillator of the receiving link through a fourth switch, and the second ends of the first PLL and the second PLL are connected through the first switch;

[0231] In the first state, the first switch, the second switch and the third switch are all in a closed state, and the fourth switch is in an open state;

[0232] In the second state of the PLL, the first switch and the third switch are both in a closed state, and the second switch and the fourth switch are in an open state;

[0233] In a third state of the PLL, the first switch is in an open state, and the second switch, the third switch, and the fourth switch are all in a closed state;

[0234] In a fourth state of the PLL, the first switch and the third switch are both in an open state, and the second switch and the fourth switch are both in a closed state.

[0235] The signal processing device can realize Figure 2 The various processes implemented in the method embodiment can achieve the same technical effect, and to avoid repetition, they will not be described here.

[0236] It should be noted that the electronic device provided in the embodiments of the present application is a device capable of executing the above-mentioned signal processing method. Therefore, all implementation methods in the above-mentioned signal processing method embodiments are applicable to the electronic device and can achieve the same or similar beneficial effects. To avoid repetition, this embodiment will not be described in detail.

[0237] The embodiment of the present application also provides a communication device. Since the principle of solving the problem of the communication device is similar to the signal processing method in the embodiment of the present application, the implementation of the communication device can refer to the implementation of the method, and the repeated parts will not be repeated. Figure 7 As shown, the communication device of the embodiment of the present application includes: a processor 700, which is used to read the program in the memory 720 and perform the following process:

[0238] Turning on a first state of a phase-locked loop (PLL) in a radio frequency transceiver chip, wherein the radio frequency transceiver chip is a radio frequency transceiver chip in a time division duplex (TDD) transceiver system, the radio frequency transceiver chip includes a transmit link and a receive link, the PLL is connected to a local oscillator of the transmit link and to a local oscillator of the receive link, and the first state is one of at least two states of the PLL;

[0239] Acquire a first DC offset of a signal of the receiving link;

[0240] When the first DC offset is greater than or equal to a preset value, switch the state of the PLL from the first state to a target state, where the target state is one of the at least two states other than the first state, and in the target state, the DC offset of the signal of the receiving link is less than the preset value.

[0241] Wherein, in Figure 7 In, the bus architecture may include any number of interconnected buses and bridges, specifically various circuits of one or more processors represented by processor 700 and memories represented by memories 720 are linked together. The bus architecture may also link together various other circuits such as peripheral devices, voltage regulators, and power management circuits, which are well known in the art and thus will not be further described herein. The bus interface provides an interface. The transceiver 710 may be a plurality of elements, that is, including a transmitter and a transceiver, and provides a unit for communicating with various other devices on the transmission medium. The processor 700 is responsible for managing the bus architecture and general processing, and the memory 720 may store data used by the processor 700 when performing operations.

[0242] Optionally, the processor 700 is further configured to read a program in the memory 720 and execute switching the state of the PLL from the first state to the target state when the first DC offset is greater than or equal to the preset value, including:

[0243] When the first DC offset is greater than or equal to the preset value, switch the state of the PLL from the first state to the second state among the at least two states during a reception time slot, where the PLL generates local oscillator signals with the same frequency for the transmission link and the receiving link in the first state, and the second state is a state of interrupting the transmission of the local oscillator signal of the transmission link;

[0244] Obtain a second DC offset of the signal of the receiving link;

[0245] Determine the target state of the PLL according to the second DC offset.

[0246] Optionally, the processor 700 is further configured to read a program in the memory 720 and execute determining the target state of the PLL according to the second DC offset, including:

[0247] When the second DC offset is greater than or equal to the preset value, switch the state of the PLL from the second state to the third state among the at least two states, and in the third state, the PLL generates a first local oscillator signal for the transmission link and a second local oscillator signal for the receiving link, and the frequencies of the first local oscillator signal and the second local oscillator signal are different;

[0248] Filter the DC signal of the receiving link through a baseband filter until the DC signal offset of the receiving link is less than the preset value.

[0249] Optionally, the processor 700 is further configured to read the program in the memory 720 and execute the following steps:

[0250] Obtain the adjacent channel leakage ratio (ACLR) of the transmitting link;

[0251] When the ACLR is less than a preset threshold, switch the state of the PLL from the third state to the fourth state among the at least two states during the transmission time slot, wherein in the fourth state, the PLL interrupts the transmission of the local oscillator signal of the receiving link;

[0252] The filtering the DC signal of the receiving link through a baseband filter until the DC signal offset of the receiving link is less than the preset value includes:

[0253] When the ACLR is greater than or equal to the preset threshold, filter the DC signal of the receiving link through a baseband filter until the DC signal offset of the receiving link is less than the preset value.

[0254] Optionally, the processor 700 is further configured to read the program in the memory 720 and execute determining the target state of the PLL according to the second DC offset, including:

[0255] When the second DC offset is less than the preset value, determine the second state as the target state of the PLL.

[0256] Optionally, the processor 700 is further configured to read the program in the memory 720 and execute the following steps:

[0257] Obtain the first temperature value inside the radio frequency transceiver chip;

[0258] Obtain the second temperature value inside the radio frequency transceiver chip;

[0259] When the first DC offset is less than the preset value and the difference between the second temperature value and the first temperature value is greater than a preset threshold, update the temperature of the radio frequency transceiver chip from the first temperature value to the second temperature value, and detect the DC offset of the signal of the receiving link based on the updated temperature value.

[0260] Optionally, the local oscillator of the transmitting link is connected to the reference signal transmitting device through the PLL, and the local oscillator of the receiving link is connected to the PLL through a first switch;

[0261] The local oscillator of the transmitting link is connected to the mixer of the transmitting link through a second switch;

[0262] The local oscillator of the receiving link is connected to the mixer of the receiving link through a third switch;

[0263] In the first state, the first switch, the second switch, and the third switch are all in the closed state;

[0264] In the second state of the PLL, the first switch and the third switch are both in the closed state, and the second switch is in the open state.

[0265] Optionally, the PLL includes a first PLL and a second PLL;

[0266] The first ends of the first PLL and the second PLL are connected to the reference signal transmitting device, and the frequencies of the signals output by the first PLL and the second PLL are different;

[0267] The second end of the first PLL is connected to the local oscillator of the transmitting link, the second end of the second PLL is connected to the local oscillator of the receiving link through a fourth switch, and the second ends of the first PLL and the second PLL are connected through the first switch;

[0268] In the first state, the first switch, the second switch, and the third switch are all in the closed state, and the fourth switch is in the open state;

[0269] In the second state of the PLL, the first switch and the third switch are both in the closed state, and the second switch and the fourth switch are in the open state;

[0270] In the third state of the PLL, the first switch is in the open state, and the second switch, the third switch, and the fourth switch are all in the closed state;

[0271] In the fourth state of the PLL, the first switch and the third switch are both in the open state, and the second switch and the fourth switch are both in the closed state.

[0272] The communication device provided by the embodiments of the present application can execute the above method embodiments, and its implementation principle and technical effects are similar, which will not be elaborated here in this embodiment.

[0273] The embodiments of the present application further provide a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, it implements each process of the above signal processing method embodiment and can achieve the same technical effect. To avoid repetition, it will not be elaborated here. Among them, the computer-readable storage medium includes, for example, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disc, etc.

[0274] The embodiments of the present application further provide a computer program product, including computer instructions. When the computer instructions are executed by a processor, they implement each process of the above Figure 2 shown method embodiment and can achieve the same technical effect. To avoid repetition, it will not be elaborated here.

[0275] It should be noted that in this article, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or further includes elements inherent to such process, method, article or device. Without more limitations, an element defined by the statement "including one..." does not exclude the existence of another identical element in the process, method, article or device including that element.

[0276] Through the description of the above embodiments, those skilled in the art can clearly understand that the above embodiment method can be implemented by means of software plus a necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. The computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disc), and includes several instructions for causing a terminal (which can be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) to execute the methods described in each embodiment of the present application.

[0277] The embodiments of the present application have been described above in conjunction with the accompanying drawings. However, the present application is not limited to the above specific implementation manners. The above specific implementation manners are merely illustrative and not restrictive. Under the inspiration of the present application, those of ordinary skill in the art can also make many forms without departing from the purpose of the present application and the scope protected by the claims, and all of them belong to the protection scope of the present application.

Claims

1. A signal processing method, characterized in that, Including: Turn on the first state of the phase-locked loop (PLL) in the radio frequency (RF) transceiver chip, where the RF transceiver chip is the RF transceiver chip in a time-division duplex (TDD) transceiver system. The RF transceiver chip includes a transmit link and a receive link. The PLL is connected to the local oscillators of both the transmit link and the receive link. The first state is one of at least two states of the PLL. Obtain the first direct current (DC) offset of the signal of the receive link. When the first DC offset is greater than or equal to a preset value, switch the state of the PLL from the first state to a target state, where the target state is one of the at least two states other than the first state. In the target state, the DC offset of the signal of the receive link is less than the preset value. The step of, when the first DC offset is greater than or equal to the preset value, switching the state of the PLL from the first state to the target state includes: When the first DC offset is greater than or equal to the preset value, switch the state of the PLL from the first state to the second state among the at least two states during a receive time slot. In the first state, the PLL generates local oscillator signals with the same frequency for both the transmit link and the receive link. The second state is a state where the transmission of the local oscillator signal of the transmit link is interrupted. Obtain the second DC offset of the signal of the receive link. Determine the target state of the PLL according to the second DC offset.

2. The method according to claim 1, wherein The step of determining the target state of the PLL according to the second DC offset includes: When the second DC offset is greater than or equal to the preset value, switch the state of the PLL from the second state to the third state among the at least two states. In the third state, the PLL generates a first local oscillator signal for the transmit link and a second local oscillator signal for the receive link, and the frequencies of the first local oscillator signal and the second local oscillator signal are different. Filter the DC signal of the receive link through a baseband filter until the DC signal offset of the receive link is less than the preset value.

3. The method according to claim 2, wherein After the step of switching the state of the PLL from the second state to the third state among the at least two states, the method further includes: Obtain the adjacent channel leakage ratio (ACLR) of the transmit link. When the ACLR is less than a preset threshold value, switch the state of the PLL from the third state to the fourth state among the at least two states during a transmit time slot. In the fourth state, the PLL interrupts the transmission of the local oscillator signal of the receive link. The step of filtering the DC signal of the receive link through a baseband filter until the DC signal offset of the receive link is less than the preset value includes: When the ACLR is greater than or equal to the preset threshold value, filter the DC signal of the receive link through a baseband filter until the DC signal offset of the receive link is less than the preset value.

4. The method according to claim 1, wherein Determining the target state of the PLL according to the second DC offset includes: When the second DC offset is less than the preset value, determining the second state as the target state of the PLL.

5. The method according to any one of claims 1 to 4, characterized in that Before the first state of the PLL in the radio frequency transceiver chip is turned on, the method further includes: Obtaining a first temperature value inside the radio frequency transceiver chip; After the first state of the PLL in the radio frequency transceiver chip is turned on, the method further includes: Obtaining a second temperature value inside the radio frequency transceiver chip; When the first DC offset is less than the preset value and the difference between the second temperature value and the first temperature value is greater than a preset threshold, updating the temperature of the radio frequency transceiver chip from the first temperature value to the second temperature value, and detecting the DC offset of the signal in the receiving link based on the updated temperature value.

6. The method according to any one of claims 1 to 4, characterized in that, The local oscillator of the transmitting link is connected to the reference signal transmitting device through the PLL, and the local oscillator of the receiving link is connected to the PLL through a first switch; The local oscillator of the transmitting link is connected to the mixer of the transmitting link through a second switch; The local oscillator of the receiving link is connected to the mixer of the receiving link through a third switch; In the first state, the first switch, the second switch, and the third switch are all in the closed state; In the second state of the PLL, the first switch and the third switch are both in the closed state, and the second switch is in the open state.

7. The method according to claim 6, characterized in that, The PLL includes a first PLL and a second PLL; The first ends of the first PLL and the second PLL are connected to the reference signal transmitting device, and the frequencies of the signals output by the first PLL and the second PLL are different; The second end of the first PLL is connected to the local oscillator of the transmitting link, the second end of the second PLL is connected to the local oscillator of the receiving link through a fourth switch, and the second ends of the first PLL and the second PLL are connected through the first switch; In the first state, the first switch, the second switch, and the third switch are all in the closed state, and the fourth switch is in the open state; In the second state of the PLL, the first switch and the third switch are both in the closed state, and the second switch and the fourth switch are in the open state; In the third state of the PLL, the first switch is in the open state, and the second switch, the third switch, and the fourth switch are all in the closed state; In the fourth state of the PLL, the first switch and the third switch are both in the open state, and the second switch and the fourth switch are all in the closed state.

8. A signal processing device, characterized in that, Including: An enabling module, configured to enable a first state of a phase-locked loop (PLL) in a radio frequency transceiver chip, where the radio frequency transceiver chip is a radio frequency transceiver chip in a time-division duplex (TDD) transceiver system, the radio frequency transceiver chip includes a transmitting link and a receiving link, the PLL is connected to the local oscillator of the transmitting link and is connected to the local oscillator of the receiving link, and the first state is one of at least two states of the PLL; A first acquisition module, configured to acquire a first DC offset of a signal of the receiving link; A switching module, configured to switch a state of the PLL from the first state to a target state when the first DC offset is greater than or equal to a preset value, where the target state is a state other than the first state among the at least two states, and in the target state, a DC offset of a signal of the receiving link is less than the preset value; The switching module includes: A switching sub-module, configured to switch a state of the PLL from the first state to a second state among the at least two states during a receiving time slot when the first DC offset is greater than or equal to the preset value, where the PLL generates local oscillator signals with the same frequency for the transmitting link and the receiving link in the first state, and the second state is a state of interrupting transmission of the local oscillator signal of the transmitting link; An acquisition sub-module, configured to acquire a second DC offset of a signal of the receiving link; A determination sub-module, configured to determine a target state of the PLL according to the second DC offset.

9. An electronic device, characterized in that, It includes: A processor, a memory, and a program stored on the memory and executable on the processor, where when the program is executed by the processor, steps of the signal processing method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium, characterized in that, A computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, steps of the signal processing method according to any one of claims 1 to 7 are implemented.

11. A computer program product, characterized in that, It includes computer instructions, and when the computer instructions are executed by a processor, steps of the signal processing method according to any one of claims 1 to 7 are implemented.

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