A method and device for processing digital signals at an HDMI receiving end

Abstract

The present invention provides a method for processing digital signals at an HDMI receiving end. The method comprises: performing 8-level caching on each chromaticity channel data of three received chromaticity channel data by multiplexing eight registers of a register unit, wherein each register caches 10-bit data, and combines the data with the chromaticity channel data input by the ninth clock into a 90-bit data sequence for output; detecting the output 90-bit data sequence, and when eight consecutive special character sequences are detected, generating a 10-bit special character sequence detection unit flag signal and assigning a value according to the detection result; selecting the output value of the register unit according to the generated special character sequence detection unit flag signal, and continuously outputting eight special characters as starting point data for bit alignment; and outputting the three chromaticity channel data after the alignment processing after clock synchronization. The present invention also provides a device for processing digital signals at an HDMI receiving end.

Description

Technical Field

[0001] The present invention belongs to the technical field of data transmission, and in particular relates to a method and device for processing digital signals at an HDMI receiving end. Background Art

[0002] High-Definition Multimedia Interface (HDMI), a digital video transmission standard based on Transition Minimized Differential Signaling (TMDS) encoding, uses three TMDS data channels and one TMDS clock channel to achieve high-speed data transmission. In the HDMI transmission system, the receiver starts working at any time relative to the transmitter, which means that the receiver may start receiving data from any position in the transmitted data stream. Therefore, if the existing SerDes PHY IP (physical layer IP core of the serial deserializer) is directly connected to the TMDS data channel of the receiver, in the absence of bit alignment, the received data may be disordered and the original information cannot be accurately restored, thus failing to meet the user's usage requirements. At the same time, the aligned data needs to be further synchronized through channels so that the processed video data can meet the usage requirements.

[0003] To solve the above problems, it is necessary to introduce the bit alignment unit and channel synchronization unit. The main responsibility of the bit alignment unit is to identify the first data bit transmitted by the transmitter in each independent data channel to ensure that the receiver can correctly interpret the entire data frame. The channel synchronization unit is dedicated to dealing with the data skew problem that may occur between multiple data channels, that is, the inconsistent data arrival time caused by the physical length difference between different channels or other factors.

[0004] Therefore, it is necessary to improve the existing HDMI receiving end, and add a bit synchronization function and a channel synchronization function to the existing HDMI receiving end so that the received data will not be disordered. Summary of the invention

[0005] The present invention provides a method for processing digital signals at an HDMI receiving end, which prevents data at the receiving end from being disordered by adding a bit alignment function and a channel synchronization function at the receiving end.

[0006] The present invention also provides a HDMI receiving end digital signal processing device, which prevents the receiving end data from being disordered by adding a bit alignment device and a channel synchronization device to the receiving end.

[0007] Other purposes and advantages of the present invention can be further understood from the technical features disclosed in the present invention.

[0008] To achieve one or part or all of the above purposes or other purposes, a technical solution of the present invention provides a method for processing digital signals at an HDMI receiving end, wherein each of the 3 chromaticity channel data received is cached in 8 levels of 8 registers of a register unit, each register caches 10 bits of data, and is combined with the chromaticity channel data input by the 9th clock to form a 90-bit data sequence for output; the output 90-bit data sequence is detected, and when 8 consecutive special character sequences are detected, a 10-bit special character sequence detection unit flag signal is generated and assigned according to the detection result; according to the generated special character sequence detection unit flag signal, the output value of the register unit is selected, and 8 special characters are continuously output as starting data for bit alignment; the 3 chromaticity channel data after alignment are output after clock synchronization.

[0009] The 90-bit data sequence output by the register unit is generated into 8 groups of data with 10 bits as a group; one data value is selected from the highest bit of the data sequence as the starting data of the 8 groups of data in sequence to generate 10 different 8 groups of data; the 10 generated 8 groups of data are detected in sequence to determine whether there is a continuous sequence of 8 special characters.

[0010] If each group of 10-bit data in any of the 8 groups of data is equal to the special character sequence, a special character sequence detection unit flag signal is generated and the corresponding bit is assigned a value of 1.

[0011] If each 10-bit data value in any of the 8 groups of data is equal to any of the special character sequences data_k1, data_k2, data_k3, or data_k4, a special character sequence detection unit flag signal is generated and the corresponding bit is assigned a value of 1.

[0012] According to the generation order of 10 kinds of 8 groups of data, each kind of 8 groups of data is detected in sequence, and the special character sequence detection unit flag signal is assigned according to the detection order and the detection result. Each kind of 8 groups of data detection result corresponds to a one-bit assignment result of the 10-bit special character sequence detection unit flag signal; if any kind of 8 groups of data is equal to the special character sequence, the special character sequence detection unit flag signal value of the corresponding bit is 1.

[0013] The generated special character sequence detection unit flag signal is detected, and when the special character sequence detection unit flag signal value is not 0, a signal flag detection unit flag signal is generated and set to 0, and no special character sequence detection is performed.

[0014] According to the generated special character sequence detection unit flag signal, the output value of the register unit is selected, including selecting to generate a number from 0-9 according to the special character sequence detection unit flag signal value, and selecting continuous 10 bits of data from the 89th to 71st bits of the output value of the register unit.

[0015] The aligned 3-channel chromaticity channel data are processed using clock synchronization, including writing the received 3-channel chromaticity channel data into 3 storage devices respectively by writing addresses; counting the interval time of special character sequences in the received 3-channel chromaticity channel data, and generating a synchronization signal or an error signal according to the statistical result to indicate whether to perform data synchronization; when the synchronization signal is received, the 3-channel chromaticity channel data is processed with clock synchronization so that the data meets the synchronization requirements in time.

[0016] The time intervals of special character sequences in the received 3-channel chromaticity channel data are counted, including setting 3 counters and setting the maximum count value of the counters, finding the special character sequence in each data channel through the counters within the counting cycle, outputting the count value, and when the count value does not reach the maximum count value, performing a logic "AND" operation with the count value of the counter in the range of 0 to the maximum count value, and outputting a counter flag signal; performing a logic "AND" operation on the counter flag signals generated by the 3 channels to generate an intermediate synchronization signal, and outputting the rising edge signal of the intermediate synchronization signal as a synchronization signal; otherwise, an error signal is generated.

[0017] Another technical solution of the present invention provides an HDMI receiving end digital signal processing device, comprising a bit alignment unit and a channel synchronization unit; the bit alignment unit comprises a data register unit for receiving chroma channel data, the register unit multiplexes 8 registers for 8-level cache of each of the 3 chroma channel data received, each register caches 10 bits of data, and combines with the chroma channel data input by the 9th clock to form a 90-bit data sequence for output; a special character sequence detection unit detects the data sequence, and generates a special character sequence detection unit flag signal when 8 special character sequences are detected continuously; a channel data selection unit generates a channel data selection unit flag signal according to the input special character sequence detection unit flag signal and inputs it to a chroma channel data output unit; the chroma channel data output unit selects a register unit output value according to the channel data selection unit flag signal, and continuously outputs a target number of special characters as bit alignment starting point data; the chroma channel data that has completed the data alignment process enters the channel synchronization unit and is output after clock synchronization.

[0018] When the signal flag detection unit flag signal output by the signal flag detection unit is 1, the special character sequence detection unit detects the special character sequence in the data sequence output by the register unit; the signal flag detection unit receives the special character sequence detection unit flag signal output by the special character sequence detection unit, and when the special character sequence detection unit flag signal value is not 0, generates a signal flag detection unit flag signal and sets it to 0.

[0019] Generate 8 groups of data by taking the 90-bit data sequence output by the register unit as a group of 10 bits; select one bit of data value from the highest bit of the data sequence as the start data of the 8 groups of data in sequence to generate 10 different 8 groups of data; detect the 10 generated 8 groups of data in sequence, and determine whether there are 8 consecutive special character sequences; if each group of 10 bits of data in any 8 groups of data is equal to the special character sequence, a special character sequence detection unit flag signal is generated and the corresponding bit is assigned a value of 1.

[0020] According to the generation order of 10 kinds of 8 groups of data, each kind of 8 groups of data is detected in sequence, and the special character sequence detection unit flag signal is assigned according to the detection order and the detection result. Each kind of 8 groups of data detection result corresponds to a one-bit assignment result of the 10-bit special character sequence detection unit flag signal; if any kind of 8 groups of data is equal to the special character sequence, the special character sequence detection unit flag signal value of the corresponding bit is 1.

[0021] The channel data selection unit selects a number from 0 to 9 as the channel data selection unit flag signal according to the special character sequence detection unit flag signal value; the chrominance channel data output unit selects continuous 10 bits of data from the 89th to 71st bits of the output register unit output value according to the channel data selection unit flag signal.

[0022] The channel synchronization unit includes a data receiving unit, which is provided with three storage devices for writing chromaticity channel data; a data detection unit receives the three chromaticity channel data stored in the data receiving unit, counts the mutual interval time of the special character sequences between the three chromaticity channel data, and generates a synchronization signal or an error signal; after receiving the synchronization signal, the data synchronization unit synchronously processes the three chromaticity channel data stored in the data receiving unit under the clock signal.

[0023] The data detection unit includes three counters, the maximum count value of the counter is set, each counter receives one channel of chrominance channel data respectively, finds out the special character sequence in the three data channels through the counter within the counting cycle, and outputs the count value; a first logic judgment module is used to judge whether the count values ​​of the three counters have reached the maximum count value, and outputs a judgment signal when the maximum count value is reached; three first logic "AND" circuits, when the count value has not reached the maximum count value, perform a logic operation on the count value in the range of 0 to the maximum count value and the count value of the counter, and output a counter flag signal; a second logic "AND" circuit, performs a logic operation on the generated three counter flag signals to generate an intermediate synchronization signal; a second logic judgment module outputs the high-potential signal of the generated intermediate synchronization signal as a synchronization signal; a third logic "AND" circuit, performs a logic operation on the low-potential signal in the intermediate synchronization signal output by the second logic judgment module and the judgment signal, and outputs an error signal.

[0024] Compared with the prior art, the beneficial effects of the present invention mainly include: the present invention realizes the alignment and synchronization of multi-channel chromaticity data by setting the bit alignment function and the channel synchronization function, thereby reducing the risk of data disorder.

[0025] In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0027] Figure 1 The figure is a schematic diagram of a digital signal processing device at an HDMI receiving end according to the present invention.

[0028] Figure 2 It is a schematic diagram of the structure of the bit alignment unit of the present invention.

[0029] Figure 3 This is a schematic diagram of traversing a special character sequence according to the present invention.

[0030] Figure 4 It is a schematic diagram of the structure of the channel synchronization unit of the present invention.

[0031] Figure 5 Schematic diagram of a data detection unit of the present invention.

[0032] Figure 6This is a data processing flow chart of the HDMI receiving end of the present invention. DETAILED DESCRIPTION

[0033] The above and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of a preferred embodiment with reference to the drawings. The directional terms mentioned in the following embodiments, such as up, down, left, right, front or back, etc., are only referenced to the directions of the attached drawings. Therefore, the directional terms used are used to illustrate and not to limit the present invention.

[0034] Embodiment 1 Embodiment 1 provides a method for processing digital signals at an HDMI receiving end, wherein each of the 3 received chromaticity channel data is cached at 8 levels by multiplexing 8 registers of a register unit, each register caches 10 bits of data, and is combined with the chromaticity channel data input by the 9th clock to form a 90-bit data sequence for output; the output 90-bit data sequence is detected, and when 8 consecutive special character sequences are detected, a 10-bit special character sequence detection unit flag signal is generated and assigned a value according to the detection result; according to the generated special character sequence detection unit flag signal, an output value of the register unit is selected, and 8 special characters are continuously output as starting point data for bit alignment; the 3 chromaticity channel data after alignment processing are output after clock synchronization.

[0035] The following is a detailed explanation of the solution of the first embodiment of the present invention in conjunction with the accompanying drawings. Figure 6 , a method for processing digital signals at an HDMI receiving end according to the first embodiment includes the following steps: Step S1: a bit alignment step, performing a bit alignment operation on the received three-channel chrominance channel data, specifically comprising: Step S1-1: 3 chromaticity channel data outputted by the physical layer IP core of the serial deserializer are received by multiplexing 8 registers and 8-level caches, each chromaticity channel data corresponds to a component of a pixel, and three chromaticity channels transmit one pixel together, each chromaticity channel data corresponds to 10 bits of data, and one pixel consists of 30 bits of data. Each data is respectively combined with the chromaticity channel data inputted by the 9th clock into a 90-bit data sequence, and the register unit outputs a 90-bit data sequence; Here, the chroma channel data of the 9th clock input means that when the data in each chroma channel is bit-aligned, the register level 8 caches 80 bits of data and then combines it with the 9th input data of the channel. The digital video transmission standard HDMI (High Definition Multimedia Interface) has three TMDS data channels and one TMDS clock channel. The TMDS clock channel provides a clock signal, and the three TMDS data channels follow the clock signal for data transmission.

[0036] Step S1-2: Receive a 90-bit data sequence and perform special character sequence detection. The specific detection method is to generate 8 groups of data by grouping the 90-bit data sequence data_seq with 10 bits per group, and select one bit of data from the highest bit of the data as the starting data of the 8 groups of data in sequence, generate 10 types of 8 groups of data, traverse these 10 types of 8 groups of data in sequence, and determine whether 8 special character sequences can be detected continuously. When 8 special character sequences are detected continuously, a 10-bit special character sequence detection unit flag signal key_flag is generated, and the corresponding bit of key_flag is assigned a value according to the detection result. For the specific assignment process, refer to Figure 3 To explain: Figure 3 A total of 10 types of 8 groups of data are generated. These 10 types of 8 groups of data are obtained by combining 8 groups of 10 bits of continuous data in a 90-bit data sequence with each bit as a step value. During detection, the detection is also carried out in the order in which the 10 types of 8 groups of data are generated. Figure 3 First, the 8 groups of data generated in stage 1 are tested to see whether data_seq[89:80], data_seq[79:70], data_seq[69:60], data_seq[59:50], data_seq[49:40], data_seq[39:30], data_seq[29:20], and data_seq[19:10] are equal to any of the special character sequences data_k1, data_k2, data_k3, and data_k4. The special character sequences data_k1, data_k2, data_k3, and data_k4 are control characters based on TMDS encoding technology in the HDMI protocol, and each special character sequence corresponds to a fixed 10-bit binary sequence. Each of the 8 groups of data generated in step S1-2 has 10 bits of data. Therefore, 10 bits of data are used as a group for comparison, which is convenient for comparison. If they are equal, a special character sequence detection unit flag signal key_flag is generated and the highest bit of key_flag is set to 1, otherwise it is set to 0 and the detection of stage 2 is started. The detection of stage 2 is the same as that of stage 1. If there is a special character sequence number in stage 2, the second highest bit of key_flag is set to 1, otherwise it is set to 0 and the detection of stage 3 is started. Repeat the above detection method until all 8 groups of data are detected, and then the 10-bit special character sequence detection unit flag signal key_flag is finally assigned.

[0037] Step S1-3: Receive the special character sequence detection unit flag signal key_flag output by step S1-2 and perform detection. When the flag signal key_flag is not 0, a signal flag detection unit flag signal key_detect is generated and set to 0. When a sequence similar to the 8 special character sequences appears subsequently, it is determined to be chroma channel data, and the special character sequence detection link is no longer executed.

[0038] Step S1-4: According to the generated special character sequence detection unit flag signal key_flag, select the output value of the register unit, including selecting to generate a number from 0 to 9 according to the special character sequence detection unit flag signal value, and selecting to output the continuous 10 bits of data in the 89th to 71st bits of the register unit output value. For example: when the generated value is 0, output [89:80], when the generated value is 1, output [88:79], and so on, when the generated value is 9, output [80:71].

[0039] Step S1-5: Based on the register value output in step S1-4, eight special characters are continuously output as bit alignment starting point data. When the value generated in step S1-4 remains unchanged, the video or data island cycle data is output in sequence. When the value generated in step S1-4 changes, the video or data island cycle data is not transmitted, thereby realizing the output after data alignment.

[0040] Step S2: outputting the received three-channel chrominance channel data after completing data bit alignment using clock synchronization, specifically including: Step S2-1: Write the received three chrominance channel data into three storage devices respectively through writing addresses.

[0041] Step S2-2: Counting the intervals of the special character sequences in the received 3-channel chrominance channel data, and generating a synchronization signal or an error signal according to the statistical results, specifically including: Step S2-21: set three counters, and set the maximum count value of the counters to 15, for example, find the special character sequence in each data channel through the counters within the counting cycle, and output the count values ​​cnt_clk0, cnt_clk1, and cnt_clk2; Step S2-22: When the count value does not reach the maximum count value, perform a logic “AND” operation with the count value of the counter within the range of 0 to the maximum count value (for example, within 0-15), and output three counter flag signals cnt_clk0_r, cnt_clk1_r, and cnt_clk2_r; Step S2-23: performing a logic “AND” operation on the counter flag signals generated by the three channels to generate an intermediate synchronization signal data_out_ep; Step S2-24: using a logic judgment module to output the rising edge signal of the intermediate synchronization signal as a synchronization signal ep_en; Step S2-3: When the data synchronization signal ep_en is received, clock synchronization processing is performed on the 3-channel chrominance channel data so that the data meets the synchronization requirement in time.

[0042] Among them, the generated synchronization signal is used to indicate that within the maximum interval time range, the special character sequences of the three data channels can be transmitted, so the three signals can be synchronized by the clock within the maximum interval time range. When the error signal error_flag is generated, it indicates that within the maximum interval time range, the special character sequences of the three data channels are too far apart from each other, and it is meaningless to use the clock for synchronization at this time.

[0043] Embodiment 2 Embodiment 2 provides an HDMI receiving end digital signal processing device, including a bit alignment unit and a channel synchronization unit; the bit alignment unit includes a data register unit for receiving chroma channel data, the register unit multiplexes 8 registers for 8-level cache of each of the 3 chroma channel data received, each register caches 10 bits of data, and is combined with the chroma channel data input by the 9th clock to form a 90-bit data sequence for output; a special character sequence detection unit detects the data sequence, and when 8 special character sequences are continuously detected, a special character sequence detection unit flag signal is generated; a channel data selection unit generates a channel data selection unit flag signal according to the input special character sequence detection unit flag signal and inputs it to a chroma channel data output unit; the chroma channel data output unit selects a register unit output value according to the channel data selection unit flag signal, and continuously outputs a target number of special characters as bit alignment starting point data; the chroma channel data that has completed the data alignment process enters the channel synchronization unit and is output after clock synchronization.

[0044] The following is a detailed description of the HDMI receiving end digital signal processing device in the second embodiment in conjunction with the accompanying drawings. Figure 1-Figure 5 The HDMI receiving end digital signal processing device of the present invention includes a bit alignment unit and a channel synchronization unit. The specific structure of the bit alignment unit is as follows: Figure 2As shown, it includes a data storage unit, a special character sequence detection unit, a channel data selection unit, a chroma channel data output unit and a signal flag detection unit, wherein the data storage unit receives each chroma channel data of the three chroma channel data respectively, the data storage unit has multiple registers, each register receives 10-bit chroma channel data, and the multiple registers in the data register unit cache the received chroma channel data in multiple levels and combine them with the chroma channel data input by the 9th clock to output a 90-bit data sequence to the special character sequence detection unit for detection. When the signal flag detection unit flag signal key_detect output by the signal flag detection unit is 1, the special character sequence detection unit detects whether there are 8 consecutive special character sequences in the data sequence, and outputs the special character sequence detection unit flag signal key_flag when there are 8 consecutive special character sequences, and assigns a value to the corresponding bit of key_flag according to the detection result. For the specific assignment process, refer to Figure 3 .

[0045] As an implementation method, the process of the special character sequence detection unit detecting and assigning special characters in the data sequence can be referred to step S1-2 in the above embodiment 1, which will not be repeated here.

[0046] The signal flag detection unit is also used to receive the special character sequence detection unit flag signal key_flag output by the special character sequence detection unit, and when key_flag is not 0, it generates a signal flag detection unit flag signal key_detect and sets it to 0, and the special character sequence detection link is no longer executed. After the signal flag detection unit is reset, key_detect is first set to 1, and the special character sequence detection is performed by default, and when the special character sequence detection unit flag signal key_flag is not 0, key_detect is set to 0, indicating that the special code sequence has been found. There is no need to detect the special character sequence again in the future. Even if a sequence identical to the special character sequence appears, the special character sequence detection link will not be executed unless it is restarted.

[0047] The channel data selection unit receives the special character sequence detection unit flag signal key_flag output by the special character sequence detection unit, and outputs a channel data selection unit flag signal data_pos. Specifically, according to the special character sequence detection unit flag signal key_flag, a number among 0-9 is selected and generated as the channel data selection unit flag signal data_pos.

[0048] The channel data selection unit flag signal data_pos is input to the chroma channel data output unit, and the chroma channel data output unit selects the register unit output value according to the channel data selection unit flag signal data_pos. Specifically, the chroma channel data output unit selects the continuous 10-bit data in the 89th-71st bits of the output value of the output register unit. For example: when the generated value is 0, [89:80] is output, when the generated value is 1, [88:79] is output, and so on, when the generated value is 9, [80:71] is output. At the same time, the chroma channel data output unit continuously outputs the target number of special characters as the bit alignment starting point data, thereby completing the bit alignment of the data.

[0049] See also Figure 4 The channel synchronization unit includes a data receiving unit, a data detection unit and a data synchronization unit. The data receiving unit is provided with three storage devices RAM1, RAM2 and RAM3, which are used to write the three-way aligned data respectively ( Figure 4 Taking 10 bits of data per channel as an example for explanation); the data detection unit receives the 3-channel chromaticity channel data data0_en, data1_en, and data2_en stored in the data receiving unit, and counts the mutual interval time of the special character sequences between the 3-channel chromaticity channel data to generate a synchronization signal or an error signal; after receiving the synchronization signal, the data synchronization unit synchronizes the 3-channel chromaticity channel data stored in the data receiving unit under the unit clock signal.

[0050] See also Figure 5 The data detection unit includes three counters, sets the maximum count value of the counter, and each counter receives one channel of chrominance channel data. During the counting period, the counter finds the special character sequence in the three data channels and outputs the count values ​​cnt_clk0, cnt_clk1, and cnt_clk2. The first logic judgment module ( Figure 5 The logic judgment 1 in the figure is used to judge whether the count value of the three counters has reached the maximum count value, and output a judgment signal (value 0) when the count value of the three counters has reached the maximum count value. Figure 5 The output value of the logic judgment 1 in the circuit is 1, and the ... Figure 5 The logic AND 0, logic AND 1, logic AND 2 of the counter are respectively logically operated with the count value of the counter in the range of 0 to the maximum count value, and three counter flag signals cnt_clk0_r, cnt_clk1_r, cnt_clk2_r are output; The three counter flag signals cnt_clk0_r, cnt_clk1_r, cnt_clk2_r are generated through a logic "AND" circuit ( Figure 5The logic AND 3) is used to generate the intermediate synchronization signal data_out_ep, and a second logic judgment module ( Figure 5 The logic judgment module 0) outputs the high potential signal of the intermediate synchronization signal as the synchronization signal ep_en, indicating that the special character sequences of the three data channels can be transmitted within the maximum interval time. At the same time, the second logic judgment module compares the low potential signal of the intermediate synchronization signal with the first logic judgment module ( Figure 5 The judgment signal (value 0) output by the logic judgment 1) passes through a third logic "AND" circuit ( Figure 5 The logic AND in 4) performs a logic operation and outputs an error signal. This indicates that the special character sequences of the three data channels are too far apart within the maximum interval time range and cannot be synchronized.

[0051] After being detected by the data detection unit, the output synchronization signal and the error signal are input into the data synchronization unit and synchronized by the clock clk_sync in the data synchronization unit.

[0052] The above is a detailed introduction to a HDMI receiving end digital signal processing method and device provided by the present invention. This article uses specific examples to illustrate the structure and working principle of the present invention. The description of the above embodiments is only used to help understand the method and core idea of ​​the present invention. It should be pointed out that for ordinary technicians in this technical field, without departing from the principle of the present invention, the present invention can also be improved and modified, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. A method for processing digital signals at an HDMI receiving end, characterized in that: Each of the 3 chromaticity channel data received is cached in 8 levels using 8 registers of the register unit, each register caches 10 bits of data, and is combined with the chromaticity channel data input by the 9th clock into a 90-bit data sequence for output; Detect the output 90-bit data sequence, and when 8 consecutive special character sequences are detected, generate a 10-bit special character sequence detection unit flag signal and assign a value according to the detection result; According to the generated special character sequence detection unit flag signal, select the output value of the register unit, and continuously output 8 special characters as the starting point data of the bit alignment; The 3-channel chroma channel data is aligned and output after clock synchronization.

2. The HDMI receiving end digital signal processing method according to claim 1, characterized in that: The 90-bit data sequence output by the register unit is grouped into 8 groups of data with 10 bits of data; Starting from the highest bit of the data sequence, one bit of data value is selected in sequence as the starting data of 8 groups of data to generate 10 different 8 groups of data; The generated 10 types of 8 groups of data are tested in turn to determine whether there are continuous sequences of 8 special characters.

3. A method for processing digital signals at an HDMI receiving end according to claim 2, characterized in that: If each group of 10-bit data in any of the 8 groups of data is equal to the special character sequence, a special character sequence detection unit flag signal is generated and the corresponding bit is assigned a value of 1.

4. A method for processing digital signals at an HDMI receiving end according to claim 3, characterized in that: If each 10-bit data value in any of the 8 groups of data is equal to any of the special character sequences data_k1, data_k2, data_k3, or data_k4, a special character sequence detection unit flag signal is generated and the corresponding bit is assigned a value of 1.

5. The HDMI receiving end digital signal processing method according to claim 3, characterized in that: According to the generation order of 10 kinds of 8 groups of data, each kind of 8 groups of data is detected in sequence, and according to the detection order and the detection result, the special character sequence detection unit flag signal is assigned a value, and each kind of 8 groups of data detection result corresponds to a one-bit assignment result of the 10-bit special character sequence detection unit flag signal; If any of the 8 groups of data is equal to the special character sequence, the special character sequence detection unit flag signal value of the corresponding position is 1.

6. The HDMI receiving end digital signal processing method according to claim 1, characterized in that: The generated special character sequence detection unit flag signal is detected, and when the special character sequence detection unit flag signal value is not 0, a signal flag detection unit flag signal is generated and set to 0, and no special character sequence detection is performed.

7. The HDMI receiving end digital signal processing method according to claim 1, characterized in that: According to the generated special character sequence detection unit flag signal, the output value of the register unit is selected, including selecting to generate a number from 0-9 according to the special character sequence detection unit flag signal value, and selecting continuous 10 bits of data from the 89th to 71st bits of the output value of the register unit.

8. The method for processing digital signals at an HDMI receiving end according to claim 1, wherein: The aligned 3-way chroma channel data are processed using clock synchronization, including writing the received 3-way chroma channel data into 3 storage devices respectively through write addresses; Count the interval time of the special character sequence in the received 3-channel chrominance channel data, and generate a synchronization signal or an error signal according to the statistical result to indicate whether to perform data synchronization; After receiving the synchronization signal, the clock synchronization processing is performed on the 3-channel chrominance channel data so that the data meets the synchronization requirements in time.

9. A method for processing digital signals at an HDMI receiving end according to claim 8, characterized in that: The time interval of the special character sequence in the received 3-channel chrominance channel data is counted, including setting 3 counters and setting the maximum count value of the counters, finding the special character sequence in each data channel through the counters within the counting cycle, outputting the count value, and performing a logical "AND" operation with the count value of the counter within the range of 0 to the maximum count value when the count value does not reach the maximum count value, and outputting a counter flag signal; Perform a logic "AND" operation on the counter flag signals generated by the three channels to generate an intermediate synchronization signal, and output the rising edge signal of the intermediate synchronization signal as the synchronization signal; Otherwise an error signal is generated.

10. A HDMI receiving end digital signal processing device, characterized in that: including a bit alignment unit and a channel synchronization unit; The bit alignment unit includes a data register unit for receiving chroma channel data, wherein the register unit multiplexes each of the 3 chroma channel data received into 8 registers for 8-level cache, each register caches 10 bits of data, and combines the data with the chroma channel data input by the 9th clock into a 90-bit data sequence for output; A special character sequence detection unit detects the data sequence and generates a special character sequence detection unit flag signal when eight special character sequences are detected continuously; The channel data selection unit generates a channel data selection unit flag signal according to the input special character sequence detection unit flag signal and inputs the signal to the chrominance channel data output unit; The chroma channel data output unit selects the register unit output value according to the channel data selection unit flag signal, and continuously outputs a target number of special characters as bit alignment starting point data; The chrominance channel data that has completed the data alignment process enters the channel synchronization unit and is output after being synchronized with the clock.

11. The HDMI receiving end digital signal processing device according to claim 10, characterized in that: The special character sequence detection unit detects the special character sequence in the data sequence output by the register unit when the signal flag detection unit flag signal output by the signal flag detection unit is 1; The signal flag detection unit receives the special character sequence detection unit flag signal output by the special character sequence detection unit, and generates a signal flag detection unit flag signal and sets it to 0 when the value of the special character sequence detection unit flag signal is not 0.

12. The HDMI receiving end digital signal processing device according to claim 10, characterized in that: The 90-bit data sequence output by the register unit is grouped into 8 groups of data with 10 bits of data; Starting from the highest bit of the data sequence, one bit of data value is selected in sequence as the starting data of 8 groups of data to generate 10 different 8 groups of data; Detect the 10 types of 8 groups of data generated in turn and determine whether there is a continuous sequence of 8 special characters; If each group of 10-bit data in any of the 8 groups of data is equal to the special character sequence, a special character sequence detection unit flag signal is generated and the corresponding bit is assigned a value of 1.

13. The HDMI receiving end digital signal processing device according to claim 12, characterized in that: According to the generation order of 10 kinds of 8 groups of data, each kind of 8 groups of data is detected in sequence, and according to the detection order and the detection result, the special character sequence detection unit flag signal is assigned a value, and each kind of 8 groups of data detection result corresponds to a one-bit assignment result of the 10-bit special character sequence detection unit flag signal; If any of the 8 groups of data is equal to the special character sequence, the special character sequence detection unit flag signal value of the corresponding position is 1.

14. The HDMI receiving end digital signal processing device according to claim 10, characterized in that: The channel data selection unit selects a number from 0 to 9 as the channel data selection unit flag signal according to the special character sequence detection unit flag signal value; The chrominance channel data output unit selects continuous 10 bits of data from bits 89 to 71 of the output value of the output register unit according to the channel data selection unit flag signal.

15. The HDMI receiving end digital signal processing device according to claim 10, characterized in that: The channel synchronization unit includes a data receiving unit, and the data receiving unit is provided with three storage devices for writing chrominance channel data; The data detection unit receives the 3-channel chromaticity channel data stored in the data receiving unit, calculates the time intervals between the special character sequences between the 3-channel chromaticity channel data, and generates a synchronization signal or an error signal; After receiving the synchronization signal, the data synchronization unit synchronously processes the three chromaticity channel data stored in the data receiving unit under the clock signal.

16. The HDMI receiving end digital signal processing device according to claim 15, characterized in that: The data detection unit includes three counters, the maximum count value of the counters is set, each counter receives one channel of chrominance channel data respectively, finds out the special character sequence in the three data channels through the counter within the counting cycle, and outputs the count value; The first logic judgment module is used to judge whether the count values ​​of the three counters have reached the maximum count value, and output a judgment signal when the maximum count value is reached; 3 first logic "AND" circuits, when the count value does not reach the maximum count value, perform a logic operation on the count value within the range of 0 to the maximum count value and the count value of the counter, and output a counter flag signal; a second logic "AND" circuit, performing a logic operation on the three generated counter flag signals to generate an intermediate synchronization signal; A second logic judgment module outputs the generated high potential signal of the intermediate synchronization signal as a synchronization signal; A third logic “AND” circuit performs a logic operation on the low potential signal in the intermediate synchronization signal output by the second logic judgment module and the judgment signal, and outputs an error signal.

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