Stereoscopic image display system and method based on FPGA

Abstract

The present invention provides a FPGA-based stereoscopic image display system and method, including: an acquisition module receives two image source signals and obtains two YUV single-edge data signals; a processing module stores one single-edge data signal in a DDR particle and uses the clock of another single-edge data signal to read the data in the DDR particle; a stereoscopic image signal is obtained by using the two single-edge data signals; and an output module outputs the stereoscopic image signal. Since the signal frequency of the YUV format is low and the bit width is large, it is conducive to FPGA to process data in parallel, and the amount of data is small, saving the internal resources of the FPGA; by storing one data signal in the DDR particle and reading from the DDR particle using the clock of the other data signal, not only can the space cost of storing the image in the DDR be saved, but also the resolution information can be efficiently identified, and the image frame rate can be improved, thereby improving the clarity of the stereoscopic image display, solving the problem that the existing FPGA-based stereoscopic image display technology occupies a large amount of storage resources and has a low display clarity.

Description

Technical Field

[0001] The present invention relates to the field of image display technology, and in particular to a FPGA-based stereoscopic image display system and method. Background Art

[0002] As people's living standards improve, more and more display devices with 3D stereoscopic display effects are available. The display principle of existing 3D stereoscopic display devices is usually to generate two different images based on the different visual distances of the left and right eyes of a person from a 2D plane image, and then integrate them on the screen for display to achieve a 3D stereoscopic display effect. Since the video clarity depends on the high resolution of the display device, and high resolution means that a larger storage capacity device is required, in order to obtain a clearer display effect, the existing display device needs to be configured with hardware with a larger storage capacity, resulting in increased costs.

[0003] At present, in the field of image display, DDR is usually used as a storage device based on FPGA. By controlling the reading and writing of DDR, the display of three-dimensional images can be realized. However, currently images are generally in RGB888 format, that is, each color component of RGB is 8 bits, thus forming a 256-pixel value space. This image format requires a large amount of storage space, resulting in a large consumption of DDR resources.

[0004] In addition, since FPGA itself is a data chip for logical operations and is not good at data storage, existing image display technology cannot achieve higher-resolution stereoscopic image processing based on FPGA, making the clarity of its image display unable to meet the demand, limiting its scope of use. Summary of the invention

[0005] The object of the present invention is to provide a FPGA-based stereoscopic image display system and method to solve the problem that the existing FPGA-based stereoscopic image display technology occupies a large amount of storage resources and has low display clarity.

[0006] In order to solve the above technical problems, the present invention provides a FPGA-based stereoscopic image display system, comprising: An acquisition module is used to receive an A-channel image source signal and a B-channel image source signal, and sample and process the A-channel image source signal and the B-channel image source signal to obtain an A-channel single-edge data signal in a YUV format and a B-channel single-edge data signal in a YUV format; A processing module is used to store the B-channel single-edge data signal in the DDR particle, and use the clock of the A-channel single-edge data signal as a reference clock to read the B-channel single-edge data signal in the DDR particle, and then perform image overlap processing on the A-channel single-edge data signal and the B-channel single-edge data signal according to the chrominance value to obtain a fused stereoscopic image signal; The output module is used to output a stereoscopic image signal to display a stereoscopic image.

[0007] Optionally, in the FPGA-based stereoscopic image display system, the acquisition module includes an A-channel image source acquisition unit and a B-channel image source acquisition unit; The A-channel image source acquisition unit is used to acquire the A-channel image source signal, and perform sampling processing on the A-channel image source signal to generate the A-channel single-edge data signal, the A-channel synchronization signal and the A-channel image coordinate information in the YUV format; The B-channel image source acquisition unit is used to acquire the B-channel image source signal, and sample and process the B-channel image source signal to generate a B-channel single-edge data signal in YUV format, a storage indication signal and a write instruction, so as to store the B-channel single-edge data signal in YUV format in the write storage space according to the storage indication signal and the write instruction.

[0008] Optionally, in the FPGA-based stereoscopic image display system, the A-channel image source signal includes an A-channel image data signal, an A-channel DE synchronization signal, an A-channel VS synchronization signal, and an A-channel HS synchronization signal; the A-channel image source acquisition unit includes an A-channel image data processing circuit and an A-channel synchronization signal processing circuit; The A-channel image data processing circuit is used to convert the A-channel image data signal from a double-edge data signal to a clock single-edge data signal by using IDDR, and then perform splicing processing to obtain the A-channel single-edge data signal in YUV format; The A-channel synchronization signal processing circuit is used to use IDDR to convert the A-channel DE synchronization signal, the A-channel VS synchronization signal and the A-channel HS synchronization signal from double-edge data signals to clock single-edge data signals, and then perform OR operations on them to obtain the A-channel single-edge DE synchronization signal, the A-channel single-edge VS synchronization signal and the A-channel single-edge HS synchronization signal respectively; it is also used to generate the A-channel coordinate mark signal according to the A-channel single-edge VS synchronization signal, and generate the A-channel image coordinate information according to the A-channel coordinate mark signal and the A-channel single-edge HS synchronization signal.

[0009] Optionally, in the FPGA-based stereoscopic image display system, the B-channel image source signal includes a B-channel image data signal, a B-channel DE synchronization signal, a B-channel VS synchronization signal, and a B-channel HS synchronization signal; the B-channel image source acquisition unit includes a B-channel image data processing circuit and a B-channel synchronization signal processing circuit; The B-channel image data processing circuit is used to convert the B-channel image data signal from a double-edge data signal to a clock single-edge data signal by using IDDR, and then perform splicing processing to obtain the B-channel single-edge data signal in YUV format; The B-channel synchronization signal processing circuit is used to use IDDR to convert the B-channel DE synchronization signal, the B-channel VS synchronization signal and the B-channel HS synchronization signal from double-edge data signals to clock single-edge data signals, and then perform OR operation processing to obtain the B-channel single-edge DE synchronization signal, the B-channel single-edge VS synchronization signal and the B-channel single-edge HS synchronization signal respectively; it is also used to generate a B-channel coordinate flag signal and a storage indication signal according to the B-channel single-edge VS synchronization signal, generate B-channel image coordinate information according to the B-channel coordinate flag signal and the B-channel single-edge HS synchronization signal, and generate a write instruction according to the B-channel image coordinate information and the B-channel single-edge DE synchronization signal.

[0010] Optionally, in the FPGA-based stereoscopic image display system, the processing module includes an image restoration unit, a storage control unit, and a color gamut conversion unit; The image recovery unit is used to recover the image synchronization information and the bit width of the image data according to the A-channel image coordinate information, and generate a read instruction at the same time; The storage control unit is used to parse the write instruction and the read instruction to read the B-path single-edge data signal in the YUV format stored in the write storage space into the read storage space; The color gamut conversion unit is used to convert the A-channel single-edge data signal in the YUV format generated by the A-channel image source acquisition unit into the A-channel image signal in the RGB format, and convert the B-channel single-edge data signal in the YUV format in the read storage space into the B-channel image signal in the RGB format; and is also used to determine whether the A-channel image signal and the B-channel image signal meet a preset condition, and select to output the A-channel image signal or the B-channel image signal according to the determination result; The image restoration unit is further used to receive the image signal output by the color gamut conversion unit, and output a stereoscopic image signal after adding synchronization information to the image signal.

[0011] Optionally, in the FPGA-based stereoscopic image display system, the storage control unit includes a command arbitration circuit, a read and write data state machine, a control signal generation circuit, a memory controller and a DDR physical layer; The command arbitration circuit is used to receive a write instruction and a read instruction, and start the read / write data state machine according to the write instruction or the read instruction in a first-in-first-out arbitration manner; The read / write data state machine is used to generate address information and read / write commands for controlling the DDR physical layer according to a write instruction or a read instruction; The control signal generating circuit is used to generate a read address signal and a read enable signal according to a write instruction; and is also used to generate a write address signal and a write enable signal according to a read instruction; The memory controller is used to send data signals in the write storage space to the DDR particles through the DDR physical layer using address signals, read and write commands, read address signals and read enable signals; and is also used to read data signals from the DDR particles through the DDR physical layer and write them into the read storage space using address signals, read and write commands, write address signals and write enable signals.

[0012] In order to solve the above technical problems, the present invention further provides a FPGA-based stereoscopic image display method, which is applied to the FPGA-based stereoscopic image display system as described in any one of the above items, and the FPGA-based stereoscopic image display method includes: Respectively receive channel A image source signal and channel B image source signal; Obtain the A-channel single-edge data signal in YUV format from the A-channel image source signal, and generate the A-channel image coordinate information and read instruction; Obtaining a B-channel single-edge data signal in a YUV format from a B-channel image source signal, and generating a storage indication signal and a write instruction; The B-channel single-edge data signal in the YUV format is stored in the write storage space according to the storage indication signal and the write instruction; Parse the read instruction and the write instruction to read the B-channel single-edge data signal in the YUV format stored in the write storage space into the read storage space via the DDR particles; Convert the single-edge data signal of A channel in YUV format into the image signal of A channel in RGB888 format, and convert the single-edge data signal of B channel in YUV format in the read storage space into the image signal of B channel in RGB888 format; Determine whether the A-channel image signal and the B-channel image signal meet the preset conditions, and select to output the A-channel image signal or the B-channel image signal according to the determination result; After adding synchronization information to the output image signal, a stereoscopic image signal is output.

[0013] Optionally, in the FPGA-based stereoscopic image display method, the method of obtaining the A-channel single-edge data signal in YUV format from the A-channel image source signal and generating the A-channel image coordinate information includes: By using IDDR, the A-channel image data signal is converted from a double-edge data signal to a clock single-edge data signal, and then spliced ​​to obtain the A-channel single-edge data signal in YUV format; By using IDDR, the A-channel DE synchronization signal, the A-channel VS synchronization signal and the A-channel HS synchronization signal are respectively converted from double-edge data signals to clock single-edge data signals, and then respectively processed by OR operation to obtain the A-channel single-edge DE synchronization signal, the A-channel single-edge VS synchronization signal and the A-channel single-edge HS synchronization signal; Detect the rising edge of the single-edge VS synchronization signal of channel A according to the sampling clock to generate a coordinate mark signal of channel A; The A-channel image coordinate information is generated according to the A-channel coordinate mark signal and the A-channel single-edge HS synchronization signal.

[0014] Optionally, in the FPGA-based stereoscopic image display method, the method of obtaining a B-channel single-edge data signal in a YUV format from a B-channel image source signal and generating a storage indication signal and a write instruction includes: Using IDDR, the B-channel image data signal is converted from a double-edge data signal to a clock single-edge data signal, and then spliced ​​to obtain a B-channel single-edge data signal in a YUV format; By using IDDR, the B-channel DE synchronization signal, the B-channel VS synchronization signal and the B-channel HS synchronization signal are respectively converted from double-edge data signals to clock single-edge data signals, and then respectively processed by OR operation to obtain the B-channel single-edge DE synchronization signal, the B-channel single-edge VS synchronization signal and the B-channel single-edge HS synchronization signal; Detect the rising edge of the single-edge VS synchronization signal of the B-way according to the sampling clock to generate the B-way coordinate mark signal and the storage indication signal; Generate B-channel image coordinate information according to the B-channel coordinate mark signal and the B-channel single-edge HS synchronization signal; Generate a write instruction based on the B-channel image coordinate information and the B-channel single-edge DE synchronization signal.

[0015] Optionally, in the FPGA-based stereoscopic image display method, the method of parsing the read instruction and the write instruction to read the B-path single-edge data signal in the YUV format stored in the write storage space into the read storage space via the DDR particles includes: Receive write instructions and read instructions; According to the first-in-first-out arbitration method, a read address signal and a read enable signal are generated according to the write instruction; Read the data signal from the write storage space according to the read address signal and the read enable signal, and send the read data signal to the DDR particle through the DDR physical layer according to the address signal and the read and write command; According to the first-in-first-out arbitration method, a write address signal and a write enable signal are generated according to the read instruction; According to the address signal and the read / write command, the data signal is read from the DDR particle through the DDR physical layer, and according to the write address signal and the write enable signal, the read data signal is written into the read storage space.

[0016] Optionally, in the FPGA-based stereoscopic image display method, before converting the A-channel single-edge data signal in the YUV format into the A-channel image signal in the RGB888 format, the FPGA-based stereoscopic image display method further includes: Obtain the initial coordinate position of the currently executed image row according to the image coordinate information of path A; Read the B-channel single-edge data signal 2 lines ahead of the currently executed image line.

[0017] Optionally, in the FPGA-based stereoscopic image display method, the method of judging whether the A-channel image signal and the B-channel image signal meet preset conditions and selecting to output the A-channel image signal or the B-channel image signal according to the judgment result includes: Determine whether the R channel value, B channel value and G channel value in the B-channel image signal are all greater than the first preset channel threshold. If so, output the B-channel image signal. Otherwise, determine whether the R channel value, B channel value and G channel value in the A-channel image signal are all greater than the second preset channel threshold. If so, output the A-channel image signal. Otherwise, output the default blue background image.

[0018] The present invention provides a FPGA-based stereoscopic image display system and method, comprising: an acquisition module, used for receiving an A-channel image source signal and a B-channel image source signal, and respectively sampling and processing the A-channel image source signal and the B-channel image source signal to obtain an A-channel single-edge data signal in a YUV format and a B-channel single-edge data signal in a YUV format; a processing module, used for storing the B-channel single-edge data signal in a DDR particle, using the clock of the A-channel single-edge data signal as a reference clock, reading the B-channel single-edge data signal in the DDR particle, and then performing image overlap processing on the A-channel single-edge data signal and the B-channel single-edge data signal according to a chromaticity value to obtain a fused stereoscopic image signal; and an output module, used for outputting the stereoscopic image signal to display a stereoscopic image. By sampling and processing the image source signal to obtain a single-edge data signal in YUV format, the frequency of the image data becomes lower and the bit width becomes larger, which is conducive to giving full play to the ability of FPGA to process parallel data. At the same time, the amount of image data is reduced by half compared with the RGB format, thereby effectively saving the internal storage resources of the FPGA; by storing the B-channel single-edge data signal in the DDR particle and using the clock of the A-channel single-edge data signal as the reference clock to read the data in the DDR particle, not only can the space cost of storing the image in the DDR be saved, but also the resolution information of the image source signal can be more efficiently and automatically identified, avoiding the asynchronous timing caused by the use of the local clock, and improving the image frame rate, thereby improving the clarity of the stereoscopic image display, and solving the problem that the existing FPGA-based stereoscopic image display technology occupies a large amount of storage resources and has low display clarity. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 A block diagram of the FPGA-based stereoscopic image display system provided in this embodiment; Figure 2 A schematic diagram of the structure of the A-channel image source acquisition unit provided in this embodiment; Figure 3 A schematic diagram of the structure of a B-channel image source acquisition unit provided in this embodiment; Figure 4 A schematic diagram of the structure of the processing module provided in this embodiment; Figure 5 A schematic diagram of the structure of the storage control unit provided in this embodiment; Figure 6 A schematic diagram of the structure of a color gamut conversion unit provided in this embodiment; Figure 7 A flowchart of a FPGA-based stereoscopic image display method provided in this embodiment; Figure 8 A schematic diagram of data storage in the read storage space provided in this embodiment; Fig. 9 A schematic diagram of the color gamut conversion unit provided in this embodiment reading a B-channel single-edge data signal from a read storage space; Fig.10 A schematic diagram of converting the B-channel signal provided in this embodiment from the YUV format to the RGB format. DETAILED DESCRIPTION

[0020] The following is a further detailed description of the FPGA-based stereoscopic image display system and method proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the accompanying drawings is often a part of the actual structure. In particular, the emphasis of each accompanying drawing is different, and sometimes different proportions are used.

[0021] It should be noted that the terms "first", "second", etc. in the specification, claims and drawings of the present invention are used to distinguish similar objects in order to describe the embodiments of the present invention, rather than to describe a specific order or sequence. It should be understood that the structures used in this way can be interchanged under appropriate circumstances. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0022] In order to clearly illustrate the implementation scheme of the transceiver delay calibration system and method provided in this embodiment, the technical terms involved in this embodiment are explained as follows: FPGA: Field Programmable Gate Array, field programmable gate array; DDR SDRAM: Double Data Rate Synchronous Dynamic Random Access Memory, double data rate synchronous dynamic random access memory, referred to as DDR; IDDR: input double-data-rate, input double data rate; MC: Memory Controller, memory controller; PHY: Physical Layer, physical layer; FIFO: First Input First Output, first in first out; RAM: Random Access Memory, random access memory; RGB: Read Green Blue, red, green and blue primary colors; YUV: YCbCr, a color encoding based on brightness and chrominance; CMD:Command, command; BANK: a block in DDR; TTL: Transistor Transistor Logic, level standard; HDMI: High Definition Multimedia Interface, high-definition multimedia interface; DE: A single-bit synchronization signal used for stereoscopic image display, indicating the effective display portion of the image; HS: A single-bit synchronization signal used for stereoscopic image display, indicating the starting point of each line of the image; VS: A single-bit synchronization signal used for stereoscopic image display, indicating the start mark of each frame of the image.

[0023] This embodiment provides a 3D image display system based on FPGA, such as Figure 1 As shown, including: An acquisition module is used to receive an A-channel image source signal and a B-channel image source signal, and sample and process the A-channel image source signal and the B-channel image source signal to obtain an A-channel single-edge data signal in a YUV format and a B-channel single-edge data signal in a YUV format; A processing module is used to store the B-channel single-edge data signal in the DDR particle, and use the clock of the A-channel single-edge data signal as a reference clock to read the B-channel single-edge data signal in the DDR particle, and then perform image overlap processing on the A-channel single-edge data signal and the B-channel single-edge data signal according to the chrominance value to obtain a fused stereoscopic image signal; The output module is used to output a stereoscopic image signal to display a stereoscopic image.

[0024] The FPGA-based stereoscopic image display system provided in this embodiment obtains a single-edge data signal in a YUV format by sampling and processing the image source signal, so that the frequency of the image data becomes lower and the bit width becomes larger, which is conducive to giving full play to the ability advantage of FPGA in processing parallel data. At the same time, the amount of image data is reduced by half compared with the RGB format, thereby effectively saving the internal storage resources of the FPGA; by storing the B-channel single-edge data signal in a DDR particle and using the clock of the A-channel single-edge data signal as a reference clock to read the data in the DDR particle, not only can the space cost of storing the image in the DDR be saved, but also the resolution information of the image source signal can be more efficiently and automatically identified, avoiding asynchronous timing caused by the use of a local clock, thereby improving the image frame rate, and thus improving the clarity of the stereoscopic image display, solving the problem that the existing FPGA-based stereoscopic image display technology occupies a large amount of storage resources and has a low display clarity.

[0025] Specifically, in this embodiment, the acquisition module includes an A-channel image source acquisition unit and a B-channel image source acquisition unit.

[0026] The A-channel image source acquisition unit is used to acquire the A-channel image source signal, and perform sampling processing on the A-channel image source signal to generate the A-channel single-edge data signal, A-channel synchronization signal and A-channel image coordinate information in YUV format.

[0027] In a specific embodiment, the A-channel image source signal includes an A-channel image data signal rxa_ttl, an A-channel DE synchronization signal rxa_rtl_de, an A-channel VS synchronization signal rxa_rtl_vs, and an A-channel HS synchronization signal rxa_rtl_hs. Figure 2 As shown, the A-channel image source acquisition unit includes an A-channel image data processing circuit and an A-channel synchronization signal processing circuit. Specifically, the A-channel synchronization signal processing circuit includes three branches to process three synchronization signals respectively.

[0028] The A-channel image data processing circuit is used to convert the A-channel image data signal from a double-edge data signal to a clock single-edge data signal using IDDR, and then perform splicing processing to obtain the A-channel single-edge data signal in YUV format. Figure 2As shown, the A-channel image data signal rxa_ttl is a signal for double data transmission, usually with a bit width of 36 bits. In order to facilitate subsequent data processing, in this embodiment, the high 32-bit data is intercepted as the A-channel effective image data signal. After passing through the internal hard-core IDDR of the FPGA, the double data A-channel effective image data signal rxa_ttl is parsed into a group of two 32-bit-wide clock single-edge data rxa_ttl_x and rxa_ttl_y. These two data are parallel, so they can be spliced ​​to form a group of 64-bit data, thereby obtaining the A-channel single-edge data signal rxa_data. In addition, since the input A-channel image data signal is in YUV format, the obtained A-channel single-edge data signal is also in YUV format, specifically, it can be in YUV420 format.

[0029] The A-channel synchronous signal processing circuit is used to use IDDR to convert the A-channel DE synchronous signal, the A-channel VS synchronous signal and the A-channel HS synchronous signal from double-edge data signals to clock single-edge data signals, and then perform OR operations to obtain the A-channel single-edge DE synchronous signal, the A-channel single-edge VS synchronous signal and the A-channel single-edge HS synchronous signal. Figure 2 As shown, the A-channel DE synchronization signal rxa_rtl_de, the A-channel VS synchronization signal rxa_rtl_vs and the A-channel HS synchronization signal rxa_rtl_hs are single-bit indication signals. After passing through the internal hard-core IDDR of the FPGA, the double data A-channel DE synchronization signal rxa_rtl_de is parsed into a group of 2 clock single-edge data rxa_de_x and rxa_de_y; similarly, the double data A-channel VS synchronization signal rxa_rtl_vs is parsed into a group of 2 clock single-edge data rxa_vs_x and rxa_vs_y, and the double data A-channel HS synchronization signal rxa_rtl_hs is parsed into a group of 2 clock single-edge data rxa_hs_x and rxa_hs_y. Afterwards, each group of clock single-edge data is respectively OR-operated to obtain a single-edge image synchronization signal, that is, rxa_de_x and rxa_de_y are OR-operated to obtain the A-path single-edge DE synchronization signal rxa_de; rxa_vs_x and rxa_vs_y are OR-operated to obtain the A-path single-edge VS synchronization signal rxa_vs; rxa_hs_x and rxa_hs_y are OR-operated to obtain the A-path single-edge HS synchronization signal rxa_hs.

[0030] The A-channel image source acquisition unit also includes an A-channel frame start circuit and an A-channel coordinate generation circuit. Figure 2As shown, the A-channel single-edge VS synchronization signal rxa_vs is input to the A-channel frame start circuit, and its rising edge is detected according to the sampling clock, thereby generating the A-channel coordinate flag signal vsa_flag. Since the VS synchronization signal represents the starting coordinates of each frame, the A-channel coordinate flag signal vsa_flag is used to inform the starting point and end point of the coordinate generation. The A-channel coordinate flag signal vsa_flag and the A-channel single-edge HS synchronization signal rxa_hs are input to the A-channel coordinate generation circuit. Since the HS synchronization signal represents the starting point of each row of the image, that is, the coordinate starting point of cnt_x, when the A-channel coordinate flag signal vsa_flag is received, cnt_y in the coordinate generation circuit begins to accumulate. For each additional row of the A-channel single-edge HS synchronization signal rxa_hs, the number of rows of cnt_y is increased by 1, thereby generating the A-channel image coordinate information cnt_x and cnt_y.

[0031] In addition, the B-channel image source acquisition unit is used to acquire the B-channel image source signal, and sample and process the B-channel image source signal to generate a B-channel single-edge data signal, a storage indication signal and a write instruction in a YUV format, so as to store the B-channel single-edge data signal in a YUV format in a write storage space according to the storage indication signal and the write instruction.

[0032] In a specific embodiment, the B-channel image source signal includes a B-channel image data signal rxb_ttl, a B-channel DE synchronization signal rxb_rtl_de, a B-channel VS synchronization signal rxb_rtl_vs, and a B-channel HS synchronization signal rxb_rtl_hs. Figure 3 As shown, the B-channel image source acquisition unit includes a B-channel image data processing circuit and a B-channel synchronization signal processing circuit. Similar to the A-channel synchronization signal processing circuit, the B-channel synchronization signal processing circuit also includes three branches to process the three synchronization signals respectively.

[0033] The B-channel image data processing circuit is used to convert the B-channel image data signal from a double-edge data signal to a clock single-edge data signal using IDDR, and then perform splicing processing to obtain a B-channel single-edge data signal in YUV format. The processing process is similar to that of the A-channel image data processing circuit. Figure 3As shown, the B-channel image data signal rxb_ttl is a signal for double data transmission, usually with a bit width of 36 bits. In order to facilitate subsequent data processing, in this embodiment, the high 32-bit data is intercepted as the B-channel effective image data signal. After passing through the internal hard-core IDDR of the FPGB, the double data B-channel effective image data signal rxb_ttl is parsed into a group of two 32-bit-wide clock single-edge data rxb_ttl_x and rxb_ttl_y. These two data are parallel, so they can be spliced ​​to form a group of 64-bit data, thereby obtaining the B-channel single-edge data signal rxb_data. In addition, since the input B-channel image data signal is in YUV format, the obtained B-channel single-edge data signal is also in YUV format, specifically, it can be in YUV420 format.

[0034] The B-channel synchronous signal processing circuit is used to use IDDR to convert the B-channel DE synchronous signal, the B-channel VS synchronous signal and the B-channel HS synchronous signal from double-edge data signals to clock single-edge data signals, and then perform OR operations to obtain the B-channel single-edge DE synchronous signal, the B-channel single-edge VS synchronous signal and the B-channel single-edge HS synchronous signal. The processing process is similar to that of the A-channel synchronous signal processing circuit. Figure 3 As shown, the B-channel DE synchronization signal rxb_rtl_de, the B-channel VS synchronization signal rxb_rtl_vs and the B-channel HS synchronization signal rxb_rtl_hs are single-bit indication signals. After passing through the internal hard core IDDR of the FPGB, the B-channel DE synchronization signal rxb_rtl_de of the double data is parsed into a group of 2 clock single-edge data rxb_de_x and rxb_de_y; similarly, the B-channel VS synchronization signal rxb_rtl_vs of the double data is parsed into a group of 2 clock single-edge data rxb_vs_x and rxb_vs_y, and the B-channel HS synchronization signal rxb_rtl_hs of the double data is parsed into a group of 2 clock single-edge data rxb_hs_x and rxb_hs_y. Afterwards, each group of clock single-edge data is respectively ORed to obtain a single-edge image synchronization signal, that is, rxb_de_x and rxb_de_y are ORed to obtain the B-path single-edge DE synchronization signal rxb_de; rxb_vs_x and rxb_vs_y are ORed to obtain the B-path single-edge VS synchronization signal rxb_vs; rxb_hs_x and rxb_hs_y are ORed to obtain the B-path single-edge HS synchronization signal rxb_hs.

[0035] The B-channel image source acquisition unit also includes a B-channel frame start circuit, a B-channel coordinate generation circuit and a write address generation circuit. Figure 3As shown, the B-channel single-edge VS synchronization signal rxb_vs is input to the B-channel frame start circuit, and its rising edge is detected according to the sampling clock, thereby generating the B-channel coordinate flag signal vsb_flag. Since the VS synchronization signal represents the starting coordinates of each frame, the B-channel coordinate flag signal vsb_flag is used to inform the starting point and end point of the coordinate generation; at the same time, the B-channel frame start circuit also outputs a storage indication signal fram, which is used to guide the data to be stored in a specific area of ​​the BANK of the DDR particle. The B-channel coordinate flag signal vsb_flag and the B-channel single-edge HS synchronization signal rxb_hs are input to the B-channel coordinate generation circuit. Since the HS synchronization signal represents the starting point of each line of the image, that is, the coordinate starting point of cnt_x, when the B-channel coordinate flag signal vsb_flag is received, cnt_y in the coordinate generation circuit begins to accumulate, and the number of lines of cnt_y is increased by 1 for each additional line of the B-channel single-edge HS synchronization signal rxb_hs, thereby generating the B-channel image coordinate information cnt_x and cnt_y. The B-channel single-edge DE synchronization signal rxb_de and the B-channel image coordinate information cnt_x and cnt_y are input to the write address generation circuit, and the write address generation circuit generates a write instruction. The write instruction includes the write FIFO command signal rx_rfifo_we (write FIFO enable signal), rx_rfifo_wdata (write FIFO data signal), rx_ram_we (write storage enable signal), and rx_ram_addr (write storage address signal), among which rx_rfifo_wdata can identify the data image width and the current number of rows from the B-channel single-edge data signal rxb_data.

[0036] Preferably, in order to temporarily store the generated write instruction and B-way single-edge data signal so as to facilitate the subsequent functional unit in the processing module to retrieve and use, in this embodiment, the acquisition module is also configured with a B-way storage unit and a B-way FIFO unit. When a row of valid image data input ends, that is, when the falling edge of the B-way single-edge DE synchronization signal rxb_de arrives, the generated rx_rfifo_we (write FIFO enable signal) and rx_rfifo_wdata (write FIFO data signal) are sent to the B-way FIFO unit. At the same time, according to the image valid interval, that is, according to the rising edge of the B-way single-edge DE synchronization signal rxb_de and the row and column information of the B-way coordinate generation circuit, the generated rx_ram_we (write storage enable signal) and rx_ram_addr (write storage address signal) are alternately sent to the B-way storage unit. When the HS synchronization signal arrives, it means that a new row of image data has arrived, the low bit of the address information is reset to 0, and the high bit is inverted to realize ping-pong storage.

[0037] Furthermore, in this embodiment, if Figure 4As shown, the processing module includes an image recovery unit, a storage control unit and a color gamut conversion unit.

[0038] The image recovery unit is used to recover the image synchronization information and the bit width of the image data according to the A-channel image coordinate information, and generate a read instruction at the same time. Figure 4 As shown, the image recovery unit receives the A-channel image coordinate information cnt_x / cnt_y output by the A-channel image source acquisition unit, and then performs recovery processing on the image signal converted by the color gamut conversion unit; the generated read instruction is sent to the storage control unit to read out the required B-channel single-edge data signal through the storage control unit. In addition, the image recovery unit is also used to receive the image signal output by the color gamut conversion unit, and output a stereoscopic image signal after adding synchronization information to the image signal.

[0039] And, the storage control unit is used to parse the write instruction and the read instruction to read the B-way single-edge data signal in the YUV format stored in the write storage space into the read storage space. In this embodiment, the write storage space can be a B-way storage unit.

[0040] In practical applications, such as Figure 4 and Figure 5 As shown, the storage control unit is externally connected to a DDR particle. In this embodiment, the DDR particle may be DDR2. Figure 4 As shown, the storage control unit includes a command arbitration circuit, a read and write data state machine, a control signal generation circuit, a memory controller and a DDR physical layer.

[0041] The command arbitration circuit is used to receive write instructions and read instructions, and start the read / write data state machine according to the write instruction or the read instruction in a first-in-first-out arbitration mode. Specifically, the write instruction and the read instruction are obtained through the control pins rx_fifo_re and rx_fifo_rdata of the external write FIFO module and the control pins tx_fifo_re and tx_fifo_rdata of the external read FIFO module.

[0042] It should be noted that the write instruction here is different from the write instruction generated by the write address generation circuit in the B-channel image acquisition unit; the read instruction is different from the read instruction generated by the image recovery unit. The write instruction and read instruction here are both issued by the external module to control the start of the read and write data state machine and to confirm whether to perform a read operation or a write operation.

[0043] Furthermore, the read / write data state machine is used to generate an address signal and a read / write command for controlling the DDR physical layer according to a write instruction or a read instruction.

[0044] Furthermore, the control signal generating circuit is used to generate a read address signal and a read enable signal according to a write instruction; and is also used to generate a write address signal and a write enable signal according to a read instruction. Figure 5 As shown, the control signal generating circuit includes a read signal generating circuit and a write signal generating circuit. The read signal generating circuit is used to generate a read address signal rx_ram_raddr and a read enable signal rx_ram_re according to a read storage data signal rx_ram_rdata, wherein the read storage data signal rx_ram_rdata is a 128-bit data signal provided by an external module according to a write instruction; similarly, the write signal generating circuit is used to generate a write address signal tx_ram_waddr and a write enable signal tx_ram_we according to a write storage data signal tx_ram_wdata, wherein the write storage data signal tx_ram_wdata is a 128-bit data signal provided by an external module according to a read instruction.

[0045] Furthermore, the memory controller is used to send data signals in the write storage space to the DDR particles through the DDR physical layer using address signals, read and write commands, read address signals and read enable signals; and is also used to read data signals from the DDR particles through the DDR physical layer and write them into the read storage space using address signals, read and write commands, write address signals and write enable signals.

[0046] The entire write process of the storage control unit is roughly as follows: the command arbitration circuit controls the start of the read-write data state machine according to the external control write signal; the read-write data state machine generates the necessary address signals and write instructions to control the DDR physical layer, and the read signal generation circuit reads the data in the write storage space according to the read address signal and the read enable signal, and passes it to the memory controller; the memory controller writes the acquired data into the DDR particles through the DDR physical layer according to the address signal and the write instruction.

[0047] The entire reading process of the storage control unit is roughly as follows: the command arbitration circuit controls the start of the read and write data state machine according to the external control read signal; the read and write data state machine generates the necessary address signals and read instructions to control the DDR physical layer, and the memory controller reads the data in the DDR particles through the DDR physical layer according to the address signal and read instruction, and provides it to the write signal generation circuit; the write signal generation circuit writes the read data into the read storage space according to the write address signal and write enable signal.

[0048] In practical applications, the storage control unit can use the clock of the single-edge data signal of channel A to generate the working clock of the DDR particles, thereby maximizing the high-bandwidth performance of the DDR particles and improving the data reading and writing efficiency.

[0049] In this embodiment, the storage control unit stores the B-channel single-edge data signal read from the write storage space in the DDR particles, and then the storage control unit reads the data in the DDR particles to the read storage space. Since the DDR particles themselves have a very high working speed, the DDR physical layer (DDR PHY) in the storage control unit is a hard core in the FPGA, which can multiply the data and better adapt the data output by the memory controller (MC) to the timing of the DDR particles. In this way, the MC can quickly operate the DDR particles. By using time division multiplexing, the reading and writing of multiple lines of DDR data can be completed within the display period of one line of image.

[0050] Furthermore, the color gamut conversion unit is used to convert the A-channel single-edge data signal in YUV format generated by the A-channel image source acquisition unit into an A-channel image signal in RGB format, and to convert the B-channel single-edge data signal in YUV format in the read storage space into an B-channel image signal in RGB format; and is also used to determine whether the A-channel image signal and the B-channel image signal meet preset conditions, and select to output the A-channel image signal or the B-channel image signal according to the determination result.

[0051] In actual applications, the color gamut conversion unit can know the specific position of the real-time image in a frame through the input A-channel image coordinate information cnt_x / cnt_y. According to the initial coordinate position of each line, the data of the corresponding line of the B-channel image stored in the DDR particles is read 2 lines in advance. The BANK of the read data is the location where the previous frame of the image currently written to the DDR is stored. In this way, the display frame offset caused by the difference in the frequency of the A and B-channel image data can be effectively prevented, and the stereoscopic display effect of the final output image can be guaranteed.

[0052] Since RGB image data is the most basic three primary colors, the color levels increase in decimal order; while the YUV format is a conversion method based on the brightness of the color, and the value of Y does not increase as the color deepens, the image data must be converted to RGB format to accurately determine the pixel value.

[0053] like Figure 6As shown, the A-channel single-edge data signal in the YUV format output by the A-channel image source acquisition unit is converted into the A-channel image signal in the RGB format via the A-channel RGB conversion circuit; the B-channel single-edge data signal read from the read storage space is converted into the B-channel image signal in the RGB format via the B-channel RGB conversion circuit. Then the A-channel image signal and the B-channel image signal in the RGB format are judged by the judgment selection circuit to determine whether to output the A-channel image signal or the B-channel image signal according to the judgment result to obtain the image signal. In a specific embodiment, it can be first judged whether the R channel value, the B channel value and the G channel value in the B-channel image signal are all greater than the first preset channel threshold value. If so, the B-channel image signal is output. Otherwise, it is judged whether the R channel value, the B channel value and the G channel value in the A-channel image signal are all greater than the second preset channel threshold value. If so, the A-channel image signal is output, otherwise the default blue background image is output, thereby obtaining the image signal.

[0054] Among them, the values ​​of the first preset channel threshold and the second preset channel threshold can be reasonably set according to actual needs, and the values ​​of the two can be the same or different, and this application does not impose any restrictions on this.

[0055] In practical applications, in order to reduce the amount of conversion calculations of the color gamut conversion unit, only the B-channel single-edge data signal can be converted, and the A-channel single-edge data signal can be used as the base image without conversion. In this way, when making a judgment, only the R channel value, B channel value and G channel value in the B-channel image signal are judged whether they are all greater than the preset channel threshold. If so, the B-channel single-edge data signal is output, otherwise, the A-channel single-edge data signal is output.

[0056] In practical applications, the FPGA-based stereoscopic image display system provided in this embodiment can also be configured with a flash memory module, a power module, etc., so that the flash memory module is used to store the program of the internal function of the FPGA, and the power module is used to power each module, so that the FPGA automatically loads the program after power-on to achieve stereoscopic image display.

[0057] The FPGA-based stereoscopic image display system provided in this embodiment inputs two different image sources, which are divided into an upper image and a lower base image, and then overlaps the images according to the chromaticity value, selectively outputs the pixels of the upper image, and replaces the unselected parts with the base image, thereby achieving a stereoscopic effect. The difference between this system and the prior art is that it uses built-in DDR particles to reduce the user's design of external circuit processes; at the same time, the data processing part uses the YUV format, thereby effectively compressing the data volume and realizing low-cost stereoscopic image display; in addition, users can also create the text to be displayed by themselves to realize the watermark function, and can also add some dynamic picture effects on the basis of the original base image to enhance the visual appeal of the original image.

[0058] The FPGA-based stereoscopic image display system provided in this embodiment uses the clock of the A channel image as the reference clock of the system for both input and output, making it easier for the product to converge in timing and run faster, and can easily achieve two-way image display with 2k resolution and 144 frame rate or 4K 60Hz display. If the DDR performance is further improved or a higher level FPGA is used, a 4K 144Hz display can also be achieved. The system is suitable for application scenarios with extremely high refresh rate requirements. In addition, the system is based on FPGA, which reduces the internal logic circuit of the FPGA, thereby reducing the power consumption of the system, and the high integration of functional modules is conducive to the long-term maintenance of the product.

[0059] This embodiment also provides a FPGA-based stereoscopic image display method, which is applied to the FPGA-based stereoscopic image display system as described above. Figure 7 As shown, the FPGA-based stereoscopic image display method includes: S1 receives A-channel image source signals and B-channel image source signals respectively.

[0060] Specifically, in this embodiment, the A-channel image source signal includes an A-channel image data signal, an A-channel DE synchronization signal, an A-channel VS synchronization signal and an A-channel HS synchronization signal; the B-channel image source signal includes a B-channel image data signal, a B-channel DE synchronization signal, a B-channel VS synchronization signal and a B-channel HS synchronization signal.

[0061] In practical applications, the A-channel image source signal and the B-channel image source signal can be input through an external high-definition video chip (HDMI chip). In addition, the A-channel image data signal and the B-channel image data signal can be image data signals in YUV420 format, thereby effectively reducing the amount of image data.

[0062] The data format output by the HDMI chip used here is HDMI2.0 to TTL36bit YUV420 format.

[0063] S2, obtain the A-channel single-edge data signal in YUV format from the A-channel image source signal, and generate the A-channel image coordinate information and read instruction.

[0064] Specifically, in this embodiment, the method for implementing this step includes: S21, using IDDR, converting the A-channel image data signal from a double-edge data signal to a clock single-edge data signal, and then performing splicing processing to obtain the A-channel single-edge data signal in a YUV format; S22, using IDDR, converting the A-channel DE synchronization signal, the A-channel VS synchronization signal, and the A-channel HS synchronization signal from double-edge data signals to clock single-edge data signals, and then performing OR operations on them to obtain the A-channel single-edge DE synchronization signal, the A-channel single-edge VS synchronization signal, and the A-channel single-edge HS synchronization signal; S23, detecting the rising edge of the single-edge VS synchronization signal of channel A according to the sampling clock to generate a coordinate mark signal of channel A; S24, generating the A-channel image coordinate information according to the A-channel coordinate mark signal and the A-channel single-edge HS synchronization signal.

[0065] S3, obtaining a B-channel single-edge data signal in a YUV format from the B-channel image source signal, and generating a storage indication signal and a write instruction.

[0066] Specifically, in this embodiment, the method for implementing this step includes: S31, using IDDR, converting the B-channel image data signal from a double-edge data signal to a clock single-edge data signal, and then performing splicing processing to obtain a B-channel single-edge data signal in a YUV format; S32, using IDDR, converting the B-channel DE synchronization signal, the B-channel VS synchronization signal, and the B-channel HS synchronization signal from double-edge data signals to clock single-edge data signals, and then performing OR operations on them to obtain the B-channel single-edge DE synchronization signal, the B-channel single-edge VS synchronization signal, and the B-channel single-edge HS synchronization signal; S33, detecting the rising edge of the single-edge VS synchronization signal of the B path according to the sampling clock to generate a B path coordinate mark signal and a storage indication signal; S34, generating B-channel image coordinate information according to the B-channel coordinate mark signal and the B-channel single-edge HS synchronization signal; S35, generating a write instruction according to the B-channel image coordinate information and the B-channel single-edge DE synchronization signal.

[0067] It should be noted that, in practical applications, the order of implementation of step S2 and step S3 can be swapped or performed simultaneously, and the adjustment of the order does not affect the implementation of the stereoscopic image display method provided by this application. The technical solution after the order adjustment without violating the main purpose of this application should also fall within the scope of protection of this application.

[0068] S4, storing the B-channel single-edge data signal in the YUV format in a write storage space according to the storage indication signal and the write instruction. Specifically, the write storage space may be a RAM.

[0069] S5, parsing the read instruction and the write instruction to read the B-path single-edge data signal in the YUV format stored in the write storage space into the read storage space via the DDR particles.

[0070] Specifically, in this embodiment, the method for implementing this step includes: S51, receiving a write instruction and a read instruction; S52, generating a read address signal and a read enable signal according to a write instruction in a first-in-first-out arbitration manner; S53, reading a data signal from the write storage space according to the read address signal and the read enable signal, and sending the read data signal to the DDR particle through the DDR physical layer according to the address signal and the read / write command; S54, generating a write address signal and a write enable signal according to the read instruction in a first-in-first-out arbitration manner; S55, reading data signals from DDR particles through the DDR physical layer according to the address signal and the read / write command, and writing the read data signals into the read storage space according to the write address signal and the write enable signal.

[0071] Specifically, in this embodiment, considering that the data signal in the read storage space needs to be converted from the YUV format to the RGB format later, the read storage space needs to be divided into two independent RAMs to sequentially store the read data signals of channel B. Figure 8 As shown, the B-channel image data read from the DDR particles are stored in sequence: the low bit txb_ram00 of the first RAM, the low bit txb_ram10 of the second RAM, the high bit rxb_ram01 of the first RAM, and the high bit rxb_ram11 of the second RAM. The read data is read in parallel according to the low or high bits of the two RAMs, and the same address is read out to the color gamut conversion unit for format conversion calculation.

[0072] S6, converting the A-channel single-edge data signal in the YUV format into the A-channel image signal in the RGB888 format, and converting the B-channel single-edge data signal in the YUV format in the read storage space into the B-channel image signal in the RGB888 format.

[0073] Specifically, in practical applications, the method of converting the A-channel single-edge data signal in the YUV format into the A-channel image signal in the RGB888 format can be implemented by using the existing conventional format conversion method. In order to reduce the amount of calculation for color gamut conversion, the A-channel single-edge data signal may not be converted.

[0074] For the conversion of the B-channel single-edge data signal, it is necessary to first obtain the initial coordinate position of the currently executed image row based on the A-channel image coordinate information; then, read the B-channel single-edge data signal 2 rows in advance of the currently executed image row, and then perform format conversion.

[0075] When converting the B-channel single-edge data signal to RGB format, since the B-channel single-edge data signal is stored in YUV format, that is, the data stored in a YUV is converted from the image data distributed on two rows of RGB, at least two rows of YUV420 images are required to calculate the corresponding two complete RGB image rows. The specific calculation formula is as follows, using the YUV to RGB formula in the BT2020 protocol, where Cb corresponds to U and Cr corresponds to V:

[0076]

[0077]

[0078] Since the calculation method of the stereoscopic image display system of this embodiment is implemented based on FPGA, both sides of the above equation can be multiplied by 256 and the decimal places in the formula can be removed, so that the FPGA can directly perform the calculation.

[0079] Take the first pixel converted to RGB888 as an example. Fig. 9 and Fig.10 As shown, the pixel values ​​stored in the first position of txb_ram0 and txb_ram1 are read out at the same time, where txb_ram0 stores the pixel information of the first row, then the first YUV pixel point of the first row is Fig.10 The first pixel in the second row is represented by Y00, U00, V10, and so on. The first pixel value of "RGB0" in the first row can be obtained through the logic operation of FPGA. Similarly, the next pixel to be calculated is the third YUV value "RGB2" in the first row.

[0080] S7, judging whether the A-channel image signal and the B-channel image signal meet a preset condition, and selecting to output the A-channel image signal or the B-channel image signal according to the judging result.

[0081] Specifically, after color gamut conversion is performed on the A-channel single-edge data signal and the B-channel single-edge data signal, it can be determined whether the R channel value, the B channel value and the G channel value in the B-channel image signal are all greater than the first preset channel threshold. If so, the B-channel image signal is output; otherwise, it is determined whether the R channel value, the B channel value and the G channel value in the A-channel image signal are all greater than the second preset channel threshold. If so, the A-channel image signal is output; otherwise, the default blue background image is output.

[0082] If only the B-channel single-edge data signal is converted into color gamut, it can be determined whether the R channel value, B channel value and G channel value in the B-channel image signal are all greater than the preset channel threshold. If so, the B-channel single-edge data signal is output; otherwise, the A-channel single-edge data signal is output.

[0083] In a specific embodiment, the value of the preset channel threshold may be 50. Of course, in other embodiments, the value of the channel threshold may be reasonably set according to actual needs, and the present application does not limit this.

[0084] S8, adding synchronization information to the output image signal and then outputting a stereoscopic image signal.

[0085] In this embodiment, the image restoration unit can be used to add synchronization information to the output image signal. At this time, the format of the output image signal is still in YUV format. That is to say, the purpose of the color gamut conversion unit in performing the color gamut conversion in step S6 is to achieve the judgment in step S7, but when outputting the image signal, the image signal in YUV format is still selected for output to reduce the amount of data in the FPGA.

[0086] And, in this embodiment, the image recovery unit generates external synchronization data of a valid image according to the image coordinate information, including HS, DE, and VS information, and restores the image data to 36 bits, and outputs a stereoscopic image signal after aligning the synchronization information.

[0087] Finally, the stereoscopic image signal is output through an external high-definition video chip (HDMI chip), thus displaying a stereoscopic effect.

[0088] The data format output by the HDMI chip used here is the conversion of YUV420 36-bit TTL data into HDMI2.0 data that can be transmitted over long distances.

[0089] The FPGA-based stereoscopic image display method provided in this embodiment receives two different image sources, divides them into an upper image and a lower base image, and then overlaps the images according to the chromaticity value, selectively outputs the pixels of the upper image, and replaces the unselected parts with the base image, thereby achieving a stereoscopic effect. At the same time, the data processing part uses the YUV format, thereby effectively compressing the data volume and realizing low-cost stereoscopic image display.

[0090] The FPGA-based stereoscopic image display method provided in this embodiment uses the clock of the A channel image as the reference clock of the system for both input and output, making it easier for the product to converge in timing and run faster, and can easily achieve two-way image display with 2k resolution and 144 frame rate or 4K 60Hz display. If the DDR performance is further improved or a higher level FPGA is used, a 4K 144Hz display can also be achieved. The system is suitable for application scenarios with extremely high refresh rate requirements. In addition, the system is based on FPGA, which reduces the internal logic circuit of the FPGA, thereby reducing the power consumption of the system, and the high integration of functional modules is conducive to the long-term maintenance of the product.

[0091] In the FPGA-based stereoscopic image display method provided in this embodiment, the read storage space uses two RAMs to cross-store the B-channel image data read from the DDR particles. At the same time, the data is read in advance according to the synchronization information of the A-channel image, which saves the space cost of storing the image in the DDR and avoids the asynchronous timing caused by the use of the local clock, resulting in a low output frame rate. In addition, the RGB format data obtained by conversion is only used for the judgment of the output image signal, and the YUV format is still used during transmission, thereby avoiding the image color error during the RGB data transmission process and improving the display effect of the stereoscopic image.

[0092] The FPGA-based stereoscopic image display method provided in this embodiment is different from the prior art in that the FPGA uses built-in DDR particles, which reduces the user's external circuit design process, reduces the debugging cost and circuit development cost. In addition, the user can also create the text to be displayed by himself to realize the watermark function, and can also add some dynamic picture effects on the basis of the original base map to enhance the visual appeal of the original image.

[0093] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other. In addition, the different parts between the various embodiments can also be used in combination with each other, and the present invention is not limited to this.

[0094] The FPGA-based stereoscopic image display system and method provided in this embodiment include: an acquisition module, used to receive an A-channel image source signal and a B-channel image source signal, and sample and process the A-channel image source signal and the B-channel image source signal respectively to obtain an A-channel single-edge data signal in a YUV format and a B-channel single-edge data signal in a YUV format; a processing module, used to store the B-channel single-edge data signal in a DDR particle, and use the clock of the A-channel single-edge data signal as a reference clock to read the B-channel single-edge data signal in the DDR particle, and then perform image overlap processing on the A-channel single-edge data signal and the B-channel single-edge data signal according to the chromaticity value to obtain a fused stereoscopic image signal; an output module, used to output the stereoscopic image signal to display a stereoscopic image. By sampling and processing the image source signal to obtain a single-edge data signal in YUV format, the frequency of the image data becomes lower and the bit width becomes larger, which is conducive to giving full play to the ability of FPGA to process parallel data. At the same time, the amount of image data is reduced by half compared with the RGB format, thereby effectively saving the internal storage resources of the FPGA; by storing the B-channel single-edge data signal in the DDR particle and using the clock of the A-channel single-edge data signal as the reference clock to read the data in the DDR particle, not only can the space cost of storing the image in the DDR be saved, but also the resolution information of the image source signal can be more efficiently and automatically identified, avoiding the asynchronous timing caused by the use of the local clock, and improving the image frame rate, thereby improving the clarity of the stereoscopic image display, and solving the problem that the existing FPGA-based stereoscopic image display technology occupies a large amount of storage resources and has low display clarity.

[0095] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A 3D image display system based on FPGA, characterized in that: include: An acquisition module is used to receive an A-channel image source signal and a B-channel image source signal, and sample and process the A-channel image source signal and the B-channel image source signal to obtain an A-channel single-edge data signal in a YUV format and a B-channel single-edge data signal in a YUV format; A processing module is used to store the B-channel single-edge data signal in the DDR particle, and use the clock of the A-channel single-edge data signal as a reference clock to read the B-channel single-edge data signal in the DDR particle, and then perform image overlap processing on the A-channel single-edge data signal and the B-channel single-edge data signal according to the chrominance value to obtain a fused stereoscopic image signal; The output module is used to output a stereoscopic image signal to display a stereoscopic image.

2. The FPGA-based stereoscopic image display system according to claim 1, characterized in that: The acquisition module includes an A-channel image source acquisition unit and a B-channel image source acquisition unit; The A-channel image source acquisition unit is used to acquire the A-channel image source signal, and perform sampling processing on the A-channel image source signal to generate the A-channel single-edge data signal, the A-channel synchronization signal and the A-channel image coordinate information in the YUV format; The B-channel image source acquisition unit is used to acquire the B-channel image source signal, and sample and process the B-channel image source signal to generate a B-channel single-edge data signal in YUV format, a storage indication signal and a write instruction, so as to store the B-channel single-edge data signal in YUV format in the write storage space according to the storage indication signal and the write instruction.

3. The FPGA-based stereoscopic image display system according to claim 2, characterized in that: The A-channel image source signal includes an A-channel image data signal, an A-channel DE synchronization signal, an A-channel VS synchronization signal and an A-channel HS synchronization signal; the A-channel image source acquisition unit includes an A-channel image data processing circuit and an A-channel synchronization signal processing circuit; The A-channel image data processing circuit is used to convert the A-channel image data signal from a double-edge data signal to a clock single-edge data signal by using IDDR, and then perform splicing processing to obtain the A-channel single-edge data signal in YUV format; The A-channel synchronization signal processing circuit is used to use IDDR to convert the A-channel DE synchronization signal, the A-channel VS synchronization signal and the A-channel HS synchronization signal from double-edge data signals to clock single-edge data signals, and then perform OR operations on them to obtain the A-channel single-edge DE synchronization signal, the A-channel single-edge VS synchronization signal and the A-channel single-edge HS synchronization signal respectively; it is also used to generate the A-channel coordinate mark signal according to the A-channel single-edge VS synchronization signal, and generate the A-channel image coordinate information according to the A-channel coordinate mark signal and the A-channel single-edge HS synchronization signal.

4. The FPGA-based stereoscopic image display system according to claim 2, characterized in that: The B-channel image source signal includes a B-channel image data signal, a B-channel DE synchronization signal, a B-channel VS synchronization signal and a B-channel HS synchronization signal; the B-channel image source acquisition unit includes a B-channel image data processing circuit and a B-channel synchronization signal processing circuit; The B-channel image data processing circuit is used to convert the B-channel image data signal from a double-edge data signal to a clock single-edge data signal by using IDDR, and then perform splicing processing to obtain the B-channel single-edge data signal in YUV format; The B-channel synchronization signal processing circuit is used to use IDDR to convert the B-channel DE synchronization signal, the B-channel VS synchronization signal and the B-channel HS synchronization signal from double-edge data signals to clock single-edge data signals, and then perform OR operation processing to obtain the B-channel single-edge DE synchronization signal, the B-channel single-edge VS synchronization signal and the B-channel single-edge HS synchronization signal respectively; it is also used to generate a B-channel coordinate flag signal and a storage indication signal according to the B-channel single-edge VS synchronization signal, generate B-channel image coordinate information according to the B-channel coordinate flag signal and the B-channel single-edge HS synchronization signal, and generate a write instruction according to the B-channel image coordinate information and the B-channel single-edge DE synchronization signal.

5. The FPGA-based stereoscopic image display system according to claim 2, characterized in that: The processing module includes an image recovery unit, a storage control unit and a color gamut conversion unit; The image recovery unit is used to recover the image synchronization information and the bit width of the image data according to the A-channel image coordinate information, and generate a read instruction at the same time; The storage control unit is used to parse the write instruction and the read instruction to read the B-path single-edge data signal in the YUV format stored in the write storage space into the read storage space; The color gamut conversion unit is used to convert the A-channel single-edge data signal in the YUV format generated by the A-channel image source acquisition unit into the A-channel image signal in the RGB format, and convert the B-channel single-edge data signal in the YUV format in the read storage space into the B-channel image signal in the RGB format; and is also used to determine whether the A-channel image signal and the B-channel image signal meet a preset condition, and select to output the A-channel image signal or the B-channel image signal according to the determination result; The image restoration unit is further used to receive the image signal output by the color gamut conversion unit, and output a stereoscopic image signal after adding synchronization information to the image signal.

6. The FPGA-based stereoscopic image display system according to claim 2, characterized in that: The storage control unit includes a command arbitration circuit, a read and write data state machine, a control signal generation circuit, a memory controller and a DDR physical layer; The command arbitration circuit is used to receive a write instruction and a read instruction, and start the read / write data state machine according to the write instruction or the read instruction in a first-in-first-out arbitration manner; The read / write data state machine is used to generate address information and read / write commands for controlling the DDR physical layer according to a write instruction or a read instruction; The control signal generating circuit is used to generate a read address signal and a read enable signal according to a write instruction; It is also used to generate a write address signal and a write enable signal according to a read instruction; The memory controller is used to send data signals in the write storage space to the DDR particles through the DDR physical layer using address signals, read and write commands, read address signals and read enable signals; and is also used to read data signals from the DDR particles through the DDR physical layer and write them into the read storage space using address signals, read and write commands, write address signals and write enable signals.

7. A 3D image display method based on FPGA, applied to the 3D image display system based on FPGA as claimed in any one of claims 1 to 6, characterized in that: The FPGA-based stereoscopic image display method comprises: Respectively receive channel A image source signal and channel B image source signal; Obtain the A-channel single-edge data signal in YUV format from the A-channel image source signal, and generate the A-channel image coordinate information and read instruction; Obtaining a B-channel single-edge data signal in a YUV format from a B-channel image source signal, and generating a storage indication signal and a write instruction; The B-channel single-edge data signal in the YUV format is stored in the write storage space according to the storage indication signal and the write instruction; Parse the read instruction and the write instruction to read the B-channel single-edge data signal in the YUV format stored in the write storage space into the read storage space via the DDR particles; Convert the single-edge data signal of A channel in YUV format into the image signal of A channel in RGB888 format, and convert the single-edge data signal of B channel in YUV format in the read storage space into the image signal of B channel in RGB888 format; Determine whether the A-channel image signal and the B-channel image signal meet the preset conditions, and select to output the A-channel image signal or the B-channel image signal according to the determination result; After adding synchronization information to the output image signal, a stereoscopic image signal is output.

8. The FPGA-based stereoscopic image display method according to claim 7, characterized in that: The method of obtaining a single-edge data signal of channel A in a YUV format from a channel A image source signal and generating the coordinate information of channel A image comprises: By using IDDR, the A-channel image data signal is converted from a double-edge data signal to a clock single-edge data signal, and then spliced ​​to obtain the A-channel single-edge data signal in YUV format; By using IDDR, the A-channel DE synchronization signal, the A-channel VS synchronization signal and the A-channel HS synchronization signal are respectively converted from double-edge data signals to clock single-edge data signals, and then respectively processed by OR operation to obtain the A-channel single-edge DE synchronization signal, the A-channel single-edge VS synchronization signal and the A-channel single-edge HS synchronization signal; Detect the rising edge of the single-edge VS synchronization signal of channel A according to the sampling clock to generate a coordinate mark signal of channel A; The A-channel image coordinate information is generated according to the A-channel coordinate mark signal and the A-channel single-edge HS synchronization signal.

9. The FPGA-based stereoscopic image display method according to claim 7, characterized in that: The method for obtaining a B-channel single-edge data signal in a YUV format from a B-channel image source signal and generating a storage indication signal and a write instruction comprises: Using IDDR, the B-channel image data signal is converted from a double-edge data signal to a clock single-edge data signal, and then spliced ​​to obtain a B-channel single-edge data signal in a YUV format; By using IDDR, the B-channel DE synchronization signal, the B-channel VS synchronization signal and the B-channel HS synchronization signal are respectively converted from double-edge data signals to clock single-edge data signals, and then respectively processed by OR operation to obtain the B-channel single-edge DE synchronization signal, the B-channel single-edge VS synchronization signal and the B-channel single-edge HS synchronization signal; Detect the rising edge of the single-edge VS synchronization signal of the B-way according to the sampling clock to generate the B-way coordinate mark signal and the storage indication signal; Generate B-channel image coordinate information according to the B-channel coordinate mark signal and the B-channel single-edge HS synchronization signal; Generate a write instruction based on the B-channel image coordinate information and the B-channel single-edge DE synchronization signal.

10. The FPGA-based stereoscopic image display method according to claim 7, characterized in that: The method for parsing the read instruction and the write instruction to read the B-path single-edge data signal in the YUV format stored in the write storage space into the read storage space via the DDR particles includes: Receive write instructions and read instructions; According to the first-in-first-out arbitration method, a read address signal and a read enable signal are generated according to the write instruction; Read the data signal from the write storage space according to the read address signal and the read enable signal, and send the read data signal to the DDR particle through the DDR physical layer according to the address signal and the read and write command; According to the first-in-first-out arbitration method, a write address signal and a write enable signal are generated according to the read instruction; According to the address signal and the read / write command, the data signal is read from the DDR particle through the DDR physical layer, and according to the write address signal and the write enable signal, the read data signal is written into the read storage space.

11. The FPGA-based stereoscopic image display method according to claim 8, characterized in that: Before converting the A-channel single-edge data signal in the YUV format into the A-channel image signal in the RGB888 format, the FPGA-based stereoscopic image display method further includes: Obtain the initial coordinate position of the currently executed image row according to the image coordinate information of path A; Read the B-channel single-edge data signal 2 lines ahead of the currently executed image line.

12. The FPGA-based stereoscopic image display method according to claim 7, characterized in that: The method of judging whether the A-channel image signal and the B-channel image signal meet preset conditions and selecting to output the A-channel image signal or the B-channel image signal according to the judgment result comprises: Determine whether the R channel value, B channel value and G channel value in the B-channel image signal are all greater than the first preset channel threshold. If so, output the B-channel image signal. Otherwise, determine whether the R channel value, B channel value and G channel value in the A-channel image signal are all greater than the second preset channel threshold. If so, output the A-channel image signal. Otherwise, output the default blue background image.

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