Airborne camera calibration method and device

Abstract

Methods and apparatus for onboard camera calibration are disclosed. The disclosed apparatus for an aircraft includes an interface circuit communicatively coupled to a camera of the aircraft, the camera capturing an image; a machine readable instruction; and programmable circuitry to instantiate or execute at least one of the machine-readable instructions to: generate a randomized image from an image stored in a data storage device carried by the aircraft; determining at least a relationship between the image captured by the camera and the randomized image while the aircraft is flying; and determining parameters of the camera to calibrate the camera based on at least the relationship.

Description

Technical Field

[0001] The present disclosure relates generally to onboard cameras of an aircraft, and more particularly to methods and apparatus for onboard camera calibration. Background Art

[0002] Autonomous aircraft, such as unmanned aerial vehicles (UAVs), often use redundancy in their navigation systems. To this end, camera systems are often used as a source of auxiliary information for aircraft navigation. However, such known camera systems may require significant calibration, which is usually performed in a laboratory environment and may be relatively time-consuming and / or result in a long downtime of the aircraft. Summary of the invention

[0003] An example apparatus for an aircraft includes: an interface circuit communicatively coupled to a camera of the aircraft, the camera capturing images; machine-readable instructions; and programmable circuitry for instantiating or executing at least one of the machine-readable instructions to generate a randomized image from images stored in a data storage device carried by the aircraft; determining at least one relationship between an image captured by the camera while the aircraft is flying and the randomized image; and determining parameters of the camera based on the at least one relationship to calibrate the camera.

[0004] An example non-transitory machine-readable storage medium includes instructions that cause a programmable circuit to at least perform the following operations: generate a randomized image from images stored in a data storage device carried by an aircraft; determine at least one relationship between an image captured by a camera of the aircraft while the aircraft is flying and the randomized image; and determine parameters of the camera based on the at least one relationship to calibrate the camera.

[0005] An exemplary method includes: generating a random image from images stored in a data storage device carried by an aircraft by using a programmable circuit to execute instructions; determining at least one relationship between an image captured by a camera of the aircraft while the aircraft is flying and the random image by using the programmable circuit to execute instructions; and calibrating the camera by using the programmable circuit to execute instructions to determine parameters of the camera based on the at least one relationship. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is an example platform on which the examples disclosed herein may be implemented.

[0007] Figure 2 is a block diagram of an example process flow for calibrating a camera according to the teachings of the present disclosure.

[0008] Figure 3 is a block diagram of an example camera calibration circuit in accordance with the teachings of the present disclosure.

[0009] Figure 4An example analysis framework is shown that may be implemented in the examples disclosed herein.

[0010] Figure 5A and Figure 5B Example aspects of image processing that may be implemented in the examples disclosed herein are shown.

[0011] Figure 6 and Figure 7 It means that it can be executed, instantiated and / or implemented by an example programmable circuit to implement Figure 3 Example machine readable instructions and / or a flowchart of example operations of a camera calibration circuit.

[0012] Figure 8 is comprised of an apparatus configured to execute, instantiate and / or perform example machine-readable instructions and / or execute Figure 6 and Figure 7 An example of operating a programmable circuit to implement Figure 3 Block diagram of an example processing platform for a camera calibration circuit.

[0013] Fig. 9 yes Figure 8 A block diagram of an example implementation of a programmable circuit.

[0014] Fig.10 yes Figure 8 A block diagram of another exemplary embodiment of a programmable circuit.

[0015] Generally, the same reference numerals will be used throughout the drawings and the accompanying written description to refer to the same or similar parts. The drawings are not necessarily drawn to scale. Instead, the thickness of a layer or region may be exaggerated in the drawings. Although the drawings show layers and regions with clean lines and boundaries, some or all of these lines and / or boundaries may be idealized. In practice, boundaries and / or lines may be invisible, mixed, and / or irregular. DETAILED DESCRIPTION

[0016] Methods and apparatus for onboard camera calibration are disclosed. Aircraft utilizing vision-based camera systems for navigation and perception capabilities may need to relatively accurately calibrate such camera systems for position and velocity calculations. Degradation of the camera during operation (e.g., caused by vibration, temperature changes, zoom, etc.) may result in relatively small and / or incremental shifts in optical parameters.

[0017] During relatively high altitude flight, a near-planar terrain view from the perspective of the aircraft is a common situation because the downward-facing camera at a relatively high altitude views the terrain, and therefore, the view of the terrain is close to a planar scene. In known systems, the onboard camera can view the runway, which can also represent a scene that is primarily planar. These situations can present geometric advantages for calibrating the camera of the aircraft and can present significant limitations. Although the intrinsic properties of the camera can be estimated when the runway is in view, only a moderate estimate of the distortion model of the camera can be obtained. In addition, these known methods may be invalid during relatively level flights at relatively medium to high altitudes, which is very common in aviation. Other known systems correct the singularities presented at these altitudes by assuming knowledge and / or recognition of the accurate relative displacement between camera images. However, the use of relative displacement may be restrictive and / or require a large amount of hardware or computing resources.

[0018] Examples disclosed herein can effectively and efficiently calibrate (e.g., automatically calibrate) a vehicle's camera during movement of the vehicle. Examples disclosed herein can be utilized in a wide range of altitudes, including relatively high altitudes. Examples disclosed herein can effectively calibrate a camera during flight and / or movement of a vehicle, thereby reducing or eliminating the need for stationary and / or ground-based camera calibration, which can result in downtime and significant labor and cost.

[0019] The examples disclosed herein utilize image registration in conjunction with optical calibration (e.g., homography-based calibration, homography analysis, etc.). Specifically, image registration is a technique for determining the alignment between images of the same scene from different sources (e.g., different perspectives, different viewpoints, etc.). According to the examples disclosed herein, a combination of feature recognition and matching enables the image to be transformed into a common coordinate system. The examples disclosed herein combine and align images from two different sources, including images captured by an onboard camera of an aircraft / vehicle and sample / stored images (e.g., stored satellite images, reference images, database images, orthophotos, geographically referenced terrain images, etc.). The sample / stored images may be previously acquired images of a base plane. Furthermore, the examples disclosed herein determine the relationship (e.g., positional relationship, etc.) between the image captured by the onboard camera and the sample / stored image (e.g., a transformed and / or randomized version of the sample / stored image). The determined relationship is then used to calibrate the onboard camera via, for example, homography-based calibration (e.g., for determining the intrinsic properties of the onboard camera). As a result of the calibration, for example, parameters including a distortion model and / or a posture estimation model may be determined and / or generated. Thus, examples disclosed herein enable calibrating an onboard camera while an aircraft / vehicle is in motion and / or in flight.

[0020] In some examples, a first point of an image from an onboard camera is compared to a second point of a sample / stored image and / or a transformed sample / stored image to determine a relationship. In some examples disclosed herein, an output of the camera is corrected and / or adjusted based on the relationship. In some examples, a distortion model of the camera is generated. Additionally or alternatively, the position of the camera and / or the aircraft is determined (e.g., the position of the aircraft is determined based on a known / assumed spatial relationship between the fuselage of the aircraft and the camera).

[0021] Figure 1 is an example platform 100 on which the examples disclosed herein may be implemented. Figure 1 In the example of FIG. 1 , platform 100 is an unmanned aerial vehicle (UAV) 104. Although Figure 1 The example depicts a UAV, but the example platform 100 may be any other vehicle or movable platform, including but not limited to a manned aircraft, a rotorcraft, an autonomous vehicle, a remotely controlled (RC) vehicle, an automobile, a watercraft (such as a boat), a submarine, and the like.

[0022] The exemplary UAV 104 includes at least one lifting surface (e.g., wing) 110 for maneuvering the UAV when the UAV 104 is self-guided (e.g., autonomously controlled). It should also be understood that other non-aerospace vehicle platforms do not include lifting surfaces (e.g., quadcopters, rockets, etc.). The exemplary UAV 104 also includes control surfaces 112, 114 and a propulsion system 116. The propulsion system 116 can be implemented by propellers, reciprocating engines, turbines, electric motors, rocket propulsion, etc.

[0023] Figure 1 The UAV 104 also includes an image sensor system 118. Figure 1 In the example of FIG. 1 , the image sensor system 118 is an onboard camera (e.g., a monocular camera) capable of recording video and / or images. In the example shown, the camera 118 can be used for navigation. According to the examples disclosed herein, the controller 120 is communicatively coupled to the camera 118 and the data storage device 122. As shown below in conjunction with Figure 2-Figure 10 As discussed in more detail, examples disclosed herein utilize stored images (e.g., stored geo-referenced satellite images, etc.) in conjunction with at least one image obtained / captured by the camera 118 to calibrate the camera 118. Thus, examples disclosed herein may advantageously determine camera parameters while the UAV 104 is in flight, including, but not limited to, properties of the camera 118 (e.g., intrinsic camera properties, extrinsic camera properties, etc.), generated estimated distortion models, etc.

[0024] Figure 2 is a block diagram of an example process flow 200 for tracking and classifying objects according to the teachings of the present disclosure. The example process flow 200 may be composed of Figure 1 In this example, when the UAV 104 ( Figure 1 ) While in flight, the camera 118 is calibrated using a combination of image registration and homography-based calibration techniques.

[0025] At step 202, state data (e.g., flight parameters) of the UAV 104 is obtained and / or determined, for example (e.g., by instruments of the UAV 104 and / or the controller 120). According to examples disclosed herein, the state data may include, but is not limited to, flight parameters, position, orientation, altitude, attitude, uncertainty, etc. In some examples, estimates of intrinsic properties and / or uncertainties of the camera 118 are obtained and / or determined, which estimates may correspond to default / manufacturing values.

[0026] At step 204, according to examples disclosed herein, a randomized sample of transformed location-reference images is generated to define a set of virtual images 206. In this specific example, the transformation is performed on geo-referenced satellite images, which are orthoimages stored in an onboard satellite image database of the aforementioned data storage device 122. Employing transformed orthoimages from a geo-referenced dataset may provide benefits, as the camera pose and its intrinsic properties are well known for these images, and therefore, may provide additional information for automatic calibration, such as the true / actual 3D coordinates of feature points used to calculate homographies between images, thereby increasing the accuracy of homography-based methods.

[0027] At step 208, in this example, the camera 118 ( Figure 1 Thus, in some examples, the relationship between images captured by camera 118 is estimated relative to the virtual images in the aforementioned virtual image 206 (e.g., an initial estimate of the relationship is determined based on the images captured by camera 118 and the points of virtual image 206).

[0028] according to Figure 2 In the example shown, at step 210, a homography-based calibration process is performed (e.g., substantially in real time). According to the examples disclosed herein, a homography-based calibration process is utilized to obtain intrinsic properties of the camera 118, including (but not limited to) focal length, principal point coordinates, etc. Additionally or alternatively, corresponding distortion parameters and / or distortion models of the camera 118 are determined and / or generated. In some examples, the pose and / or extrinsic parameters of the camera may be determined for calibration of the camera 118.

[0029] At step 212, outputs from the calibration process of step 210 are provided, and the example process flow 200 ends. According to some examples disclosed herein, the outputs may include intrinsic information about the camera 118, a distortion model of the camera 118, and / or a pose estimate of the camera 118, etc. However, any other suitable parameters, values, expressions / equations, and / or outputs for calibration and / or adjustment of the output of the camera 118 may alternatively be implemented.

[0030] Figure 3 is a block diagram of an example camera calibration circuit 300 for calibrating the camera 118 during flight and / or movement of the UAV 104. For example, the camera calibration circuit 300 may be used Figure 1 The controller 120 shown in FIG. 1 is implemented. Figure 3 The camera calibration circuit 300 may be instantiated (e.g., created as an instance, brought to any length of time, embodied, implemented, etc.) by a programmable circuit, such as a central processing unit (CPU) executing a first instruction. Additionally or alternatively, Figure 3 The camera calibration system may be instantiated (e.g., created as an instance, brought to any length of time, concretized, implemented, etc.) by (i) an application specific integrated circuit (ASIC) and / or (ii) a field programmable gate array (FPGA) constructed and / or configured to perform operations corresponding to the first instruction in response to the execution of the second instruction. It should be understood that Figure 3 Some or all of the circuits of may thus be instantiated at the same or different times. For example, the circuits may be instantiated in one or more threads that are executed concurrently on the hardware and / or serially on the hardware. Figure 3 In addition, in some examples, Figure 3 Some or all of the circuits may be implemented by microprocessor circuits executing instructions and / or FPGA circuits performing operations for implementing one or more virtual machines and / or containers.

[0031] The illustrated example camera calibration circuit 300 includes an example flight data analyzer circuit 302, an example state data analyzer circuit 304, an example image generator circuit 306, an example image relationship analyzer circuit 308, an example calibrator circuit 310, and an example camera characteristics determiner circuit 312. In this example, the camera calibration circuit 300 includes and / or is communicatively coupled to the data storage device 122.

[0032] The example flight data analyzer circuit 302 is implemented to obtain and / or access flight data of the UAV 104. In the present example, the flight data analyzer circuit 302 accesses, acquires and / or receives data from instruments and / or sensors of the UAV 104. In some examples, the flight data analyzer circuit 302 is instantiated by a programmable circuit that executes flight data analyzer circuit instructions and / or is configured to perform operations such as by Figure 6 and Figure 7 The flowchart represents those operations.

[0033] The state data analyzer circuit 304 of the illustrated example determines and / or calculates state data of the UAV 104 based on data obtained and / or accessed by the flight data analyzer circuit 302. According to some examples described herein, the state data analyzer circuit 304 determines and / or calculates parameters including, but not limited to, the position, orientation, and / or uncertainty of the UAV 104. However, any other suitable parameters / state data may be used instead. In some examples, the state data analyzer circuit 304 is executed by executing state data analyzer instructions and / or is configured to perform operations such as Figure 6 and Figure 7 Those operations represented by the flowchart are instantiated by a programmable circuit.

[0034] exist Figure 3 In the example shown, the image generator circuit 306 generates a transformed randomized sample of stored images (e.g., stored geo-referenced satellite images or aerial images) stored in the aforementioned data storage device 122. Specifically, the example image generator 306 generates a randomized sample of transformed geo-referenced satellite images. According to the examples disclosed herein, based on the position and attitude of the camera 118 (e.g., and their corresponding uncertainties), a sampling of N transformed satellite images is generated. Additionally or alternatively, images are generated based on estimated camera intrinsic properties (e.g., focal length, principal point, etc.). In some examples, the images are randomized by changing the attitude and intrinsic parameters in a substantially random manner. In some examples, the image generator circuit 306 is instantiated by a programmable circuit that executes image generator instructions and / or is configured to perform as described by Figure 6 and Figure 7 The operations represented by the flowchart.

[0035] In the examples herein, the image relationship analyzer circuit 308 determines a relationship (e.g., an initial relationship) between a baseline image (or images) captured by the camera 118 and the image samples generated from the image generator circuit 306. In the examples herein, the baseline image captured by the camera 118 contains at least a certain degree of texture and / or features. According to some examples disclosed herein, at least one of the aforementioned generated image samples is adjusted / transformed / processed based on the image captured by the camera 118. In some examples, the image relationship analyzer circuit 308 is instantiated by a programmable circuit that executes image relationship instructions and / or is configured to perform as described by Figure 6 and Figure 7 The operations represented by the flowchart.

[0036] According to examples disclosed herein, the calibrator circuit 310 is implemented to calibrate the camera 118 based on the aforementioned relationship. In this example, the calibrator circuit 310 calibrates the camera via the example stages described below.

[0037] In a first example stage of calibration performed by the calibrator circuit 310, features are extracted and / or feature matching is performed. In this example, for each of a plurality of images including a reference image obtained by the onboard camera 118 and a generated image, feature points (e.g., feature points that exceed a significant threshold) are extracted. In some examples, feature points are extracted using a scale-invariant feature transform (SIFT) method, which is mentioned in "Object recognition from local scale-invariant features." Proceedings of the Seventh IEEE International Conferenceon Computer Vision 2 pp. 1150-1157, 1999, which is incorporated herein by reference. Subsequently, according to the examples disclosed herein, a matching algorithm such as that described in "Fast Approximate Nearest Neighbors with Automatic Algorithm Configuration," International Conference on Computer Vision Theory and Applications, 2009 (which is incorporated herein by reference) can be used to obtain the correspondence between the feature points of each generated image and the feature points of the reference image. The following is combined with Figure 5B Describe exemplary results of this process.

[0038] In a second example stage of calibration performed by the calibrator circuit 310, homographies are calculated by utilizing the image coordinates of the matching points and information provided by the generated images (e.g., via a known or assumed calibration). In this example stage, a homography is calculated between each generated image and the reference image.

[0039] In a third example stage of calibration, projection beam adjustment is performed by the calibrator circuit 310. In this example stage, distortion effects (not considered in the previous example stages) are taken into account. This example beam adjustment process, which may include nonlinear minimization, is performed to refine the estimated coordinates of the principal point and the parameters of the distortion model.

[0040] In a fourth example stage of calibration, an auto-calibration based on homography is performed by the calibrator circuit 310. In this example stage, an initial guess of the camera focal length is calculated and the coordinates of the principal point are recalibrated, thereby achieving a first estimate of the intrinsic matrix. In this example, the distortion is ignored and / or not included in the calculations because it has already been compensated in the previous example stage.

[0041] In a fifth example calibration phase, a metric reconstruction is performed by the calibrator circuit 310 using the aforementioned initial estimate of the intrinsic matrix of the reference image. In this example, estimates of rotation and translation are obtained, which correspond to the extrinsic parameters of the camera 118 relative to the virtual camera of the generated image. Based on these extrinsic parameters, estimates of the 3D positions of the feature points can be calculated, for example, in world coordinates and / or a world reference system.

[0042] In a sixth example calibration phase, to complete the calibration, a metric bundle adjustment is performed by the calibrator circuit 310. The purpose of this example phase is to refine the 3D coordinates of points in the scene and the intrinsic and extrinsic properties of the camera 118 in a relatively simultaneous manner. The examples disclosed herein can advantageously utilize known parameters of the generated images that provide the actual 3D coordinates of each feature point, thereby constraining the reprojection error, for example, through nonlinear optimization. In some examples, the calibrator circuit 310 is instantiated by a programmable circuit that executes calibrator instructions and / or is configured to perform operations, such as by Figure 6 and Figure 7 The flowchart represents those operations.

[0043] In this example, the camera characteristic determiner circuit 312 is implemented to output parameters of the camera 118, such as properties (e.g., focal length, intrinsic properties, extrinsic properties, etc.) for calibration thereof. Specifically, when the UAV 104 is in flight, the camera 118 can be calibrated using the output parameters. In some examples, the camera characteristic determiner circuit 312 adjusts the output of the camera 118 based on the parameters of the camera 118. Additionally or alternatively, the camera characteristic determiner circuit 312 determines the position of the UAV 104 and / or the camera 118 based on the extrinsic properties of the camera 118 (e.g., in conjunction with known geometric relationships of the UAV 104). In some examples, the camera characteristic determiner circuit 312 is instantiated by a programmable circuit that executes camera characteristic determiner instructions and / or is configured to perform operations such as by Figure 6 and Figure 7 A flowchart represents the operations.

[0044] Figure 4 An example analysis framework that can be implemented in the examples disclosed herein is shown. Figure 4 In the illustrated example, a planar surface (e.g., a ground surface depicted with texture features and / or texture) 401 is shown with a reference coordinate system 403. In the example herein, a first representation 402 of a first viewpoint is shown with an observation plane 404 and projection points 406 corresponding to feature points 410, 412, 414, 416. Further, a second representation 420 of a second viewpoint different from the first viewpoint includes an observation plane 422 with projection points 424 corresponding to the aforementioned feature points 410, 412, 414, 416. The examples disclosed herein utilize the differences between the first representation 402 and the second representation 420 with respect to the feature points 410, 412, 414, 416 to analyze, calculate, and / or characterize the differences between the aforementioned first viewpoint and the second viewpoint.

[0045] Figure 5A and Figure 5B Example aspects of image processing that can be implemented in the examples disclosed herein are shown. Figure 5A , shows an example generation of a transformed satellite image. Figure 5A In the example shown, an input / captured image 502 captured by the camera 118 (e.g., an image from an onboard monocular camera 118 that has not been calibrated) and generated / transformed images 504, 506 are shown. In this example, the images 504, 506 are images generated using different variations (e.g., random variations). The variations may correspond to, for example, intrinsic or extrinsic properties of the UAV 104.

[0046] Figure 5BAn example match between feature points in a reference image 510 captured by the onboard camera 118 and a generated image 512 is depicted. In this example, line 514 indicates the correspondence between feature points in the captured reference image 510 and the generated image 512. Figure 3 As mentioned, these correspondences may be generated using the SIFT method in combination with the FLANN matching algorithm. However, any other feature point extraction / matching method and / or algorithm may be implemented instead.

[0047] Although in Figure 3 The implementation is shown in Figure 3 The camera calibration circuit 300 is an example of a method, but Figure 3 One or more of the elements, processes and / or devices shown in the drawings may be combined, divided, rearranged, omitted, eliminated and / or implemented in any other manner. Figure 3 The example flight data analyzer circuit 302, the example state data analyzer circuit 304, the example image generator circuit 306, the example image relationship analyzer circuit 308, the example calibrator circuit 310, the example camera characteristic determiner 312, and / or more generally the example camera calibration circuit 300 may be implemented by hardware alone or by hardware in combination with software and / or firmware. Thus, for example, any of the example flight data analyzer circuit 302, the example state data analyzer circuit 304, the example image generator circuit 306, the example image relationship analyzer circuit 308, the example calibrator circuit 310, the example camera characteristic determiner 312, and / or more generally the example camera calibration circuit 300 may be implemented by programmable circuitry in combination with machine-readable instructions (e.g., but not limited to: firmware or software), processor circuitry, analog circuitry, digital circuitry, logic circuitry, a programmable processor, a programmable microcontroller, a graphics processing unit (GPU), a digital signal processor (DSP), an ASIC, a programmable logic device (PLD), and / or a field programmable logic device (FPLD), such as an FPGA. Still further, Figure 3 The example camera calibration circuit 300 may include in addition to or in place of Figure 3 One or more elements, processes and / or devices of those shown, and / or may include more than one of any or all of the elements, processes and devices shown.

[0048] Figure 6 and Figure 7 The diagram shows a method that can be performed by a programmable circuit to implement and / or instantiate Figure 3 The example machine-readable instructions and / or representations of the camera calibration circuit 300 may be executed by a programmable circuit to implement and / or instantiate Figure 3Flowchart of example operations of camera calibration circuit 300. The machine-readable instructions may be one or more executable programs or portions of one or more executable programs for execution by programmable circuits, such as in the following combination Figure 8 The programmable circuit 812 shown in the example processor platform 800 discussed above and / or may be a combination of the following: Fig. 9 and / or Fig.10 The example programmable circuit (e.g., FPGA) discussed herein performs one or more functions or portions of functions. In some examples, machine-readable instructions cause operations, tasks, etc. to be performed and / or executed in an automated manner in the real world. As used herein, "automated" means without human involvement.

[0049] The program may be embodied as instructions (e.g., software and / or firmware) stored on one or more non-transitory computer-readable and / or machine-readable storage media, such as cache memory, magnetic storage devices or disks (e.g., floppy disks, hard disk drives (HDDs), etc.), optical storage devices or disks (e.g., Blu-ray disks, compact disks (CDs), digital versatile disks (DVDs), etc.), redundant arrays of independent disks (RAIDs), registers, ROMs, solid-state drives (SSDs), SSD memory, non-volatile memory (e.g., electrically erasable programmable read-only memory (EEPROM), flash memory, etc.), volatile memory (e.g., any type of random access memory (RAM), etc.), and / or any other storage device or storage disk. The instructions of the non-transitory computer-readable and / or machine-readable media may be programmed and / or executed by programmable circuits located in one or more hardware devices, but the entire program and / or portions thereof may alternatively be executed and / or instantiated and / or embodied as dedicated hardware by one or more hardware devices other than programmable circuits. The machine-readable instructions may be distributed across multiple hardware devices and / or executed by two or more hardware devices (e.g., server and client hardware devices). For example, the client hardware device may be implemented by an end-client hardware device (e.g., a hardware device associated with a human and / or machine user) or an intermediate client hardware device gateway (e.g., a radio access network (RAN)) that can facilitate communication between a server and an end-client hardware device. Similarly, a non-transitory computer-readable storage medium may include one or more media. In addition, although reference is made to Figure 6 and Figure 7The flowchart shown in describes an example procedure, but many other methods of implementing the example camera calibration circuit 300 may alternatively be used. For example, the order of execution of the blocks of the flowchart may be changed, and / or some of the blocks described may be changed, eliminated, or combined. In addition or alternatively, any or all of the blocks of the flowchart may be implemented by one or more hardware circuits (e.g., processor circuits, discrete and / or integrated analog and / or digital circuits, FPGAs, ASICs, comparators, operational amplifiers (op-amps), logic circuits, etc.), which are configured to perform corresponding operations without executing software or firmware. The programmable circuits may be distributed in different network locations and / or local to one or more hardware devices (e.g., single-core processors (e.g., single-core CPUs), multi-core processors (e.g., multi-core CPUs, XPUs, etc.). For example, the programmable circuit may be a CPU and / or FPGA located in the same package (e.g., the same integrated circuit (IC) package or in two or more separate housings), one or more processors in a single machine, multiple processors distributed across multiple servers of a server rack, multiple processors distributed across one or more server racks, etc., and / or any combination thereof.

[0050] The machine-readable instructions described herein may be stored in one or more of a compressed format, an encrypted format, a segmented format, a compiled format, an executable format, a packaged format, etc. The machine-readable instructions as described herein may be stored as data (e.g., computer-readable data, machine-readable data, one or more bits (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), a bitstream (e.g., a computer-readable bitstream, a machine-readable bitstream, etc.), or a data structure (e.g., as part of instructions, code, a representation of code, etc.) that may be used to create, manufacture, and / or generate machine-executable instructions. For example, the machine-readable instructions may be segmented and stored in one or more storage devices, disks, and / or computing devices (e.g., servers) located in the same or different locations (e.g., in the cloud, in edge devices, etc.) of a network or collection of networks. The machine-readable instructions may require one or more of installation, modification, adaptation, updating, combination, supplementation, configuration, decryption, decompression, unpacking, distribution, reassignment, compilation, etc., in order to make them directly readable, interpretable, and / or executable by a computing device and / or other machine. For example, the machine-readable instructions may be stored in multiple parts that are individually compressed, encrypted, and / or stored on separate computing devices, where the parts, when decrypted, decompressed, and / or combined, form a set of computer-executable instructions and / or machine-executable instructions that implement one or more functions and / or operations that may together form a program such as described herein.

[0051] In another example, the machine-readable instructions may be stored in a state where they can be read by a programmable circuit, but require the addition of a library (e.g., a dynamic link library (DLL)), a software development kit (SDK), an application programming interface (API), etc., in order to execute the machine-readable instructions on a particular computing device or other device. In another example, the machine-readable instructions may need to be configured (e.g., stored settings, data inputs, recorded network addresses, etc.) before the machine-readable instructions and / or corresponding programs can be executed in whole or in part. Thus, as used herein, a machine-readable, computer-readable and / or machine-readable medium may include instructions and / or programs regardless of the specific format or state of the machine-readable instructions and / or programs.

[0052] The machine-readable instructions described herein may be represented by any past, present, or future instruction language, scripting language, programming language, etc. For example, the machine-readable instructions may be represented using any of the following languages: C, C++, Java, C#, Perl, Python, JavaScript, Hypertext Markup Language (HTML), Structured Query Language (SQL), Swift, etc.

[0053] As mentioned above, Figure 6 and Figure 7The example operations of may be implemented using executable instructions (e.g., computer-readable and / or machine-readable instructions) stored on one or more non-transitory computer-readable and / or machine-readable media. As used herein, the terms "non-transitory computer-readable medium, non-transitory computer-readable storage medium, non-transitory machine-readable medium, and / or non-transitory machine-readable storage medium" are expressly defined to include any type of computer-readable storage device and / or storage disk and exclude propagating signals and exclude transmission media. Examples of such non-transitory computer-readable media, non-transitory computer-readable storage media, non-transitory machine-readable storage media, and / or non-transitory machine-readable storage media include optical storage devices, magnetic storage devices, HDDs, flash memory, read-only memory (ROM), CDs, DVDs, caches, any type of RAM, registers, and / or any other storage device or storage disk in which information is stored for any duration (e.g., for an extended period of time, permanently, for a short instance, for temporary buffering, and / or for caching information). As used herein, the terms "non-volatile computer-readable storage device" and "non-volatile machine-readable storage medium" are defined to include any physical (mechanical, magnetic, and / or electrical) hardware to retain information over a period of time, but to exclude propagating signals and to exclude transmission media. Examples of non-transitory computer-readable storage devices and / or non-transitory machine-readable storage devices include any type of random access memory, any type of read-only memory, solid-state memory, flash memory, optical disks, magnetic disks, disk drives, and / or redundant arrays of independent disks (RAID) systems. As used herein, the term "device" refers to a physical structure, such as a mechanical and / or electrical device, hardware, and / or circuitry, which may or may not be configured by computer-readable instructions, machine-readable instructions, etc., and / or manufactured to perform computer-readable instructions, machine-readable instructions, etc.

[0054] Figure 6 is a flow diagram representative of example machine readable instructions and / or example operations 600 that may be executed, instantiated, and / or performed by programmable circuitry to automatically calibrate the camera 118 . Figure 6 The example machine readable instructions and / or example operations 600 begin at block 602 , where the flight data analyzer circuit 302 receives and / or accesses output from flight sensors and / or flight instruments of the UAV 104 .

[0055] At block 603, the state data analyzer circuit 304 determines and / or calculates state data for the UAV 104. In this example, the state data is determined by the state data analyzer circuit 304 based on outputs from flight sensors and / or flight instruments of the UAV 104 and / or data forwarded from the flight data analyzer circuit 302.

[0056] At block 604, in some examples, the state data analyzer circuit 304 estimates intrinsic properties and / or uncertainties of the camera 118. In some such examples, the camera intrinsic properties and / or uncertainties are estimated based on default / assumed characteristics of the camera 118 (e.g., previous calibration data, default properties, etc.).

[0057] At block 606, the example image generator circuit 306 generates a randomized sample of transformed images (eg, randomized images, randomized transformed images, etc.), as described below in conjunction with Figure 7 In some examples, the randomized sample of transformed images is based on a collection of geo-referenced satellite images stored in the data storage device 122 .

[0058] At block 608 , the flight data analyzer circuit 302 causes the camera 118 to obtain / capture an image (eg, a reference image) while the UAV 104 is in flight and / or moving. Additionally or alternatively, the flight data analyzer circuit 302 obtains and / or accesses an image from the camera 118 .

[0059] At block 610, the image relationship analyzer circuit 308 determines at least one relationship between the acquired / captured image and the randomized sample of the transformed image by comparing the captured image with the feature points of the transformed image. In this example, a first point of the randomized sample is compared with a second point of the captured image to determine at least one relationship.

[0060] At block 612 , the calibrator circuit 310 determines camera properties and / or parameters based on the at least one relationship determined by the image relationship analyzer circuit 308 (block 610 ). In this example, the camera properties and / or parameters are to be used for calibration of the camera 118 .

[0061] At block 614 , the example calibrator circuit 310 determines image correction parameters to calibrate the camera 118 .

[0062] At block 616, the calibrator circuit 310 of the illustrated example determines whether the calibration of the camera 118 is within the threshold parameters. If the calibration is within the threshold parameters, then control of the process passes to block 620. Otherwise, the process returns to block 602 (or, alternatively, the process returns to block 603, block 604, or block 606).

[0063] At block 620, in some examples, the camera characteristics determiner circuit 312 corrects / adjusts the output of the camera 118. For example, the camera characteristics determiner circuit 312 utilizes the calibration, properties and / or parameters of the camera 118 to adjust the data and / or output of the camera 118 used to guide the UAV 104.

[0064] At block 622, according to some examples disclosed herein, the camera characteristic determiner circuit 312 determines the position of the camera 118 and / or the UAV 104 and the process ends. According to some examples disclosed herein, the position of the UAV 104 is calculated based on the determined position of the camera 118 in combination with a known / assumed spatial relationship between the camera 118 and the body or other features / components of the UAV 104.

[0065] Figure 7 is a flow diagram representative of example machine-readable instructions and / or example operations 606 that may be performed, instantiated, and / or executed by programmable circuitry to generate randomized / transformed images for automatic calibration of the camera 118 . Figure 7 The example machine readable instructions and / or example operations 606 begin at block 702, where the example image generator circuit 306 retrieves and / or selects an image (e.g., an ortho-satellite image with corresponding geolocation data) from the data storage device 122. In some examples, the image generation circuit 306 selects the image based on flight data and / or status data of the UAV 104. In a specific example, the image generator circuit 306 selects the image from a set of images stored in the data storage device 122 based on a position and attitude (or other flight parameters) corresponding to the camera 118 and / or the UAV 104.

[0066] At block 704, the example image generator circuit 306 estimates the pose and intrinsic parameters of the camera 118 for use with the selected image. According to examples disclosed herein, the pose and intrinsic parameters are estimated (eg, roughly estimated), and this estimate can be used as a starting point for subsequent random changes.

[0067] At block 706, the example image generator circuit 306 introduces random variation to select a set of camera poses and intrinsic parameter configurations for generating an image. In some examples, the random variation is based on the estimated poses and intrinsic parameters.

[0068] At block 708 , the example image generator circuit 306 generates a transformed image (eg, a transformed synthetic / virtual image) after introducing random variations to the selected image. The process then ends / returns.

[0069] Figure 8 is constructed to execute and / or instantiate Figure 6 and Figure 7 Example machine readable instructions and / or example operations to implement Figure 3800. The programmable circuit platform 800 may be, for example, a server, a personal computer, a workstation, a self-learning machine (e.g., a neural network), a mobile device (e.g., a cellular phone, a smart phone, an iPad, etc.). TM tablet computer), personal digital assistant (PDA), Internet appliance, DVD player, CD player, digital video recorder, Blu-ray player, game console, personal video recorder, set-top box, headset (e.g., augmented reality (AR) headset, virtual reality (VR) headset, etc.) or other wearable device, or any other type of computing and / or electronic device.

[0070] The programmable circuit platform 800 of the illustrated example includes a programmable circuit 812. The programmable circuit 812 of the illustrated example is hardware. For example, the programmable circuit 812 can be implemented by one or more integrated circuits, logic circuits, FPGAs, microprocessors, CPUs, GPUs, DSPs, and / or microcontrollers from any desired family or manufacturer. The programmable circuit 812 can be implemented by one or more semiconductor-based (e.g., silicon-based) devices. In this example, the programmable circuit 812 implements the example flight data analyzer circuit 302, the example state data analyzer circuit 304, the example image generator circuit 306, the example image relationship analyzer circuit 308, the example calibrator circuit 310, and the example camera characteristic determiner circuit 312.

[0071] The programmable circuit 812 of the illustrated example includes a local memory 813 (e.g., cache, registers, etc.). The programmable circuit 812 of the illustrated example communicates with a main memory 814, 816 including a volatile memory 814 and a non-volatile memory 816 via a bus 818. The volatile memory 814 can be implemented by a synchronous dynamic random access memory (SDRAM), a dynamic random access memory (DRAM), a RAMBUS® dynamic random access memory (RDRAM®), and / or any other type of RAM device. The non-volatile memory 816 can be implemented by a flash memory and / or any other desired type of storage device. The memory controller 817 controls access to the main memory 814, 816 of the illustrated example. In some examples, the memory controller 817 can be implemented by one or more integrated circuits, logic circuits, microcontrollers, or any other type of circuit for managing data flow to and from the main memory 814, 816 from any desired family or manufacturer.

[0072] The programmable circuit platform 800 of the illustrated example also includes an interface circuit 820. The interface circuit 820 may be implemented by hardware according to any type of interface standard, such as an Ethernet interface, a universal serial bus (USB) interface, a Bluetooth interface, or a USB interface.® interface, a near field communication (NFC) interface, a peripheral component interconnect (PCI) interface, and / or a peripheral component interconnect express (PCIe) interface.

[0073] In the example shown, one or more input devices 822 are connected to the interface circuit 820. The input devices 822 allow a user (e.g., a human user, a machine user, etc.) to input data and / or commands into the programmable circuit 812. The input devices 822 may be implemented by, for example, an audio sensor, a microphone, a camera (still or video), a keyboard, buttons, a mouse, a touch screen, a track pad, a track ball, an isochronous device, and / or a voice recognition system.

[0074] One or more output devices 824 are also connected to the interface circuit 820 of the illustrated example. The output device 824 can be implemented, for example, by a display device (e.g., a light emitting diode (LED), an organic light emitting diode (OLED), a liquid crystal display (LCD), a cathode ray tube (CRT) display, an in-situ switching (IPS) display, a touch screen, etc.), a tactile output device, a printer, and / or a speaker. Therefore, the interface circuit 820 of the illustrated example typically includes a graphics driver card, a graphics driver chip, and / or a graphics processor circuit such as a GPU.

[0075] The interface circuitry 820 of the illustrated example also includes communication devices such as transmitters, receivers, transceivers, modems, residential gateways, wireless access points, and / or network interfaces to facilitate data exchange with external machines (e.g., any kind of computing device) over the network 826. Communications may be through, for example, an Ethernet connection, a digital subscriber line (DSL) connection, a telephone line connection, a coaxial cable system, a satellite system, a beyond-line-of-sight wireless system, a line-of-sight wireless system, a cellular telephone system, an optical connection, etc.

[0076] The programmable circuit platform 800 of the illustrated example also includes one or more mass storage disks or mass storage devices 828 for storing firmware, software, and / or data. Examples of such mass storage disks or mass storage devices 828 include magnetic storage devices (e.g., floppy disks, drives, HDDs, etc.), optical storage devices (e.g., Blu-ray disks, CDs, DVDs, etc.), RAID systems, and / or solid-state storage disks or mass storage devices such as flash memory devices and / or SSDs.

[0077] Can be Figure 6 and Figure 7 The machine-readable instructions 832 implemented by the machine-readable instructions may be stored in the mass storage device 828, in the volatile memory 814, in the non-volatile memory 816, and / or on at least one non-transitory computer-readable storage medium (such as a CD or DVD) that may be removable.

[0078] Fig. 9 yes Figure 8 A block diagram of an exemplary implementation of a programmable circuit 812 is shown. In this example, Figure 8 The programmable circuit 812 is implemented by the processor circuit 900. For example, the processor circuit 900 may be a general-purpose microprocessor (eg, a general-purpose microprocessor circuit). The processor circuit 900 executes Figure 6 and Figure 7 Some or all of the machine readable instructions of the flowchart to effectively Figure 3 The circuits of the machine readable instructions are instantiated as logic circuits to perform operations corresponding to those machine readable instructions. In some such examples, Figure 3 The circuit is instantiated by the hardware circuit of the processor circuit 900 in combination with machine-readable instructions. For example, the processor circuit 900 may be implemented by a multi-core hardware circuit such as a CPU, DSP, GPU, XPU, etc. Although it may include any number of example cores 902 (e.g., 1 core), the processor circuit 900 of this example is a multi-core semiconductor device including N cores. The cores 902 of the processor circuit 900 may operate independently or may cooperate to execute machine-readable instructions. For example, machine code corresponding to a firmware program, an embedded software program, or a software program may be executed by one of the cores 902 or may be executed by multiple cores in the cores 902 at the same or different times. In some examples, the machine code corresponding to the firmware program, the embedded software program, or the software program is divided into threads and executed in parallel by two or more cores 902. The software program may correspond to a thread executed by Figure 6 and Figure 7 A flowchart may represent a portion or all of machine-readable instructions and / or operations.

[0079] The core 902 can communicate via an example first bus 904. In some examples, the first bus 904 can be implemented by a communication bus to communicate with one (or more) of the cores in the core 902. For example, the first bus 904 can be implemented by at least one of an inter-integrated circuit (I2C) bus, a serial peripheral interface (SPI) bus, a PCI bus, or a PCIe bus. In addition or alternatively, the first bus 904 can be implemented by any other type of computing bus or electrical bus. The core 902 can obtain data, instructions, and / or signals from one or more external devices through an example interface circuit 906. The core 902 can output data, instructions, and / or signals to one or more external devices through the interface circuit 906. Although the core 902 of this example includes an example level 1 (L1) cache 920 (e.g., a level 1 (L1) cache that can be divided into an L1 data cache and an L1 instruction cache) as a local memory, the processor circuit 900 also includes, for example, an example level 2 (L2 cache) 910 that can be shared by the core for high-speed access to data and / or instructions as a shared memory. Data and / or instructions may be transferred (e.g., shared) by writing to and / or reading from the level 2 (L2) cache 910. The level 1 (L1) cache 920 and the level 2 (L2) cache 910 of each core 902 may be a plurality of levels of cache memory and main memory (e.g., Figure 8 Cache memory is part of a hierarchy of storage devices (e.g., main memory 814, 816). Typically, higher level memory in the hierarchy exhibits lower access times and has smaller storage capacity than lower level memory. Changes to different levels of the cache hierarchy are managed (e.g., coordinated) by a cache coherence policy.

[0080] Each core 902 may be referred to as a CPU, DSP, GPU, etc., or any other type of hardware circuit. Each core 902 includes a control unit circuit 914, an arithmetic and logic (AL) circuit (sometimes referred to as an ALU) 916, a plurality of registers 918, a level 1 (L1) cache 920, and an example second bus 922. Other structures may exist. For example, each core 902 may include a vector unit circuit, a single instruction multiple data (SIMD) unit circuit, a load / store unit (LSU) circuit, a branch / jump unit circuit, a floating point unit (FPU) circuit, etc. The control unit circuit 914 includes a semiconductor-based circuit configured to control (e.g., coordinate) data movement within the corresponding core 902. The AL circuit 916 includes a semiconductor-based circuit configured to perform one or more mathematical and / or logical operations on data within the corresponding core 902. The AL circuit 916 of some examples performs integer-based operations. In other examples, the AL circuit 916 also performs floating-point operations. In other examples, AL circuit 916 may include a first AL circuit that performs integer-based operations and a second AL circuit that performs floating-point operations. In some examples, AL circuit 916 may be referred to as an arithmetic logic unit (ALU).

[0081] Registers 918 are semiconductor-based structures for storing data and / or instructions, such as the results of one or more of the operations performed by the AL circuit 916 of the corresponding core 902. For example, registers 918 may include vector register(s), SIMD register(s), general register(s), flag register(s), segment register(s), machine-specific register(s), instruction pointer register(s), control register(s), debug register(s), memory management register(s), machine check register(s), etc. Registers 918 may be arranged as follows: Fig. 9 Alternatively, registers 918 may be organized in any other arrangement, format, or structure, such as by being distributed throughout core 902 to reduce access time. Second bus 922 may be implemented by at least one of an I2C bus, an SPI bus, a PCI bus, or a PCIe bus.

[0082] Each core 902 and / or more generally, the processor circuit 900 may include additional and / or alternative structures to those shown and described above. For example, there may be one or more clock circuits, one or more power supplies, one or more power gates, one or more cache home agents (CHAs), one or more aggregation / common mesh stations (CMSs), one or more shifters (e.g., (one or more) barrel shifters), and / or other circuits. The processor circuit 900 is a semiconductor device that is fabricated to include many transistors interconnected to implement the above structures in one or more integrated circuits (ICs) contained in one or more packages.

[0083] The processor circuit 900 may include and / or cooperate with one or more accelerators (e.g., acceleration circuits, hardware accelerators, etc.). In some examples, the accelerator is implemented by a logic circuit to perform some tasks faster and / or more efficiently than can be done by a general-purpose processor. Examples of accelerators include ASICs and FPGAs, such as those discussed herein. GPUs, DSPs, and / or other programmable devices may also be accelerators. The accelerator may be on the processor circuit 900, in the same chip package as the processor circuit 900, and / or in one or more packages separate from the processor circuit 900.

[0084] Fig.10 yes Figure 8 1 is a block diagram of another exemplary embodiment of a programmable circuit 812. In this example, the programmable circuit 812 is implemented by an FPGA circuit 1000. For example, the FPGA circuit 1000 can be implemented by an FPGA. The FPGA circuit 1000 can be used, for example, to execute a programmable circuit 812 that can be implemented by an FPGA. Fig. 9 However, once configured, FPGA circuit 1000 instantiates the operations and / or functions corresponding to the machine-readable instructions in hardware, and thus can generally perform these operations / functions faster than they could be performed by a general-purpose microprocessor executing corresponding software.

[0085] More specifically, Fig. 9 The processor circuit 900 (which is a general purpose device that can be programmed to perform the Figure 6 and Figure 7 A flowchart represents some or all of the machine-readable instructions, but its interconnections and logic circuits are fixed once they are manufactured. Fig.10 The example FPGA circuit 1000 includes interconnects and logic circuits that can be configured, structured, programmed, and / or interconnected in different ways after fabrication to instantiate, for example, a device corresponding to a device represented by Figure 6 and Figure 71000. Specifically, FPGA circuit 1000 can be thought of as an array of logic gates, interconnects, and switches. The switches can be programmed to change how the logic gates are connected through the interconnects, effectively forming one or more dedicated logic circuits (unless and until FPGA circuit 1000 is reprogrammed). The configured logic circuits enable the logic gates to cooperate in different ways to perform different operations on the data received by the input circuits. Those operations may correspond to the operations performed by Figure 6 and Figure 7 1000. Thus, FPGA circuit 1000 may be configured and / or structured to effectively implement the corresponding Figure 6 and Figure 7 Some or all of the operations / functions of the machine-readable instructions of the flowchart of FIG. 1000 are instantiated as dedicated logic circuits for performing the operations / functions corresponding to those software instructions in a dedicated manner similar to an ASIC. Thus, the FPGA circuit 1000 can perform the same Figure 6 and Figure 7 Some or all of the machine-readable instructions correspond to operations / functions that are faster than a general-purpose microprocessor can perform those operations / functions.

[0086] exist Fig.10 In the example of , FPGA circuit 1000 is configured and / or structured in response to being programmed (and / or reprogrammed one or more times) based on a binary file. In some examples, the binary file may be compiled and / or generated based on instructions in a hardware description language (HDL) (such as Lucid, Very High Speed ​​Integrated Circuit (VHSIC) Hardware Description Language (VHDL), or Verilog). For example, a user (e.g., a human user, a machine user, etc.) may write code or a program corresponding to one or more operations / functions in the HDL; the code / program may be translated into a low-level language as needed; and the code / program (e.g., code / program in a low-level language) may be converted (e.g., by a compiler, a software application, etc.) into a binary file. In some examples, Fig.10 The FPGA circuit 1000 can access and / or load a binary file to make Fig.10 The FPGA circuit 1000 is configured and / or structured to perform one or more operations / functions. For example, a binary file may be generated by Fig.10 The FPGA circuit 1000 can access the bit stream (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), data (e.g., computer-readable data, machine-readable data, etc.) and / or machine-readable instructions to implement Fig.10 Configuration and / or structuring of FPGA circuit 1000 or a portion thereof.

[0087] In some examples, a binary file is compiled, generated, transformed, and / or otherwise output from a unified software platform for programming the FPGA. For example, the unified software platform can translate a first instruction (e.g., code or program) corresponding to one or more operations / functions in a high-level language (e.g., C, C++, Python, etc.) into a second instruction corresponding to one or more operations / functions in an HDL. In some such examples, a binary file is compiled, generated, and / or otherwise output from the unified software platform based on the second instruction. In some examples, Fig.10 The FPGA circuit 1000 can access and / or load a binary file to make Fig.10 The FPGA circuit 1000 is configured and / or structured to perform one or more operations / functions. For example, a binary file may be generated by Fig.10 The FPGA circuit 1000 can access a bit stream (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), data (e.g., computer-readable data, machine-readable data, etc.) and / or machine-readable instructions to implement Fig.10 Configuration and / or structuring of FPGA circuit 1000 or a portion thereof.

[0088] Fig.10 FPGA circuit 1000 includes example input / output (I / O) circuit 1002 to obtain and / or output data to / from example configuration circuit 1004 and / or external hardware 1006. For example, configuration circuit 1004 may be implemented by an interface circuit that may obtain a binary file that may be implemented by a bitstream, data, and / or machine-readable instructions to configure FPGA circuit 1000 or a portion thereof. In some such examples, configuration circuit 1004 may obtain the binary file from a user, a machine (e.g., a hardware circuit (e.g., a programmable or dedicated circuit) that may implement an artificial intelligence / machine learning (AI / ML) model to generate a binary file), etc. and / or any combination thereof. In some examples, external hardware 1006 may be implemented by an external hardware circuit. For example, external hardware 1006 may be implemented by Fig. 9 The processor circuit 900 is implemented as described above.

[0089] FPGA circuit 1000 also includes an array of example logic gate circuits 1008, a plurality of example configurable interconnects 1010, and example storage circuits 1012. Logic gate circuits 1008 and configurable interconnects 1010 may be configured to instantiate a Figure 6 and Figure 7 at least some machine readable instructions and / or one or more operations / functions of other desired operations. Fig.10The logic gate circuits 1008 shown in are manufactured as blocks or groups. Each block includes a semiconductor-based electrical structure that can be configured into a logic circuit. In some examples, the electrical structure includes a logic gate (e.g., an AND gate, an OR gate, a NOR gate, etc.) that provides a basic building block for the logic circuit. There are electrically controllable switches (e.g., transistors) in each of the logic gate circuits 1008 to enable configuration of the electrical structure and / or logic gates to form a circuit for performing the desired operation / function. The logic gate circuits 1008 may include other electrical structures such as a lookup table (LUT), a register (e.g., a flip-flop or a latch), a multiplexer, etc.

[0090] The configurable interconnect 1010 of the illustrated example is a conductive path, trace, via, etc. that may include electrically controllable switches (e.g., transistors), the states of which may be changed by programming (e.g., using an HDL instruction language) to activate or disconnect one or more connections between one or more logic gate circuits in the logic gate circuit 1008 in order to program the desired logic circuit.

[0091] The storage circuit 1012 of the illustrated example is configured to store one or more results of the operations performed by the corresponding logic gates. The storage circuit 1012 may be implemented by a register, etc. In the illustrated example, the storage circuit 1012 is distributed between the logic gate circuits 1008 to facilitate access and increase execution speed.

[0092] Fig.10 The example FPGA circuit 1000 also includes an example dedicated operation circuit 1014. In this example, the dedicated operation circuit 1014 includes a dedicated circuit 1016, which can be called to implement common functions to avoid the need to program those functions in the field. Examples of such dedicated circuits 1016 include memory (e.g., DRAM) controller circuits, PCIe controller circuits, clock circuits, transceiver circuits, memories, and multiplier accumulator circuits. There may be other types of dedicated circuits. In some examples, the FPGA circuit 1000 may also include an example general-purpose programmable circuit 1018, such as an example CPU 1020 and / or an example DSP 1022. In addition or alternatively, there may be other general-purpose programmable circuits 1018, such as GPUs, XPUs, etc., which can be programmed to perform other operations.

[0093] although Fig. 9 and Fig.10 Shows Figure 8 These are two exemplary implementations of programmable circuit 812, but many other approaches are contemplated. For example, an FPGA circuit may include an onboard CPU, such as Fig. 9 One or more example CPUs 1020. Therefore, Figure 8The programmable circuit 812 may additionally at least Fig. 9 The example processor circuit 900 and Fig.10 In some such hybrid examples, Fig. 9 One or more cores 902 may execute Figure 6 and Figure 7 The flowchart represents a first portion of machine-readable instructions to perform a first operation / function, Fig.10 The FPGA circuit 1000 may be configured and / or structured to perform operations corresponding to Figure 6 and Figure 7 A second operation / function of a second portion of the machine-readable instructions represented by a flowchart, and / or the ASIC may be configured and / or structured to perform the operation corresponding to the operation by Figure 6 and Figure 7 The flowchart represents a third operation / function of a third portion of the machine readable instructions.

[0094] It should be understood that Figure 3 Some or all of the circuits of may thus be instantiated at the same or different times. Fig. 9 The same and / or different portions of processor circuit 900 may be programmed to execute portions of machine-readable instructions at the same and / or different times. In some examples, Fig.10 The same and / or different portions of FPGA circuit 1000 may be configured and / or structured to perform operations / functions corresponding to (one or more) portions of the machine-readable instructions at the same and / or different times.

[0095] In some examples, Figure 3 Some or all of the circuitry of may be instantiated, for example, in one or more threads that execute concurrently and / or serially. Fig. 9 The processor circuit 900 may execute machine-readable instructions in one or more threads that are executed concurrently and / or serially. In some examples, Fig.10 The FPGA circuit 1000 may be configured and / or structured to perform operations / functions concurrently and / or serially. In addition, in some examples, Figure 3 Some or all of the circuitry may be Fig. 9 The processor circuit 900 is implemented within one or more virtual machines and / or containers executed on the processor circuit 900.

[0096] In some examples, Figure 8 The programmable circuit 812 may be in one or more packages. For example, Fig. 9 The processor circuit 900 and / or Fig.10 The FPGA circuit 1000 may be in one or more packages. In some examples, the XPU may be provided by Figure 8 The XPU may be implemented in a programmable circuit 812 in one or more packages. For example, the XPU may include a CPU in one package (e.g., Fig. 9 The processor circuit 900, Fig.10 CPU 1020, etc.), a DSP in another package (e.g., Fig.10 DSP 1022 of ), a GPU in yet another package, and an FPGA in yet another package (e.g., Fig.10 FPGA circuit 1000).

[0097] Example methods, devices, systems, and articles of manufacture that allow for automatic calibration of cameras on a vehicle are disclosed herein. Other examples and combinations thereof include the following:

[0098] Example 1 includes an apparatus for use with an aircraft, the apparatus comprising an interface circuit communicatively coupled to a camera of the aircraft, the camera capturing an image, machine-readable instructions, and programmable circuitry for at least one of instantiating or executing the machine-readable instructions to generate a randomized image from an image stored in a data storage device carried by the aircraft, determine at least one relationship between an image captured by the camera while the aircraft is flying and the randomized image, and determine a parameter of the camera based on the at least one relationship to calibrate the camera.

[0099] Example 2 includes the apparatus of Example 1, wherein the programmable circuit is to determine a first point of the randomized image, determine a second point of the captured image, and compare the first point to the second point to determine at least one relationship.

[0100] Example 3 includes the apparatus of Example 1, wherein the programmable circuit is to at least one of correct or adjust the output of the camera based on the parameter.

[0101] Example 4 includes the apparatus of Example 1, wherein the at least one relationship is determined by performing a homography analysis of the image captured by the camera and the randomized image.

[0102] Example 5 includes the apparatus of Example 1, wherein the programmable circuit is to generate the randomized image by selecting an orthophoto image stored in the data storage device based on a flight parameter of the aircraft.

[0103] Example 6 includes the apparatus of Example 1, wherein the programmable circuit is to generate a distortion model of the camera based on the at least one relationship.

[0104] Example 7 includes the apparatus of Example 1, wherein the programmable circuit is used to reconstruct the scene corresponding to the randomized image.

[0105] Example 8 includes a non-transitory machine-readable storage medium comprising instructions that cause a programmable circuit to at least perform the following operations: generate a randomized image from images stored in a data storage device carried by an aircraft; determine at least one relationship between an image captured by a camera of the aircraft while the aircraft is flying and the randomized image; and determine parameters of the camera based on the at least one relationship to calibrate the camera.

[0106] Example 9 includes the non-transitory machine-readable storage medium of Example 8, wherein the instructions cause the programmable circuit to determine a first point of the randomized image, determine a second point of the captured image, and compare the first point to the second point to determine at least one relationship.

[0107] Example 10 includes the non-transitory machine-readable storage medium of Example 8, wherein the instructions cause the programmable circuit to at least one of correct or adjust an output of the camera based on the parameter.

[0108] Example 11 includes the non-transitory machine-readable storage medium of Example 8, wherein the at least one relationship is determined by performing a homography analysis of the image captured by the camera and the randomized image.

[0109] Example 12 includes the non-transitory machine-readable storage medium of Example 8, wherein the instructions cause the programmable circuit to generate the randomized image by selecting an orthophoto image stored in a data storage device based on a flight parameter of the aircraft.

[0110] Example 13 includes the non-transitory machine-readable storage medium of Example 9, wherein the instructions cause the programmable circuit to generate a distortion model for the camera based on the at least one relationship.

[0111] Example 14 includes the non-transitory machine-readable storage medium of Example 9, wherein the instructions cause the programmable circuit to reconstruct the scene corresponding to the randomized image.

[0112] Example 15 includes a method comprising: generating a randomized image from images stored in a data storage device carried by an aircraft by using a programmable circuit to execute instructions; determining at least one relationship between an image captured by a camera of the aircraft while the aircraft is flying and the randomized image by using a programmable circuit to execute instructions; and determining parameters of the camera based on the at least one relationship to calibrate the camera by using the programmable circuit to execute instructions.

[0113] Example 16 includes the method of Example 15, further comprising determining a first point of the randomized image by executing instructions using a programmable circuit, determining a second point of the captured image by executing instructions using a programmable circuit, and comparing the first point to the second point to determine at least one relationship by executing instructions using a programmable circuit.

[0114] Example 17 includes the method of Example 15, further comprising performing at least one of correction or adjustment of an output of the camera based on the parameter by executing the instructions using the programmable circuit.

[0115] Example 18 includes the method of Example 15, wherein the at least one relationship is determined by performing a homography analysis of the image captured by the camera and the randomized image.

[0116] Example 19 includes the method of Example 15, wherein the randomized image is generated by selecting an orthophoto image stored in a data storage device based on a flight parameter of the aircraft.

[0117] Example 20 includes the method of Example 15, further comprising: generating a distortion model of the camera based on the at least one relationship by executing instructions using a programmable circuit.

[0118] "Including" and "comprising" (and all forms and tenses thereof) are used herein as open-ended terms. Thus, whenever a claim employs any form of "include" or "comprise" (e.g., comprises, includes, comprising, including, having, etc.) as a preamble or within any kind of claim recitation, it should be understood that additional elements, terms, etc. may be present without falling outside the scope of the corresponding claim or recitation. As used herein, when the phrase "at least" is used as a transitional term, such as in the preamble of a claim, it is open-ended in the same manner as the terms "include" and "comprising" are open-ended. For example, when used in the form of A, B, and / or C, the term "and / or" refers to any combination or subset of A, B, and C, such as (1) A alone, (2) B alone, (3) C alone, (4) A and B, (5) A and C, (6) B and C, or (7) A and B and C and C. As used herein in the context of describing structures, components, items, objects, and / or things, the phrase “at least one of A and B” is intended to refer to implementations that include any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing structures, components, items, objects, and / or things, the phrase “at least one of A or B” is intended to refer to implementations that include any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. As used herein in the context of describing the performance or execution of a process, instruction, action, activity, or the like, the phrase “at least one of A and B” is intended to refer to implementations that include any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing the performance or execution of a process, instruction, action, activity, etc., the phrase "at least one of A or B" is intended to refer to an implementation that includes any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.

[0119] As used herein, singular references (e.g., "one," "a," "first," "second," etc.) do not exclude a plurality. As used herein, the term "a" or "an" object refers to one or more of the object. The terms "one" (or "a kind"), "one or more," and "at least one" are used interchangeably herein. Furthermore, although listed separately, multiple devices, elements, or actions may be implemented by, for example, the same entity or object. Furthermore, although individual features may be included in different examples or claims, these features may be combined, and the inclusion in different examples or claims does not imply that a combination of features is not feasible and / or advantageous.

[0120] As used herein, unless otherwise specified, the term "above" describes the relationship of two parts relative to the earth. A first part is above a second part if the second part has at least a portion between the earth and the first part. Likewise, as used herein, a first part is "below" a second part when the first part is closer to the earth than the second part. As described above, the first part can be above or below the second part, have one or more other parts between the first part and the second part, have no other parts between the first part and the second part, have the first part and the second part in contact, or have the first part and the second part not in direct contact with each other.

[0121] Notwithstanding the foregoing, in reference to semiconductor devices (e.g., transistors), semiconductor dies containing semiconductor devices, and / or integrated circuit (IC) packages containing semiconductor dies, during manufacture or fabrication, “above” is not referenced to ground, but rather to an underlying substrate on which the associated components are manufactured, assembled, mounted, supported, or otherwise provided. Thus, as used herein and unless the context states or implies otherwise, a first component (e.g., a transistor or other semiconductor device) within a semiconductor die is “above” a second component within a semiconductor die when the first component is further away from a substrate (e.g., a semiconductor wafer) than a second component on which the two components are manufactured or otherwise provided during manufacture / fabrication. Similarly, a first component within an IC package (e.g., a semiconductor die) is “above” a second component within the IC package when, during fabrication, the first component within the IC package is further away from a printed circuit board (PCB) to which the IC package is to be mounted or attached, unless the context states or implies otherwise. It should be understood that semiconductor devices are typically used in an orientation different from that in which they are manufactured during fabrication. Thus, when referring to semiconductor devices (e.g., transistors), semiconductor dies including semiconductor devices, and / or integrated circuit (IC) packages including semiconductor dies, the definition of “above” in the preceding paragraph (i.e., the term “above” describes the relationship of two parts relative to the earth) will likely govern based on the context of usage.

[0122] As used in this patent, stating that any component is in any manner on another component (e.g., positioned on another component, located on another component, arranged on another component, or formed on another component, etc.) indicates that the referenced component is in contact with the other component, or that the referenced component is located above the other component such that one or more intermediate components are located therebetween.

[0123] Unless otherwise specifically stated, descriptors such as "first," "second," "third," etc., are used herein without representing or otherwise indicating any meaning of priority, physical order, arrangement in a list, and / or ordering in any manner, but are merely used as labels and / or arbitrary names to distinguish elements to facilitate understanding of the disclosed examples. In some examples, the descriptor "first" may be used to refer to an element in a specific embodiment, while the same element may be referred to in the claims as having a different descriptor such as "second" or "third." In such cases, it should be understood that such descriptors are only used to clearly identify the element in the context of the discussion (e.g., in the claims), where the elements may, for example, otherwise share the same name.

[0124] As used herein, "approximately" and "about" modify the subject matter / values ​​thereof to recognize the potential for variations that occur in real-world applications. For example, "approximately" and "approximately" may modify dimensions that may not be exact due to manufacturing tolerances and / or other real-world imperfections, as will be understood by one of ordinary skill in the art. For example, "about" and "approximately" may indicate that such dimensions may be within a tolerance range of + / - 10%, unless otherwise specified herein.

[0125] As used herein, "substantially real time" means occurring in a nearly instantaneous manner recognizing that there may be real-world delays for computation time, transmission, etc. Thus, unless otherwise specified, "substantially real time" means real time + 1 second.

[0126] As used herein, the phrase "communicate" (including variations thereof) encompasses direct communication and / or indirect communication through one or more intermediate components, and does not require direct physical (e.g., wired) communication and / or constant communication, but additionally includes selective communication at periodic intervals, scheduled intervals, non-periodic intervals, and / or one-time events.

[0127] As used herein, "programmable circuit" is defined to include (i) one or more special-purpose circuits (e.g., application-specific circuits (ASICs)) that are structured to perform specific operation(s) and include one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors), and / or (ii) one or more general-purpose semiconductor-based circuits that are programmable with instructions to perform specific function(s) and / or operation(s) and include one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of programmable circuits include a programmable microprocessor (such as a central processing unit (CPU)) that can execute a first instruction to perform one or more operations and / or functions, a field programmable gate array (FPGA) that can be programmed with a second instruction to configure and / or structure the FPGA to instantiate one or more operations and / or functions corresponding to the first instruction, a graphics processor unit (GPU) that can execute the first instruction to perform one or more operations and / or functions, a digital signal processor (DSP) that can execute the first instruction to perform one or more operations and / or functions, an XPU, a network processing unit (NPU), one or more microcontrollers that can execute the first instruction to perform one or more operations and / or functions, and / or an integrated circuit such as an application specific integrated circuit (ASIC). For example, the XPU can be implemented by a heterogeneous computing system that includes multiple types of programmable circuits (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more NPUs, one or more DSPs, etc., and / or any combination thereof) and an orchestration technology (e.g., an application programming interface (API)) that can assign (one or more) computing tasks to any one (one or more) of the multiple types of programmable circuits that are suitable and available to perform (one or more) computing tasks.

[0128] As used herein, an integrated circuit / circuit is defined as one or more semiconductor packages containing one or more circuit elements, such as transistors, capacitors, inductors, resistors, current paths, diodes, etc. For example, an integrated circuit may be implemented as one or more of an ASIC, an FPGA, a chip, a microchip, a programmable circuit, a semiconductor substrate coupling multiple circuit elements, a system on a chip (SoC), etc.

[0129] Based on the foregoing, it will be appreciated that example systems, devices, articles, and methods have been disclosed that enable effective camera calibration while a vehicle is moving or in flight. The examples disclosed herein can increase the accuracy of camera calibration. The examples disclosed herein can also be highly effective in runway landing scenarios, among other scenarios. The examples disclosed herein can enable accurate estimation of distortion models. The examples disclosed herein can be easily embedded in an aircraft or other vehicle and can be operated before performing a vision-based navigation process to limit the drift of position estimates that is typically caused by uncertainty in the intrinsic properties of the camera. The disclosed systems, devices, articles, and methods improve the efficiency of using computing devices by enabling computationally efficient on-board analysis of camera images. Therefore, the disclosed systems, devices, articles, and methods relate to one or more improvements in the operation of machines such as computers or other electronic and / or mechanical devices.

[0130] The following claims are hereby incorporated by reference into this detailed description. Although some example systems, devices, articles, and methods have been disclosed herein, the coverage of this patent is not limited thereto. On the contrary, this patent covers all systems, devices, articles, and methods that fully fall within the scope of the claims of this patent.

Claims

1. A device (100) for an aircraft (104), the device comprising: an interface circuit (820) communicatively coupled to a camera (118) of the aircraft, the camera (118) capturing images; machine readable instructions (832); and Programmable circuitry (812) for at least one of instantiating the machine-readable instructions and executing the machine-readable instructions to: generating a randomized image from images stored in a data storage device (122) carried by the aircraft; determining at least one relationship between an image captured by the camera while the aircraft is in flight and the randomized image; as well as Parameters of the camera are determined based on the at least one relationship to calibrate the camera.

2. The device according to claim 1, wherein The programmable circuit is used to: determining a first point of the randomized image; determining a second point of the captured image; and The first point is compared to the second point to determine the at least one relationship.

3. The device according to claim 1, wherein: The programmable circuit is used to at least one of calibrate and adjust an output of the camera based on the parameters.

4. The device according to claim 1, wherein: The at least one relationship is determined by performing a homography analysis of the image captured by the camera and the randomized image.

5. The device according to claim 1, wherein: The programmable circuit is used to generate the randomized image by selecting an orthophoto image stored in the data storage device based on flight parameters of the aircraft.

6. The device according to claim 1, wherein: The programmable circuit is configured to generate a distortion model for the camera based on the at least one relationship.

7. The device according to claim 1, wherein: The programmable circuit is used to reconstruct a scene corresponding to the randomized image.

8. A non-transitory machine-readable storage medium comprising instructions that cause a programmable circuit to at least: generating a randomized image from images stored in a data storage device carried by the aircraft; determining at least one relationship between an image captured by a camera of the aircraft while the aircraft is in flight and the randomized image; as well as Parameters of the camera are determined based on the at least one relationship to calibrate the camera.

9. The non-transitory machine-readable storage medium of claim 8, wherein: The instructions cause the programmable circuit to: determining a first point of the randomized image; determining a second point of the captured image; and The first point is compared to the second point to determine the at least one relationship.

10. The non-transitory machine-readable storage medium of claim 8, wherein: The instructions cause the programmable circuit to at least one of correct or adjust an output of the camera based on the parameters.

11. The non-transitory machine-readable storage medium of claim 8, wherein: The at least one relationship is determined by performing a homography analysis of the image captured by the camera and the randomized image.

12. The non-transitory machine-readable storage medium of claim 8, wherein: The instructions cause the programmable circuit to generate the randomized image by selecting an orthophoto image stored in the data storage device based on flight parameters of the aircraft.

13. The non-transitory machine-readable storage medium of claim 9, wherein: The instructions cause the programmable circuit to generate a distortion model for the camera based on the at least one relationship.

14. The non-transitory machine-readable storage medium of claim 9, wherein: The instructions cause the programmable circuit to reconstruct a scene corresponding to the randomized image.

15. An airborne camera calibration method, comprising: generating a randomized image from images stored in a data storage device carried by the aircraft by executing instructions using a programmable circuit; determining, by executing instructions using the programmable circuit, at least one relationship between an image captured by a camera of the aircraft while the aircraft is in flight and the randomized image; as well as By executing instructions using the programmable circuit, parameters of the camera are determined based on the at least one relationship to calibrate the camera.

16. The airborne camera calibration method according to claim 15, further comprising: determining a first point of the randomized image by executing instructions using the programmable circuit; determining a second point of the captured image by executing the instructions using the programmable circuit; as well as By executing instructions using the programmable circuit, the first point is compared to the second point to determine the at least one relationship.

17. The onboard camera calibration method of claim 15, further comprising at least one of correcting and adjusting an output of the camera based on the parameters by executing instructions using the programmable circuit.

18. The airborne camera calibration method according to claim 15, wherein: The at least one relationship is determined by performing a homography analysis of the image captured by the camera and the randomized image.

19. The airborne camera calibration method according to claim 15, wherein: The randomized image is generated by selecting an orthophoto image stored in the data storage device based on flight parameters of the aircraft.

20. The onboard camera calibration method of claim 15, further comprising generating a distortion model of the camera based on the at least one relationship by executing instructions using the programmable circuit.

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