Image sensing apparatus and imaging apparatus

Abstract

The invention relates to an image sensing apparatus and an imaging apparatus. An image sensing apparatus for generating a high dynamic range (HDR) image is disclosed. The image sensing apparatus includes: a first pixel configured to generate a first pixel signal based on light received during a first exposure time; and a second pixel configured to share the floating diffusion region with the first pixel and generate a second pixel signal based on light received during a second exposure time different from the first exposure time. When the floating diffusion region is reset based on the pixel reset signal in the first period, the reset signal is read out, the first pixel signal is read out in the second period, and the second pixel signal is read out in the third period. The first period, the second period, and the third period are included in one frame.

Description

Technical Field

[0001] Techniques, implementations, and embodiments disclosed in this disclosure generally relate to image sensing devices capable of generating high dynamic range (HDR) images. Background Art

[0002] Image sensing devices are devices for capturing optical images by converting light into electrical signals using photosensitive semiconductor materials that react to light. With the development of the automotive, medical, computer, and communication industries, the demand for high-performance image sensing devices has increased in various fields such as smart phones, smart wearable devices, digital cameras, game consoles, IoT (Internet of Things), robots, surveillance cameras, medical miniature cameras, and the like.

[0003] Recently, in order to provide high-quality images, interest in HDR images is rapidly increasing, and various technologies capable of acquiring HDR images are being developed. Among these technologies, interlaced HDR (or line-based HDR) technology can be used to create an HDR image by merging two or more exposures captured for a frame of a scene. Here, the two or more exposures can have different exposure times (e.g., a long exposure time and a short exposure time for a frame of a scene).

[0004] However, the interlaced HDR technique may perform a readout operation several times to output data for each exposure time, resulting in an increase in the number of readout operations. In addition, the interlaced HDR technique may increase the amount of noise when merging image signals with different exposure times. Summary of the invention

[0005] According to an embodiment of the present disclosure, an image sensing device may include: a first pixel configured to generate a first pixel signal based on light received during a first exposure time; and a second pixel configured to share a floating diffusion region with the first pixel and generate a second pixel signal based on light received during a second exposure time different from the first exposure time. When the floating diffusion region is reset based on a pixel reset signal in a first period, the reset signal is read out, the first pixel signal is read out in a second period, and the second pixel signal is read out in a third period. The first period, the second period, and the third period are included in one frame.

[0006] According to another embodiment of the present disclosure, an imaging device may include: an image sensing device including a pixel array configured to generate a plurality of pixel signals having different sensitivities based on received light; and an image signal processor configured to generate an image by synthesizing the plurality of pixel signals. The pixel array may include: a first pixel configured to generate a first pixel signal based on light received during a first exposure time; a second pixel configured to share a floating diffusion region with the first pixel and generate a second pixel signal based on light received during the first exposure time; and a third pixel configured to share a floating diffusion region with the first pixel and the second pixel, and generate a third pixel signal based on light received during a second exposure time different from the first exposure time. When the floating diffusion region is reset based on a pixel reset signal in a first period, the reset signal is read out, the first pixel signal and the second pixel signal are summed and read out in a second period, and the third pixel signal is read out in a third period.

[0007] According to another embodiment of the present disclosure, an image sensing device may include: a first pixel, which includes a first photoelectric conversion element configured to generate and accumulate charges based on the intensity of light, and a first transfer transistor, which is connected between the first photoelectric conversion element and a floating diffusion region and is configured to be controlled by a first transfer signal, thereby outputting an electrical signal corresponding to a reset floating diffusion region as a first pixel signal; a second pixel, which includes a second photoelectric conversion element configured to generate and accumulate charges based on the intensity of light, and a second transfer transistor, which is connected between the second photoelectric conversion element and the floating diffusion region and is configured to be controlled by a second transfer signal, thereby outputting an electrical signal corresponding to the reset floating diffusion region as a second pixel signal; and a third pixel, which includes a third photoelectric conversion element configured to generate and accumulate charges based on the intensity of light, and a third transfer transistor, which is connected between the third photoelectric conversion element and the floating diffusion region and is configured to be controlled by a third transfer signal, thereby outputting an electrical signal corresponding to the reset floating diffusion region as a third pixel signal. When the floating diffusion area is reset based on the pixel reset signal in the first period, the reset signal is read out, the first pixel signal and the second pixel signal are summed and read out in the second period, and the third pixel signal is read out in the third period. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other features and advantageous aspects of the disclosed technology will become apparent with reference to the following detailed description when considered in conjunction with the accompanying drawings.

[0009] Figure 1 is a schematic diagram illustrating an example of pixels having different exposure times in a pixel array used in an image sensing device according to some embodiments of the present disclosure.

[0010] Figure 2 Some embodiments of the present disclosure are illustrated. Figure 1 A detailed circuit diagram of an example of a subpixel array is shown.

[0011] Figure 3 and Figure 4 is a schematic diagram illustrating an example of a pixel array used in an image sensing device according to some embodiments of the present disclosure.

[0012] Figure 5 Some embodiments of the present disclosure are illustrated. Figure 4 A timing diagram of an example operation of a subpixel array is shown.

[0013] Figure 6 is a block diagram illustrating an example of an imaging device according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0014] The present disclosure provides embodiments and examples of image sensing devices capable of generating high dynamic range (HDR) images, which can be used in a configuration to substantially solve one or more technical or engineering problems and alleviate limitations or shortcomings encountered in some image sensing devices in the art. Some embodiments of the present disclosure relate to image sensing devices that can reduce the amount of noise during a readout action while reducing the loss of a frame rate. Recognizing the above problems, image sensing devices based on some embodiments of the present disclosure can reduce the amount of noise during a readout action while reducing the loss of a frame rate.

[0015] Reference will now be made in detail to some embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. As far as possible, the same reference numerals will be used throughout the accompanying drawings to refer to the same or similar parts. Although the present disclosure is susceptible to various modifications and alternative forms, its specific embodiments are shown by way of example in the accompanying drawings. However, the present disclosure should not be construed as being limited to the embodiments set forth herein.

[0016] Hereinafter, various embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that the disclosed technology is not limited to a specific embodiment, but includes various modifications, equivalents and / or substitutions of the embodiments. The embodiments of the present disclosure can provide various effects that can be directly or indirectly recognized by the disclosed technology.

[0017] Various embodiments of the present disclosure are directed to an image sensing device that can reduce the amount of noise during a readout operation while reducing the loss of a frame rate.

[0018] It is to be understood that both the foregoing general description and the following detailed description of the present disclosure are exemplary and descriptive and are intended to provide further description of embodiments of the disclosure as claimed.

[0019] Figure 1 is a schematic diagram illustrating an example of pixels having different exposure times in a pixel array 100 used in an image sensing device according to some embodiments of the present disclosure.

[0020] High dynamic range (HDR) technology may refer to a technology of capturing the same object at different exposure times to create multiple captured images obtained at different exposure times and processing the multiple captured images to increase the dynamic range of such images.

[0021] Figure 1 is a diagram illustrating an example of a sub-pixel array (SPX) classified according to different exposure times to generate an HDR image.

[0022] Reference Figure 1 , the pixel array 100 may include a plurality of sub-pixel arrays (SPX1 to SPX4). Each of the plurality of sub-pixel arrays (SPX1 to SPX4) may include a plurality of pixels (PX) having filters of the same color. A plurality of pixels (PX) adjacent to each other in the row direction and the column direction of each of the plurality of sub-pixel arrays (SPX1 to SPX4) may share one floating diffusion region (FD).

[0023] For example, Figure 1 The pixel array 100 shown may have a pattern (so-called “quadruple pattern”) in which sub-pixel arrays (SPX1 to SPX4) each including (2×2) pixels are repeatedly arranged in the row and column directions of the pixel array 100.

[0024] For example, the sub-pixel array (SPX1) may include (2×2) pixels (ie, a total of 4 pixels, B1 to B4) having filters of the same color (eg, blue 'B'), and the (2×2) pixels may share one floating diffusion region (FD, see Figure 2 ). The sub-pixel array (SPX2) may include (2×2) pixels (i.e., a total of 4 pixels, Ga1 to Ga4) having filters of the same color (e.g., green 'G'), and the (2×2) pixels may share one floating diffusion region (FD). The sub-pixel array (SPX3) may include (2×2) pixels (i.e., a total of 4 pixels, Gb1 to Gb4) having filters of the same color (e.g., green 'G'), and the (2×2) pixels may share one floating diffusion region (FD). The sub-pixel array (SPX4) may include (2×2) pixels (i.e., a total of 4 pixels, R1 to R4) having filters of the same color (e.g., red 'R'), and the (2×2) pixels may share one floating diffusion region (FD).

[0025] Although the above pixel array 100 has been described as including a red filter, a green filter, and a blue filter for the convenience of description and better understanding of the disclosed technology, the scope or spirit of the present disclosure is not limited thereto, and at least one of the various colors may be sensed by a unit color pixel. In another example, the pixel (PX) may include a color filter such as a yellow filter, a cyan filter, a magenta filter, etc.

[0026] from Figure 1 It can be seen that although the pixel array 100 according to some embodiments of the present disclosure is shown as including four sub-pixel arrays (SPX1 to SPX4) for convenience of description, the number of sub-pixel arrays used for the pixel array 100 is not limited thereto.

[0027] In addition, the pixel array 100 according to some embodiments of the present disclosure is shown to include a quadruple pattern, but other embodiments are possible, and it should be noted that the arrangement of pixels (PX) can be implemented in various ways and the pattern of the pixel array 100 is not limited thereto.

[0028] The pixels (PX) of the pixel array 100 may be classified into long exposure pixels and short exposure pixels. Here, the long exposure pixels may refer to pixels that are continuously exposed within a predetermined exposure time to generate pixel signals. In addition, the short exposure pixels may refer to pixels that are intermittently exposed within a predetermined exposure time to generate pixel signals.

[0029] In the following, for convenience of description, a pixel (PX) marked with 'L' represents a long exposure pixel and a pixel (PX) marked with 'S' represents a short exposure pixel. Figure 1 The pixels (B4, Ga4, Gb4, R4) shown may be short-exposure pixels, and the remaining pixels (B1 to B3, Ga1 to Ga3, Gb1 to Gb3, R1 to R3) except the pixels (B4, Ga4, Gb4, R4) may be long-exposure pixels.

[0030] That is, the pixel array 100 can generate an HDR image based on two different exposure times. Each of the sub-pixel arrays (SPX1 to SPX4) can generate a pixel signal during an exposure time selected from a first exposure time and a second exposure time shorter than the first exposure time. The long exposure pixels (B1 to B3, Ga1 to Ga3, Gb1 to Gb3, R1 to R3) can generate a pixel signal during the first exposure time. The short exposure pixels (B4, Ga4, Gb4, R4) can generate a pixel signal during the second exposure time.

[0031] However, Figure 1The illustrated pixel array 100 is merely an example embodiment, the scope or spirit of the disclosed technology is not limited thereto, and it should be noted that a pixel array in which long-exposure pixels and short-exposure pixels are arranged in various ways may also be implemented.

[0032] Figure 2 Some embodiments of the present disclosure are illustrated. Figure 1 A detailed circuit diagram of an example of a sub-pixel array (SPX) is shown.

[0033] Figure 2 The sub-pixel array (SPX) can be used with Figure 1 The sub-pixel arrays (SPX1 to SPX4) shown in FIG. Figure 2 A single sub-pixel array (SPX) is shown, but the scope or spirit of the disclosed technology is not limited thereto, and it should be noted that Figure 2 A single sub-pixel array (SPX) may also have a structure and operation substantially the same as those of other sub-pixel arrays.

[0034] Reference Figure 2 , the sub-pixel array (SPX) may include first to fourth photoelectric conversion elements (PD1, PD2, PD3, PD4), first to fourth transfer transistors (TX1, TX2, TX3, TX4), a reset transistor (RX), a selection transistor (SX) and a drive transistor (DX). Figure 2 The circuit structure of is merely an example and the sub-pixel array (SPX) is not limited thereto. For example, the sub-pixel array (SPX) may further include a conversion gain transistor and a capacitor required to configure a conversion gain variable circuit.

[0035] In the sub-pixel array (SPX), the first to fourth photoelectric conversion elements (PD1, PD2, PD3, PD4) and the first to fourth transfer transistors (TX1, TX2, TX3, TX4) may be included in Figure 1 In more detail, the first photoelectric conversion element (PD1) and the first transfer transistor (TX1) may be included in the pixel (B1), the second photoelectric conversion element (PD2) and the second transfer transistor (TX2) may be included in the pixel (B2), the third photoelectric conversion element (PD3) and the third transfer transistor (TX3) may be included in the pixel (B3), and the fourth photoelectric conversion element (PD4) and the fourth transfer transistor (TX4) may be included in the pixel (B4).

[0036] The four pixels (B1 to B4) of the sub-pixel array (SPX) may share a floating diffusion region (FD), a reset transistor (RX), a drive transistor (DX), and a select transistor (SX). Although the floating diffusion region (FD), the reset transistor (RX), the drive transistor (DX), and the select transistor (SX) may be distributed to the pixels (B1 to B4) and arranged in the pixels (B1 to B4), their arrangement positions may be changed in various ways.

[0037] Each of the first to fourth photoelectric conversion elements (PD1, PD1, PD3, PD4) can generate and accumulate photocharges in response to the amount of incident light or the intensity of incident light. The first to fourth photoelectric conversion elements (PD1, PD2, PD3, PD4) can correspond to four pixels (PX) included in the unit sub-pixel array (SPX), respectively. For example, each of the first to fourth photoelectric conversion elements (PD1, PD2, PD3, PD4) can be implemented as a photodiode, a phototransistor, a photogate, a pinned photodiode, or a combination thereof. When the first to fourth photoelectric conversion elements (PD1, PD2, PD3, PD4) are implemented as photodiodes, each photoelectric conversion element can be a region doped with a second conductive impurity (e.g., an N-type impurity) in a substrate including a first conductive impurity (e.g., a P-type impurity).

[0038] The first to fourth transfer transistors (TX1, TX2, TX3, TX4) may be connected between the floating diffusion region (FD) and the first to fourth photoelectric conversion elements (PD1, PD2, PD3, PD4). In more detail, the first transfer transistor (TX1) may be connected between the floating diffusion region (FD) and the first photoelectric conversion element (PD1), the second transfer transistor (TX2) may be connected between the floating diffusion region (FD) and the second photoelectric conversion element (PD2), the third transfer transistor (TX3) may be connected between the floating diffusion region (FD) and the third photoelectric conversion element (PD3), and the fourth transfer transistor (TX4) may be connected between the floating diffusion region (FD) and the fourth photoelectric conversion element (PD4). The charges accumulated in the first to fourth photoelectric conversion elements (PD1, PD2, PD3, PD4) may be transferred to the floating diffusion region (FD) through the first to fourth transfer transistors (TX1, TX2, TX3, TX4). In more detail, the charges accumulated in the first photoelectric conversion element (PD1) can be transferred to the floating diffusion region (FD) through the first transfer transistor (TX1), the charges accumulated in the second photoelectric conversion element (PD2) can be transferred to the floating diffusion region (FD) through the second transfer transistor (TX2), the charges accumulated in the third photoelectric conversion element (PD3) can be transferred to the floating diffusion region (FD) through the third transfer transistor (TX3), and the charges accumulated in the fourth photoelectric conversion element (PD4) can be transferred to the floating diffusion region (FD) through the fourth transfer transistor (TX4).

[0039] The gate electrodes (ie, transmission gates) of the first to fourth transmission transistors (TX1, TX2, TX3, TX4) may be controlled by the first to fourth transmission signals (TG1, TG2, TG3, TG4), respectively. Figure 6 The row driver 110 (or the timing controller 140) shown generates the first to fourth transmission signals (TG1, TG2, TG3, TG4). The exposure time of the first to fourth photoelectric conversion elements (PD1, PD2, PD3, PD4) can be controlled by the first to fourth transmission signals (TG1, TG2, TG3, TG4), respectively.

[0040] For example, the first transfer signal (TG1) may turn on the first transfer transistor (TX1) to transfer the charge accumulated in the first photoelectric conversion element (PD1) to the floating diffusion region (FD), and may turn off the first transfer transistor (TX1) to control the first photoelectric conversion element (PD1) to accumulate the charge. Once the charge is accumulated in the first to third photoelectric conversion elements (PD1, PD2, PD3), the exposure time may begin. Then, the exposure time may continue until the first transfer signal (TG1) turns on the first transfer transistor (TX1) again to transfer the accumulated charge to the floating diffusion region (FD). The duration of the exposure time may be determined based on an operating mode determined by a row driver (or timing controller) to be described later.

[0041] As an example, the first to fourth transmission transistors (TX1, TX2, TX3, TX4) may be connected to Figure 1 Then, among the pixels (B1 to B4) of the sub-pixel array (SPX1), the pixels (B1 to B3) may correspond to the long-exposure pixels and the pixel B4 may correspond to the short-exposure pixel.

[0042] The floating diffusion region (FD) can accumulate photocharges received from the first to fourth photoelectric conversion elements (PD1, PD2, PD3, PD4). The first to fourth photoelectric conversion elements (PD1, PD2, PD3, PD4) can share the floating diffusion region (FD). That is, a plurality of pixels (PX) included in a unit sub-pixel array (SPX) can share the floating diffusion region (FD). The driving transistor (DX) can be controlled according to the amount of photocharge accumulated in the floating diffusion region (FD).

[0043] The reset transistor (RX) can reset the charge accumulated in the floating diffusion region (FD). The drain electrode of the reset transistor (RX) can be connected to the floating diffusion region (FD) and the source electrode of the reset transistor (RX) can be connected to the pixel power supply voltage (VDDPX). When the reset transistor (RX) is turned on according to the pixel reset signal (RG), the pixel power supply voltage (VDDPX) can be transmitted to the floating diffusion region (FD). In this case, the charge accumulated in the floating diffusion region (FD) can be discharged to the outside and the floating diffusion region FD can be reset.

[0044] The driving transistor (DX) may be a source follower buffer amplifier that generates a source-drain current in proportion to the amount of charge of the floating diffusion region (FD) connected to its gate electrode. The driving transistor (DX) may be connected between a pixel power supply voltage (VDDPX) input terminal and a selection transistor (SX). The driving transistor (DX) may amplify a potential change in the floating diffusion region (FD) and may output the amplified signal as a pixel signal (PS) through the selection transistor (SX).

[0045] The selection transistor (SX) may select a sub-pixel array (SPX) to be read based on a row. The selection transistor (SX) may be connected between the drive transistor (DX) and an output terminal of a pixel signal (PS). When the selection transistor (SX) is turned on by a selection signal (SG) provided from a row driver to be described later, an analog electrical signal output from the drive transistor (DX) may be output as a pixel signal (PS).

[0046] Figure 3 and Figure 4 is a schematic diagram illustrating an example of a pixel array used in an image sensing device according to some embodiments of the present disclosure.

[0047] Reference Figure 3 , the pixel array 100 may include a plurality of sub-pixel arrays (SPX1 to SPX4). Each of the plurality of sub-pixel arrays (SPX1 to SPX4) may include (3×3) pixels having filters of the same color. For example, Figure 3 The pixel array 100 shown may have a pattern (so-called “nona-pattern”) in which sub-pixel arrays (SPX1 to SPX4) each including (3×3) pixels are repeatedly arranged in the row direction and the column direction.

[0048] For example, the sub-pixel array (SPX1) may include (3×3) pixels (i.e., a total of 9 pixels, B1 to B9) having filters of the same color (e.g., blue 'B'), and the (3×3) pixels may share one floating diffusion region (FD). The sub-pixel array (SPX2) may include (3×3) pixels (i.e., a total of 9 pixels, Ga1 to Ga9) having filters of the same color (e.g., green 'G'), and the (3×3) pixels may share one floating diffusion region (FD). The sub-pixel array (SPX3) may include (3×3) pixels (i.e., a total of 9 pixels, Gb1 to Gb9) having filters of the same color (e.g., green 'G'), and the (3×3) pixels may share one floating diffusion region (FD). The sub-pixel array (SPX4) may include (3×3) pixels (ie, 9 pixels in total, R1 to R9) having filters of the same color (eg, red 'R'), and the (3×3) pixels may share one floating diffusion region (FD).

[0049] When the pixel array 100 includes Figure 3 When there are 9 pixels shown, a sub-pixel array (e.g., sub-pixel array SPX1) may include 9 photoelectric conversion elements and 9 transfer transistors. The nine pixels (B1 to B9) of the sub-pixel array (SPX1) may share a floating diffusion region (FD), a reset transistor (RX), a drive transistor (DX), and a select transistor (SX). Although the floating diffusion region (FD), the reset transistor (RX), the drive transistor (DX), and the select transistor (SX) may be distributed to the pixels (B1 to B9) and arranged in the pixels (B1 to B9), their arrangement positions may be changed in various ways.

[0050] Reference Figure 4 , the pixel array 100 may include a plurality of sub-pixel arrays (SPX1 to SPX4). Each of the plurality of sub-pixel arrays (SPX1 to SPX4) may include (4×4) pixels having filters of the same color. For example, Figure 4 The pixel array 100 shown may have a pattern (so-called “hexadecimal pattern”) in which sub-pixel arrays (SPX1 to SPX4) each including (4×4) pixels are repeatedly arranged in the row direction and the column direction.

[0051] For example, the sub-pixel array (SPX1) may include (4×4) pixels (i.e., a total of 16 pixels, B1 to B16) having filters of the same color (e.g., blue 'B'), and the (4×4) pixels may share one floating diffusion region (FD). The sub-pixel array (SPX2) may include (4×4) pixels (i.e., a total of 16 pixels, Ga1 to Ga16) having filters of the same color (e.g., green 'G'), and the (4×4) pixels may share one floating diffusion region (FD). The sub-pixel array (SPX3) may include (4×4) pixels (i.e., a total of 16 pixels, Gb1 to Gb16) having filters of the same color (e.g., green 'G'), and the (4×4) pixels may share one floating diffusion region (FD). The sub-pixel array (SPX4) may include (4×4) pixels (ie, a total of 16 pixels, R1 to R16) having filters of the same color (eg, red 'R'), and the (4×4) pixels may share one floating diffusion region (FD).

[0052] When the pixel array 100 includes Figure 4 When there are 16 pixels shown, a sub-pixel array (e.g., sub-pixel array SPX1) may include 16 photoelectric conversion elements and 16 transfer transistors. The 16 pixels (B1 to B16) of the sub-pixel array (SPX1) may share a floating diffusion region (FD), a reset transistor (RX), a drive transistor (DX), and a select transistor (SX). Although the floating diffusion region (FD), the reset transistor (RX), the drive transistor (DX), and the select transistor (SX) may be distributed to the pixels (B1 to B16) and arranged in the pixels (B1 to B16), their arrangement positions may be changed in various ways.

[0053] Figure 5 Some embodiments of the present disclosure are illustrated. Figure 2 A timing diagram of an example operation of a subpixel array is shown.

[0054] Reference Figure 5 , a logic high level may refer to a voltage level for activating (eg, turning on) a corresponding element (eg, a transistor), and a logic low level may refer to a voltage level for deactivating (eg, turning off) a corresponding element (eg, a transistor).

[0055] On top Figure 1Among the pixels (B1 to B4) described in , the pixels (B1 to B3) may correspond to long exposure pixels and the pixel (B4) may correspond to short exposure pixels. Among the first to fourth transfer transistors (TX1, TX2, TX3, TX4), the first to third transfer transistors (TX1, TX2, TX3) may correspond to long exposure pixels (B1 to B3), respectively. Among the first to fourth transfer transistors (TX1, TX2, TX3, TX4), the fourth transfer transistor (TX4) may correspond to the above-mentioned short exposure pixel (B4).

[0056] Reference Figure 5 , in the sub-pixel array (SPX), when the pixel reset signal (RG) transitions to a logic high level in a time period (T1), the reset transistor (RX) may be turned on to reset charges accumulated in the floating diffusion region (FD).

[0057] During the time period (T1), when the first transmission signal to the third transmission signal (TG1, TG2, TG3) is changed to a logic high level, the first transmission transistor to the third transmission transistor (TX1, TX2, TX3) may be turned on. In more detail, when the first transmission signal (TG1) is changed to a logic high level, the first transmission transistor (TX1) may be turned on. When the second transmission signal (TG2) is changed to a logic high level, the second transmission transistor (TX2) may be turned on. When the third transmission signal (TG3) is changed to a logic high level, the third transmission transistor (TX3) may be turned on.

[0058] The charges accumulated in the first to third photoelectric conversion elements (PD1, PD2, PD3) can be transferred to the floating diffusion region (FD) through the first to third transfer transistors (TX1, TX2, TX3), so that the first to third photoelectric conversion elements (PD1, PD2, PD3) can be reset. In more detail, the charges accumulated in the first photoelectric conversion element (PD1) can be transferred to the floating diffusion region (FD) through the first transfer transistor (TX1), so that the first photoelectric conversion element (PD1) can be reset. The charges accumulated in the second photoelectric conversion element (PD2) can be transferred to the floating diffusion region (FD) through the second transfer transistor (TX2), so that the second photoelectric conversion element (PD2) can be reset. The charges accumulated in the third photoelectric conversion element (PD3) can be transferred to the floating diffusion region (FD) through the third transfer transistor (TX3), so that the third photoelectric conversion element (PD3) can be reset.

[0059] After a time period (T1), when the first to third transfer signals (TG1, TG2, TG3) transition to a logic low level and the first to third transfer transistors (TX1, TX2, TX3) are turned off, charge can be accumulated in the first to third photoelectric conversion elements (PD1, PD2, PD3). Once the charge is accumulated in the first to third photoelectric conversion elements (PD1, PD2, PD3), the exposure time can be started. Then, the exposure time (LT1, LT2, LT3) can continue until the first to third transfer signals (TG1, TG2, TG3) turn on the first to third transfer transistors (TX1, TX2, TX3) again to transfer the accumulated charge to the floating diffusion region (FD).

[0060] That is to say, from Figure 5 It can be seen that pixel (B1) may have an exposure time indicated by 'LT1', pixel (B2) may have an exposure time indicated by 'LT2', and pixel (B3) may have an exposure time indicated by 'LT3'. Here, the exposure times (LT1, LT2, LT3) may be substantially the same or have similar times.

[0061] In some embodiments, photocharges output from the first photoelectric conversion element (PD1), photocharges output from the second photoelectric conversion element (PD2), and photocharges output from the third photoelectric conversion element (PD3) may be transferred to the floating diffusion region (FD) at the same time point (e.g., T4).

[0062] Thereafter, when the pixel reset signal (RG) transitions back to a logic high level in a period (T2), the reset transistor (RX) may be turned on to reset the charges accumulated in the floating diffusion region (FD).

[0063] During the time period (T2), when the fourth transfer signal (TG4) is turned to a logic high level, the fourth transfer transistor (TX4) can be turned on. Therefore, the charge accumulated in the fourth photoelectric conversion element (PD4) can be transferred to the floating diffusion region (FD) through the fourth transfer transistor (TX4), so that the fourth photoelectric conversion element (PD4) can be reset.

[0064] After the time period (T2), when the fourth transfer signal (TG4) transitions to a logic low level and the fourth transfer transistor (TX4) is turned off, the charge can be accumulated in the fourth photoelectric conversion element (PD4). Once the charge is accumulated in the fourth photoelectric conversion element (PD4), the exposure time (ST) can be started. Then, the exposure time (ST) can continue until the fourth transfer signal (TG4) turns on the fourth transfer transistor (TX4) again to transfer the accumulated charge to the floating diffusion region (FD). That is, the pixels (B1 to B3) each having a long exposure time can be charged with photocharge during the exposure time (LT1 to LT3), and the pixel (B4) having a short exposure time can be charged with photocharge during the exposure time (ST).

[0065] Subsequently, in a time period (T3), when the pixel reset signal (RG) is turned to a logic high level again, the reset transistor (RX) may be turned on to reset the charge accumulated in the floating diffusion region (FD). After the time period (T3), when the pixel reset signal (RG) is turned back to a logic low level, the reset transistor (RX) may be turned off.

[0066] Thereafter, in the time period (T4), when the first to third transmission signals (TG1, TG2, TG3) are converted back to a logic high level, the first to third transmission transistors (TX1, TX2, TX3) may be turned on. Therefore, the charges accumulated in the first to third photoelectric conversion elements (PD1, PD2, PD3) may be respectively transferred to the floating diffusion region (FD) through the first to third transmission transistors (TX1, TX2, TX3). In some embodiments, when the first to third transmission transistors (TX1, TX2, TX3) are turned on, the long exposure pixels (B1 to B3) may transfer the photocharges generated during the exposure time (LT1 to LT3) to the floating diffusion region (FD) at the same time point (T4).

[0067] Then, when the fourth transfer signal (TG4) is converted back to a logic high level in the time period (T5), the fourth transfer transistor (TX4) can be turned on. Therefore, the charge accumulated in the fourth photoelectric conversion element (PD4) can be transferred to the floating diffusion region (FD) through the fourth transfer transistor (TX4). In some embodiments, after the first to third transfer transistors (TX1, TX2, TX3) are turned on, the short exposure pixel (B4) does not need to perform a separate reset operation, but transfers the photocharge generated during the exposure time (ST) to the floating diffusion region (FD) at the time point (T5). That is, the sub-pixel array (SPX) can first read the image signals of the long exposure pixels (B1 to B3) in the time period (T4), and can then read the image signals of the short exposure pixels (B4) in the time period (T5).

[0068] The sub-pixel array based on some embodiments of the present disclosure has been described as an example in which the long exposure pixels (B1 to B3) are first read out in the time period (T4) and then the short exposure pixels (B4) are read out in the time period (T5), but is not limited thereto. Alternatively, the sub-pixel array may first read out the short exposure pixels (B4) and then read out the remaining long exposure pixels (B1 to B3). The order of reading out the long exposure pixels (B1 to B3) and the short exposure pixels (B4) may be changed to another order.

[0069] like Figure 5 As shown, the method of sequentially reading out the reset signal (read out from time period T3), the high-sensitivity image signal (read out from time period T4), and the low-sensitivity image signal (read out from time period T5) during the readout period of the sub-pixel array (SPX) can be called a reset-signal-signal (RSS) readout method.

[0070] That is, interleaved HDR may refer to a technology capable of extending the dynamic range of an HDR image by combining multiple images output via multiple exposures (i.e., multi-exposure). However, as the dynamic range of the HDR image is extended when creating the HDR image, the frame rate may decrease. In addition, interleaved HDR may control the exposure conditions of the image sensor for each row so that the number of readout times required to detect images with different exposure times may increase. In interleaved HDR, when multiple image data with different exposure times are summed and then processed, noise may inevitably increase.

[0071] Therefore, the image sensing device based on some embodiments of the present disclosure can enable the pixel array 100 including the first to fourth photoelectric conversion elements (PD1 to PD4) that share both the reset transistor (RX) and the floating diffusion region (FD) to output multi-exposure image data within the same frame. As a result, when creating an HDR image, the image sensing device based on some embodiments of the present disclosure can increase the frame rate and can output a high-sensitivity image and a low-sensitivity image within only one frame, thereby reducing the amount of noise.

[0072] In order to acquire an HDR image, multiple frames for incident light with different exposure levels may be required. Here, a frame may refer to an image acquired when a signal output by a unit pixel included in the pixel array 100 is detected once. On the other hand, an image sensing device based on some embodiments of the present disclosure may perform signal detection only once for each sub-pixel array (SPX) included in the pixel array 100, and may therefore generate a pixel signal (PS) corresponding to incident light with different exposure levels received from one pixel group (i.e., one sub-pixel array SPX). Therefore, an image sensing device based on some embodiments of the present disclosure may acquire an HDR image with only one frame.

[0073] In some embodiments, the time period (T6) may represent a “readout time period”. The readout time period (T6) may include three time periods (T3 to T5). That is, when the time period (T6) starts after the time period (T2) has passed, an operation for reading out the pixel signal (PS) may be performed.

[0074] When the selection signal (SG) is activated to a logic high level in a time period (T6), the selection transistor (SX) may be turned on. In this state, when the pixel reset signal (RG) is turned to a logic high level in a time period (T3), the reset transistor (RX) is turned on and the reset signal may be read out. Thereafter, in a time period (T4), when the first to third transmission signals (TG1 to TG3) are turned to a logic high level, a pixel signal (PS) corresponding to a high-sensitivity image signal may be read out first. In a time period (T5), when the fourth transmission signal (TG4) is turned to a logic high level, a pixel signal (PS) corresponding to a low-sensitivity image signal may be read out. When the selection signal (SG) is deactivated to a logic low level after the time period (T5), the readout period (T6) may be ended.

[0075] In the time period (T4), the first to third photoelectric conversion elements (PD1 to PD3) respectively included in the pixels (B1 to B3) can transfer the photocharges generated during the exposure time (LT1 to LT3) to the floating diffusion area (FD), and such photocharges can be output as pixel signals (PS) (also referred to as "first pixel signals"). The pixels (B1 to B3) can have filters of the same color, the pixel signals output from the pixels (B1 to B3) can be summed, and the sum of the pixel signals output from the pixels (B1 to B3) can be output as the pixel signal (PS). In the time period (T5), the fourth photoelectric conversion element (PD4) included in the pixel (B4) can transfer the photocharges generated during the exposure time (ST) to the floating diffusion area (FD), and such photocharges can be output as the pixel signal (PS) (also referred to as "second pixel signal"). The pixel signal (PS) output from the sub-pixel array (SPX) can be transmitted through Figure 6 The readout circuit 120 is shown transmitting to an image signal processor (ISP).

[0076] In the time period (T6), the image sensing device based on some embodiments of the present disclosure can output pixel signals of long exposure pixels (B1 to B3) and pixel signals of short exposure pixels (B4) in only one frame. The readout circuit 120 can convert the pixel signal (PS) output from the pixel array 100 into image data (IDATA). For example, the image sensing device can subtract the component of the reset signal from the sum of the three pixel signals sensed by the long exposure pixels (B1 to B3) (i.e., the first pixel signal), can subtract the component of the reset signal from the pixel signal sensed by the short exposure pixel (B4) (i.e., the second pixel signal), and can output the resulting signal. As described above with reference to Figure 2 As described, the sub-pixel array (SPX) can be configured so that one floating diffusion region (FD) is shared by four transfer transistors (TX1 to TX4). As a result, when the pixel reset signal (RG) is activated, the pixel signal (PS) of the pixel (B1 to B4) can be output to the readout circuit 120 in only one frame. In this way, the method of generating and outputting an image signal with a plurality of exposure times in one frame can be referred to as an interlaced HDR method.

[0077] The image data (IDATA) output from the readout circuit 120 may be transmitted to and synthesized by an image signal processor (ISP). The image signal processor (ISP) may generate an HDR image by performing a tone mapping process on the image data (IDATA). That is, the image signal processor (ISP) may generate an HDR image by merging a high-sensitivity image signal and a low-sensitivity image signal.

[0078] Figure 6 is a block diagram illustrating an example of an imaging device 1 according to some embodiments of the present disclosure.

[0079] Reference Figure 6 The imaging device 1 may refer to a device such as a digital still camera for capturing still images or a digital video camera for capturing moving images. For example, the imaging device 1 may be implemented as a digital single-lens reflex (DSLR) camera, a mirrorless camera, or a smart phone, etc. The imaging device 1 may include a device having both a lens and an image pickup element, so that the device can capture (or capture) a target object and thus can create an image of the target object.

[0080] The imaging device 1 may include an image sensing device 10 and an image signal processor (ISP).

[0081] The image sensing device 10 may be a complementary metal oxide semiconductor image sensor (CIS) for converting incident light into an electrical signal. The image sensing device 10 may include a pixel array 100 , a row driver 110 , a readout circuit 120 , a column driver 130 , and a timing controller 140 . Figure 6 The components of image sensing device 10 shown are discussed by way of example only and the present disclosure encompasses numerous other changes, substitutions, variations, alterations, and modifications.

[0082] The pixel array 100 may include a plurality of imaging pixels (PX) arranged in a two-dimensional (2D) pixel array including rows and columns. The plurality of imaging pixels (PX) may be arranged continuously in the column direction and the row direction. The pixel array 100 according to some embodiments of the present disclosure may include the above-mentioned Figures 1 to 4 The same structure as in Figure 5 In another example, multiple imaging pixels (PX) may be arranged in a three-dimensional (3D) pixel array. Multiple imaging pixels may convert optical signals into electrical signals on a unit pixel or pixel group basis, wherein pixels in a pixel group share at least some internal circuits.

[0083] The pixel array 100 may receive a driving signal including a row selection signal, a pixel reset signal, and a transfer signal from the row driver 110. Upon receiving the driving signal, the corresponding imaging pixel in the pixel array 100 may be activated to perform operations corresponding to the row selection signal, the pixel reset signal, and the transfer signal. Each pixel (PX) may generate a photocharge corresponding to the intensity (or illumination) of incident light and may generate an electrical signal having a magnitude corresponding to the amount of the generated photocharge, thereby detecting the incident light.

[0084] The exposure time and sensitivity of the pixel array 100 may be adjusted by the timing controller 140. Each pixel (PX) in the pixel array 100 may have at least two different sensitivities. Here, the sensitivity may represent an increase (or an increase in response) in the image data IDATA relative to an increase in the intensity of the incident light. That is, as the sensitivity increases, the increase in the image data (IDATA) in response to an increase in the intensity of the incident light increases. As the sensitivity decreases, the increase in the image data (IDATA) in response to an increase in the intensity of the incident light decreases.

[0085] The row driver 110 may activate the pixel array 100 to perform certain operations on the imaging pixels in the corresponding rows based on command and control signals provided by a controller circuit such as the timing controller 140. In some embodiments, the row driver 110 may select one or more imaging pixels arranged in one or more rows of the pixel array 100. The row driver 110 may generate a row selection signal to select one or more rows among the plurality of rows.

[0086] The row driver 110 may sequentially enable a pixel reset signal for resetting the imaging pixels (PX) corresponding to at least one selected row and a transmission signal for the pixels (PX) corresponding to at least one selected row. Therefore, a reference signal and an image signal, which are analog signals generated by each imaging pixel (PX) of the selected row, may be sequentially transmitted to the readout circuit 120. The reference signal may be an electrical signal provided to the readout circuit 120 when a sensing node (e.g., a floating diffusion region) of the imaging pixel is reset, and the image signal may be an electrical signal provided to the readout circuit 120 when a photocharge generated by the imaging pixel is accumulated in the sensing node. As required, the reference signal indicating the unique reset noise of each pixel and the image signal indicating the intensity of the incident light may be collectively referred to as a pixel signal.

[0087] The image sensing device 10 can use correlated double sampling (CDS) to remove an undesired offset value of a pixel known as fixed pattern noise by sampling a pixel signal twice to remove the difference between the two samples. In one example, correlated double sampling (CDS) can remove an undesired offset value of a pixel by comparing a pixel output voltage obtained before and after photocharges generated by incident light are accumulated in a sensing node, thereby measuring a pixel output voltage based only on the incident light.

[0088] In some embodiments of the present disclosure, the readout circuit 120 may sequentially sample and hold the voltage levels of the reference signal and the image signal provided to each of the plurality of column lines from the pixel array 100. That is, the readout circuit 120 may sample and hold the voltage levels of the reference signal and the image signal corresponding to each column of the pixel array 100. That is, the analog-to-digital converter (ADC) included in the readout circuit 120 may sample and hold the pixel signal of each column when receiving the pixel signal from each column line of the pixel array 100, may convert the resultant signal into a digital signal (IDATA), and may output the digital signal (IDATA). In some embodiments, the ADC may be implemented as a ramp comparison type ADC. The ramp comparison type ADC may include a comparator circuit for comparing an analog pixel signal with a ramp signal that rises or falls according to a time ramp, and a timer (or counter) for performing counting until the voltage of the ramp signal matches the analog pixel signal.

[0089] The column driver 130 may select a column of the readout circuit 120 upon receiving a control signal from the timing controller 140, and may sequentially output the image data (IDATA) temporarily stored in the selected column of the readout circuit 120. In some embodiments, when receiving an address signal from the timing controller 140, the column driver 130 may generate a column selection signal based on the address signal and may select a column of the readout circuit 120, thereby outputting the image data (IDATA) as an output signal from the selected column of the readout circuit 120.

[0090] The timing controller 140 may control the operation of at least one of the row driver 110, the readout circuit 120, and the column driver 130. The timing controller 140 may provide the row driver 110, the readout circuit 120, and the column driver 130 with clock signals required for the operation of the corresponding components of the image sensing device 10, control signals for timing control, and address signals for selecting rows or columns.

[0091] The image signal processor (ISP) may perform image processing on the image data received from the image sensing device 10. The image signal processor (ISP) may reduce noise of the image data and may perform various types of image signal processing (e.g., interpolation, synthesis, gamma correction, color filter array interpolation, color matrix, color correction, color enhancement, lens distortion correction, etc.) for image quality improvement of the image data.

[0092] In addition, the image signal processor (ISP) can compress image data that has been created by performing image signal processing for image quality improvement, so that the image signal processor (ISP) can use the compressed image data to create an image file. Alternatively, the image signal processor (ISP) can restore the image data from the image file. In this case, the scheme for compressing such image data can be a reversible format or an irreversible format. As a representative example of such a compression format, in the case of using a still image, a Joint Photographic Experts Group (JPEG) format, a JPEG 2000 format, or the like can be used. In addition, in the case of using a moving image, a plurality of frames can be compressed according to the Moving Picture Experts Group (MPEG) standard so that a moving image file can be created. For example, an image file can be created according to the Exchangeable Image File Format (Exif) standard.

[0093] The image signal processor (ISP) may generate an HDR image by synthesizing at least two images having different sensitivities. For example, the image sensing device 10 may output a low sensitivity image generated from low sensitivity pixels having relatively low sensitivity and a high sensitivity image generated from high sensitivity pixels having relatively high sensitivity. The image signal processor (ISP) may combine the low sensitivity image and the high sensitivity image, resulting in an HDR image. Here, low sensitivity and high sensitivity may correspond to relative concepts, and the image sensing device 10 may generate image data (IDATA) having at least N different sensitivities, where N is an integer of 2 or greater.

[0094] An image signal processor (ISP) may perform HDR processing on the image data (IDATA). Here, the HDR processing may include linearization processing and dynamic range compression (DRC) processing. The DRC processing may include tone mapping (e.g., gamma correction). Based on such tone mapping, relatively bright areas of the image may be corrected to be dark and relatively dark areas of the image may be corrected to be bright. As HDR processing is performed on the merged image and at least one image, an HDR image with an increased dynamic range and improved SNR (signal-to-noise ratio) may be generated. The various image processing described above may be performed on the HDR image. However, the scope or spirit of the disclosed technology is not limited thereto, and at least one of the various image processing for accurate and clear expression of the image may also be performed during HDR processing.

[0095] The image signal processor (ISP) may transmit the ISP image data to a host device (not shown). The host device (not shown) may be a processor (e.g., an application processor) for processing the ISP image data received from the image signal processor (ISP), a memory (e.g., a nonvolatile memory) for storing the ISP image data, or a display device (e.g., a liquid crystal display (LCD)) for visually displaying the ISP image data.

[0096] In addition, the image signal processor (ISP) may transmit a control signal for controlling the operation of the image sensing device 10 (eg, whether to operate, operation timing, operation mode, etc.) to the image sensing device 10 .

[0097] As is apparent from the above description, the image sensing device according to the embodiment of the present disclosure can reduce the amount of noise during the readout action while reducing the loss of the frame rate.

[0098] The embodiments of the present disclosure may provide various effects that can be directly or indirectly recognized through the present disclosure.

[0099] Although a number of exemplary embodiments have been described, it should be understood that modifications and enhancements to the disclosed embodiments and other embodiments may be designed based on what is described and / or illustrated in this disclosure. In addition, the embodiments may be combined to form additional embodiments.

[0100] CROSS-REFERENCE TO RELATED APPLICATIONS

[0101] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0132244, filed on October 5, 2023, which is hereby incorporated by reference in its entirety.

Claims

1. An image sensing device, comprising: a first pixel that generates a first pixel signal based on light received during a first exposure time; as well as a second pixel disposed to share a floating diffusion region with the first pixel and generating a second pixel signal based on light received during a second exposure time different from the first exposure time, wherein when the floating diffusion region is reset based on a pixel reset signal in a first period, the reset signal is read out, the first pixel signal is read out in a second period, and the second pixel signal is read out in a third period, and The first time period, the second time period and the third time period are included in one frame.

2. The image sensing device according to claim 1, wherein: The first time period, the second time period and the third time period are continuous time periods.

3. The image sensing device according to claim 1, wherein: The first pixel comprises: a first photoelectric conversion element that generates and accumulates charge based on the intensity of light received during the first exposure time; and a first transfer transistor connected between the first photoelectric conversion element and the floating diffusion region and controlled by a first transfer signal.

4. The image sensing device according to claim 3, wherein: The second pixel comprises: a second photoelectric conversion element that generates and accumulates charge based on the intensity of light received during a second exposure time; and a second transfer transistor connected between the second photoelectric conversion element and the floating diffusion region and controlled by a second transfer signal.

5. The image sensing device according to claim 4, wherein: In a first reset period before the first period, resetting the floating diffusion region based on the pixel reset signal, and When the first transfer transistor is turned on based on the first transfer signal, the first photoelectric conversion element transfers the charge accumulated in the first photoelectric conversion element to the floating diffusion region, so that the first photoelectric conversion element is reset.

6. The image sensing device according to claim 5, wherein: In a second reset period after the first reset period and before the first period, resetting the floating diffusion region based on the pixel reset signal, and When the second transfer transistor is turned on based on the second transfer signal, the second photoelectric conversion element transfers the charge accumulated in the second photoelectric conversion element to the floating diffusion region, so that the second photoelectric conversion element is reset. 7 . The image sensing device according to claim 1 , further comprising a selection transistor, wherein the selection transistor remains turned on during the one frame according to a selection signal.

8. An imaging device, comprising: an image sensing device including a pixel array that generates a plurality of pixel signals having different sensitivities based on received light; as well as an image signal processor that generates an image by synthesizing the plurality of pixel signals, Wherein, the pixel array comprises: a first pixel that generates a first pixel signal based on light received during a first exposure time; a second pixel disposed to share a floating diffusion region with the first pixel and generating a second pixel signal based on light received during the first exposure time; and a third pixel disposed to share the floating diffusion region with the first pixel and the second pixel and generating a third pixel signal based on light received during a second exposure time different from the first exposure time, When the floating diffusion area is reset based on a pixel reset signal in a first period, the reset signal is read out, a sum of the first pixel signal and the second pixel signal is read out in a second period, and the third pixel signal is read out in a third period.

9. The imaging device according to claim 8, wherein: The first period, the second period, and the third period are included in one frame.

10. The imaging device according to claim 8, wherein: The first to third pixels have filters of the same color.

11. The imaging device according to claim 8, wherein: The first time period, the second time period and the third time period are continuous time periods.

12. The imaging device according to claim 8, wherein: Each of the first to third pixels includes: a photoelectric conversion element that generates and accumulates electric charge based on the intensity of light received during a corresponding one of the first exposure time and the second exposure time; and A transfer transistor is connected between the photoelectric conversion element and the floating diffusion region and is controlled by a transfer signal.

13. The imaging device according to claim 12, in, The pixel array comprises: a reset transistor connected between the floating diffusion region and a power supply voltage input terminal and controlled by the pixel reset signal; a drive transistor connected to the power supply voltage input terminal and having a gate terminal connected to the floating diffusion region; and a selection transistor connected between the drive transistor and an output terminal of a pixel signal and controlled by a selection signal, and The reset transistor, the drive transistor and the selection transistor are shared by the first pixel to the third pixel.

14. The imaging device according to claim 13, wherein: The selection transistor remains turned on during a section including the first period to the third period.

15. The imaging device according to claim 12, wherein: In a first reset period before the first period, resetting the floating diffusion region based on the pixel reset signal, and When the transfer transistors respectively included in the first pixel and the second pixel are turned on, the photoelectric conversion elements respectively included in the first pixel and the second pixel transfer the charges accumulated in the photoelectric conversion elements to the floating diffusion region, so that the photoelectric conversion elements respectively included in the first pixel and the second pixel are reset.

16. The imaging device according to claim 15, wherein: In a second reset period after the first reset period and before the first period, resetting the floating diffusion region based on the pixel reset signal, and When the transfer transistor included in the third pixel is turned on, the photoelectric conversion element included in the third pixel transfers the charge accumulated in the photoelectric conversion element to the floating diffusion region, so that the photoelectric conversion element included in the third pixel is reset.

17. The imaging device according to claim 8, in, The image signal processor generates the image by synthesizing the first signal and the second signal, and The first signal is obtained by subtracting a component of the reset signal from a value corresponding to a sum of the first pixel signal and the second pixel signal, and the second signal is obtained by subtracting a component of the reset signal from the third pixel signal.

18. An image sensing device, comprising: A first pixel, the first pixel comprising: a first photoelectric conversion element that generates and accumulates electric charge based on the intensity of light; and a first transfer transistor connected between the first photoelectric conversion element and a floating diffusion region and controlled by a first transfer signal, wherein the first pixel outputs a first pixel signal to the floating diffusion region that has been reset; A second pixel, the second pixel comprising: a second photoelectric conversion element that generates and accumulates electric charge based on the intensity of light; and a second transfer transistor connected between the second photoelectric conversion element and the floating diffusion region and controlled by a second transfer signal, wherein the second pixel outputs a second pixel signal to the floating diffusion region that has been reset; and A third pixel, the third pixel comprising: a third photoelectric conversion element that generates and accumulates electric charge based on the intensity of light; and a third transfer transistor connected between the third photoelectric conversion element and the floating diffusion region and controlled by a third transfer signal, wherein the third pixel outputs a third pixel signal to the floating diffusion region that has been reset, and When the floating diffusion area is reset based on a pixel reset signal in a first period, the reset signal is read out, a sum of the first pixel signal and the second pixel signal is read out in a second period, and the third pixel signal is read out in a third period.

19. The image sensing device according to claim 18, wherein: The first period, the second period, and the third period are included in one frame.

20. The image sensing device according to claim 19, wherein: Each of the first photoelectric conversion element and the second photoelectric conversion element receives light during a first exposure time, and The third photoelectric conversion element receives the light during a second exposure time different from the first exposure time.

Images