Indoor broadcast voice hearing aid driver system and implementation method thereof

Abstract

The present invention relates to an indoor broadcast voice hearing aid driver system and implementation method, including an analog audio input interface module and a digital audio input interface module for obtaining indoor voice signals; an analog audio processing module for receiving broadcast voice signals and processing the broadcast voice signals to obtain analog broadcast voice signals; a digital audio processing module for isolating and receiving digital broadcast voice signals, and sending the analog broadcast voice signals to an embedded processor module for data processing; an audio signal processing module for processing audio signals of analog and digital audio input interfaces; a loop current electromagnetic conversion module for generating magnetic field signals, and then receiving the magnetic field signals through the hearing aid T gear to convert them into amplified audio signals finally received by human ears. The present invention only receives, processes and transmits useful digital or analog broadcast voice signals, and ensures that the audio signals are transmitted to the ears of hearing-impaired patients in a complete, clear and high-fidelity manner.

Description

Technical Field

[0001] The present invention relates to the field of hearing aid technology, and specifically, it shows an indoor broadcast voice hearing aid driver system and an implementation method thereof. Background Art

[0002] A hearing aid is a sound amplification device that can help people with hearing loss improve their hearing and language communication skills.

[0003] A hearing aid system generally comprises an input transducer, an audio input signal processing unit and an output transducer. The input transducer may be a microphone and is configured to receive sound from the surrounding environment and convert the received acoustic signal into an electrical audio input signal. In the audio input signal processing unit, the electrical audio input signal is processed by applying a specific processing mode. After processing the electrical audio input signal, the audio input signal processing unit provides an electrical audio output signal received by the output transducer. Subsequently, the output transducer provides an output signal that is based on the electrical audio output signal and can be perceived as sound by a user of the hearing aid system.

[0004] Existing assistive listening devices are all composed of pure audio input, processing and output units. For hearing aids, most of the usage scenarios are to hear the content of conversations between people. However, in indoor environments, there will be a lot of noisy noises, and the excess noise cannot be filtered out well, resulting in the user being unable to distinguish the audio source they want to hear, resulting in poor applicability of hearing aids. Summary of the invention

[0005] In view of this, an object of the present invention is to provide an indoor broadcast speech hearing aid driver system and an implementation method thereof, so as to at least partially solve the problems existing in the prior art.

[0006] In the first aspect, the present invention provides a technical solution, which is applied to an indoor broadcast voice hearing aid driver system in an indoor environment where a hearing aid driver and a current loop are installed. The solution is as follows:

[0007] Analog audio input interface module and digital audio input interface module are used to obtain indoor voice signals;

[0008] An analog audio processing module, electrically connected to the analog audio input interface module, for receiving a broadcast voice signal and processing the broadcast voice signal to obtain an analog broadcast voice signal;

[0009] A digital audio processing module, electrically connected to the output end of the digital audio input interface module, for isolating and receiving digital broadcast voice signals, and sending analog broadcast voice signals to the embedded processor module for data processing;

[0010] An audio signal processing module, electrically connected to the control signal output terminal of the embedded processor module, and electrically connected to the audio signal interface of the analog audio processing module, and processes the audio signals of the analog and digital audio input interfaces under the control of the embedded processing module;

[0011] The loop current electromagnetic conversion module is electrically connected to the output signal of the audio signal processing module. The output single-ended audio signal is converted into a differential audio signal after being processed by the differential amplifier circuit, and used as the input of the audio power amplifier circuit. The amplified audio differential signal is electrically connected to the output interface of the hearing aid driver to obtain a loop current signal. A loop wire is then connected to the output interface to generate a magnetic field signal. The magnetic field signal is then received by the hearing aid T gear to be converted into an amplified audio signal finally received by the human ear.

[0012] Optionally, an audio conversion module is further included, the output end of the embedded processor module is electrically connected to the audio conversion module, and the output end of the audio conversion module is electrically connected to the audio signal processing module.

[0013] Furthermore, the embedded processor module is connected to an LCD display screen and buttons with human-computer interaction functions.

[0014] Optionally, the analog audio processing module includes a first operational amplifier U1A, a second operational amplifier U1B, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, a twenty-third resistor R23, a twenty-fourth resistor R24, a twenty-fifth resistor R25, a twenty-sixth resistor R26, a twenty-seventh resistor R27, and a transformer T1;

[0015] The positive power supply terminal VCC of the first operational amplifier U1A is electrically connected to the 5V power supply terminal, and is also electrically connected in parallel with the second capacitor C2 and the first capacitor C1 and then grounded. The negative power supply terminal VEE of the first operational amplifier U1A is grounded. The output terminal of the first operational amplifier U1A is electrically connected to the audio signal processing module. The twenty-fifth resistor R25 and the seventh capacitor C7 are connected in parallel between the output terminal of the first operational amplifier U1A and the inverting input terminal of the first operational amplifier U1A. The non-inverting input terminal of the first operational amplifier U1A is electrically connected to the inverting input terminal of the second operational amplifier U1B through the twenty-third resistor R23.

[0016] The output terminal of the second operational amplifier U1B is electrically connected to the inverting input terminal of the second operational amplifier U1B, and the non-inverting input terminal of the second operational amplifier U1B is electrically connected to the 5V power supply terminal through the twenty-sixth resistor R26, and is also electrically connected in parallel with the twenty-seventh resistor R27 and the eighth capacitor C8 and then grounded;

[0017] The like-name end of the primary coil of the transformer T1 is electrically connected to the first end of the analog audio input interface module through the third capacitor C3, the different-name end of the primary coil of the transformer T1 is electrically connected to the second end of the analog audio input interface module, a fifth capacitor C5 is connected in series between the like-name end of the primary coil of the transformer T1 and the different-name end of the primary coil of the transformer T1, the like-name end of the secondary coil of the transformer T1 is grounded, the different-name end of the secondary coil of the transformer T1 is electrically connected to the inverting input end of the first operational amplifier U1A through the sixth capacitor C6 and the twenty-fourth resistor R24 ​​in sequence, and a fourth capacitor C4 is connected in series between the like-name end of the secondary coil of the transformer T1 and the different-name end of the secondary coil of the transformer T1.

[0018] Optionally, the audio signal processing module includes a processor U17, a crystal oscillator X4, a MOS tube Q1, an inductor B5, a one-hundred-and-seventh capacitor C107, a one-hundred-and-eighth capacitor C108, a one-hundred-and-nineth capacitor C109, a one-hundred-tenth capacitor C110, a one-hundred-eleventh capacitor C111, a one-hundred-thirty-seventh capacitor C137, a one-hundred-forty capacitor C140, a one-hundred-forty-first capacitor C141, a one-hundred-forty-second capacitor C142, a one-hundred-forty-third capacitor C143, a one-hundred-forty-fourth capacitor C144, a one-hundred-forty-fifth capacitor C145, a one-hundred-forty-sixth capacitor C146, a one-hundred-forty-seventh capacitor C147, a one-hundred-forty-eighth capacitor C148, and a one-hundred-forty-ninth capacitor C1 49. The one-hundred-fiftieth capacitor C150, the one-hundred-fifty-fourth capacitor C154, the one-hundred-fifty-fifth capacitor C155, the one-hundred-fifty-eighth capacitor C158, the ninety-third resistor R93, the ninety-fourth resistor R94, the ninety-fifth resistor R95, the ninety-eighth resistor R98, the ninety-ninth resistor R99, the one-hundredth resistor R100, the one-hundred-first resistor R101, the one-hundred-second resistor R102, the one-hundred-third resistor R103, the one-hundred-seventh resistor R107, the one-hundred-fourteenth resistor R114, the one-hundred-fifteenth resistor R115, the one-hundred-sixty-second resistor R162, the one-hundred-sixty-fifth resistor R165, the one-hundred-sixth resistor R166, the one-hundred-seventh resistor R167;

[0019] The IO circuit power pin IOVDD of the processor U17 is electrically connected to the IO power supply end, the core circuit power pin PVDD of the processor U17 is connected to the two analog circuit power pins AVDD of the processor U17, the two digital circuit power pins DVDD of the processor U17 are connected together, the working voltage pin VDRIVE of the processor U17 is electrically connected to the IO power supply end through the ninety-third resistor R93, the gate and source of the MOS tube Q1 are electrically connected to the two ends of the ninety-third resistor R93 respectively, the drain of the MOS tube Q1 is connected to the digital power supply end through the inductor B5, and the inductor B5 is connected in parallel with the one hundred and ninth capacitor C109, the one hundred and seventh capacitor C107, and the one hundred and eighth capacitor C108 and then grounded;

[0020] The first output voltage pin VOUT0 of the processor U17 is connected to the differential amplifier circuit through the one hundred and fifty-fourth capacitor C154 and the one hundred and seventh resistor R107 in sequence, the second end of the one hundred and seventh resistor R107 is grounded through the one hundred and fifty-fifth capacitor C155, the second output voltage pin VOUT1 of the processor U17 is grounded through the one hundred and fortyth capacitor C140, the third output voltage pin VOUT2 of the processor U17 is grounded through the one hundred and forty-first capacitor C141, and the fourth output voltage pin VOUT3 of the processor U17 is grounded through the one hundred and forty-second capacitor C142;

[0021] The reset pin RESET# of the processor U17 is connected in parallel with two diodes, one of which is electrically connected to the analog positive power supply terminal, the digital filter pin FILTD of the processor U17 is grounded through the one hundred and forty-ninth capacitor C149 and the one hundred and fiftieth capacitor C150 connected in parallel, and the phase-locked loop pin PLL_LF of the processor U17 is connected in parallel with the one hundred and forty-seventh capacitor C147, the one hundred and forty-eighth capacitor C148, and the one hundred and second resistor R102 and then connected to the analog positive power supply terminal;

[0022] The analog-to-digital conversion pin ADC1 of the processor U17 is electrically connected to the output end of the analog audio processing module through the 114th resistor R114, and the output pin ADC0 of the processor U17 is electrically connected to the input end of the audio conversion module through the 115th resistor R115 and the 137th capacitor C137 in sequence, and the 137th capacitor C137 is also grounded through the 158th capacitor C158;

[0023] The 10th pin MP1 / SDATA_IN0 of the processor U17 is electrically connected to the data output port DOUT through the 165th resistor R165, the 8th pin of the processor U17 is electrically connected to the left and right audio channel clock pins LRCKO through the 166th resistor R166, and the 9th pin of the processor U17 is electrically connected to the main clock pin BCKO through the 167th resistor R167;

[0024] The clock output pin OSCO of the processor U17 is grounded through the one-hundred-eleventh capacitor C110, the main clock input pin MCLKI of the processor U17 is electrically connected to the common end of the one-hundred-eleventh capacitor C110 through the ninety-fourth resistor R94 and the ninety-fifth resistor R95 in sequence, the first end of the ninety-fourth resistor R94 is also electrically connected to the main clock signal MCK through the one-hundred-sixty-second resistor R162, the second end of the ninety-fourth resistor R94 and the common end of the one-hundred-eleventh capacitor C110 are connected to the crystal oscillator X4, and the crystal oscillator X4 is grounded through the one-hundred-eleventh capacitor C111;

[0025] The analog-to-digital conversion output pin ADC_RES of the processor U17 is grounded through the one hundred and first resistor R101, the analog filter pin FILTA of the processor U17 is grounded through the one hundred and forty-fifth capacitor C145 and the one hundred and forty-sixth capacitor C146 connected in parallel, and the reference voltage pin CM of the processor U17 is grounded through the one hundred and forty-third capacitor C143 and the one hundred and forty-fourth capacitor C144 connected in parallel.

[0026] Optionally, the loop current electromagnetic conversion module includes a power amplifier U6, a first ferrite bead FB1, a second ferrite bead FB2, an eighth capacitor C8, an eleventh capacitor C11, a twelfth capacitor C12, a seventeenth capacitor C17, an eighteenth capacitor C18, a twenty-second capacitor C22, a twenty-third capacitor C23, a twenty-fifth capacitor C25, a twenty-eighth capacitor C28, a twenty-ninth capacitor C29, a thirtieth capacitor C30, a thirty-first capacitor C31, a thirty-second capacitor C32, a thirty-third capacitor C33, a thirty-fourth capacitor C34, and a thirty-third capacitor C35. The fifth capacitor C35, the thirty-sixth capacitor C36, the thirty-seventh capacitor C37, the thirty-eighth capacitor C38, the thirty-ninth capacitor C39, the fortieth capacitor C40, the forty-first capacitor C41, the forty-second capacitor C42, the forty-fourth capacitor C44, the tenth resistor R10, the nineteenth resistor R19, the twentieth resistor R20, the twenty-fifth resistor R25, the twenty-seventh resistor R27, the forty-ninth resistor R49, the fiftieth resistor R50, the fifty-first resistor R51, the fifty-second resistor R52, the relay J2, the second inductor L2, and the third inductor L3;

[0027] The first output pin OUTPA of the power amplifier U6 is electrically connected to the first pin and the second pin of the relay J2 through the second inductor L2 and the second ferrite bead FB2 in sequence, and the second output pin OUTNA of the power amplifier U6 is electrically connected to the third pin and the fourth pin of the relay J2 through the third inductor L3 and the first ferrite bead FB1 in sequence; the tenth resistor R10 and the eighteenth capacitor C18 are connected in series between the first end of the second inductor L2 and the first end of the third inductor L3 in sequence, the twelfth capacitor C12 and the eleventh capacitor C11 are connected in parallel between the second end of the second inductor L2 and the second end of the third inductor L3, the eighth capacitor C8 and the seventeenth capacitor C17 are connected in series between the first end of the second ferrite bead FB2 and the first end of the first ferrite bead FB1, and the eighth capacitor C8 and the seventeenth capacitor C17 are grounded;

[0028] The third output pin PVCCA and the fourth output pin PVCCB of the power amplifier U6 are respectively electrically connected to the first end of the thirty-ninth capacitor C39, the first end of the twenty-ninth capacitor C29, the first end of the thirty-fifth capacitor C35, and the first end of the thirty-sixth capacitor C36 after being connected in parallel; the fifth output pin PGNDA and the sixth output pin PGNDB of the power amplifier U6 are respectively electrically connected to the second end of the thirty-ninth capacitor C39, the second end of the twenty-ninth capacitor C29, the second end of the thirty-fifth capacitor C35, and the second end of the thirty-sixth capacitor C36 after being connected in parallel; the first end of the thirty-sixth capacitor C36 is electrically connected to the 24V power supply terminal, and the second end of the thirty-sixth capacitor C36 is grounded;

[0029] A twenty-seventh resistor R27 and a forty-fourth capacitor C44 are connected in series between the seventh output pin OUTPB and the eighth output pin OUTNB of the power amplifier U6;

[0030] The SUB_GND pin of the power amplifier U6 is grounded; the first input pin INPA of the power amplifier U6 is connected in parallel to the thirty-first capacitor C31 and the thirty-seventh capacitor C37, the second input pin INNA of the power amplifier U6 is connected in parallel to the thirty-eighth capacitor C38 and the thirty-second capacitor C32, the thirty-seventh capacitor C37 and the thirty-second capacitor C32 are connected in series and grounded, and the first input pin INPA of the power amplifier U6 and the second input pin INNA of the power amplifier U6 are connected to the differential amplifier circuit;

[0031] The SGND pin of the power amplifier U6 is grounded, the VDDS pin of the power amplifier U6 and the DIAG pin of the power amplifier U6 are electrically connected to both ends of the twentieth resistor R20, respectively, the VDDS pin of the power amplifier U6 is also grounded through the thirty-fourth capacitor C34, the VDDPW pin of the power amplifier U6 is electrically connected to the twenty-fifth resistor R25, the twenty-fifth resistor R25 is connected in series with the twentieth resistor R20, and the forty-first capacitor C41 is electrically connected between the VDDPW pin of the power amplifier U6 and the PGND pin of the power amplifier U6;

[0032] The GAIN0 pin of the power amplifier U6 is connected in parallel with a forty-ninth resistor R49 and a fiftieth resistor R50, the fiftieth resistor R50 is grounded, the GAIN1 pin of the power amplifier U6 is connected in parallel with a fifty-first resistor R51 and a fifty-second resistor R52, the fifty-first resistor R51 is grounded, and the GAIN1 pin of the power amplifier U6 is also grounded through a fortieth capacitor C40;

[0033] A twenty-third capacitor C23 is connected between the SVCC pin of the power amplifier U6 and the VSS pin of the power amplifier U6, a twenty-eighth capacitor C28 and a twenty-fifth capacitor C25 are connected in series between the INPB pin of the power amplifier U6 and the INNB pin of the power amplifier U6, the twenty-fifth capacitor C25 is grounded, and a forty-ninth resistor R49 and a thirty-third capacitor C33 are connected in parallel to the ROSC pin of the power amplifier U6 and then grounded;

[0034] The MUTE pin and the STBY pin of the power amplifier U6 are connected to the GAIN1 pin of the power amplifier U6. The STBY pin of the power amplifier U6 is also connected in parallel to the forty-second capacitor C42 and then grounded. The SVR pin of the power amplifier U6 is grounded through the thirtieth capacitor C30. The VREF pin of the power amplifier U6 is grounded through the twenty-second capacitor C22.

[0035] Further, the differential amplifier circuit includes a third operational amplifier U5A, a fourth operational amplifier U5B, a ninth capacitor C9, a tenth capacitor C10, a thirteenth capacitor C13, a fourteenth capacitor C14, a fifteenth capacitor C15, a sixteenth capacitor C16, a fifty-ninth resistor R59, a sixtieth resistor R60, a sixty-first resistor R61, a sixty-second resistor R62, a sixty-third resistor R63, a sixty-fourth resistor R64, a sixty-fifth resistor R65, and a sixty-sixth resistor R66;

[0036] The positive power terminal VCC of the third operational amplifier U5A is grounded through the thirteenth capacitor C13 and the thirty-first capacitor C31 connected in parallel, the negative power terminal VEE of the third operational amplifier U5A is grounded, and the output end of the third operational amplifier U5A is electrically connected to the first input pin INPA of the power amplifier U6 through the fifteenth capacitor C15 and the sixty-fifth resistor R65 in sequence;

[0037] A sixty-sixth resistor R66 and a sixteenth capacitor C16 are connected in parallel between the output end of the third operational amplifier U5A and the inverting input end of the third operational amplifier U5A, the inverting input end of the third operational amplifier U5A is also electrically connected in sequence to a sixty-fourth resistor R64 and a fourteenth capacitor C14 and then connected to the audio signal processing module, and a twelfth capacitor C12 and a sixty-third resistor R63 are connected in parallel to the non-inverting input end of the third operational amplifier U5A and then grounded;

[0038] The output end of the fourth operational amplifier U5B is electrically connected to the second input pin INNA of the power amplifier U6 through the eleventh capacitor C11 and the sixty-first resistor R61 in sequence, the tenth capacitor C10 and the sixtieth resistor R60 are connected in parallel between the output end of the fourth operational amplifier U5B and the inverting input end of the fourth operational amplifier U5B, and the inverting input end of the fourth operational amplifier U5B is also electrically connected to the fifty-ninth resistor R59 and the ninth capacitor C9 in sequence, and then connected to the single-ended audio signal;

[0039] The non-inverting input terminal of the fourth operational amplifier U5B is electrically connected to the non-inverting input terminal of the third operational amplifier U5A, and the non-inverting input terminal of the fourth operational amplifier U5B is also grounded after being connected in parallel with the sixty-second resistor R62.

[0040] In a second aspect, the present invention provides another technical solution, a method for implementing an indoor broadcast voice hearing aid driver, the implementation method is used to execute the indoor broadcast voice hearing aid driver system as described above, and the solution is as follows:

[0041] The hearing aid driver obtains the analog audio signal and the digital audio signal in the room through the analog audio input interface module and the digital audio input interface module respectively;

[0042] The analog audio signal is connected to the analog audio processing module through an audio transformer to amplify the analog audio signal to obtain a standard analog voice signal;

[0043] The digital audio signal passes through the digital audio processing module and the embedded processor module, and is converted into an analog signal through the audio conversion module;

[0044] Both the standard analog voice signal and the analog signal are multi-processed by the audio signal processing module, and the processed audio signal is sent to the loop current electromagnetic conversion module to convert the loop current signal into a magnetic signal and send it out in the form of electromagnetic waves;

[0045] After receiving the magnetic signal, the hearing aid converts and processes the signal, ultimately obtaining an audio signal that can be heard by the human ear.

[0046] Furthermore, the embedded processor module is also connected to an LCD display screen and buttons with human-computer interaction functions, and the signal processing effect can be selected through human-computer interaction processing to achieve the output of different audio effects.

[0047] The hearing aid driver obtains audio signals through the voice input module. Audio signals are divided into analog audio signals and digital audio signals. The analog audio signal is connected to the audio preamplifier circuit module (analog audio processing module) through an audio transformer, and the voice signal is amplified to obtain a standard analog voice signal. The signal is multi-processed through a digital signal processor (audio signal processing module), and the processed audio signal is sent to the loop current electromagnetic conversion module, and the loop current signal is converted into a magnetic signal and sent out in the form of electromagnetic waves. The digital audio signal is connected to the embedded processor through a network transformer (digital audio processing module), and the digital signal is converted into an analog signal through a dedicated voice conversion chip (audio conversion module). The signal output is also processed by a digital signal processor (audio signal processing module) until an electromagnetic wave signal is output. After receiving the magnetic signal, the hearing aid converts and processes the signal to finally obtain an audio signal that can be heard by the human ear.

[0048] Compared with the prior art, the beneficial effect of the present invention is that it not only takes into account the reception, processing and transmission of effective digital audio signals and analog audio signals, but also ensures the integrity, clarity and high fidelity of the audio signal input. The analog audio processing module and the digital audio processing module are used for processing. The analog audio processing module ensures the isolation, filtering and signal gain adjustment of the signal to generate analog audio 1; the digital audio processing module ensures the isolation and decoding of the signal, and then the digital signal is sent to the audio conversion module through the data algorithm processing of the embedded processor module to complete the conversion from digital audio to analog audio, generating analog audio 2, and then used as the input of the audio signal processing module like analog audio 1. The audio signal processing module completes various processing and amplification of the input audio signal under the control of the embedded processor module and then gives it to the loop current electromagnetic conversion module to generate an electromagnetic field signal, and then the hearing aid receives, converts, filters, amplifies, etc. the electromagnetic signal, and finally sends the digital or analog audio signal of the input driver to the human ear to realize the hearing aid driving of indoor broadcast voice.

[0049] The present invention proposes an indoor broadcast voice hearing aid driving system and implementation method, which isolates, filters and transmits the input drive start analog audio and digital audio signals, and can still accurately collect signals in a complex electromagnetic environment. The audio is controllably adjusted and the signal is enhanced through the digital analog processing module, conversion module and audio signal processing module in the driver, and the electromagnetic conversion principle is used to realize the conversion of analog-to-digital audio signals to electromagnetic signals and then to audio signals, and finally the signals are sent to the human ear through the hearing aid, effectively ensuring that the indoor broadcast voice is received and heard by people wearing hearing aids to the greatest extent, truly realizing the effective transmission of indoor broadcast voice for people wearing hearing aids. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Figure 1 It is a module schematic diagram of the indoor broadcast voice hearing aid driver system of the present invention;

[0051] Figure 2 is a schematic diagram related to an embedded processor module of the present invention;

[0052] Figure 3 It is a circuit design diagram of the analog audio processing module of the present invention;

[0053] Figure 4 It is a circuit design diagram of the audio signal processing module of the present invention;

[0054] Figure 5 It is a circuit design diagram of the loop current electromagnetic conversion module of the present invention;

[0055] Figure 6 It is a circuit design diagram of a differential amplifier circuit of the present invention;

[0056] Related marks in the accompanying drawings: 10 - analog audio input interface module, 20 - digital audio input interface module, 30 - analog audio processing module, 40 - digital audio processing module, 50 - audio signal processing module, 60 - loop current electromagnetic conversion module, 70 - embedded processor module, 80 - hearing aid, 90 - audio conversion module, 710 - LCD display, 720 - button. DETAILED DESCRIPTION

[0057] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0058] Embodiment 1:

[0059] An indoor broadcast voice hearing aid driver system is used in an indoor environment where a hearing aid driver and a current loop are installed. The system includes:

[0060] The analog audio input interface module 10 and the digital audio input interface module 20 are used to obtain the voice signal in the room;

[0061] The analog audio processing module 30 is electrically connected to the analog audio input interface module 10, and is used to receive the broadcast voice signal and filter the broadcast voice signal to obtain an analog broadcast voice signal;

[0062] The digital audio processing module 40 is electrically connected to the output end of the digital audio input interface module 20, and is used to isolate and receive the digital broadcast voice signal, and send the analog broadcast voice signal to the embedded processor module 70 for data processing;

[0063] The audio signal processing module 50 is electrically connected to the control signal output terminal of the embedded processor module 70 and the audio signal interface of the analog audio processing module 30 to process the audio signals of the analog and digital audio input interfaces;

[0064] The loop current electromagnetic conversion module 60 is electrically connected to the output signal of the audio signal processing module 50. The output single-ended audio signal is converted into a differential audio signal after being processed by the differential amplifier circuit, and used as the input of the audio power amplifier circuit. The amplified audio differential signal is electrically connected to the output interface of the hearing aid driver 80 to obtain a loop current signal. The output interface is then connected to an external loop wire to generate a magnetic field signal, which is then received by the hearing aid 80T gear to be converted into an amplified audio signal finally received by the human ear.

[0065] It also includes an audio conversion module, which is a general dedicated voice conversion chip. The output end of the embedded processor module is electrically connected to the audio conversion module, and the output end of the audio conversion module is electrically connected to the audio signal processing module. The main purpose is to convert digital signals into analog signals.

[0066] Combination Figure 1 and Figure 2 As shown, the embedded processor module 70 adopts the embedded processor STM32, and connected to the embedded processor STM32 are also an LCD display screen 710 and a button 720 with human-computer interaction function. Through the human-computer interaction processing, the signal processing effect can be selected and the output of different audio effects can be achieved.

[0067] In this embodiment, each electronic component can select a suitable product model or specification according to actual conditions, and the specific specification parameters are shown in the figure.

[0068] like Figure 3 As shown, the analog audio processing module 30 includes: a first operational amplifier U1A, a second operational amplifier U1B, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, a twenty-third resistor R23, a twenty-fourth resistor R24, a twenty-fifth resistor R25, a twenty-sixth resistor R26, a twenty-seventh resistor R27, and a transformer T1.

[0069] The positive power supply terminal VCC of the first operational amplifier U1A is electrically connected to the 5V power supply terminal, and is also electrically connected in parallel with the second capacitor C2 and the first capacitor C1 and then grounded. The negative power supply terminal VEE of the first operational amplifier U1A is grounded. The output terminal of the first operational amplifier U1A is electrically connected to the audio signal processing module. The twenty-fifth resistor R25 and the seventh capacitor C7 are connected in parallel between the output terminal of the first operational amplifier U1A and the inverting input terminal of the first operational amplifier U1A. The non-inverting input terminal of the first operational amplifier U1A is electrically connected to the inverting input terminal of the second operational amplifier U1B through the twenty-third resistor R23.

[0070] The output end of the second operational amplifier U1B is electrically connected to the inverting input end of the second operational amplifier U1B, and the non-inverting input end of the second operational amplifier U1B is electrically connected to the 5V power supply end through the twenty-sixth resistor R26, and is also electrically connected in parallel with the twenty-seventh resistor R27 and the eighth capacitor C8 and then grounded.

[0071] The like-name end of the primary coil of the transformer T1 is electrically connected to the first end of the analog audio input interface module through the third capacitor C3, the different-name end of the primary coil of the transformer T1 is electrically connected to the second end of the analog audio input interface module, a fifth capacitor C5 is connected in series between the like-name end of the primary coil of the transformer T1 and the different-name end of the primary coil of the transformer T1, the like-name end of the secondary coil of the transformer T1 is grounded, the different-name end of the secondary coil of the transformer T1 is electrically connected to the inverting input end of the first operational amplifier U1A through the sixth capacitor C6 and the twenty-fourth resistor R24 ​​in sequence, and a fourth capacitor C4 is connected in series between the like-name end of the secondary coil of the transformer T1 and the different-name end of the secondary coil of the transformer T1.

[0072] like Figure 4As shown, the audio signal processing module 50 includes a processor U17, a crystal oscillator X4, a MOS tube Q1, an inductor B5, a one-hundred-and-seventh capacitor C107, a one-hundred-and-eighth capacitor C108, a one-hundred-and-ninth capacitor C109, a one-hundred-tenth capacitor C110, a one-hundred-eleventh capacitor C111, a one-hundred-thirty-seventh capacitor C137, a one-hundred-forty capacitor C140, a one-hundred-forty-first capacitor C141, a one-hundred-forty-second capacitor C142, a one-hundred-forty-third capacitor C143, a one-hundred-forty-fourth capacitor C144, a one-hundred-forty-fifth capacitor C145, a one-hundred-forty-sixth capacitor C146, a one-hundred-forty-seventh capacitor C147, a one-hundred-forty-eighth capacitor C148, and a one-hundred-forty-ninth capacitor C1 49. The one-hundred-and-fiftieth capacitor C150, the one-hundred-and-fifty-fourth capacitor C154, the one-hundred-and-fifty-fifth capacitor C155, the one-hundred-and-fifty-eighth capacitor C158, the ninety-third resistor R93, the ninety-fourth resistor R94, the ninety-fifth resistor R95, the ninety-eighth resistor R98, the ninety-ninth resistor R99, the one-hundredth resistor R100, the one-hundred-and-first resistor R101, the one-hundred-and-second resistor R102, the one-hundred-and-third resistor R103, the one-hundred-and-seventh resistor R107, the one-hundred-and-fourteenth resistor R114, the one-hundred-and-fifteenth resistor R115, the one-hundred-and-sixty-second resistor R162, the one-hundred-and-sixty-fifth resistor R165, the one-hundred-and-sixth resistor R166, and the one-hundred-and-seventh resistor R167.

[0073] The IO circuit power pin IOVDD of the processor U17 is electrically connected to the IO power supply end, the core circuit power pin PVDD of the processor U17 is connected to the two analog circuit power pins AVDD of the processor U17, the two digital circuit power pins DVDD of the processor U17 are connected together, the working voltage pin VDRIVE of the processor U17 is electrically connected to the IO power supply end through the ninety-third resistor R93, the gate and source of the MOS tube Q1 are electrically connected to the two ends of the ninety-third resistor R93 respectively, the drain of the MOS tube Q1 is connected to the digital power supply end through the inductor B5, and the inductor B5 is connected in parallel to the one-hundred-ninth capacitor C109, the one-hundred-seventh capacitor C107, and the one-hundred-eighth capacitor C108 and then grounded.

[0074] The first output voltage pin VOUT0 of the processor U17 is connected to the differential amplifier circuit through the one-hundred-and-fifty-fourth capacitor C154 and the one-hundred-and-seventh resistor R107 in sequence. The second end of the one-hundred-and-seventh resistor R107 is grounded through the one-hundred-and-fifty-fifth capacitor C155. The second output voltage pin VOUT1 of the processor U17 is grounded through the one-hundred-and-forty capacitor C140. The third output voltage pin VOUT2 of the processor U17 is grounded through the one-hundred-and-forty-first capacitor C141. The fourth output voltage pin VOUT3 of the processor U17 is grounded through the one-hundred-and-forty-second capacitor C142.

[0075] The reset pin RESET# of the processor U17 is connected in parallel with two diodes, one of which is electrically connected to the analog positive power supply terminal. The digital filter pin FILTD of the processor U17 is grounded through the one-hundred-and-forty-ninth capacitor C149 and the one-hundred-and-fiftieth capacitor C150 connected in parallel. The phase-locked loop pin PLL_LF of the processor U17 is connected in parallel with the one-hundred-and-forty-seventh capacitor C147, the one-hundred-and-forty-eighth capacitor C148 and the one-hundred-and-second resistor R102 and then connected to the analog positive power supply terminal.

[0076] The analog-to-digital conversion pin ADC1 of the processor U17 is electrically connected to the output end of the analog audio processing module through the 114th resistor R114, and the output pin ADC0 of the processor U17 is electrically connected to the input end of the audio conversion module through the 115th resistor R115 and the 137th capacitor C137 in sequence. The 137th capacitor C137 is also grounded through the 158th capacitor C158.

[0077] Pin 10 MP1 / SDATA_IN0 of processor U17 is electrically connected to data output port DOUT through the one-hundred-sixty-fifth resistor R165, pin 8 of processor U17 is electrically connected to left and right audio channel clock pins LRCKO through the one-hundred-sixty-sixth resistor R166, and pin 9 of processor U17 is electrically connected to the total clock pin BCKO through the one-hundred-sixty-seventh resistor R167.

[0078] The clock output pin OSCO of the processor U17 is grounded through the one-hundred-and-eleventh capacitor C110, and the main clock input pin MCLKI of the processor U17 is electrically connected to the common end of the one-hundred-and-eleventh capacitor C110 through the ninety-fourth resistor R94 and the ninety-fifth resistor R95 in sequence. The first end of the ninety-fourth resistor R94 is also electrically connected to the main clock signal MCK through the one-hundred-and-sixty-second resistor R162. The crystal oscillator X4 is connected between the second end of the ninety-fourth resistor R94 and the common end of the one-hundred-and-eleventh capacitor C110, and the crystal oscillator X4 is grounded through the one-hundred-and-eleventh capacitor C111.

[0079] The analog-to-digital conversion output pin ADC_RES of the processor U17 is grounded through the one hundred and first resistor R101, the analog filter pin FILTA of the processor U17 is grounded through the one hundred and forty-fifth capacitor C145 and the one hundred and forty-sixth capacitor C146 connected in parallel, and the reference voltage pin CM of the processor U17 is grounded through the one hundred and forty-third capacitor C143 and the one hundred and forty-fourth capacitor C144 connected in parallel.

[0080] like Figure 5As shown, the loop current electromagnetic conversion module 60 includes a power amplifier U6, a first ferrite bead FB1, a second ferrite bead FB2, an eighth capacitor C8, an eleventh capacitor C11, a twelfth capacitor C12, a seventeenth capacitor C17, an eighteenth capacitor C18, a twenty-second capacitor C22, a twenty-third capacitor C23, a twenty-fifth capacitor C25, a twenty-eighth capacitor C28, a twenty-ninth capacitor C29, a thirtieth capacitor C30, a thirty-first capacitor C31, a thirty-second capacitor C32, a thirty-third capacitor C33, a thirty-fourth capacitor C34, and a thirty-third capacitor C35. The fifth capacitor C35, the thirty-sixth capacitor C36, the thirty-seventh capacitor C37, the thirty-eighth capacitor C38, the thirty-ninth capacitor C39, the fortieth capacitor C40, the forty-first capacitor C41, the forty-second capacitor C42, the forty-fourth capacitor C44, the tenth resistor R10, the nineteenth resistor R19, the twentieth resistor R20, the twenty-fifth resistor R25, the twenty-seventh resistor R27, the forty-ninth resistor R49, the fiftieth resistor R50, the fifty-first resistor R51, the fifty-second resistor R52, the relay J2, the second inductor L2, and the third inductor L3.

[0081] The first output pin OUTPA of the power amplifier U6 is electrically connected to the first and second pins of the relay J2 through the second inductor L2 and the second ferrite bead FB2 in sequence, and the second output pin OUTNA of the power amplifier U6 is electrically connected to the third and fourth pins of the relay J2 through the third inductor L3 and the first ferrite bead FB1 in sequence; the tenth resistor R10 and the eighteenth capacitor C18 are connected in series between the first end of the second inductor L2 and the first end of the third inductor L3 in sequence, the twelfth capacitor C12 and the eleventh capacitor C11 are connected in parallel between the second end of the second inductor L2 and the second end of the third inductor L3, the eighth capacitor C8 and the seventeenth capacitor C17 are connected in series between the first end of the second ferrite bead FB2 and the first end of the first ferrite bead FB1, and the eighth capacitor C8 and the seventeenth capacitor C17 are grounded.

[0082] The third output pin PVCCA and the fourth output pin PVCCB of the power amplifier U6 are connected in parallel and are respectively electrically connected to the first end of the thirty-ninth capacitor C39, the first end of the twenty-ninth capacitor C29, the first end of the thirty-fifth capacitor C35, and the first end of the thirty-sixth capacitor C36. The fifth output pin PGNDA and the sixth output pin PGNDB of the power amplifier U6 are connected in parallel and are respectively electrically connected to the second end of the thirty-ninth capacitor C39, the second end of the twenty-ninth capacitor C29, the second end of the thirty-fifth capacitor C35, and the second end of the thirty-sixth capacitor C36. The first end of the thirty-sixth capacitor C36 is electrically connected to the 24V power supply end, and the second end of the thirty-sixth capacitor C36 is grounded.

[0083] A twenty-seventh resistor R27 and a forty-fourth capacitor C44 are connected in series between the seventh output pin OUTPB and the eighth output pin OUTNB of the power amplifier U6 .

[0084] The SUB_GND pin of the power amplifier U6 is grounded; the first input pin INPA of the power amplifier U6 is connected in parallel to the thirty-first capacitor C31 and the thirty-seventh capacitor C37, the second input pin INNA of the power amplifier U6 is connected in parallel to the thirty-eighth capacitor C38 and the thirty-second capacitor C32, the thirty-seventh capacitor C37 and the thirty-second capacitor C32 are connected in series and grounded, and the first input pin INPA of the power amplifier U6 and the second input pin INNA of the power amplifier U6 are connected to the differential amplifier circuit;

[0085] The SGND pin of the power amplifier U6 is grounded, the VDDS pin of the power amplifier U6 and the DIAG pin of the power amplifier U6 are electrically connected to the two ends of the twentieth resistor R20 respectively, the VDDS pin of the power amplifier U6 is also grounded through the thirty-fourth capacitor C34, the VDDPW pin of the power amplifier U6 is electrically connected to the twenty-fifth resistor R25, the twenty-fifth resistor R25 is connected in series with the twentieth resistor R20, and the forty-first capacitor C41 is electrically connected between the VDDPW pin of the power amplifier U6 and the PGND pin of the power amplifier U6.

[0086] The GAIN0 pin of the power amplifier U6 is connected in parallel to the forty-ninth resistor R49 and the fiftieth resistor R50, and the fiftieth resistor R50 is grounded. The GAIN1 pin of the power amplifier U6 is connected in parallel to the fifty-first resistor R51 and the fifty-second resistor R52, and the fifty-first resistor R51 is grounded. The GAIN1 pin of the power amplifier U6 is also grounded through the fortieth capacitor C40.

[0087] The twenty-third capacitor C23 is connected between the SVCC pin of the power amplifier U6 and the VSS pin of the power amplifier U6, the twenty-eighth capacitor C28 and the twenty-fifth capacitor C25 are connected in series between the INPB pin of the power amplifier U6 and the INNB pin of the power amplifier U6, the twenty-fifth capacitor C25 is grounded, and the ROSC pin of the power amplifier U6 is connected in parallel with the forty-ninth resistor R49 and the thirty-third capacitor C33 and then grounded.

[0088] The MUTE pin of power amplifier U6 and the STBY pin of power amplifier U6 are connected to the GAIN1 pin of power amplifier U6. The STBY pin of power amplifier U6 is also connected in parallel to the forty-second capacitor C42 and then grounded. The SVR pin of power amplifier U6 is grounded through the thirtieth capacitor C30. The VREF pin of power amplifier U6 is grounded through the twenty-second capacitor C22.

[0089] Specifically, Figure 6As shown, the differential amplifier circuit includes a third operational amplifier U5A, a fourth operational amplifier U5B, a ninth capacitor C9, a tenth capacitor C10, a thirteenth capacitor C13, a fourteenth capacitor C14, a fifteenth capacitor C15, a sixteenth capacitor C16, a fifty-ninth resistor R59, a sixtieth resistor R60, a sixty-first resistor R61, a sixty-second resistor R62, a sixty-third resistor R63, a sixty-fourth resistor R64, a sixty-fifth resistor R65, and a sixty-sixth resistor R66.

[0090] The positive power terminal VCC of the third operational amplifier U5A is grounded through the thirteenth capacitor C13 and the thirty-first capacitor C31 connected in parallel, the negative power terminal VEE of the third operational amplifier U5A is grounded, and the output terminal of the third operational amplifier U5A is electrically connected to the first input pin INPA of the power amplifier U6 through the fifteenth capacitor C15 and the sixty-fifth resistor R65 in sequence.

[0091] The sixty-sixth resistor R66 and the sixteenth capacitor C16 are connected in parallel between the output end of the third operational amplifier U5A and the inverting input end of the third operational amplifier U5A. The inverting input end of the third operational amplifier U5A is also electrically connected in sequence to the sixty-fourth resistor R64 and the fourteenth capacitor C14 and then to the audio signal processing module. The non-inverting input end of the third operational amplifier U5A is connected in parallel to the twelfth capacitor C12 and the sixty-third resistor R63 and then to ground.

[0092] The output end of the fourth operational amplifier U5B is electrically connected to the second input pin INNA of the power amplifier U6 through the eleventh capacitor C11 and the sixty-first resistor R61 in sequence. The tenth capacitor C10 and the sixtieth resistor R60 are connected in parallel between the output end of the fourth operational amplifier U5B and the inverting input end of the fourth operational amplifier U5B. The inverting input end of the fourth operational amplifier U5B is also electrically connected to the fifty-ninth resistor R59 and the ninth capacitor C9 in sequence, and then connected to the single-ended audio signal.

[0093] The non-inverting input terminal of the fourth operational amplifier U5B is electrically connected to the non-inverting input terminal of the third operational amplifier U5A, and the non-inverting input terminal of the fourth operational amplifier U5B is also grounded after being connected in parallel with the sixty-second resistor R62.

[0094] Embodiment 2:

[0095] A method for implementing an indoor broadcast voice hearing aid driver is provided, using the indoor broadcast voice hearing aid driver system of embodiment 1, the method comprising:

[0096] First, the hearing aid driver obtains the analog audio signal and the digital audio signal in the room through the analog audio input interface module and the digital audio input interface module respectively.

[0097] Next, the analog audio signal is connected to the analog audio processing module through an audio transformer to amplify the analog audio signal to obtain a standard analog voice signal;

[0098] The digital audio signal passes through the digital audio processing module and the embedded processor module, and is converted into an analog signal through the audio conversion module.

[0099] Afterwards, the standard analog voice signal and the analog signal are multi-processed by the audio signal processing module, and the processed audio signal is sent to the loop current electromagnetic conversion module to convert the loop current signal into a magnetic signal and send it out in the form of electromagnetic waves.

[0100] Finally, after receiving the magnetic signal, the hearing aid converts and processes the signal, and finally obtains an audio signal that can be heard by the human ear.

[0101] The embedded processor module can also be connected to an LCD display and buttons with human-computer interaction functions. Through the human-computer interaction processing, the signal processing effect can be selected and the output of different audio effects can be achieved.

[0102] The indoor broadcast voice hearing aid driving system and implementation method proposed in the above embodiments isolate, filter and transmit the input drive start analog audio and digital audio signals, and can still accurately collect signals in a complex electromagnetic environment. The audio is controllably adjusted and the signal is enhanced through the digital analog processing module, conversion module and audio signal processing module in the driver, and the electromagnetic conversion principle is used to realize the conversion of analog-to-digital audio signals to electromagnetic signals and then to audio signals, and finally the signals are sent to the human ear through the hearing aid, effectively ensuring that the indoor broadcast voice is received and heard by people wearing hearing aids to the greatest extent, truly realizing the effective transmission of indoor broadcast voice for people wearing hearing aids.

[0103] The above are only some embodiments of the present invention. For those skilled in the art, several modifications and improvements can be made without departing from the creative concept of the present invention, which all belong to the protection scope of the present invention.

Claims

1. An indoor broadcast voice hearing aid driver system, applied to an indoor environment where a hearing aid driver and a current loop are installed, characterized in that: include: Analog audio input interface module and digital audio input interface module are used to obtain indoor voice signals; An analog audio processing module, electrically connected to the analog audio input interface module, for receiving a broadcast voice signal and processing the broadcast voice signal to obtain an analog broadcast voice signal; A digital audio processing module, electrically connected to the output end of the digital audio input interface module, for isolating and receiving digital broadcast voice signals, and sending analog broadcast voice signals to the embedded processor module for data processing; An audio signal processing module, electrically connected to the control signal output terminal of the embedded processor module, electrically connected to the audio signal interface of the analog audio processing module, and processes the audio signals of the analog and digital audio input interfaces; The loop current electromagnetic conversion module is electrically connected to the output signal of the audio signal processing module. The output single-ended audio signal is converted into a differential audio signal after being processed by the differential amplifier circuit, and used as the input of the audio power amplifier circuit. The amplified audio differential signal is electrically connected to the output interface of the hearing aid driver to obtain a loop current signal. A loop wire is then connected to the output interface to generate a magnetic field signal. The magnetic field signal is then received by the hearing aid T gear to be converted into an amplified audio signal finally received by the human ear.

2. An indoor broadcast voice hearing aid driver system according to claim 1, characterized in that: It also includes an audio conversion module, the output end of the embedded processor module is electrically connected to the audio conversion module, and the output end of the audio conversion module is electrically connected to the audio signal processing module.

3. An indoor broadcast voice hearing aid driver system according to claim 2, characterized in that: Also connected to the embedded processor module are an LCD display screen and buttons with human-computer interaction functions.

4. The indoor broadcast voice hearing aid driver system according to claim 1, characterized in that: The analog audio processing module includes a first operational amplifier U1A, a second operational amplifier U1B, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, a twenty-third resistor R23, a twenty-fourth resistor R24, a twenty-fifth resistor R25, a twenty-sixth resistor R26, a twenty-seventh resistor R27, and a transformer T1; The positive power supply terminal VCC of the first operational amplifier U1A is electrically connected to the 5V power supply terminal, and is also electrically connected in parallel with the second capacitor C2 and the first capacitor C1 and then grounded. The negative power supply terminal VEE of the first operational amplifier U1A is grounded. The output terminal of the first operational amplifier U1A is electrically connected to the audio signal processing module. The twenty-fifth resistor R25 and the seventh capacitor C7 are connected in parallel between the output terminal of the first operational amplifier U1A and the inverting input terminal of the first operational amplifier U1A. The non-inverting input terminal of the first operational amplifier U1A is electrically connected to the inverting input terminal of the second operational amplifier U1B through the twenty-third resistor R23. The output terminal of the second operational amplifier U1B is electrically connected to the inverting input terminal of the second operational amplifier U1B, and the non-inverting input terminal of the second operational amplifier U1B is electrically connected to the 5V power supply terminal through the twenty-sixth resistor R26, and is also electrically connected in parallel with the twenty-seventh resistor R27 and the eighth capacitor C8 and then grounded; The like-name end of the primary coil of the transformer T1 is electrically connected to the first end of the analog audio input interface module through the third capacitor C3, the different-name end of the primary coil of the transformer T1 is electrically connected to the second end of the analog audio input interface module, a fifth capacitor C5 is connected in series between the like-name end of the primary coil of the transformer T1 and the different-name end of the primary coil of the transformer T1, the like-name end of the secondary coil of the transformer T1 is grounded, the different-name end of the secondary coil of the transformer T1 is electrically connected to the inverting input end of the first operational amplifier U1A through the sixth capacitor C6 and the twenty-fourth resistor R24 ​​in sequence, and a fourth capacitor C4 is connected in series between the like-name end of the secondary coil of the transformer T1 and the different-name end of the secondary coil of the transformer T1.

5. The indoor broadcast voice hearing aid driver system according to claim 1, characterized in that: The audio signal processing module includes a processor U17, a crystal oscillator X4, a MOS tube Q1, an inductor B5, a one-hundred-and-seventh capacitor C107, a one-hundred-and-eighth capacitor C108, a one-hundred-and-ninth capacitor C109, a one-hundred-and-eleventh capacitor C110, a one-hundred-and-eleventh capacitor C111, a one-hundred-and-thirty-seventh capacitor C137, a one-hundred-and-forty-first capacitor C141, a one-hundred-and-forty-second capacitor C142, a one-hundred-and-forty-third capacitor C143, a one-hundred-and-forty-fourth capacitor C144, a one-hundred-and-forty-fifth capacitor C145, a one-hundred-and-forty-sixth capacitor C146, a one-hundred-and-forty-seventh capacitor C147, a one-hundred-and-forty-eighth capacitor C148, and a one-hundred-and-forty-ninth capacitor C149 , the one-hundred-and-fiftieth capacitor C150, the one-hundred-and-fifty-fourth capacitor C154, the one-hundred-and-fifty-fifth capacitor C155, the one-hundred-and-fifty-eighth capacitor C158, the ninety-third resistor R93, the ninety-fourth resistor R94, the ninety-fifth resistor R95, the ninety-eighth resistor R98, the ninety-ninth resistor R99, the one-hundredth resistor R100, the one-hundred-and-first resistor R101, the one-hundred-and-second resistor R102, the one-hundred-and-third resistor R103, the one-hundred-and-seventh resistor R107, the one-hundred-and-fourteenth resistor R114, the one-hundred-and-fifteenth resistor R115, the one-hundred-and-sixty-second resistor R162, the one-hundred-and-sixty-fifth resistor R165, the one-hundred-and-sixth resistor R166, and the one-hundred-and-seventh resistor R167; The IO circuit power pin IOVDD of the processor U17 is electrically connected to the IO power supply end, the core circuit power pin PVDD of the processor U17 is connected to the two analog circuit power pins AVDD of the processor U17, the two digital circuit power pins DVDD of the processor U17 are connected together, the working voltage pin VDRIVE of the processor U17 is electrically connected to the IO power supply end through the ninety-third resistor R93, the gate and source of the MOS tube Q1 are electrically connected to the two ends of the ninety-third resistor R93 respectively, the drain of the MOS tube Q1 is connected to the digital power supply end through the inductor B5, and the inductor B5 is connected in parallel with the one hundred and ninth capacitor C109, the one hundred and seventh capacitor C107, and the one hundred and eighth capacitor C108 and then grounded; The first output voltage pin VOUT0 of the processor U17 is connected to the differential amplifier circuit through the one hundred and fifty-fourth capacitor C154 and the one hundred and seventh resistor R107 in sequence, the second end of the one hundred and seventh resistor R107 is grounded through the one hundred and fifty-fifth capacitor C155, the second output voltage pin VOUT1 of the processor U17 is grounded through the one hundred and fortyth capacitor C140, the third output voltage pin VOUT2 of the processor U17 is grounded through the one hundred and forty-first capacitor C141, and the fourth output voltage pin VOUT3 of the processor U17 is grounded through the one hundred and forty-second capacitor C142; The reset pin RESET# of the processor U17 is connected in parallel with two diodes, one of which is electrically connected to the analog positive power supply terminal, the digital filter pin FILTD of the processor U17 is grounded through the one hundred and forty-ninth capacitor C149 and the one hundred and fiftieth capacitor C150 connected in parallel, and the phase-locked loop pin PLL_LF of the processor U17 is connected in parallel with the one hundred and forty-seventh capacitor C147, the one hundred and forty-eighth capacitor C148, and the one hundred and second resistor R102 and then connected to the analog positive power supply terminal; The analog-to-digital conversion pin ADC1 of the processor U17 is electrically connected to the output end of the analog audio processing module through the 114th resistor R114, and the output pin ADC0 of the processor U17 is electrically connected to the input end of the audio conversion module through the 115th resistor R115 and the 137th capacitor C137 in sequence, and the 137th capacitor C137 is also grounded through the 158th capacitor C158; The 10th pin MP1 / SDATA_IN0 of the processor U17 is electrically connected to the data output port DOUT through the 165th resistor R165, the 8th pin of the processor U17 is electrically connected to the left and right audio channel clock pins LRCKO through the 166th resistor R166, and the 9th pin of the processor U17 is electrically connected to the main clock pin BCKO through the 167th resistor R167; The clock output pin OSCO of the processor U17 is grounded through the one-hundred-eleventh capacitor C110, the main clock input pin MCLKI of the processor U17 is electrically connected to the common end of the one-hundred-eleventh capacitor C110 through the ninety-fourth resistor R94 and the ninety-fifth resistor R95 in sequence, the first end of the ninety-fourth resistor R94 is also electrically connected to the main clock signal MCK through the one-hundred-sixty-second resistor R162, the second end of the ninety-fourth resistor R94 and the common end of the one-hundred-eleventh capacitor C110 are connected to the crystal oscillator X4, and the crystal oscillator X4 is grounded through the one-hundred-eleventh capacitor C111; The analog-to-digital conversion output pin ADC_RES of the processor U17 is grounded through the one hundred and first resistor R101, the analog filter pin FILTA of the processor U17 is grounded through the one hundred and forty-fifth capacitor C145 and the one hundred and forty-sixth capacitor C146 connected in parallel, and the reference voltage pin CM of the processor U17 is grounded through the one hundred and forty-third capacitor C143 and the one hundred and forty-fourth capacitor C144 connected in parallel.

6. The indoor broadcast voice hearing aid driver system according to claim 1, characterized in that: The loop current electromagnetic conversion module includes a power amplifier U6, a first ferrite bead FB1, a second ferrite bead FB2, an eighth capacitor C8, an eleventh capacitor C11, a twelfth capacitor C12, a seventeenth capacitor C17, an eighteenth capacitor C18, a twenty-second capacitor C22, a twenty-third capacitor C23, a twenty-fifth capacitor C25, a twenty-eighth capacitor C28, a twenty-ninth capacitor C29, a thirtieth capacitor C30, a thirty-first capacitor C31, a thirty-second capacitor C32, a thirty-third capacitor C33, a thirty-fourth capacitor C34, a thirty-fifth capacitor C35, a thirty-third capacitor C36, a thirty-third capacitor C37, a thirty-third capacitor C38, a thirty-fifth capacitor C39, a thirty-fifth capacitor C40, a thirty-first capacitor C41, a thirty-second capacitor C42, a thirty-third capacitor C43, a thirty-fourth capacitor C44, a thirty-fifth capacitor C45, a twenty-third capacitor C46, ​​a thirty-fifth capacitor C47, a thirty-fifth capacitor C48, a thirty-fifth capacitor C49, a thirty-fifth capacitor C41, a thirty-fifth capacitor C4 Capacitor C35, thirty-sixth capacitor C36, thirty-seventh capacitor C37, thirty-eighth capacitor C38, thirty-ninth capacitor C39, fortieth capacitor C40, forty-first capacitor C41, forty-second capacitor C42, forty-fourth capacitor C44, tenth resistor R10, nineteenth resistor R19, twentieth resistor R20, twenty-fifth resistor R25, twenty-seventh resistor R27, forty-ninth resistor R49, fiftieth resistor R50, fifty-first resistor R51, fifty-second resistor R52, relay J2, second inductor L2, third inductor L3; The first output pin OUTPA of the power amplifier U6 is electrically connected to the first pin and the second pin of the relay J2 through the second inductor L2 and the second ferrite bead FB2 in sequence, and the second output pin OUTNA of the power amplifier U6 is electrically connected to the third pin and the fourth pin of the relay J2 through the third inductor L3 and the first ferrite bead FB1 in sequence; the tenth resistor R10 and the eighteenth capacitor C18 are connected in series between the first end of the second inductor L2 and the first end of the third inductor L3 in sequence, the twelfth capacitor C12 and the eleventh capacitor C11 are connected in parallel between the second end of the second inductor L2 and the second end of the third inductor L3, the eighth capacitor C8 and the seventeenth capacitor C17 are connected in series between the first end of the second ferrite bead FB2 and the first end of the first ferrite bead FB1, and the eighth capacitor C8 and the seventeenth capacitor C17 are grounded; The third output pin PVCCA and the fourth output pin PVCCB of the power amplifier U6 are respectively electrically connected to the first end of the thirty-ninth capacitor C39, the first end of the twenty-ninth capacitor C29, the first end of the thirty-fifth capacitor C35, and the first end of the thirty-sixth capacitor C36 after being connected in parallel; the fifth output pin PGNDA and the sixth output pin PGNDB of the power amplifier U6 are respectively electrically connected to the second end of the thirty-ninth capacitor C39, the second end of the twenty-ninth capacitor C29, the second end of the thirty-fifth capacitor C35, and the second end of the thirty-sixth capacitor C36 after being connected in parallel; the first end of the thirty-sixth capacitor C36 is electrically connected to the 24V power supply terminal, and the second end of the thirty-sixth capacitor C36 is grounded; A twenty-seventh resistor R27 and a forty-fourth capacitor C44 are connected in series between the seventh output pin OUTPB and the eighth output pin OUTNB of the power amplifier U6; The SUB_GND pin of the power amplifier U6 is grounded; the first input pin INPA of the power amplifier U6 is connected in parallel to the thirty-first capacitor C31 and the thirty-seventh capacitor C37, the second input pin INNA of the power amplifier U6 is connected in parallel to the thirty-eighth capacitor C38 and the thirty-second capacitor C32, the thirty-seventh capacitor C37 and the thirty-second capacitor C32 are connected in series and grounded, and the first input pin INPA of the power amplifier U6 and the second input pin INNA of the power amplifier U6 are connected to the differential amplifier circuit; The SGND pin of the power amplifier U6 is grounded, the VDDS pin of the power amplifier U6 and the DIAG pin of the power amplifier U6 are electrically connected to both ends of the twentieth resistor R20, respectively, the VDDS pin of the power amplifier U6 is also grounded through the thirty-fourth capacitor C34, the VDDPW pin of the power amplifier U6 is electrically connected to the twenty-fifth resistor R25, the twenty-fifth resistor R25 is connected in series with the twentieth resistor R20, and the forty-first capacitor C41 is electrically connected between the VDDPW pin of the power amplifier U6 and the PGND pin of the power amplifier U6; The GAIN0 pin of the power amplifier U6 is connected in parallel with a forty-ninth resistor R49 and a fiftieth resistor R50, the fiftieth resistor R50 is grounded, the GAIN1 pin of the power amplifier U6 is connected in parallel with a fifty-first resistor R51 and a fifty-second resistor R52, the fifty-first resistor R51 is grounded, and the GAIN1 pin of the power amplifier U6 is also grounded through a fortieth capacitor C40; A twenty-third capacitor C23 is connected between the SVCC pin of the power amplifier U6 and the VSS pin of the power amplifier U6, a twenty-eighth capacitor C28 and a twenty-fifth capacitor C25 are connected in series between the INPB pin of the power amplifier U6 and the INNB pin of the power amplifier U6, the twenty-fifth capacitor C25 is grounded, and a forty-ninth resistor R49 and a thirty-third capacitor C33 are connected in parallel to the ROSC pin of the power amplifier U6 and then grounded; The MUTE pin and the STBY pin of the power amplifier U6 are connected to the GAIN1 pin of the power amplifier U6. The STBY pin of the power amplifier U6 is also connected in parallel to the forty-second capacitor C42 and then grounded. The SVR pin of the power amplifier U6 is grounded through the thirtieth capacitor C30. The VREF pin of the power amplifier U6 is grounded through the twenty-second capacitor C22.

7. An indoor broadcast voice hearing aid driver system according to claim 6, characterized in that: The differential amplifier circuit includes a third operational amplifier U5A, a fourth operational amplifier U5B, a ninth capacitor C9, a tenth capacitor C10, a thirteenth capacitor C13, a fourteenth capacitor C14, a fifteenth capacitor C15, a sixteenth capacitor C16, a fifty-ninth resistor R59, a sixtieth resistor R60, a sixty-first resistor R61, a sixty-second resistor R62, a sixty-third resistor R63, a sixty-fourth resistor R64, a sixty-fifth resistor R65, and a sixty-sixth resistor R66; The positive power terminal VCC of the third operational amplifier U5A is grounded through the thirteenth capacitor C13 and the thirty-first capacitor C31 connected in parallel, the negative power terminal VEE of the third operational amplifier U5A is grounded, and the output end of the third operational amplifier U5A is electrically connected to the first input pin INPA of the power amplifier U6 through the fifteenth capacitor C15 and the sixty-fifth resistor R65 in sequence; A sixty-sixth resistor R66 and a sixteenth capacitor C16 are connected in parallel between the output end of the third operational amplifier U5A and the inverting input end of the third operational amplifier U5A, the inverting input end of the third operational amplifier U5A is also electrically connected in sequence to a sixty-fourth resistor R64 and a fourteenth capacitor C14 and then connected to the audio signal processing module, and a twelfth capacitor C12 and a sixty-third resistor R63 are connected in parallel to the non-inverting input end of the third operational amplifier U5A and then grounded; The output end of the fourth operational amplifier U5B is electrically connected to the second input pin INNA of the power amplifier U6 through the eleventh capacitor C11 and the sixty-first resistor R61 in sequence, the tenth capacitor C10 and the sixtieth resistor R60 are connected in parallel between the output end of the fourth operational amplifier U5B and the inverting input end of the fourth operational amplifier U5B, and the inverting input end of the fourth operational amplifier U5B is also electrically connected to the fifty-ninth resistor R59 and the ninth capacitor C9 in sequence, and then connected to the single-ended audio signal; The non-inverting input terminal of the fourth operational amplifier U5B is electrically connected to the non-inverting input terminal of the third operational amplifier U5A, and the non-inverting input terminal of the fourth operational amplifier U5B is also grounded after being connected in parallel with the sixty-second resistor R62.

8. A method for implementing an indoor broadcast voice hearing aid driver, characterized in that: The implementation method is used to execute the indoor broadcast voice hearing aid driver system according to any one of claims 1 to 7, comprising the following steps: The hearing aid driver obtains the analog audio signal and the digital audio signal in the room through the analog audio input interface module and the digital audio input interface module respectively; The analog audio signal is connected to the analog audio processing module through an audio transformer to amplify the analog audio signal to obtain a standard analog voice signal; The digital audio signal passes through the digital audio processing module and the embedded processor module, and is converted into an analog signal through the audio conversion module; Both the standard analog voice signal and the analog signal are multi-processed by the audio signal processing module, and the processed audio signal is sent to the loop current electromagnetic conversion module to convert the loop current signal into a magnetic signal and send it out in the form of electromagnetic waves; After receiving the magnetic signal, the hearing aid converts and processes the signal, ultimately obtaining an audio signal that can be heard by the human ear.

9. The method for implementing an indoor broadcast voice hearing aid driver according to claim 8, characterized in that: The embedded processor module is also connected to an LCD display screen and buttons with a human-computer interaction function. Through the processing of human-computer interaction, the signal processing effect can be selected and the output of different audio effects can be achieved.

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