Distributed base station system

Abstract

The application relates to the technical field of communication, in particular to a distributed base station system, which comprises at least: a plurality of baseband chips, the baseband chips being UCP4008 chips; a field programmable gate array chip, a first data end of the field programmable gate array chip being connected with the plurality of baseband chips through optical fibers and performing data interaction with the baseband chips through a JESD protocol; a first data end and a second data end of a network switching device being communicatively connected with the plurality of baseband chips, the network switching device being used for realizing data interaction between a core network and the baseband chips; and a front panel device, a first data end of the front panel device being communicatively connected with a second data end of the field programmable gate array chip, the front panel device being used for transmitting data sent by the field programmable gate array chip to an air interface through a radio frequency antenna to provide a mobile access service function. The distributed base station system is lower in cost under the premise of guaranteeing overall performance.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of communication, in particular to a distributed base station system. BACKGROUND

[0002] At present, 5G base stations have weak signal coverage and unstable network, especially in some buildings with serious shielding or remote dwellings with insufficient macro station signal coverage. And with the increasing of online live broadcast, education, game, cloud VR / AR and other businesses, the deployment of small distributed base stations will increase. Compared with conventional macro base stations or indoor distributed base stations, small base stations have low cost, can be quickly and flexibly deployed, and meet the coverage needs of a certain area. Distributed small base stations can flexibly increase or reduce RRU (Remote Radio Unit) or antennas according to actual needs to adapt to changes in different coverage ranges and user densities.

[0003] In the traditional distributed base station scheme, the connection scheme between UCP4008 (a chip with a highly integrated general processing kernel and a domestic self-owned high-performance digital baseband kernel) and FPGA (Field-Programmable Gate Array) and RRU is that data transmission is performed between UCP4008 and FPGA through CPRI (Common Public Radio Interface) protocol, and then CPRI protocol is also used between FPGA and RRU. In this way, data can be transmitted from the UCP4008 chip to the RRU, and then transmitted to the user to complete the data interaction between the base station and the user. At present, the traditional base station scheme is a distributed scheme based on CPRI and eCPRI. These two transmission methods have high requirements for CPRI, eCPRI transmission rate, interface quantity and FPGA module, so the cost of FPGA is high. SUMMARY

[0004] In order to solve the above technical problems, a distributed base station system is provided in the embodiments of the present application.

[0005] The first aspect of the embodiments of the present application provides a distributed base station system, which at least includes:

[0006] A plurality of baseband chips, the baseband chips are UCP4008 chips;

[0007] A field programmable gate array chip, a first data end of the field programmable gate array chip is connected with a plurality of the baseband chips through optical fibers respectively, and data interaction is performed with the baseband chips through JESD protocol;

[0008] a network switching device, a first data end and a second data end of the network switching device are respectively connected with a plurality of the baseband chips, and the network switching device is configured to realize data interaction between a core network and the baseband chips;

[0009] a front panel device, a first data end of the front panel device is connected with a second data end of the field programmable gate array chip, and the front panel device is configured to transmit data sent by the field programmable gate array chip to an air interface through a radio frequency antenna to provide a mobile access service function.

[0010] In an optional embodiment of the present application, the plurality of baseband chips at least include a first baseband chip, a second baseband chip, a third baseband chip and a fourth baseband chip; wherein:

[0011] The first baseband chip, the second baseband chip and the third baseband chip are respectively connected with the second data end of the network switching device, and the fourth baseband chip is connected with the first data end of the network switching device, and the fourth baseband chip is configured to receive core network data and transmit the core network data to the first baseband chip, the second baseband chip and the third baseband chip through the network switching device.

[0012] In an optional embodiment of the present application, the fourth baseband chip communicates with the network switching device through a T-MAC protocol; and / or, the first baseband chip, the second baseband chip and the third baseband chip respectively communicate with the network switching device through a T-MAC protocol.

[0013] In an optional embodiment of the present application, the above-mentioned distributed base station system further includes:

[0014] a clock chip, the clock chip is connected with the first data end of the network switching device, and the clock chip is configured to provide a clock synchronization signal to the first baseband chip, the second baseband chip and the third baseband chip.

[0015] In an optional embodiment of the present application, the first baseband chip and / or the second baseband chip are deployed with a plurality of TDD NR cells;

[0016] The third baseband chip is deployed with an LTE cell.

[0017] In an optional embodiment of the present application, the number of the TDD NR cells is at least two; and / or, the number of the TDD NR cells is at least three.

[0018] In an optional embodiment of the present application, the first baseband chip and / or the second baseband chip each carries a physical layer and a protocol stack of the TDD NR cell; and / or, the third baseband chip carries a physical layer and a protocol stack of the LTE cell.

[0019] In an optional embodiment of the present application, the TDD NR cell is a 4T4R 100M TDD NR cell; and / or, the LTE cell is a 20M LTE FDD cell.

[0020] In an optional embodiment of the present application, the fourth baseband chip is deployed with an OAM function entity for realizing data transmission between the base station and the core network.

[0021] In an optional embodiment of the present application, the front panel is a radio remote unit entity.

[0022] In a first aspect, a first data end of a field programmable gate array chip FPGA is connected to a plurality of baseband chips through optical fibers, and data interaction is performed between the field programmable gate array chip FPGA and the baseband chips through a JESD protocol.

[0023] The traditional JESD (Joint Electronic Device Engineering Council, an international standard for describing and standardizing the process of transmitting radio frequency and microwave signals, including the description of signal amplitude, phase, frequency change, etc.) application mode is to transmit intermediate frequency data between the baseband chip and the Transceiver (radio frequency transceiver). The interface between the baseband and the radio frequency transceiver is internal, and in the embodiment of the present application, the data is carried by the optical fiber, but the data transmitted in the optical fiber is based on the JESD protocol, and the JESD protocol interface is used to replace the traditional CPRI transmission scheme between the UCP4008 and the field programmable gate array chip FPGA. The mapping mode and arrangement of IQ data (referring to two complex components, namely, In-phase (I) and Quadrature (Q)) of the JESD protocol are completely different from those of the CPRI protocol, and after data arrangement, data compression is not required, which can greatly reduce the demand for the number of CPRI interfaces of the field programmable gate array chip FPGA and the demand for the performance of the field programmable gate array chip FPGA, thereby reducing the cost. The embodiment of the present application realizes rapid deployment by applying the integrated base station of the UCP4008 chip to the distributed base station scheme.

[0024] In a second aspect, the data arrangement manners of the JESD protocol interface and the CPRI protocol interface are completely different. The JESD scheme does not need to compress data, so it does not need to reserve space for compression information at the front end as the CPRI protocol does, thereby saving data space. In addition, the data of the JESD protocol interface is arranged in sequence according to the antennas from 0 to 3, and the arrangement manner is simpler, and the requirements for the number and performance of the field programmable gate array (FPGA) are lower. The field programmable gate array (FPGA) can be flexibly selected according to actual needs, and the cost of the field programmable gate array (FPGA) and the overall system cost are greatly reduced. BRIEF DESCRIPTION OF DRAWINGS

[0025] The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and serve to explain the application without imposing undue limitation thereon. In the drawings:

[0026] Figure 1 FIG. 1 is a schematic diagram of an interactive structure of a traditional distributed base station system;

[0027] Figure 2 FIG. 2 is a schematic diagram of a structure of a distributed base station system provided by an embodiment of the application;

[0028] Figure 3 FIG. 3 is a schematic diagram of data arrangement of a traditional CPRI protocol interface;

[0029] Figure 4 FIG. 4 is a schematic diagram of data arrangement of a JESD protocol interface corresponding to different antennas in a distributed base station system provided by an embodiment of the application;

[0030] Figure 5 FIG. 5 is a schematic diagram of data arrangement of a JESD protocol interface in a distributed base station system provided by an embodiment of the application. DETAILED DESCRIPTION

[0031] In the process of implementing the application, the applicant finds that the FPGA cost in the current distributed base station is high.

[0032] In view of the above problems, an embodiment of the application provides a kind of distributed base station system. In order to make the purpose, technical scheme and advantage of the application more clear and obvious, the following is by embodiment, and combining with the drawings, the distributed base station system of the application is further detailed. It should be understood that the specific embodiments described herein are only used to explain the application, and not to limit the application.

[0033] The serial numbers of components in this document, such as "first", "second", etc., are only used to distinguish the described objects, and do not have any sequential or technical meaning. The "connection" and "coupling" in the present application, unless otherwise specified, include direct and indirect connections (couplings). In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise" and the like is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application.

[0034] In the present application, unless otherwise expressly specified and limited, the first feature is "on" or "under" the second feature, which can be direct contact between the first and second features, or indirect contact between the first and second features through an intermediate medium. Moreover, the first feature "above", "over" and "on" the second feature can be directly above or obliquely above the first feature, or only indicate that the horizontal height of the first feature is higher than that of the second feature. The first feature "below", "under" and "under" the second feature can be directly below or obliquely below the first feature, or only indicate that the horizontal height of the first feature is less than that of the second feature.

[0035] At present, the 5G base station has the problems of weak signal coverage and unstable network, especially in some buildings with serious shielding or remote dwellings with insufficient macro station signal coverage. And with the increasing of online live broadcast, education, game, cloud VR / AR and other services, the deployment of small distributed base stations will increase. Compared with conventional macro base stations or indoor distributed base stations, small base stations have low cost, can be quickly and flexibly deployed, and meet the coverage needs of a certain area. Distributed small base stations can flexibly increase or reduce RRU(Remote Radio Unit, Remote Radio Unit) or antennas according to actual needs, adapt to changes in different coverage ranges and user densities.

[0036] The connection scheme between the UCP4008 chip (a chip with a highly integrated general processing kernel and a domestic self-owned high-performance digital baseband kernel) and the FPGA (Field-Programmable Gate Array) and the RRU in the traditional distributed base station scheme is that data transmission is performed between the UCP4008 and the FPGA through the CPRI (Common Public Radio Interface) protocol, and then the data transmission is performed between the FPGA and the RRU through the CPRI protocol, so that the data can be transmitted from the UCP4008 chip to the RRU, and then transmitted to the user to complete the data interaction between the base station and the user. The current traditional base station scheme is a distributed scheme based on CPRI and eCPRI. The two transmission modes have high requirements for the CPRI and eCPRI transmission rate, the interface quantity and the FPGA module, and therefore the cost of the FPGA is high.

[0037] Please refer to Figure 2 To solve the above problems, the embodiment of the present application provides a distributed base station system, which at least comprises a baseband chip, a field programmable gate array chip FPGA, a network switching device switch and a front panel device, wherein:

[0038] The number of the baseband chips is multiple, and the baseband chip is a UCP4008 chip.

[0039] The first data end of the field programmable gate array chip FPGA is connected with multiple baseband chips through optical fibers, and data interaction is performed with the baseband chips through the JESD protocol.

[0040] The first data end and the second data end of the network switching device switch are respectively connected with multiple baseband chips in communication, and the network switching device switch is used for realizing data interaction between the core network and the baseband chip.

[0041] The first data end of the front panel device is connected with the second data end of the field programmable gate array chip FPGA in communication, and the front panel device is used for transmitting the data sent by the field programmable gate array chip FPGA to the air interface through a radio frequency antenna to provide a mobile access service function.

[0042] As Figure 1As shown, in the conventional scheme, the DU (Distributed Unit, an important logical network element in the 5G network, mainly responsible for processing of wireless signals and base station control, including processing of physical layer functions and real-time requirements) - field programmable gate array chip FPGA - RRU, wherein the DU and the field programmable gate array chip FPGA are externally connected, and data transmission is performed therebetween based on CPRI.

[0043] In a first aspect, a first data terminal of the field programmable gate array chip FPGA is connected to a plurality of baseband chips through optical fibers, and data interaction is performed with the baseband chips through JESD protocol, that is, the field programmable gate array chip FPGA and the baseband chips are connected through optical fibers, and data interaction is performed with the baseband chips through JESD protocol.

[0044] The conventional JESD (Joint Electronic Device Engineering Council, an international standard for describing and standardizing the transmission process of radio frequency and microwave signals, including description of signal amplitude, phase, frequency change, etc.) application mode is to transmit intermediate frequency data between the baseband chip and the Transceiver (radio frequency transceiver). The baseband and the radio frequency transceiver are internally connected, and in the embodiment of the application, the data is carried by the optical fiber, but the data transmitted in the optical fiber is based on the JESD protocol, and the JESD protocol interface is used to replace the traditional CPRI transmission scheme between the UCP4008 and the field programmable gate array chip FPGA. The mapping mode and arrangement of IQ data (referring to two complex components, namely, In-phase (I) and Quadrature (Q)) of the JESD protocol are completely different from those of the CPRI protocol, and after data arrangement, data compression is not required, which can greatly reduce the demand for the number of CPRI interfaces of the field programmable gate array chip FPGA and the demand for the performance of the field programmable gate array chip FPGA, thereby reducing the cost. The embodiment of the application realizes rapid deployment by applying the integrated base station of the UCP4008 chip to the distributed base station scheme.

[0045] Please refer to Figures 3-5 The data arrangement schemes of the JESD protocol and the conventional CPRI protocol interface are compared as follows:

[0046] CPRI protocol interface: NR (New Radio, a new radio technology, also known as 5G NR or 5G New Air Interface, is a global 5G standard based on OFDM (Orthogonal Frequency Division Multiplexing) air interface design), for example Figure 3In each cell, there are 32 AxC (Application Exchange Control, a technology for controlling and managing application exchange, used to support exchange and transmission between application programs, and data exchange between application programs and network) from AxC0 to AxC31. The AxC0-AxC31 area is the IQ data of NR cell antenna 0, the AxC0-AxC31 area is the IQ data of NR cell antenna 1, the front is the control area and the reserved area, and the last is the compression area.

[0047] JESD protocol interface: please refer to Figure 4 Take slot0-slot7 (slot refers to a time slot, which is a unit of time divided in time to transmit information) as an example, the data length of one antenna is 123008 bytes, data blocks 0, 4, 8, …, 15364, 15368, 15372 are the IQ data of the first antenna, data blocks 1, 5, 9, …, 15365, 15369, 15373 are the IQ data of the second antenna, and so on.

[0048] For convenience, it is assumed that there are two antenna ports 0 and 1, and there are 56 data blocks numbered 0-55, where the area is antenna 0 and the green area is antenna 1, and the arrangement of the data blocks in the antennas is as shown in Figure 5 The second aspect, please refer to Figures 3-5 Comparison, JESD protocol interface and CPRI protocol interface data arrangement is completely different, JESD scheme does not need to compress the data processing, so need not like CPRI protocol, in front of the compression information reserved space, save data space; In addition, the data of the JESD protocol interface is arranged in order according to the antenna from 0 to 3, and the arrangement is simpler, and the number and performance requirements of the field programmable gate array chip FPGA are lower, and any lower configuration field programmable gate array chip FPGA can be selected flexibly according to actual needs, greatly reducing the cost of field programmable gate array chip FPGA and the cost of the whole system.

[0049] Please continue to refer to Figure 2 In an optional embodiment of the present application, the plurality of baseband chips include at least: a first baseband chip UCP4008-1, a second baseband chip UCP4008-2, a third baseband chip UCP4008-3, and a fourth baseband chip UCP4008-4; wherein:

[0050] The first baseband chip UCP4008-1, the second baseband chip UCP4008-2, and the third baseband chip UCP4008-3 are respectively connected in communication with a second data end of the network switching device switch, and the fourth baseband chip UCP4008-4 is connected in communication with a first data end of the network switching device switch, and the fourth baseband chip UCP4008-4 is configured to receive core network data and transmit the core network data to the first baseband chip UCP4008-1, the second baseband chip UCP4008-2, and the third baseband chip UCP4008-3 through the network switching device switch.

[0051] In an optional embodiment of the present application, the fourth baseband chip UCP4008-4 communicates with the network switching device switch through a T-MAC protocol; and / or, the first baseband chip UCP4008-1, the second baseband chip UCP4008-2, and the third baseband chip UCP4008-3 respectively communicate with the network switching device switch through a T-MAC protocol.

[0052] In an optional embodiment of the present application, the distributed base station system further comprises a clock chip; the clock chip is connected in communication with a first data end of the network switching device switch, and the clock chip is configured to provide a clock synchronization signal to the first baseband chip UCP4008-1, the second baseband chip UCP4008-2, and the third baseband chip UCP4008-3, so as to provide an accurate clock to the baseband chips to ensure that all devices on the board card can keep clock synchronization.

[0053] In an optional embodiment of the present application, the first baseband chip UCP4008-1 and / or the second baseband chip UCP4008-2 are deployed with a plurality of TDD NR (Time Division Duplexing New Radio) cells; and the third baseband chip UCP4008-3 is deployed with an LTE (Long Term Evolution) cell.

[0054] In an optional embodiment of the present application, the number of TDD NR cells is at least two; and / or, the number of TDD NR cells is at least three.

[0055] In an optional embodiment of the present application, the first baseband chip UCP4008-1 and / or the second baseband chip UCP4008-2 each carries a physical layer and a protocol stack of the TDD NR cell; and / or, the third baseband chip UCP4008-3 carries a physical layer and a protocol stack of the LTE cell.

[0056] In an optional embodiment of the present application, the TDD NR cell is a 4T4R 100M TDD NR cell; and / or, the LTE cell is a 20M LTE FDD cell.

[0057] For example Figure 2 The UCP4008-1 chip can deploy 2 4T4R 100M TDD NR cells, and the L1 (physical layer) and L2 (protocol stack) of the cells can be deployed on a single UCP4008 chip.

[0058] For example Figure 2 The UCP4008-2 chip has the same functions as the UCP4008-1 chip, and 2 4T4R 100M TDD NR cells can also be deployed on the UCP4008-2 chip.

[0059] For example Figure 2 The UCP4008-3 chip can separately deploy LTE cells, and can support 3 2T2R 20M LTE FDD cells, and the L1 (physical layer) and L2 (protocol stack) of the three cells can be carried on the UCP4008-3 chip.

[0060] The distributed base station system provided by the embodiments of the present application can deploy 4G and 5G cells based on the UCP4008 baseband chip, the front-end interface is replaced by the JESD protocol interface instead of the traditional CPRI interface, and the JESD204B 4lane configuration can provide a transmission rate of 40Gbps, which can meet the transmission requirements of the NR single-chip 100M 4T4R double-cell and the LTE single-chip 20M 2T2R three-cell, and greatly improves the overall performance of the distributed base station system.

[0061] When performing signal synchronization between the LTE cell and the NR cell, the time and frequency are easy to be unsynchronized, therefore, in an optional embodiment of the present application, the clock chip is further configured to segment and down-sample the first air interface data of a signal sending cell to obtain a plurality of groups of primary synchronization signal sequences with the same symbol length, and adjacent primary synchronization signal sequences contain the same symbol; wherein, the signal sending cell is an LTE cell or an NR cell; calculate the correlation degree of each segment of data in the plurality of groups of primary synchronization signal sequences and the first air interface data to obtain coarse synchronization position information with the largest correlation degree with the first air interface data.

[0062] Based on the coarse synchronization position information and the data synchronization length, determine a to-be-synchronized signal in the first air interface data, the to-be-synchronized signal includes: a primary synchronization signal, a first auxiliary synchronization signal and a second auxiliary synchronization signal.

[0063] determining an actual secondary synchronization signal and a cell ID from the first secondary synchronization signal and the second secondary synchronization signal;

[0064] performing frequency offset calculation on the actual secondary synchronization signal and the primary synchronization signal to obtain frequency offset information;

[0065] performing time synchronization according to the frequency offset information and the cell ID.

[0066] In an optional embodiment of the present application, the determining of the actual secondary synchronization signal and the cell ID from the first secondary synchronization signal and the second secondary synchronization signal comprises:

[0067] respectively converting the first secondary synchronization signal and the second secondary synchronization signal into frequency domain data;

[0068] respectively performing inverse descrambling calculation on the first secondary synchronization signal and the second secondary synchronization signal of the frequency domain data to obtain inverse descrambling results and the cell ID;

[0069] taking the larger secondary synchronization signal in the inverse descrambling results as the actual secondary synchronization signal.

[0070] In an optional embodiment of the present application, before the segmenting and down-sampling of the first air interface data, the clock chip is further configured to receive center frequency point information issued by an upper node; and convert the obtained second air interface data into first air interface data corresponding to a frequency of the center frequency point information based on the center frequency point information.

[0071] In an optional embodiment of the present application, the symbol length of the primary synchronization signal sequence is less than the correlation calculation length; correspondingly, the clock chip is further configured to perform automatic gain control on the primary synchronization signal sequence, so that the symbol length of the gain-controlled primary synchronization signal sequence meets the correlation calculation requirement.

[0072] In an optional embodiment of the present application, the calculating of the correlation degrees of each segment of data in the plurality of groups of primary synchronization signal sequences and the first air interface data to obtain coarse synchronization position information with the largest correlation degree with the first air interface data comprises: performing conjugate calculation on the plurality of groups of primary synchronization signal sequences to obtain a plurality of groups of conjugate symmetric signals; performing sliding correlation calculation on the first air interface data through the plurality of groups of conjugate symmetric signals to obtain a plurality of groups of correlation value sequences representing the correlation degrees with the first air interface data; performing normalization processing on the plurality of groups of correlation value sequences to calculate power values of each segment of data in each of the correlation value sequences; and determining the coarse synchronization position information with the largest correlation degree with the first air interface data based on the largest power value.

[0073] In an optional embodiment of the present application, after the normalization processing of the multiple groups of correlation value sequences is performed to calculate the power values of each piece of data in each correlation value sequence, the clock chip is further configured to sequentially determine whether the power values of each piece of data are greater than a preset power value; if the power values of each piece of data are not greater than the preset power value, the second air interface data is reacquired; if the power value of at least one piece of data is greater than the preset power value, the coarse synchronization position information with the largest correlation degree with the first air interface data is determined based on the largest power value.

[0074] In an optional embodiment of the present application, the determination of the to-be-synchronized signal in the first air interface data based on the coarse synchronization position information and the data synchronization length, the clock chip is further configured to determine the to-be-synchronized signal including the primary synchronization signal, the first auxiliary synchronization signal and the second auxiliary synchronization signal in the first air interface data based on the coarse synchronization position information, the data synchronization length and the symbol positions of each piece of data in the current communication protocol.

[0075] In an optional embodiment of the present application, the frequency offset information obtained by performing frequency offset calculation on the actual auxiliary synchronization signal and the primary synchronization signal includes: converting the primary synchronization signal into primary synchronization frequency domain data which is frequency domain data of the primary synchronization signal; and calculating the frequency offset information of the primary synchronization frequency domain data and actual auxiliary synchronization frequency domain data which is frequency domain data corresponding to the actual auxiliary synchronization signal.

[0076] The overall performance of the distributed base station system provided by the embodiments of the present application is described as follows in combination with all the above embodiments:

[0077] The number of baseband chips is taken as an example of 4, including: a first baseband chip UCP4008-1, a second baseband chip UCP4008-2, a third baseband chip UCP4008-3 and a fourth baseband chip UCP4008-4. The first baseband chip UCP4008-1, the second baseband chip UCP4008-2, the third baseband chip UCP4008-3 and the fourth baseband chip UCP4008-4 and the field programmable gate array chip FPGA constitute a 4-chip distributed base station system, wherein: the first baseband chip UCP4008-1 and the second baseband chip UCP4008-2 are L1 / L2 of NR, and can support 2CC 4TR of NR 100M cell.

[0078] A piece of UCP4008-3 chip deploys LTE(Long Term Evolution, long-term evolution of UMTS(Universal Mobile Telecommunications System) technology standard of 3GPP(The 3rd Generation Partnership Project) organization) L1(physical layer) / L2(protocol stack), a single UCP4008-3 baseband chip can support 3CC 2TR 30M LTE FDD mode cell; the transmission rate and parameters of the LTE FDD mode cell are as shown in the following table 1:

[0079] Table 1

[0080] M S N L F K Sampling rate Indicator Rate Sysref frequency 5G 16 1 16 4 8 32 122.88M 2CC-4TR 9.8304G 3.84M 4G 16 1 16 2 16 32 30.72M 4CC-2TR 4.9152G 0.96M

[0081] The data transmission mode of the first baseband chip UCP4008-1, the second baseband chip UCP4008-2, the third baseband chip UCP4008-3 and the field programmable gate array chip FPGA is JESD protocol, so that the field programmable gate array chip FPGA only needs three interfaces to meet the data transmission demand of the entire four NR 100M TDD 4T4R cells+three LTE 20M FDD 2T2R.

[0082] The rate of option8 / 9 / 10 in the traditional CPRI protocol transmission mode is as follows:

[0083] CPRl line bit rate option 8: 10137.6Mbit / s, 64B / 66B line coding(20x491.52x 66 / 64Mbits)

[0084] CPRl line bit rate option 9: 12165.12Mbit / s, 64B / 66B line coding(24x491.52x 66 / 64Mbits)

[0085] CPRl line bit rate option 10: 24330.24Mbit / s, 64B / 66B line coding(48x491.52x 66 / 64Mbits)

[0086] When the data is transmitted from the DU to the field programmable gate array chip FPGA through the CPRI protocol interface, taking option10 as an example, the transmission rate is 24G bit / s, and the field programmable gate array chip FPGA has the following requirements:

[0087] 1) High-speed interface support: Field Programmable Gate Array (FPGA) chips need to support high-speed interfaces capable of handling data transfer rates of 24 Gbps. Modern high-end FPGA chips usually have multiple high-speed SerDes (SERializer / DESerializer) channels, supporting various high-speed serial protocols such as 10GbE, 25GbE, PCIe Gen3 / Gen4, etc.

[0088] 2) Multi-channel support: Multiple SerDes channels may be required to achieve the desired total bandwidth.

[0089] 3) High-speed data throughput: FPGA chips need sufficient logic resources (LUTs, FFs) and DSP (Digital Signal Processing) modules to handle 24 Gbps data streams. This includes but is not limited to decoding, demultiplexing, error detection and correction, etc.

[0090] 4) High-performance PLL (Phase-Locked Loop): used to generate stable clock signals to ensure data transmission accuracy and integrity.

[0091] 5) Clock management: FPGA chips need to support complex clock management mechanisms to ensure clock synchronization of all high-speed SerDes interfaces and internal logic circuits.

[0092] The application uses optical fiber to connect the baseband chip and the FPGA, and uses the JESD protocol interface to transmit data between the baseband chip and the FPGA. Compared with the traditional CPRI protocol, using the JESD204B / C protocol interface, taking 24G bit / s transmission rate as an example, the advantages of a pair of FPGAs mainly include the following aspects:

[0093] 1) Protocol characteristics:

[0094] CPRI protocol interface: involves more protocol layers and control information, including data compression, time slot synchronization, etc.

[0095] JESD204B / C protocol interface: focuses more on high-speed data transmission, simplifies data compression process, simplifies protocol stack, and mainly focuses on data frame structure and synchronization mechanism.

[0096] 2) Differences in FPGA requirements:

[0097] 2.1 High-speed serial interface support

[0098] For data transmission rates of 24 Gbps, both CPRI protocol interfaces and JESD204B / C protocol interfaces require support for high-speed SerDes (Serializer / Deserializer) interfaces. However, JESD204B / C protocol interfaces may place more emphasis on frame synchronization and clock recovery mechanisms for data.

[0099] 2.2 Data processing capabilities

[0100] CPRI protocol interface: Requires handling of additional protocol layer information such as data compression, decompression, time slot synchronization, etc.

[0101] JESD204B / C protocol interface: Mainly focuses on data frame structure and synchronization mechanisms, without data compression and decompression processes, thus data processing is simpler and processing rate is improved.

[0102] 3) Clock and synchronization

[0103] CPRI protocol interface: Requires handling of complex clock and frame synchronization mechanisms, including time slot synchronization, etc.

[0104] JESD204B / C protocol interface: Mainly relies on clock recovery and frame synchronization mechanisms, which are generally more simplified.

[0105] 4) Power consumption and heat dissipation

[0106] Due to the relatively simple data processing of JESD204B / C protocol interfaces, they have an advantage in terms of power consumption.

[0107] 5) Integration and programmability

[0108] CPRI protocol interface: May require more hard-core IP support such as Ethernet MAC, protocol stack, etc.

[0109] JESD204B / C protocol interface: Generally has high integration and requires fewer external components.

[0110] In an optional embodiment of the present application, in the distributed base station system, the fourth baseband chip UCP4008-4 is deployed with an OAM function entity (Operation Administration and Maintenance, according to the actual needs of network operation of the operator, the management of the network is usually divided into three categories: operation (Operation), management (Administration), maintenance (Maintenance), abbreviated as OAM, the OAM function entity refers to the entity device that performs the OAM function), and the OAM function entity is used to realize data transmission between the base station and the core network.

[0111] The data interaction between the NR cell and the LTE cell and the core network can be transmitted to the network switching device switch through the T-MAC protocol interface (a relay access control (MAC) protocol specially designed for wireless sensor networks, aiming to reduce the idle listening time of nodes, thereby reducing energy consumption), and then transmitted to the fourth baseband chip UCP4008-4 for processing. The fourth baseband chip UCP4008-4 can be deployed with an OAM function, which is responsible for data transmission between the base station and the core network.

[0112] In an optional embodiment of the present application, the front panel is a radio remote unit entity.

[0113] The uplink and downlink data of the 5G cell and the 4G cell are all transmitted between the first baseband chip UCP4008-1, the second baseband chip UCP4008-2, the third baseband chip UCP4008-3 and the field programmable gate array chip FPGA through the JESD protocol interface. At the same time, the field programmable gate array chip FPGA can also convert the data into a set format and then transmit it to the front panel device, such as a radio remote unit entity RRU. In this way, the data on each cell can be transmitted to the air interface through the radio antenna, and then provide mobile access service functions for users.

[0114] It should be understood that, although the steps in the flowchart are shown in a sequential order, the steps are not necessarily performed in the order shown by the arrows. Unless explicitly stated otherwise, the steps can be performed in any order, and the steps can be performed in other sequences. Moreover, at least some of the steps in the diagram can include multiple sub-steps or multiple stages, which are not necessarily performed at the same time, but can be performed at different times, and the order of the sub-steps or stages can not be sequential, but can be round-robin or alternating with at least some of the other steps or sub-steps or stages of other steps.

[0115] The technical features of the above-described embodiments can be combined in any manner. For brevity, not all possible combinations of the technical features in the above-described embodiments are described, but it should be understood that any combination of the technical features is within the scope of the present disclosure as long as the combination does not result in contradictions.

[0116] The above-described embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation on the patent scope of the present application. It should be noted that, for those skilled in the art, several modifications and improvements can be made without departing from the concept of the present application, and these are within the protection scope of the present application. Therefore, the patent protection scope of the present application should be subject to the appended claims.

Claims

1. A distributed base station system, characterized by At least comprising: a plurality of baseband chips, the baseband chips are UCP4008 chips; a field programmable gate array chip, the first data end of the field programmable gate array chip is connected with a plurality of the baseband chips through optical fibers, and the field programmable gate array chip interacts with the baseband chips through JESD protocol; a network switching device, the first data end and the second data end of the network switching device are respectively connected with a plurality of the baseband chips, and the network switching device is used to realize data interaction between a core network and the baseband chips; a front panel device, the first data end of the front panel device is connected with the second data end of the field programmable gate array chip, and the front panel device is used to transmit data sent by the field programmable gate array chip to an air interface through a radio frequency antenna to provide mobile access service function.

2. The distributed base station system of claim 1, wherein, The plurality of baseband chips at least comprises: a first baseband chip, a second baseband chip, a third baseband chip and a fourth baseband chip; wherein: the first baseband chip, the second baseband chip and the third baseband chip are respectively connected with the second data end of the network switching device, and the fourth baseband chip is connected with the first data end of the network switching device, and the fourth baseband chip is used to receive core network data and transmit the core network data to the first baseband chip, the second baseband chip and the third baseband chip through the network switching device.

3. The distributed base station system of claim 2, wherein, The fourth baseband chip communicates with the network switching device through T-MAC protocol, and / or the first baseband chip, the second baseband chip and the third baseband chip respectively communicate with the network switching device through T-MAC protocol.

4. The distributed base station system of claim 2, wherein, Further comprising: a clock chip, the clock chip is connected with the first data end of the network switching device, and the clock chip is used to provide clock synchronization signals to the first baseband chip, the second baseband chip and the third baseband chip.

5. The distributed base station system according to claim 2, wherein: the first baseband chip and / or the second baseband chip are deployed with a plurality of TDD NR cells; the third baseband chip is deployed with an LTE cell.

6. The distributed base station system of claim 5, wherein, The number of the TDD NR cells is at least 2; and / or the number of the TDD NR cells is at least 3.

7. The distributed base station system of claim 5, wherein, The first baseband chip and / or the second baseband chip carry physical layers and protocol stacks of the TDD NR cells; and / or the third baseband chip carries physical layers and protocol stacks of the LTE cell.

8. The distributed base station system of claim 6, wherein, The TDD NR cell is a 4T4R 100M TDD NR cell; and / or the LTE cell is a 20M LTE FDD cell.

9. The distributed base station system according to claim 5, wherein: the fourth baseband chip is deployed with an OAM function entity, and the OAM function entity is used to realize data transmission between a base station and a core network.

10. The distributed base station system of claim 1, wherein, The front panel is a radio frequency remote unit entity.

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