Printed circuit board

Abstract

The invention provides a printed circuit board. The printed circuit board includes: a substrate; a first through portion and a second through portion penetrating a region between an upper surface and a lower surface of the substrate; a magnetic layer disposed in the first through portion; a voltage regulator provided in the second through portion; a first through hole penetrating a region between an upper surface and a lower surface of the magnetic layer; a first insulating layer disposed on the substrate, covering the magnetic layer and the voltage regulator, and filling the second through portion and the first through hole; a second through hole penetrating a region between an upper surface and a lower surface of the first insulating layer in the first through hole; a first wiring pattern disposed over the magnetic layer; a second wiring pattern disposed below the magnetic layer; and a first via pattern disposed in the second via and connecting the first wiring pattern and the second wiring pattern to each other.

Description

[0001] This application claims the benefit of priority from Korean Patent Application No. 10-2023-0131524 filed on October 4, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The present disclosure relates to a printed circuit board. Background Art

[0003] Recently, in order to reduce the size of semiconductor chips and improve power efficiency, it may be necessary to embed various passive devices (such as capacitors and inductors) in a package substrate. In the case of an inductor, it may be necessary to improve the inductance by changing the material and structure compared to a general chip component. Summary of the invention

[0004] An aspect of the present disclosure is to provide a printed circuit board that can achieve size reduction and increase integration.

[0005] An aspect of the present disclosure is to provide a printed circuit board that can improve power efficiency.

[0006] An aspect of the present disclosure is to provide a printed circuit board that can improve noise reduction effect.

[0007] One aspect of the present disclosure is to embed a voltage regulator (VR) and a magnetic composite inductor (MCI) in a substrate. If necessary, an integrated passive device (IPD) may be further embedded in the substrate.

[0008] For example, according to an example embodiment, a printed circuit board includes: a substrate; a first through-portion and a second through-portion, which penetrate the area between the upper surface and the lower surface of the substrate; a magnetic layer, which is arranged in the first through-portion; a voltage regulator, which is arranged in the second through-portion; a first through-hole, which penetrates the area between the upper surface and the lower surface of the magnetic layer; a first insulating layer, which is arranged on the substrate, covers the magnetic layer and the voltage regulator, and fills at least a portion of each of the second through-portion and the first through-hole; a second through-hole, which penetrates the area between the upper surface and the lower surface of the first insulating layer in the first through-hole; a first wiring pattern, which is arranged above the magnetic layer; a second wiring pattern, which is arranged below the magnetic layer; and a first via pattern, which is arranged in the second through-hole and connects the first wiring pattern and the second wiring pattern to each other.

[0009] An aspect of the present disclosure is to provide a magnetic film in a through-portion of a substrate and to form an MCI on the magnetic film.

[0010] For example, according to an example embodiment, a printed circuit board includes: a substrate having a through portion; a magnetic layer, which is spaced apart from the substrate in the through portion and has a plurality of through holes; an insulating layer, which covers the substrate and the magnetic layer, at least partially fills the space between the wall surface of the through portion and the side surface of the magnetic layer, and at least partially fills each of the plurality of through holes; a first wiring pattern, which is arranged above the insulating layer; a second wiring pattern, which is arranged below the insulating layer; and a plurality of via patterns, which respectively penetrate the insulating layer in the plurality of through holes and connect the first wiring pattern and the second wiring pattern to each other.

[0011] One aspect of the present disclosure is to provide an MCI and an integrated circuit die in a substrate.

[0012] For example, according to an example embodiment, a printed circuit board includes: a substrate having a first through-portion and a second through-portion spaced apart from each other; a magnetic layer disposed in the first through-portion; an inductor disposed in the magnetic layer; an integrated circuit die disposed in the second through-portion; and an insulating layer disposed on the substrate and at least partially filling the first through-portion and the second through-portion. The inductor includes: a first wiring pattern disposed above the magnetic layer; a second wiring pattern disposed below the magnetic layer; and a via pattern penetrating the magnetic layer and connecting the first wiring pattern and the second wiring pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The above and other aspects, features and advantages of the present disclosure will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which: Figure 1 A block diagram illustrating an example of an electronic device system; Figure 2 A perspective view showing an example of an electronic device; Figure 3 A cross-sectional view of an example of a printed circuit board is shown; Figure 4 Shown along Figure 3 A cross-sectional view taken along line AA' in FIG. FIG. 5A to FIG. 5E Shows the manufacturing Figure 3 A cross-sectional view of the process of manufacturing a printed circuit board in FIG. Figure 6 Shows Figure 3 A cross-sectional view of a modified example of a printed circuit board in FIG. Figure 7 Shown along Figure 6 A cross-sectional view taken along line BB' in FIG. Figure 8 shows a cross-sectional view of another example of a printed circuit board; Fig. 9 Shown along Figure 8 A cross-sectional view taken along line CC' in FIG. FIG. 10A to FIG. 10E Shows the manufacturing Figure 8 A cross-sectional view of the process of manufacturing a printed circuit board in FIG. Fig.11 Shows Figure 8 A cross-sectional view of a modified example of a printed circuit board in FIG. Fig.12 Shown along Fig.11 A cross-sectional view taken along line D-D'; Fig.13 a cross-sectional view showing an example of a coil portion; and Fig.14 Cross-sectional views showing various examples of the coil portion. DETAILED DESCRIPTION

[0014] Hereinafter, embodiments of the present disclosure will be described as follows with reference to the accompanying drawings.

[0015] Electronic Devices Figure 1 is a block diagram illustrating an example of an electronic device system.

[0016] Reference Figure 1 , the electronic device 1000 may house a mainboard 1010 therein. Chip-related components 1020, network-related components 1030, other components 1040, etc. may be physically or electrically connected to the mainboard 1010. These components may be connected to other electronic components to be described below through various signal lines 1090.

[0017] The chip-related components 1020 may include: memory chips, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory), etc.; application processor chips, such as central processing units (e.g., central processing units (CPUs)), graphics processors (e.g., graphics processing units (GPUs)), digital signal processors, cryptographic processors, microprocessors, microcontrollers, etc.; and logic chips, such as analog-to-digital converters (ADCs), application-specific integrated circuits (ASICs), etc. However, the chip-related components 1020 are not limited thereto, and may also include other types of chip-related components. In addition, the chip-related components 1020 may be combined with each other.

[0018] The network-related components 1030 may include components that are compatible with or operate according to protocols such as: Wireless Fidelity (Wi-Fi) (Institute of Electrical and Electronics Engineers (IEEE) 802.11 series, etc.), Worldwide Interoperability for Microwave Access (WiMAX) (IEEE 802.16 series, etc.), IEEE 802.20, Long Term Evolution (LTE), Evolution-Data Optimized (Ev-DO), High Speed ​​Packet Access + (HSPA+), High Speed ​​Downlink Packet Access + (HSDPA+), High Speed ​​Uplink Packet Access + (HSUPA+), Global System for Mobile Communications (GSM), Enhanced Data Rates for GSM Evolution (EDGE), Global Positioning System (GPS), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Bluetooth, third generation mobile communication technology (3G) protocols, fourth generation mobile communication technology (4G) protocols, and fifth generation mobile communication technology (5G) protocols, as well as any other wireless protocols and wired protocols specified after the above protocols. However, the network-related component 1030 is not limited thereto, and may also include components compatible with or operating according to various other wireless standards or protocols or wired standards or protocols. In addition, the network-related component 1030 may be combined with the chip-related component 1020 described above.

[0019] The other components 1040 may include high frequency inductors, ferrite inductors, power inductors, ferrite beads, low temperature co-fired ceramic (LTCC) components, electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCC), etc. However, the other components 1040 are not limited thereto and may also include passive components for various other purposes, etc. In addition, the other components 1040 may be combined with each other together with the above-mentioned chip-related components 1020 and / or network-related components 1030.

[0020] Depending on the type of the electronic device 1000, the electronic device 1000 may include other electronic components that are physically and / or electrically connected to the mainboard 1010 or that are not physically and / or electrically connected to the mainboard 1010. These other electronic components may include, for example, a camera 1050, an antenna 1060, a display 1070, and a battery 1080. However, these other electronic components are not limited thereto, and may include an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage unit (e.g., a hard disk drive), a compact disk (CD) drive, a digital versatile disk (DVD) drive, etc. In addition, depending on the type of the electronic device 1000, the electronic device 1000 may also include other electronic components for various purposes.

[0021] The electronic device 1000 may be a smart phone, a personal digital assistant (PDA), a digital video camera, a digital camera, a network system, a computer, a monitor, a tablet PC, a laptop PC, a netbook PC, a television, a video game console, a smart watch, an automobile component, etc. However, the electronic device 1000 is not limited thereto and may be any other electronic device capable of processing data.

[0022] Figure 2 is a perspective view showing an example of an electronic device.

[0023] Reference Figure 2 , the electronic device may be, for example, a smart phone 1100. A mainboard 1110 may be housed in the smart phone 1100, and various components 1120 may be physically and / or electrically connected to the mainboard 1110. In addition, other electronic components (such as a camera module 1130 and / or a speaker 1140) that are physically and / or electrically connected to the mainboard 1110 or that are not physically or electrically connected to the mainboard 1110 may be housed in the smart phone 1100. Some of the components 1120 may be the above-mentioned chip-related components, for example, a component package 1121, but the example embodiments thereof are not limited thereto. The component package 1121 may have the form of a printed circuit board on which an electronic component (including an active component and / or a passive component) is surface-mounted. Alternatively, the component package 1121 may be constructed in the form of a printed circuit board in which an electronic component (including an active component and / or a passive component) is buried. On the other hand, the electronic device is not necessarily limited to the smart phone 1100, and may also be other electronic devices as described above.

[0024] Printed Circuit Board Figure 3 is a cross-sectional view showing an example of a printed circuit board.

[0025] Figure 4 is along Figure 3 A cross-sectional view taken along line AA' in FIG.

[0026] Reference Figure 3 and Figure 4According to the example, the printed circuit board 100A may include: a substrate 111; a first through-portion H1 and a second through-portion H2, which penetrate the area between the upper surface and the lower surface of the substrate 111; a magnetic layer 150, which is arranged in the first through-portion H1; a voltage regulator 141, which is arranged in the second through-portion H2; a first through-hole h1, which penetrates the area between the upper surface and the lower surface of the magnetic layer 150; a first insulating layer 112, which is arranged on the substrate 111, covers the magnetic layer 150 and the voltage regulator 141 and fills at least a portion of each of the second through-portion H2 and the first through-hole h1; a second through-hole h2, which penetrates the area between the upper surface and the lower surface of the first insulating layer 112 in the first through-hole h1; a first wiring pattern B1, which is arranged above the magnetic layer 150; a second wiring pattern B2, which is arranged below the magnetic layer 150; and a first via pattern M1, which is arranged in the second through-hole h2 and connects the first wiring pattern B1 and the second wiring pattern B2 to each other. The inductor 131 may be disposed in the substrate 111 through the magnetic layer 150, and the first wiring pattern B1 and the second wiring pattern B2 and the first via pattern M1 are connected to each other to surround at least a portion of the magnetic layer 150. The first insulating layer 112 may be disposed between the first wiring pattern B1 and the upper surface of the magnetic layer 150 and between the second wiring pattern B2 and the lower surface of the magnetic layer 150. The first via pattern M1 may be disposed on the wall surface of the second through hole h2, and the inductor 131 may include a first filler R1 filling a space between the first via patterns M1 in the second through hole h2.

[0027] As described above, in the printed circuit board 100A according to the example, the magnetic layer 150 and the voltage regulator 141 may be respectively provided and embedded in the first through-portion H1 and the second through-portion H2 of the substrate 111 which may be the core layer, and the MCI type inductor 131 may be formed in the magnetic layer 150. For example, a structure in which the inductor 131 and the voltage regulator 141 are embedded together may be provided. In addition, the magnetic layer 150 formed using a magnetic film may be spaced apart from the wall surface of the first through-portion H1, and the first insulating layer 112 may fill the first through-portion H1, and more specifically, the first insulating layer 112 may at least partially fill the space between the wall surface of the first through-portion H1 and the side surface of the magnetic layer 150. Therefore, the MCI type inductor 131 may be formed in the magnetic layer 150. Therefore, the thinness and integration may be increased, and the power efficiency and noise reduction effect may also be improved. In addition, the inductor 131 may be implemented by forming a first through hole h1 in the magnetic layer 150, filling the first through hole h1 with the first insulating layer 112, forming a second through hole h2 having a smaller diameter than the first through hole h1 in a portion of the first insulating layer 112 located within the first through hole h1, and forming a first via pattern M1 by plating the inner side of the second through hole h2, so that the metal oxide included in the magnetic layer 150 may not be exposed to the surface, thereby preventing the magnetic layer 150 from being dissolved into an acid solution during a manufacturing process.

[0028] Therefore, the inductor 131 may include: a first wiring pattern B1 disposed above the magnetic layer 150; a second wiring pattern B2 disposed below the magnetic layer 150; and a first via pattern M1 penetrating the magnetic layer 150 and connecting the first wiring pattern B1 and the second wiring pattern B2. In addition, as described above, the inductor 131 may further include a first filler R1 filling a space between the first via patterns M1 in the second through hole h2.

[0029] The printed circuit board 100A according to the example may include: a third through hole h3 penetrating the region between the upper surface and the lower surface of the substrate 111 and being filled with the first insulating layer 112; a fourth through hole h4 penetrating the region between the upper surface and the lower surface of the first insulating layer 112 in the third through hole h3; a first wiring layer 121 disposed on the upper surface of the first insulating layer 112 and including a first wiring pattern B1; a second wiring layer 122 disposed on the lower surface of the first insulating layer 112 and including a second wiring pattern B2; and a second via pattern M2 disposed in the fourth through hole h4 and connecting the first wiring layer 121 and the second wiring layer 122 to each other. For example, a through via 132 may also be included. The second via pattern M2 may be disposed on the wall surface of the fourth through hole h4, and the through via 132 may include a second via pattern M2 and a second filler R2 filling a space between the second via pattern M2 in the fourth through hole h4. For example, the first wiring layer 121 and the second wiring layer 122 may be provided on the upper surface and the lower surface of the first insulating layer 112, respectively, so that various wiring designs can be realized. In addition, as a material of the substrate 111, various materials such as metal, glass, and silicon may be used in addition to organic insulating materials. In addition, when the inductor 131 is formed, the through via 132 for connection between the first wiring layer 121 and the second wiring layer 122 may be formed together, and therefore, the process may be simplified and the cost and time may be reduced.

[0030] The printed circuit board 100A according to the example may further include: a third through portion H3 penetrating the region between the upper surface and the lower surface of the substrate 111; and a passive device 142 disposed in the third through portion H3. The first insulating layer 112 may cover the passive device 142 and may fill the third through portion H3. For example, in addition to the inductor 131 and the voltage regulator 141, a structure in which the passive device 142 (such as an integrated passive device) is embedded together may be provided, and thus, in addition to the above-mentioned improvement in power efficiency, the noise reduction effect may be improved. In addition, the printed circuit board 100A according to the example may further include: a first via layer 133 including a connection via (i.e., a first connection via) penetrating the upper side of the first insulating layer 112 and connecting the first wiring layer 121 to the connection pad of each of the voltage regulator 141 and the passive device 142; and a second via layer 134 including a connection via (i.e., a second connection via) penetrating the lower side of the first insulating layer 112 and connecting the second wiring layer 122 to the lower surface of the voltage regulator 141. For example, the voltage regulator 141, the passive device 142, and the inductor 131 may be electrically connected to each other through the first via layer 133 and the first wiring layer 121. That is, the voltage regulator 141 and the first via pattern M1 may be connected to each other through a path passing through the first connection via and the first wiring layer 121. In addition, heat dissipation of the voltage regulator 141 may be achieved through the second via layer 134 and the second wiring layer 122.

[0031] The printed circuit board 100A according to the example may further include: a second insulating layer 113 disposed on the upper surface of the first insulating layer 112; a third insulating layer 114 disposed on the lower surface of the first insulating layer 112; a third wiring layer 123 disposed on the upper surface of the second insulating layer 113; a fourth wiring layer 124 disposed on the lower surface of the third insulating layer 114; a third via layer 135 including a connection via (i.e., a third connection via) penetrating the second insulating layer 113 and connecting the first wiring layer 121 and the third wiring layer 123 to each other; a fourth via layer 136 including a connection via (i.e., a fourth connection via) penetrating the third insulating layer 114 and connecting the second wiring layer 122 and the fourth wiring layer 124 to each other; a first resist layer 115 disposed on the upper surface of the second insulating layer 113 and having a first opening 115h exposing the third wiring layer 123; and a second resist layer 116 disposed on the lower surface of the third insulating layer 114 and having a second opening 116h exposing the fourth wiring layer 124.

[0032] Hereinafter, components of a printed circuit board 100A according to examples will be described in more detail with reference to the accompanying drawings.

[0033] The substrate 111 may be configured as a core layer. For example, the substrate 111 may include an organic core layer, a glass core layer, a metal core layer, a silicon core layer, or a ceramic core layer. The organic core layer may include an organic insulating material. The organic insulating material may include a thermosetting resin (such as an epoxy resin), a thermoplastic resin (such as polyimide), or a material including an inorganic filler, an organic filler, and / or glass fiber (for example, a glass fabric such as glass cloth) and a resin. For example, the organic insulating material may be a non-photosensitive insulating material such as a copper clad laminate (CCL), an Ajinomoto built-up film (ABF), or a prepreg (PPG), but example embodiments thereof are not limited thereto, and other polymer materials may be used. The glass core layer may include glass. The glass may include, for example, pure silicon dioxide (approximately 100% SiO 2), soda-lime glass, borosilicate glass, aluminosilicate glass, etc. However, its exemplary embodiments are not limited thereto, and optional glass materials (e.g., fluorine glass, phosphate glass, chalcogenide glass, etc.) may also be used as materials for the glass layer. In addition, other additives may be further included to form glass with specific physical properties. These additives may include magnesium, sodium, calcium, manganese, aluminum, lead, boron, iron, chromium, potassium, sulfur, antimony, and carbonates (e.g., calcium carbonate (e.g., limestone) and sodium carbonate (e.g., soda)) and / or oxides of these and other elements. Glass may be distinguished from the above-mentioned glass fiber. The metal core layer may include a metal. The metal may include, for example, copper (Cu), Invar, etc., but its exemplary embodiments are not limited thereto. The silicon core layer may include pure silicon (Si). If necessary, the silicon core layer may include an oxide layer formed on the silicon (Si). In addition, a nitride layer formed on the oxide layer may be included. The oxide layer may include a silicon oxide film, and the nitride layer may include a silicon nitride film, but its exemplary embodiments are not limited thereto. The ceramic core layer may include a ceramic material. Ceramic materials may include, for example, aluminum oxide (Al 2 O 3 ), aluminum nitride (AlN), silicon carbide (SiC), silicon nitride (Si 3 N 4 ) etc., but example embodiments thereof are not limited thereto.

[0034] The first insulating layer 112, the second insulating layer 113, and the third insulating layer 114 may include an organic insulating material. As described above, the organic insulating material may include a thermosetting resin (such as an epoxy resin), a thermoplastic resin (such as polyimide), or a material including an inorganic filler, an organic filler, and / or glass fiber (for example, a glass fabric such as glass cloth) and a resin. For example, the organic insulating material may be a non-photosensitive insulating material such as a copper clad laminate (CCL), an Ajinomoto built-up film (ABF), or a prepreg (PPG), but example embodiments thereof are not limited thereto, and other polymer materials may be used. The first insulating layer 112, the second insulating layer 113, and the third insulating layer 114 may include the same or different organic insulating materials. If desired, the first insulating layer 112, the second insulating layer 113, and the third insulating layer 114 may be constructed as a plurality of layers.

[0035] The first resist layer 115 and the second resist layer 116 may include a liquid solder resist or a film type solder resist, but example embodiments thereof are not limited thereto and may include other organic insulating materials such as ABF. The first resist layer 115 and the second resist layer 116 may have a first opening 115h and a second opening 116h, respectively. A plurality of first openings 115h and a plurality of second openings 116h may be provided. The first opening 115h and the second opening 116h may be formed in a solder mask defined (SMD) form and / or a non-solder mask defined (NSMD) form. The first opening 115h and the second opening 116h may expose the third wiring layer 123 and the fourth wiring layer 124, respectively, and a surface treatment layer may be provided on the surface of the exposed pattern. The surface finishing layer may be formed by electrolytic gold plating, electroless gold plating, organic solderability preservative (OSP) or electroless tin plating, electroless silver plating, electroless nickel plating / alternative gold plating, direct immersion gold (DIG) plating, hot air leveling (HASL), etc., but example embodiments are not limited thereto.

[0036] Each of the first wiring layer 121 (including the first wiring pattern B1), the second wiring layer 122 (including the second wiring pattern B2), the third wiring layer 123, and the fourth wiring layer 124 may include a metal material. The metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof, etc. Preferably, the metal material may include copper (Cu), but the exemplary embodiment thereof is not limited thereto. Each of the first wiring layer 121, the second wiring layer 122, the third wiring layer 123, and the fourth wiring layer 124 may perform various functions according to the design. For example, a signal pattern, a power pattern, a ground pattern, etc. may be included. Each of these patterns may have various forms such as lines, planes, and pads. The first wiring layer 121, the second wiring layer 122, the third wiring layer 123, and the fourth wiring layer 124 may include a seed layer and a metal layer formed on the seed layer. The seed layer may be configured as an electroless plating layer (eg, a chemical copper plating layer) and / or a sputtering layer, and the metal layer may be configured as an electrolytic plating layer (eg, an electrolytic copper plating layer), but example embodiments thereof are not limited thereto.

[0037] Each of the first via pattern M1 and the second via pattern M2 may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) and / or alloys thereof, etc. Preferably, copper (Cu) may be included, but example embodiments thereof are not limited thereto. The second via pattern M2 may perform various functions according to the design. For example, a signal via pattern, a power via pattern, and a ground via pattern may be included. The first via pattern M1 and the second via pattern M2 may include a seed layer and a metal layer formed on the seed layer. The seed layer may be an electroless plating layer (e.g., a chemical copper plating layer) and / or a sputtering layer, and the metal layer may be an electrolytic plating layer (e.g., an electrolytic copper plating layer), but example embodiments thereof are not limited thereto.

[0038] The first filler R1 and the second filler R2 may include a plugging material. The plugging material may include an insulating ink including an insulating resin such as an epoxy resin. However, example embodiments thereof are not limited thereto, and if necessary, the plugging material may include a conductive ink. The first filler R1 and the second filler R2 may be formed by the same process and thus may include the same material, but example embodiments thereof are not limited thereto.

[0039] A plurality of first through holes h1 and a plurality of second through holes h2 may be formed. For example, on a plane, a second through hole h2 having a smaller diameter may be formed in the first through hole h1. Therefore, a plurality of first via patterns M1 may also be formed, and a plurality of first via patterns M1 may be formed in the second through hole h2. As described above, the inductor 131 may include a plurality of first via patterns M1, and may include a plurality of first wiring patterns B1 and a plurality of second wiring patterns B2 connected to the plurality of first via patterns M1. The plurality of first wiring patterns B1 and the plurality of second wiring patterns B2 may be included in the first wiring layer 121 and the second wiring layer 122, respectively.

[0040] A plurality of third through holes h3 and a plurality of fourth through holes h4 may be formed. For example, on a plane, a fourth through hole h4 having a smaller diameter may be formed in the third through hole h3. Therefore, a plurality of second via hole patterns M2 formed in the fourth through hole h4 may also be provided. As described above, a plurality of through holes 132 may be formed.

[0041] Each of the first via layer 133, the second via layer 134, the third via layer 135, and the fourth via layer 136 may include a metal material. As described above, the metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof, etc. Preferably, the metal material may include copper (Cu), but the exemplary embodiment thereof is not limited thereto. Each of the first via layer 133, the second via layer 134, the third via layer 135, and the fourth via layer 136 may include a filled via that fills the via hole, and may also include a conformal via disposed along the wall surface of the via hole. Each of the first via layer 133, the second via layer 134, the third via layer 135, and the fourth via layer 136 may perform various functions according to the design. For example, a ground via, a power via, and a signal via may be included. The first via layer 133 and the second via layer 134 may include a connection via that tapers in opposite directions. More specifically, the first via layer 133 and the second via layer 134 may include a first connection via and a second connection via tapered in opposite directions, respectively. The third via layer 135 and the fourth via layer 136 may include connection vias tapered in opposite directions. More specifically, the third via layer 135 and the fourth via layer 136 may include a third connection via and a fourth connection via tapered in opposite directions, respectively. The first via layer 133, the second via layer 134, the third via layer 135, and the fourth via layer 136 may each include an electroless plating layer (e.g., a chemical copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer). A sputtering layer may be included instead of the electroless plating layer (e.g., a chemical copper plating layer), or if necessary, both the sputtering layer and the electroless plating layer may be included.

[0042] The voltage regulator 141 may include a circuit for regulating a voltage. The voltage regulator 141 may be configured as a chip-type electronic component. For example, the voltage regulator 141 may be configured in the form of a semiconductor chip, and more specifically, may be configured as an integrated circuit (IC) die in which hundreds to millions of elements are integrated into one chip. The integrated circuit die may be formed based on an effective wafer, and in this case, silicon (Si), germanium (Ge), gallium arsenide (GaAs) may be used as a base material for each body. Various circuits may be formed in the body. A connection pad may be formed on the front surface of the body (i.e., Figure 3 The connection pad may be formed on the upper surface of the main body (i.e., the upper surface of the main body), and the connection pad may include a conductive material such as aluminum (Al) or copper (Cu). If necessary, the connection pad may also be formed on the rear surface of the main body (i.e., Figure 3 If necessary, a plurality of voltage regulators 141 may be provided and the plurality of voltage regulators 141 may be disposed together in the second through-portion H2, or a plurality of second through-portions H2 may be formed and the plurality of voltage regulators 141 may be disposed therein, respectively.

[0043] The passive device 142 may be configured as a chip electronic component including a resistor, a capacitor, an inductor, an impedance matching component, or a combination thereof. For example, the passive device 142 may be configured as an integrated passive device (IPD), and the integrated passive device (IPD) may also be referred to as an integrated passive component (IPC) or an embedded passive component (EPC). If necessary, a plurality of passive devices 142 may be provided, and the plurality of passive devices 142 may be arranged together in the third through portion H3, or a plurality of third through portions H3 may be formed and the plurality of passive devices 142 may be arranged therein, respectively.

[0044] The magnetic layer 150 may include a magnetic material. The magnetic material may include, for example, a ferrite-based material, a permalloy-based material, and the like. For example, the magnetic material may include a Ni-based ferrite, a Ni-Zn-based ferrite, a Ni-Zn-Cu-based ferrite, a Fe-Si-Al (FeSiAl) alloy, a Ni-Mo-Fe (MPP: molybdenum permalloy powder core) alloy, a Ni-Fe (high magnetic flux core) alloy, and the like, but the exemplary embodiment thereof is not limited thereto, and other commonly used ferrite-based materials or permalloy-based materials may also be included. In addition, various types of magnetic materials including other magnetic particles may be used. The magnetic material may be used as a paste or a composition to fill the first through portion H1, and the magnetic material may be solidified to form the magnetic layer 150. In this case, the magnetic layer 150 may be in contact with the wall surface of the first through portion H1. For example, the magnetic layer 150 may be in contact with the substrate 111.

[0045] FIG. 5A to FIG. 5E It shows the manufacturing Figure 3 A cross-sectional view of the process of making a printed circuit board.

[0046] Reference Figure 5A , a first through portion H1, a second through portion H2, a third through portion H3, and a third through hole h3 may be formed in the substrate 111. The first through portion H1, the second through portion H2, the third through portion H3, and the third through hole h3 may be formed by various methods such as laser drilling, mechanical drilling, chemical etching, and sandblasting processes according to the material of the substrate 111. In addition, the first through hole h1 may be formed by mechanical drilling through a magnetic layer 150 in the form of a magnetic film or a magnetic sheet, the magnetic layer 150 may be cut into an appropriate size, and may be disposed in the first through portion H1. In addition, the voltage regulator 141 and the passive device 142 may be disposed in the second through portion H2 and the third through portion H3, respectively. The magnetic layer 150, the voltage regulator 141, and the passive device 142 may be disposed using a tape 210.

[0047] Reference Figure 5B, the first insulating layer 112 may be laminated using a lamination process such as PPG or ABF, so that the first insulating layer 112 may cover the substrate 111, the magnetic layer 150, the voltage regulator 141, and the passive device 142, and may fill the first through-hole H1, the second through-hole H2, and the third through-hole H3, and the first through-hole h1 and the third through-hole h3. Thereafter, if necessary, the laminate may be cut into unit sizes through a trimming process.

[0048] Reference Figure 5C After that, the second through hole h2 and the fourth through hole h4 may be formed in the first through hole h1 and the third through hole h3, respectively, by mechanical drilling. In addition, the first via hole 133V and the second via hole 134V for forming the first via layer 133 and the second via layer 134, respectively, may be formed in the first insulating layer 112 by laser processing.

[0049] Reference Figure 5D , through the plating process and the plugging process, the first via hole pattern M1 and the second via hole pattern M2, the first filler R1 and the second filler R2, the first wiring layer 121 and the second wiring layer 122 (including the first wiring pattern B1 and the second wiring pattern B2, respectively), and the first via hole layer 133 and the second via hole layer 134 can be formed. Thus, the inductor 131 and the through via hole 132 can be formed. More specifically, for example, the inductor 131 and the through via hole 132 can be formed in the following manner: a plating layer is formed on the upper and lower surfaces of the first insulating layer 112 and the wall surfaces of the second through hole h2 and the fourth through hole h4 through the plating process, thereafter, the space between the plating layer (i.e., the metal layer) in the second through hole h2 and the fourth through hole h4 is filled with a plugging material through a plugging process, the plating layer and the plugging material on the upper and lower surfaces of the first insulating layer 112 are removed through a planarization process, and then, a plating layer is formed again on the upper and lower surfaces of the first insulating layer 112 through the plating process. In this process, the first wiring layer 121 and the second wiring layer 122 and the first via layer 133 and the second via layer 134 may also be formed. In the plating process, the plating layer is patterned using a dry film exposure and development process according to the design. In addition, through the planarization process, the upper and lower surfaces of the first insulating layer 112 can form flat surfaces, respectively, and an approximate interlayer boundary can be formed between the plating layer and the first insulating layer 112.

[0050] Reference Figure 5E, through the deposition process, the required number of second insulating layers 113 and third insulating layers 114, third wiring layers 123 and fourth wiring layers 124, and third via layers 135 and fourth via layers 136 may be formed, and the first resist layer 115 and the second resist layer 116 may be formed. In addition, the first opening 115h and the second opening 116h may be formed in the first resist layer 115 and the second resist layer 116, respectively. The second insulating layer 113 and the third insulating layer 114 may be formed using the above-mentioned lamination process, the third wiring layer 123 and the fourth wiring layer 124, and the third via layer 135 and the fourth via layer 136 may be formed using the above-mentioned plating process, and the first resist layer 115 and the second resist layer 116 may be formed by a lamination process or a liquid material coating process.

[0051] The printed circuit board 100A according to the above-described example may be manufactured through a series of processes, and the rest of the description may be substantially the same as the above-described description.

[0052] Figure 6 It is shown Figure 3 sectional view of a modified example of the printed circuit board in FIG.

[0053] Figure 7 is along Figure 6 A cross-sectional view taken along line BB' in FIG.

[0054] Reference Figure 6 and Figure 7 In the printed circuit board 100B according to the modified example, the third through portion H3 may not be provided, and the passive device 142 may be provided in the second through portion H2 together with the voltage regulator 141, as compared with the printed circuit board 100A according to the aforementioned example. In this way, if necessary, components can be embedded with a minimum number of through holes. Other descriptions may be substantially the same as those of the printed circuit board 100A according to the aforementioned example. Compared with the process of manufacturing the printed circuit board 100A according to the aforementioned example, the printed circuit board 100B according to the modified example may be manufactured by forming the second through portion H2 in a larger size without forming the third through portion H3, and a detailed description thereof may not be provided.

[0055] Figure 8 is a cross-sectional view showing another example of a printed circuit board.

[0056] Fig. 9 is along Figure 8 A cross-sectional view taken along line CC'.

[0057] Reference Figure 8 and Fig. 9In a printed circuit board 100C according to another example, the magnetic layer 150 may be in contact with the wall surface of the first through-portion H1, compared with the printed circuit board 100A according to the aforementioned example. That is, the magnetic layer 150 may be in contact with the substrate 111. Therefore, the first insulating layer 112 may not fill the first through-portion H1. For example, the first through-portion H1 may be filled with a paste or composition type material instead of a film type or sheet type material, and may be cured, so that the magnetic layer 150 may be formed. Thus, the magnetic layer 150 may fill the first through-portion H1. Other descriptions may be substantially the same as those of the printed circuit board 100A according to the aforementioned example, and therefore, repeated descriptions may not be provided.

[0058] FIG. 10A to FIG. 10E It shows the manufacturing Figure 8 A cross-sectional view of the process of making a printed circuit board.

[0059] Reference Fig. 10A , a first through portion H1, a second through portion H2, a third through portion H3, and a third through hole h3 may be formed on the substrate 111. The first through portion H1, the second through portion H2, the third through portion H3, and the third through hole h3 may be formed by various methods such as laser drilling, mechanical drilling, chemical etching, and sandblasting processes according to the material of the substrate 111. In addition, the first through portion H1 may be filled with a magnetic paste or a magnetic composition and may be cured, so that a magnetic layer 150 disposed in the first through portion H1 may be formed. Thereafter, a first through hole h1 may be formed on the magnetic layer 150 using mechanical drilling. In addition, a voltage regulator 141 and a passive device 142 may be disposed in the second through portion H2 and the third through portion H3, respectively. The tape 210 may be used to form the magnetic layer 150 and to dispose the voltage regulator 141 and the passive device 142.

[0060] Reference Fig. 10B , the substrate 111, the magnetic layer 150, the voltage regulator 141, and the passive device 142 may be covered by laminating the first insulating layer 112 using a lamination process such as PPG or ABF, and the second and third through-holes H2 and H3 and the first and third through-holes h1 and h3 may be filled with the first insulating layer 112. Thereafter, if necessary, the laminate may be cut into unit sizes by a trimming process.

[0061] Reference Fig. 10C After that, the second through hole h2 and the fourth through hole h4 may be formed in the first through hole h1 and the third through hole h3, respectively, by mechanical drilling. In addition, the first via hole 133V and the second via hole 134V for forming the first via layer 133 and the second via layer 134, respectively, may be formed in the first insulating layer 112 by laser processing.

[0062] Reference Fig. 10D, through the plating process and the plugging process, the first via hole pattern M1 and the second via hole pattern M2, the first filler R1 and the second filler R2, the first wiring layer 121 and the second wiring layer 122 (including the first wiring pattern B1 and the second wiring pattern B2, respectively), and the first via hole layer 133 and the second via hole layer 134 can be formed. Thus, the inductor 131 and the through via hole 132 can be formed. More specifically, for example, the inductor 131 and the through via hole 132 can be formed in the following manner: a plating layer is formed on the upper and lower surfaces of the first insulating layer 112 and the wall surfaces of the second through hole h2 and the fourth through hole h4 through the plating process, thereafter, the space between the plating layer (i.e., the metal layer) in the second through hole h2 and the fourth through hole h4 is filled with a plugging material through a plugging process, the plating layer and the plugging material on the upper and lower surfaces of the first insulating layer 112 are removed through a planarization process, and then a plating layer is formed again on the upper and lower surfaces of the first insulating layer 112 through a plating process. In this process, the first wiring layer 121 and the second wiring layer 122 and the first via layer 133 and the second via layer 134 may also be formed. In the plating process, a plating layer patterned according to the design may be formed using a dry film exposure and development process. In addition, through the planarization process, the upper and lower surfaces of the first insulating layer 112 may form flat surfaces, respectively, and an approximate layer boundary may be formed between the plating layer and the first insulating layer 112.

[0063] Reference Fig. 10E , through the deposition process, the required number of second insulating layers 113 and third insulating layers 114, third wiring layers 123 and fourth wiring layers 124, and third via layers 135 and fourth via layers 136 may be formed, and the first resist layer 115 and the second resist layer 116 may be formed. In addition, the first opening 115h and the second opening 116h may be formed in the first resist layer 115 and the second resist layer 116, respectively. The second insulating layer 113 and the third insulating layer 114 may be formed using the above-mentioned lamination process, the third wiring layer 123 and the fourth wiring layer 124, and the third via layer 135 and the fourth via layer 136 may be formed using the above-mentioned plating process, and the first resist layer 115 and the second resist layer 116 may be formed by a lamination process or a liquid material coating process.

[0064] The printed circuit board 100C according to the above-described another example may be manufactured through a series of processes, and other descriptions may be substantially the same as the above-described descriptions.

[0065] Fig.11 It is shown Figure 8 sectional view of a modified example of the printed circuit board in FIG.

[0066] Fig.12 is along Fig.11 A cross-sectional view taken along line D-D' in FIG.

[0067] Reference Fig.11 and Fig.12 In the printed circuit board 100D according to the modified example, compared with the printed circuit board 100C according to the aforementioned another example, the third through portion H3 may not be provided, and the passive device 142 may be provided in the second through portion H2 together with the voltage regulator 141. In this way, if necessary, components can be embedded with a minimum number of through holes. Other descriptions may be substantially the same as the descriptions of the printed circuit board 100A according to the aforementioned example and the printed circuit board 100C according to the another example. Compared with the process of manufacturing the printed circuit board 100C according to the aforementioned another example, the printed circuit board 100D according to the modified example may be manufactured by forming the second through portion H2 in a larger size without forming the third through portion H3, and a detailed description thereof may not be provided.

[0068] Fig.13 is a cross-sectional view showing an example of a coil portion.

[0069] Reference Fig.13 , the inductor 131 included in the above-mentioned printed circuit boards 100A, 100B, 100C and 100D may include one or more coil parts C, and in the coil part C, a plurality of first wiring patterns B1 and a plurality of second wiring patterns B2 formed on the body 180 may be alternately connected to each other with a plurality of first via patterns M1 formed in the body 180. For example, in a cross section, the coil part C may have a coil structure formed by connecting and vertically alternating a required number of second wiring patterns B2, first via patterns M1, first wiring patterns B1, first via patterns M1, second wiring patterns B2, first via patterns M1, first wiring patterns B1 and first via patterns M1. The body 180 may include the above-mentioned magnetic layer 150 and the first insulating layer 112. In addition, the first filler R1 may be filled in each of the through holes in which the first via patterns M1 are formed. As described above, the coil part C may have a structure in which the number of coils around the magnetic layer 150 may be increased, for example, a daisy chain structure that can increase inductance. The other descriptions may be substantially the same as those of the aforementioned printed circuit boards 100A, 100B, 100C, and 100D, and thus, a repeated description may not be provided.

[0070] Fig.14 are cross-sectional views showing various examples of the coil portion.

[0071] Reference Fig.14, the coil portion C described above may have various shapes on a plane. For example, as shown in A, a plurality of coils C1 and C2 arranged linearly in parallel may be included. Optionally, as shown in B, a coil C3 may be included that is arranged linearly and then bent on the right and arranged linearly again. Optionally, as shown in C, a coil C4 may be included that is arranged to be repeatedly bent upward and downward. For example, coil C4 may be repeatedly arranged in a manner of extending linearly, bending upward, extending linearly, and bending downward. Optionally, as shown in D, a coil C5 may be repeatedly arranged in a manner of tilting in one direction and then bending downward may be included. Optionally, as shown in E, a coil C6 may be repeatedly arranged to tilt in one direction, bend on the right, and then be repeatedly arranged to tilt in the opposite direction, that is, a coil C6 may be repeatedly arranged in an X shape and connected to each other on the right. Optionally, as shown in F, a coil C7 may be repeatedly arranged in an X shape. As described above, the coil part C including various types of coils C1, C2, C3, C4, C5, C6, and C7 may be applied to the above-mentioned printed circuit boards 100A, 100B, 100C, and 100D, but example embodiments thereof are not limited thereto. Other descriptions may be substantially the same as the descriptions of the above-mentioned printed circuit boards 100A, 100B, 100C, and 100D and the coil part C, and therefore, a repeated description may not be provided.

[0072] According to the aforementioned example embodiments, a printed circuit board can be provided which can achieve size reduction and can increase integration.

[0073] Furthermore, a printed circuit board capable of improving power efficiency can be provided.

[0074] Furthermore, a printed circuit board capable of improving the noise reduction effect can be provided.

[0075] In the present disclosure, the term "covering" may include a configuration in which a component is completely covered and a configuration in which a portion of a component is covered, or may include a configuration in which a component is directly covered or indirectly covered. In addition, the term "filling" may include a configuration in which a component is completely filled, and may also include a configuration in which a portion of a component is filled, and a configuration in which a component is almost filled. For example, there may be a gap. In addition, the term "surrounding" may include a configuration in which a component is completely surrounded and may also include a configuration in which a component is partially surrounded. In addition, the term "exposing" may include a configuration in which a component is completely exposed or a configuration in which a portion of a component is exposed, and "exposing" may refer to exposure from a component. For example, a configuration in which an opening may expose a pad may include exposing the pad from a resist layer, and a surface treatment layer may be further provided on the exposed pad.

[0076] In example embodiments, the configuration in which a component is disposed in a through-portion or a through-hole may include a configuration in which the component is completely disposed in the through-portion or the through-hole in cross section, and may also include a configuration in which the component partially protrudes to the upper side or the lower side in cross section. For example, in the case in which a component is disposed in a through-portion or a through-hole in a plane, the configuration may be understood in a broader sense.

[0077] In the present disclosure, example embodiments may include process errors, positional deviations, and measurement errors that occur in the process. For example, a configuration in which components are substantially perpendicular to each other may include examples in which components are completely perpendicular to each other, and may also include examples in which components are almost perpendicular to each other. In addition, a configuration in which components are substantially coplanar with each other may include examples in which components are completely on the same plane, and may also include examples in which components are almost on the same plane.

[0078] The concept of the same insulating material may mean completely the same material, and may also mean that the material may include the same type of insulating material. Therefore, the composition of the insulating material may be substantially the same, but the specific composition ratio of the insulating material may be slightly different.

[0079] In the present disclosure, a cross section refers to a cross-sectional shape when an object is cut vertically, or a cross-sectional shape when an object is viewed from the side. In addition, a configuration in which a component is on a plane may refer to a plane shape when an object is cut horizontally, or a plane shape when an object is viewed from above or below.

[0080] In the present disclosure, the terms "lower side", "lower part" and "lower surface" may be used to refer to a downward direction based on a cross section of the drawings, and "upper side", "upper part" and "upper surface" may be used to refer to a direction opposite to the above directions. However, the direction is defined for convenience of explanation, and the scope of the patent claims is not particularly limited by the description of the direction, and the terms "upper side" and "lower side" may be relative terms.

[0081] In example embodiments, the term "connection" may refer not only to "direct connection" but also to "indirect connection" through an adhesive layer or the like. Furthermore, the term "electrical connection" may include both a case where an element is "physically connected" and a case where an element is "not physically connected". Furthermore, the terms "first", "second", etc. may be used to distinguish one element from another, and may not limit the order and / or importance associated with the elements, etc. In some cases, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of example embodiments.

[0082] In the example embodiments, the term "example embodiment" may not refer to the same example embodiment, and may be provided to describe and emphasize different unique features of each example embodiment. The above-mentioned suggested example embodiments may be implemented without excluding the possibility of combining with features of other example embodiments. For example, unless otherwise indicated, even if a feature described in an example embodiment is not described in other example embodiments, the description may be understood to be related to other example embodiments.

[0083] Unless it has a clearly different meaning in the context, an expression used in the singular includes the expression in the plural.

[0084] While example embodiments have been shown and described above, it will be readily apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A printed circuit board, comprising: substrate; The first through portion and the second through portion penetrate the area between the upper surface and the lower surface of the substrate; A magnetic layer, disposed in the first through-portion; a voltage regulator, disposed in the second through-portion; a first through hole penetrating a region between an upper surface and a lower surface of the magnetic layer; a first insulating layer disposed on the substrate, covering the magnetic layer and the voltage regulator, and filling at least a portion of each of the second through-portion and the first through-hole; a second through hole penetrating through a region between an upper surface and a lower surface of the first insulating layer in the first through hole; A first wiring pattern is arranged above the magnetic layer; a second wiring pattern, disposed below the magnetic layer; as well as A first via pattern is provided in the second through hole and connects the first wiring pattern and the second wiring pattern to each other.

2. The printed circuit board according to claim 1, in, The first via pattern is disposed on a wall surface of the second through hole, and The printed circuit board further includes a first filler filling a space between the first via patterns in the second through hole.

3. The printed circuit board according to claim 1, further comprising: A first wiring layer is arranged on the upper surface of the first insulating layer; as well as a second wiring layer disposed on a lower surface of the first insulating layer, wherein the first insulating layer is disposed between the first wiring pattern and the upper surface of the magnetic layer and between the second wiring pattern and the lower surface of the magnetic layer, and The first wiring layer and the second wiring layer include the first wiring pattern and the second wiring pattern respectively.

4. The printed circuit board according to claim 3, further comprising: a third through hole penetrating a region between the upper surface and the lower surface of the substrate and at least partially filled with the first insulating layer; a fourth through hole penetrating a region between an upper surface and a lower surface of the first insulating layer in the third through hole; as well as A second via pattern is disposed in the fourth through hole and connects the first wiring layer and the second wiring layer to each other.

5. The printed circuit board according to claim 4, in, The second via pattern is disposed on a wall surface of the fourth through hole, and The printed circuit board further includes a second filler filling the space between the second via patterns in the fourth through hole.

6. The printed circuit board according to claim 3, further comprising: a first via layer including a first connection via that penetrates an upper side of the first insulating layer and connects the first wiring layer and the voltage regulator to each other, The voltage regulator and the first via pattern are connected to each other through a path passing through the first connection via and the first wiring layer.

7. The printed circuit board according to claim 6, further comprising: a second via layer including a second connection via penetrating a lower side of the first insulating layer and connecting the second wiring layer to the voltage regulator; wherein the second connecting via is connected to the lower surface of the voltage regulator, and Wherein, the first connecting via and the second connecting via taper in opposite directions.

8. The printed circuit board according to claim 3, further comprising: a second insulating layer, disposed on an upper surface of the first insulating layer; a third insulating layer, disposed on a lower surface of the first insulating layer; a third wiring layer, disposed on an upper surface of the second insulating layer; A fourth wiring layer, disposed on the lower surface of the third insulating layer; a third via layer including a third connection via that penetrates the second insulating layer and connects the first wiring layer and the third wiring layer to each other; as well as a fourth via layer including a fourth connection via that penetrates the third insulating layer and connects the second wiring layer and the fourth wiring layer to each other, Wherein, the third connecting via and the fourth connecting via taper in opposite directions.

9. The printed circuit board according to claim 8, further comprising: a first resist layer disposed on an upper surface of the second insulating layer and having a first opening exposing the third wiring layer; as well as A second resist layer is provided on the lower surface of the third insulating layer and has a second opening exposing the fourth wiring layer.

10. The printed circuit board according to claim 1, further comprising: a passive device, arranged in the second through-hole, Wherein, the first insulating layer covers the passive device.

11. The printed circuit board according to claim 1, further comprising: A third through portion penetrates a region between the upper surface and the lower surface of the substrate; as well as A passive device is arranged in the third through-hole, The first insulating layer covers the passive component and fills the third through-hole.

12. The printed circuit board according to claim 1, in, The magnetic layer is spaced apart from a wall surface of the first through portion, and The first insulating layer fills a space between a wall surface of the first through-portion and the magnetic layer.

13. The printed circuit board according to claim 1, wherein: The magnetic layer is in contact with a wall surface of the first through-portion.

14. The printed circuit board according to claim 1, wherein: The substrate includes an organic core layer, a glass core layer, a metal core layer, a silicon core layer or a ceramic core layer.

15. The printed circuit board according to claim 1, wherein The first and second wiring patterns and the first via pattern are connected to each other to surround at least a portion of the magnetic layer, thereby forming an inductor provided in the substrate.

16. A printed circuit board, comprising: A substrate having a through portion; a magnetic layer, spaced apart from the substrate in the through-portion and having a plurality of through-holes; an insulating layer covering the substrate and the magnetic layer, at least partially filling a space between a wall surface of the through-portion and a side surface of the magnetic layer, and at least partially filling each of the plurality of through holes; A first wiring pattern is arranged above the insulating layer; A second wiring pattern is arranged below the insulating layer; as well as A plurality of via patterns penetrate the insulating layer in the plurality of through holes and connect the first wiring pattern and the second wiring pattern to each other.

17. The printed circuit board according to claim 16, in, The first wiring pattern includes a plurality of first wiring patterns, wherein the second wiring pattern includes a plurality of second wiring patterns, and The plurality of first wiring patterns and the plurality of second wiring patterns are alternately connected with the plurality of via patterns to form a coil portion.

18. The printed circuit board of claim 16, further comprising a second through-portion in which an integrated circuit die is disposed.

19. The printed circuit board according to claim 18, wherein At least a portion of the second through portion is filled with the insulating layer.

20. A printed circuit board, comprising: A substrate having a first through portion and a second through portion spaced apart from each other; A magnetic layer, disposed in the first through-portion; An inductor is disposed in the magnetic layer, and the inductor comprises: A first wiring pattern is arranged above the magnetic layer, A second wiring pattern is arranged below the magnetic layer, a via pattern penetrating the magnetic layer and connecting the first wiring pattern and the second wiring pattern; an integrated circuit die, disposed in the second through-portion; and An insulating layer is disposed on the substrate and at least partially fills the first through-portion and the second through-portion.

21. The printed circuit board according to claim 20, wherein The integrated circuit die includes a voltage regulator.

22. The printed circuit board according to claim 20, further comprising: a third penetration portion; and A passive device is arranged in the third through-hole, The insulating layer covers the passive component and fills the third through-hole.

23. The printed circuit board according to claim 20, in, The magnetic layer is spaced apart from a wall surface of the first through portion, and The insulating layer fills a space between a wall surface of the first through-portion and the magnetic layer.

24. The printed circuit board according to claim 20, wherein: The magnetic layer is in contact with a wall surface of the first through-portion.

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