Semiconductor device including transistor and method for manufacturing the same

Abstract

The present disclosure relates to a semiconductor device including a transistor and a manufacturing method thereof. A semiconductor device includes: a plurality of semiconductor pillars having a first side and a second side facing each other in a first direction and arranged in a second direction intersecting the first direction; a plurality of insulating pillars having a first side and a second side facing each other in the first direction and arranged alternately with the plurality of semiconductor pillars in the second direction; a back gate line formed on a first side of the semiconductor pillar and a first side of the insulating pillar and extending in a second direction; and a front gate line formed on a second side of the semiconductor pillar and a second side of the insulating pillar and extending in the second direction, wherein the semiconductor pillars respectively include a protruding portion protruding beyond the insulating pillar toward the front gate line in the first direction, and a side of the front gate line surrounding the protruding portion.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0133104, filed on October 6, 2023, which is hereby incorporated by reference in its entirety. Technical Field

[0003] Various embodiments of the present disclosure generally relate to a semiconductor device, and more particularly, to a semiconductor device including a transistor and a method of manufacturing the semiconductor device. Background Art

[0004] The development of the electronics industry requires that electronic products become increasingly smaller, more highly integrated, and have higher performance, while also requiring that the operating speed of electronic products be increased.

[0005] In order to meet these demands, it is necessary to develop a technology that can maintain and / or improve the characteristics of unit elements (eg, transistors) constituting electronic products while reducing the size of the unit elements. Summary of the invention

[0006] Embodiments of the present disclosure relate to a semiconductor device including a transistor capable of increasing integration and improving operation characteristics. Embodiments of the present disclosure also relate to a method for manufacturing the semiconductor device.

[0007] According to an embodiment of the present disclosure, a semiconductor device includes: a plurality of semiconductor pillars having a first side and a second side facing each other in a first direction, and arranged in a second direction intersecting the first direction; a plurality of insulating pillars having a first side and a second side facing each other in the first direction, and arranged alternately with the semiconductor pillars in the second direction; a back gate line formed on a first side of the semiconductor pillar and a first side of the insulating pillar, and extending along the second direction; and a front gate line formed on a second side of the semiconductor pillar and a second side of the insulating pillar, and extending along the second direction, wherein the semiconductor pillars respectively include a protruding portion protruding beyond the insulating pillar toward the front gate line in the first direction, and a side of the front gate line surrounding the protruding portion.

[0008] According to another embodiment of the present disclosure, a semiconductor device includes: a back gate line having two sides facing each other in a first direction and extending in a second direction intersecting the first direction; two line patterns, respectively formed on both sides of the back gate line and respectively having a first side facing the back gate line, each of the two line patterns including a plurality of semiconductor pillars and a plurality of insulating pillars alternately arranged in a second direction; and two front gate lines, respectively formed on two second sides of the two line patterns facing the first side in the first direction.

[0009] According to another embodiment of the present disclosure, a method for manufacturing a semiconductor device includes: forming an initial line pattern, the initial line pattern including a plurality of initial semiconductor pillars and a plurality of initial insulating pillars arranged in a second direction intersecting a first direction; forming a back gate line between the initial line pattern and another initial line pattern adjacent to the initial line pattern; forming a line pattern including a plurality of semiconductor pillars and a plurality of insulating pillars arranged in a second direction by dividing the initial line pattern into two parts in the first direction; and forming front gate lines on opposite sides of the line pattern, respectively. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figures 1A to 10 A semiconductor device and a method for manufacturing the same according to an embodiment of the present disclosure are shown.

[0011] Figures 11 to 14 is a cross-sectional view illustrating a semiconductor device and a method of manufacturing the same according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0012] Various embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. However, the embodiments of the present disclosure can be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete, and the scope of the present disclosure will be fully conveyed to those skilled in the art. In the present disclosure, the same reference numerals refer to the same parts in multiple figures and embodiments of the present disclosure.

[0013] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0014] The drawings are not necessarily drawn to scale, and in some cases, the scale may be exaggerated to clearly illustrate features of the embodiments. When a first layer is referred to as being "on" a second layer or "on" a substrate, it refers not only to the case where the first layer is directly formed on the second layer or the substrate, but also to the case where a third layer exists between the first layer and the second layer or between the first layer and the substrate.

[0015] Figures 1A to 10 A semiconductor device and a method for manufacturing the same according to an embodiment of the present disclosure are shown. Figure 1A , Figure 2A , Figure 3A , Figure 4A , Figure 5A , Fig. 6A , Fig. 7A and Fig. 8A are shown separately Figure 1B , Figure 2B , Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B and Figure 8BPlan view at the level of line H-H'. Figure 1B is along Figure 1A A cross-sectional view taken along line AA' is shown. Figure 2B , Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B as well as Figure 8B are respectively along Figure 2A , Figure 3A , Figure 4A , Figure 5A , Fig. 6A , Fig. 7A as well as Fig. 8A A cross-sectional view taken along line BB' shown in FIG. Fig. 9 It is shown Fig. 8A and Figure 8B Cross-sectional view of the subsequent process. Fig.10 It is shown Fig. 9 Cross-sectional view of the subsequent process.

[0016] First, a method for manufacturing a semiconductor device according to the embodiment of the present disclosure will be described.

[0017] Reference Figure 1A and Figure 1B , a stacked structure including a conductive line 110 and a semiconductor layer 120 is formed on a substrate 100. The dielectric layer 130 may fill the space between the plurality of stacked structures spaced apart from each other along the first direction. Therefore, in other words, the dielectric layer 130 may fill the space between adjacent stacked structures.

[0018] The substrate 100 may be a semiconductor substrate. For example, the substrate may be made of or include a semiconductor material, such as silicon. In addition, the substrate 100 may include a lower structure (not shown), such as a driving circuit electrically connected to the wire 110 to drive the wire 110.

[0019] The wire 110 may extend in a first direction, and a plurality of wires 110 may be arranged spaced apart from each other in a second direction. The wire 110 may include a variety of conductive materials, for example, metals such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), tantalum (Ta), titanium (Ti), ruthenium (Ru), and molybdenum (Mo), compounds thereof, or alloys thereof. The wire 110 may correspond to a bit line coupled to a first end (e.g., a drain) of a transistor.

[0020] The semiconductor layer 120 may be disposed on the conductive line 110 and overlap the conductive line 110 in a plan view to have a line shape extending in the first direction. A plurality of semiconductor layers 120 may overlap the plurality of conductive lines 110, respectively. For example, the semiconductor layer 120 may be patterned together with the conductive line 110 so that both sides of the semiconductor layer 120 are aligned with both sides of the conductive line 110 in the second direction. The semiconductor layer 120 may include a plurality of semiconductor materials, such as silicon, silicon germanium, etc. The semiconductor layer 120 may include a plurality of layers. Specifically, as Figure 1B As shown in the embodiment of the present invention, the semiconductor layer 120 may include a first source / drain region 122 disposed at a lower portion of the semiconductor layer 120, a second source / drain region 126 disposed at an upper portion (also referred to as a top portion) of the semiconductor layer 120, and a channel region 124 between the first source / drain region 122 and the second source / drain region 126. For example, the source / drain region may refer to a source region or a drain region, and may be formed by doping a semiconductor material with impurities. When the conductive line 110 corresponds to a bit line, the first source / drain region 122 may correspond to a drain region, and the second source / drain region 126 may correspond to a source region.

[0021] The dielectric layer 130 may include a variety of dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0022] In an embodiment, the wire 110, the semiconductor layer 120 and the dielectric layer 130 can be formed in the following manner. First, a conductive material and a semiconductor material can be formed on the substrate 100. For example, the conductive material and the semiconductor material can be formed by a deposition method such as physical vapor deposition (PVD) or chemical vapor deposition (CVD) or an epitaxial growth method. When the semiconductor material is deposited or grown, a source / drain region can be formed in the semiconductor material by in-situ doping with impurities. Subsequently, a stacked structure of the wire 110 and the semiconductor layer 120 having a linear shape can be formed by selectively etching the conductive material and the semiconductor material. Subsequently, the dielectric layer 130 can be formed by depositing a sufficiently thick dielectric material to fill the empty space between the stacked structures and performing a planarization process (e.g., chemical mechanical polishing (CMP) or an etch-back process) until the top surface of the semiconductor layer 120 is exposed.

[0023] Reference Figure 2A and Figure 2B , preliminary semiconductor pillars 120A and preliminary insulating pillars 130A may be formed by forming linear hard mask patterns 140 extending in the second direction over the semiconductor layer 120 and the dielectric layer 130 and by etching the semiconductor layer 120 and the dielectric layer 130 using the hard mask patterns 140 as etch barriers.

[0024] The hard mask pattern 140 may include various dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, etc., or may include amorphous carbon which may be easily removed.

[0025] The initial semiconductor column 120A may overlap with the wire 110 and may be coupled to the wire 110. The initial semiconductor column 120A may be arranged in a first direction and a second direction. In addition, the initial semiconductor column 120A and the initial insulating column 130A overlapping with a hard mask pattern 140 under the hard mask pattern 140 may be alternately arranged in the second direction to form initial line patterns 120A and 130A extending in the second direction. A plurality of initial line patterns 120A and 130A may be arranged spaced apart from each other in the first direction. The etched first source / drain region, the channel region, and the second source / drain region are represented by reference numerals 122A, 124A, and 126A, respectively. The space between the stacked structures formed by the initial line patterns 120A and 130A and the hard mask pattern 140 will be referred to as the first space S1 hereinafter.

[0026] During the etching process, Figure 2A The wire 110 may be maintained as shown by the dotted line in the plan view.

[0027] Reference Figure 3A and Figure 3B , first insulating patterns 152 and 154 filling the lower portion of the first space S1, a back gate line 160 filling the middle portion of the first space S1 over the first insulating patterns 152 and 154, and second insulating patterns 172 and 174 filling the upper portion of the first space S1 over the back gate line 160 can be formed.

[0028] The back gate line 160 can control the threshold voltage of the transistor by being electrically connected to the body of the transistor. According to an embodiment of the present disclosure, the back gate line 160 can extend in the second direction while directly contacting both sides of the initial semiconductor column 120A and the initial insulating column 130A in the first direction. In addition, according to an embodiment of the present disclosure, the bottom surface of the back gate line 160 can be set higher than the top surface of the first source / drain region 122A, and the top surface of the back gate line 160 can be set lower than the bottom surface of the second source / drain region 126A. When the distance between the bottom surface of the back gate line 160 and the top surface of the first source / drain region 122A and the distance between the top surface of the back gate line 160 and the bottom surface of the second source / drain region 126A increase, leakage current, such as gate-induced drain leakage (GIDL), can be reduced. For example, the back gate line 160 may include polysilicon. However, the embodiments of the present disclosure are not limited thereto, and the back gate line 160 may include a variety of semiconductor materials or conductive materials.

[0029] The first insulating patterns 152 and 154 may be interposed between the back gate line 160 and the conductive line 110 to insulate them from each other. The first insulating patterns 152 and 154 may have a line shape extending in the second direction. According to an embodiment of the present disclosure, the first insulating patterns 152 and 154 may include a first pad pattern 152 and a first buried pattern 154. The first pad pattern 152 may be conformally formed on the contour of the bottom surface and the side of the lower portion of the first space S1, and the first buried pattern 154 may be formed to fill the remaining portion of the lower portion of the first space S1 in which the first pad pattern 152 is formed. The first pad pattern 152 may include silicon oxide, and the first buried pattern 154 may include silicon nitride. However, the embodiments of the present disclosure are not limited thereto, and each of the first pad pattern 152 and the first buried pattern 154 may be formed of different dielectric materials. In addition, the first insulating patterns 152 and 154 may not be divided into the first pad pattern 152 and the first buried pattern 154, but may be formed as a single block.

[0030] The second insulating patterns 172 and 174 may electrically insulate the back gate line 160 from constituent elements (not shown) above the back gate line 160 by covering the back gate line 160. In addition, the second insulating patterns 172 and 174 may be used to support the spacer during a subsequent process of forming the spacer (see Figure 5A and Figure 5B ” in the figure mark “180”). The second insulating patterns 172 and 174 may have a line shape extending in the second direction. According to an embodiment of the present disclosure, the second insulating patterns 172 and 174 may include a second pad pattern 172 and a second buried pattern 174. The second pad pattern 172 may be conformally formed on the contour of the side of the bottom surface and the upper portion of the first space S1, and the second buried pattern 174 may be formed to fill the remaining portion of the upper portion of the first space S1 in which the second pad pattern 172 is formed. The second pad pattern 172 may include silicon oxide, and the second buried pattern 174 may include silicon nitride. However, the embodiments of the present disclosure are not limited thereto, and each of the second pad pattern 172 and the second buried pattern 174 may be formed of different dielectric materials. In addition, the second insulating patterns 172 and 174 may not be divided into the second pad pattern 172 and the second buried pattern 174, but may be formed as a single block.

[0031] The first insulating patterns 152 and 154, the back gate line 160, and the second insulating patterns 172 and 174 may be formed in the following manner. First, the first insulating patterns 152 and 154 may be formed by the following steps: Figure 2A and Figure 2BConformally depositing a first dielectric material for forming a first pad pattern 152 on a contour of a process result of the present invention; depositing a second dielectric material for forming a first buried pattern 154 on the deposited first dielectric material; recessing the second dielectric material by a method such as an etch-back process so that the second dielectric material has a desired thickness (i.e., the bottom surface of the back gate line 160 has a desired height); and removing the first dielectric material exposed by the recessed second dielectric material. When the first insulating patterns 152 and 154 form a single block, the first insulating patterns 152 and 154 can be formed by the following steps: depositing a covering Figure 2A and Figure 2B The dielectric material for forming the first insulating patterns 152 and 154 of the process result of the back gate line 160 is deposited; and the deposited dielectric material is recessed to have a desired thickness. Subsequently, the back gate line 160 can be formed by the following steps: depositing a material for forming the back gate line 160 to cover the process result in which the first insulating patterns 152 and 154 are formed; and recessing the deposited material so that the deposited material has a desired thickness (i.e., the top surface of the back gate line 160 has a desired height). Subsequently, the second insulating patterns 172 and 174 can be formed by the following steps: conformally depositing a first dielectric material for forming a second pad pattern 172 on the contour of the process result of forming the back gate line 160; then depositing a second dielectric material for forming a second buried pattern 174 on top of the deposited first dielectric material; and performing a planarization process to expose the hard mask pattern 140. When the second insulating patterns 172 and 174 form a single block, the second insulating patterns 172 and 174 may be formed by depositing a dielectric material for forming the second insulating patterns 172 and 174 covering a process result in which the back gate line 160 is formed; and performing a planarization process to expose the hard mask pattern 140 .

[0032] refer to Figure 4A and Figure 4B , the hard mask pattern 140 may be removed using, for example, a wet etching process or a dry etching process.

[0033] The space formed by removing the hard mask pattern 140 will be referred to as an opening OP hereinafter. The opening OP may expose the top surfaces of the preliminary line patterns 120A and 130A by having a line shape extending in the second direction and overlapping the preliminary line patterns 120A and 130A. The shape of the opening OP is determined by Figure 4A The dotted lines in the plan view represent .

[0034] When the second pad pattern 172 and the hard mask pattern 140 include the same material (e.g., silicon oxide), a portion of the second pad pattern 172 may also be removed during the process of removing the hard mask pattern 140. The second pad pattern 172 whose portion is removed is indicated by reference numeral "172A". In this case, the top surface of the second pad pattern 172A and the bottom surface of the opening OP may be set at substantially the same height. However, the embodiments of the present disclosure are not limited thereto, and the second insulating patterns 172 and 174 may be retained when the hard mask pattern 140 is removed. As a result of the process, a portion of the second buried pattern 174 may protrude above the top surface of the initial semiconductor pillar 120A. When the second insulating patterns 172 and 174 are retained when the hard mask pattern 140 is removed, a portion of the second insulating patterns 172 and 174 may protrude above the top surface of the initial semiconductor pillar 120A.

[0035] Reference Figure 5A and Figure 5B , the spacers 180 may be formed on both sides of the protruding portion of the second buried pattern 174 (or the protruding portions of the second insulating patterns 172 and 174 ).

[0036] The spacer 180 may be formed during a subsequent etching process for forming semiconductor pillars and insulating pillars (see Fig. 6A and 6B ) is used as an etching barrier. The spacer 180 may have a line shape extending in the second direction. In terms of cross section, the spacer 180 may have a width that increases from top to bottom. For example, in the first direction, the width of the bottom surface of the spacer 180 may be less than half the width of the initial semiconductor pillar 120A. Therefore, one initial line pattern 120A and 130A may have a top surface partially covered by two spacers 180 overlapping the initial line patterns 120A and 130A. When the two spacers 180 overlapping the initial line patterns 120A and 130A are respectively referred to as first side spacers 180 and second side spacers 180, the first portion corresponding to less than half of the first side of the initial line patterns 120A and 130A may overlap with the first side spacer 180, and the second portion corresponding to less than half of the second side of the initial line patterns 120A and 130A may overlap with the second side spacer 180. In addition, a portion between the first and second portions of the preliminary line patterns 120A and 130A may not overlap with the spacer 180. One second buried pattern 174 (or second insulating patterns 172 and 174) and two spacers 180 (see FIG. 1 ) located on both sides of the second buried pattern 174. Figure 5AThe dotted line portion in FIG. 1 (a) may cover one back gate line 160 and portions of the two preliminary line patterns 120A and 130A disposed in the first direction on both sides of the back gate line 160. The spacers 180 may include various dielectric materials such as silicon oxide, silicon nitride, and silicon oxynitride, or may include amorphous carbon that can be easily removed.

[0037] The spacer 180 can be formed by Figure 4A and Figure 4B The material is conformally deposited on the process result of , and then a blanket etching process is performed to form. The blanket etching process may be performed to expose the top surface of the initial semiconductor pillar 120A.

[0038] Reference Fig. 6A and Figure 6B The semiconductor pillars 120B and the insulating pillars 130B may be formed by using the spacers 180 as an etching barrier and etching the preliminary semiconductor pillars 120A and the preliminary insulating pillars 130A. The semiconductor pillars 120B and the insulating pillars 130B may be alternately arranged in the second direction to form line patterns 120B and 130B extending in the second direction.

[0039] During the etching process, in the first direction, an initial semiconductor column 120A can be divided into two parts to form two semiconductor columns 120B, and an initial insulating column 130A can be divided into two parts to form two insulating columns 130B. In the first direction, the initial line patterns 120A and 130A can be divided into two parts to form two line patterns 120B and 130B. The space between the two separated line patterns 120B and 130B will be referred to as the second space S2 hereinafter. The etched first source / drain region, the channel region, and the second source / drain region are represented by reference numerals "122B", "124B", and "126B", respectively.

[0040] The etching process can be performed by a dry etching method under the condition that the etching rate of the insulating column 130B is higher than the etching rate of the semiconductor column 120B. As a result, the width W1 of the semiconductor column 120B in the first direction can be greater than the width W2 of the insulating column 130B. In this case, since the semiconductor column 120B protrudes more toward the second space S2 than the insulating column 130B in the first direction, the second side of the semiconductor column 120B facing the second space S2 on both sides in the first direction and the second side of the insulating column 130B facing the second space S2 on both sides in the first direction can be uneven. On the other hand, the first side of the semiconductor column 120B contacting one side of the back gate line 160 on both sides in the first direction and the first side of the insulating column 130B contacting one side of the back gate line 160 on both sides in the first direction can be arranged on a straight line extending along the second direction.

[0041] Reference Fig. 7A and Figure 7B After forming the third insulating patterns 192 and 194 filling the lower portion of the second space S2 , the gate dielectric layer 210 and the front gate layer 220 may be conformally formed on the contour of the process result in which the third insulating patterns 192 and 194 are formed.

[0042] The front gate layer 220 may correspond to the gate terminal of the transistor and / or word line, and may be used to control the transistor on / off. The gate dielectric layer 210 may be between the front gate layer 220 and the semiconductor pillar 120B to electrically insulate them from each other. The gate dielectric layer 210 and the front gate layer 220 may be formed to have a thin thickness that does not completely fill the second space S2 formed with the third insulating patterns 192 and 194. According to an embodiment of the present disclosure, the bottom surface of the front gate layer 220 may be set at the same or similar level as the top surface of the first source / drain region 122B, and may be set to be lower than the bottom surface of the back gate line 160. The front gate layer 220 may include a variety of conductive materials, for example, metals such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), tantalum (Ta), titanium (Ti), ruthenium (Ru), molybdenum (Mo), etc., compounds thereof, or alloys thereof. The gate dielectric layer 210 may include a variety of dielectric materials, such as silicon oxide or a low-k material having a dielectric constant lower than silicon oxide.

[0043] The third insulating patterns 192 and 194 may be interposed between the front gate layer 220 and the conductive line 110 to insulate them from each other. The third insulating patterns 192 and 194 may have a line shape extending in the second direction. According to an embodiment of the present disclosure, the third insulating patterns 192 and 194 may include a third pad pattern 192 and a third buried pattern 194. The third pad pattern 192 may be conformally formed on the contour of the bottom surface and the side of the lower portion of the second space S2, and the third buried pattern 194 may be formed to fill the remaining portion of the lower portion of the second space S2 in which the third pad pattern 192 is formed. The third pad pattern 192 may include silicon oxide, and the third buried pattern 194 may include silicon nitride. However, the embodiments of the present disclosure are not limited thereto, and each of the third pad pattern 192 and the third buried pattern 194 may be formed of different dielectric materials. In addition, the third insulating patterns 192 and 194 may not be divided into the third pad pattern 192 and the third buried pattern 194, but may be formed as a single block.

[0044] Reference Fig. 8A and Figure 8B By etching the front gate layer 220, a front gate line 220A may be formed on the second side of the semiconductor pillar 120B and the insulating pillar 130B to extend in the second direction. In the first direction, the front gate layer 220 may be divided into two parts in the second space S2 to form two front gate lines 220A.

[0045] The front gate line 220A may be formed by a blanket etching process performed on the front gate layer 220. For example, a blanket etching process may be performed to have the front gate line 220A of a desired thickness while exposing at least the gate dielectric layer 210 on the bottom surface of the second space S2 to separate the front gate lines 220A adjacent in the first direction, that is, a blanket etching process may be performed to set the top surface of the front gate line 220A lower than the top surface of the semiconductor pillar 120B. According to an embodiment of the present disclosure, the top surface of the front gate line 220A may be set at the same or similar level as the bottom surface of the second source / drain region 126B, and may be set above the top surface of the back gate line 160. In addition, the bottom surface of the front gate line 220A may be set at the same or similar level as the top surface of the first source / drain region 122B, and may be set lower than the bottom surface of the back gate line 160. Therefore, the thickness of the front gate line 220A may be greater than the thickness of the back gate line 160.

[0046] In addition, since the front gate line 220A is formed on the second side of the semiconductor column 120B and the second side of the insulating column 130B, it is formed unevenly from a plane, so the front gate line 220A can surround the side of the protruding portion of the semiconductor column 120B that protrudes more toward the front gate line 220A than the insulating column 130B. When the semiconductor column 120B has a square column shape and therefore has a third side and a fourth side facing each other in the second direction, while coupling the first side and the second side together with the above-mentioned first side and the second side, the front gate line 220A can face the second side of the semiconductor column 120B, a part of the third side, and a part of the fourth side, while the back gate line 160 faces and contacts the first side of the semiconductor column 120B. In this case, the controllability of the front gate line 220A relative to the channel of the transistor can be improved. Therefore, the operating characteristics of the transistor can be improved.

[0047] Therefore, the transistor can be formed to include: a semiconductor column 120B provided with a first source / drain region 122B, a channel region 124B, and a second source / drain region 126B; a back gate line 160 extending in the second direction while directly contacting a first side of the semiconductor column 120B; and a front gate line 220A extending in the second direction while surrounding one side of the protruding portion of the semiconductor column 120B (i.e., the second side, a portion of the third side, and a portion of the fourth side of the semiconductor column 120B) by inserting a gate dielectric layer 210. When the second source / drain region 126B of the transistor corresponds to the source region, the second source / drain region 126B can be electrically connected to a storage pattern for storing data. This will refer to Figures 9 and 10 The subsequent process shown is described.

[0048] Reference Fig. 9 , in coverage Fig. 8A and Figure 8B After the interlayer dielectric layer 230 is formed as a result of the process, a planarization process may be performed to expose the top surface of the semiconductor pillar 120B. As a result of the process, the semiconductor pillar 120B, the second buried pattern 174, the gate dielectric layer 210, and the interlayer dielectric layer 230 may form a planar top surface.

[0049] Reference Fig.10 , you can Fig. 9 A plurality of storage patterns 260 are formed on the process result, and each storage pattern 260 is electrically connected to a corresponding semiconductor pillar among the plurality of semiconductor pillars 120B, specifically, to a corresponding second source / drain region 126B, through a corresponding contact plug among the plurality of contact plugs 250.

[0050] The contact plugs 250 may include a variety of conductive materials, for example, metals such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), tantalum (Ta), titanium (Ti), ruthenium (Ru), molybdenum (Mo), etc., compounds thereof, or alloys thereof. Each contact plug 250 may correspond to a storage node contact electrically connected to a second terminal (e.g., a source) of the transistor.

[0051] The storage pattern 260 may refer to a component element that can store data in various ways. According to an embodiment of the present disclosure, each of the storage patterns 260 may include a capacitor having a dielectric layer 264 between two electrodes 262 and 266. The capacitor may be formed by the following steps: Fig. 9 Another interlayer dielectric layer (not shown) is formed on the process result of ; a hole exposing the top surface of the semiconductor pillar 120B is formed by selectively etching the interlayer dielectric layer; a first electrode 262 is formed by depositing a conductive material on the contour of the inner wall of the hole; a dielectric layer 264 is formed on the contour of the surface of the first electrode 262; and a second electrode 266 is formed by filling the remaining space of the hole where the first electrode 262 and the dielectric layer 264 are formed with a conductive material. In this case, a cylindrical capacitor can be formed.

[0052] However, the embodiments of the present disclosure are not limited to forming only cylindrical capacitors, and the storage pattern 260 may include capacitors of various shapes. In addition, the storage pattern 260 may include various elements capable of storing data in addition to capacitors. For example, the storage pattern 260 may include a variable resistance element that can store different data by switching between different resistance states.

[0053] The semiconductor device according to the embodiment of the present disclosure may be manufactured by the above-described method for manufacturing a semiconductor device.

[0054] A semiconductor device according to an embodiment of the present disclosure may include: a substrate 100; a conductive line 110 disposed on the substrate 100 and extending in a first direction; a plurality of semiconductor pillars 120B arranged in a second direction and electrically connected to the conductive line 110 on the conductive line 110; a plurality of insulating pillars 130B arranged alternately with the semiconductor pillars 120B in the second direction; a back gate line 160 formed on a first side of the semiconductor pillars 120B and the insulating pillars 130B in the first direction and extending in the second direction; a front gate line 220A formed on a second side of the semiconductor pillars 120B and the insulating pillars 130B in the first direction and extending in the second direction; and a storage pattern 260 electrically connected to the semiconductor pillars 120B through a contact plug 250 on the semiconductor pillars 120B.

[0055] Two line patterns 120B and 130B including a plurality of semiconductor pillars 120B and a plurality of insulating pillars 130B alternately arranged in the second direction may be disposed on both sides of one back gate line 160. For example, the first sides of the two line patterns 120B and 130B may contact both sides of the back gate line 160, respectively. Two front gate lines 220A may be formed on the second sides of the two line patterns 120B and 130B, respectively. Therefore, in the first direction, the line patterns 120B and 130B disposed on the first side of the back gate line 160 and the front gate line 220A, and the line patterns 120B and 130B disposed on the second side of the back gate line 160 and the front gate line 220A, may have a symmetrical structure. When a structure formed by one back gate line 160, line patterns 120B and 130B and front gate line 220A on a first side of the back gate line 160, and line patterns 120B and 130B and front gate line 220A on a second side of the back gate line 160 is referred to as a first structure, a plurality of first structures may be repeatedly arranged in the first direction.

[0056] For example, in the first direction, the semiconductor pillar 120B may have a protruding portion that protrudes further toward the front gate line 220A than the insulating pillar 130B, and the front gate line 220A may surround the side of the protruding portion of the semiconductor pillar 120B.

[0057] Since the constituent elements of the semiconductor device according to the embodiment of the present disclosure have been described in detail in the process of describing the method for manufacturing the semiconductor device, their description will be omitted here.

[0058] According to the semiconductor device and the method for manufacturing the semiconductor device described above, the following effects can be obtained.

[0059] First, since the back gate line 160 is shared between two semiconductor pillars 120B when the back gate line 160 and the front gate line 220A are alternately arranged, and the semiconductor pillar 120B having a width narrower than the limitation of the mask process can be formed when the semiconductor pillar 120B is formed by using the spacer 180, a large number of transistors can be formed in a small area. That is, the integration of the semiconductor device can be improved.

[0060] In addition, since the front gate line 220A surrounds the side of the protruding portion of the semiconductor pillar 120B, the controllability of the front gate line 220A with respect to the channel of the transistor can be improved. As a result, the operating characteristics of the transistor can be improved.

[0061] In addition, the back gate line 160 can directly contact the semiconductor pillar 120B to suppress the floating body effect, and the distance to the first source / drain region 122B and the second source / drain region 126B can be increased due to the reduction in the thickness of the back gate line 160, which can reduce leakage current. In this way, factors that may deteriorate the characteristics of the transistor can be reduced and / or eliminated.

[0062] In addition, the front gate line may have a multilayer structure including different materials to improve the characteristics of the transistor. For example, when the portion of the front gate line close to the source / drain region has a low work function, the electric field may be reduced, thereby reducing leakage current, such as gate-induced drain leakage (GIDL). Figures 11 to 14 A method for implementing a front gate line is described.

[0063] Figures 11 to 14 2 is a cross-sectional view showing a semiconductor device and a method for manufacturing the same according to another embodiment of the present disclosure. The same reference numerals may be given to substantially the same constituent elements also appearing in the above-mentioned embodiments, and their detailed description may be omitted.

[0064] Reference Fig.11 , in execution with Figures 1A to 6B The same process as described in the Figure 6B After the process result of forming the third insulating patterns 192 and 194 , the third insulating patterns 192 and 194 may be formed to fill the lower portion of the second space S2 , and the gate dielectric layer 210 may be conformally formed on the contour of the process result of forming the third insulating patterns 192 and 194 .

[0065] Subsequently, a first front gate layer 322 may be formed on the gate dielectric layer 210 to fill the lower portion of the third space defined by the side surface and the bottom surface of the gate dielectric layer 210. The first front gate layer 322 may be formed by depositing a material for forming the first front gate layer 322 on the gate dielectric layer 210 to a thickness sufficient to fill the third space, and recessing the material to a desired thickness. The first front gate layer 322 may include a material having a first work function, such as polysilicon. The top surface of the first front gate layer 322 may be set at the same or similar height as the bottom surface of the back gate line 160, but the embodiments of the present disclosure are not limited thereto, and the height of the top surface of the first front gate layer 322 may be modified differently.

[0066] Subsequently, a second front gate layer 324 may be conformally formed on the contour of the process result formed with the first front gate layer 322. The second front gate layer 324 may be formed to have a thin thickness that does not completely fill the third space. The second front gate layer 324 may include a material having a second work function greater than the first work function, such as a metal, a metal compound, or an alloy.

[0067] Reference Fig.12 , a first front gate line 322A and a second initial front gate line 324A may be formed on the second side of the semiconductor pillar 120B and the insulating pillar by etching the first front gate layer 322 and the second front gate layer 324 to extend in the second direction. In the first direction, the first front gate layer 322 and the second front gate layer 324 may be divided into two parts in the third space to form two first front gate lines 322A and two second initial front gate lines 324A.

[0068] The second preliminary front gate line 324A may be formed by a blanket etching process performed on the second front gate layer 324. For example, the blanket etching process may be performed so that the top surface of the first front gate layer 322 is exposed, and the top surface of the second preliminary front gate line 324A is disposed at least below the top surface of the spacer 180. The first front gate line 322A may be formed by etching and removing a portion of the first front gate layer 322 exposed by the second preliminary front gate line 324A. As a result, a stacked structure of the first front gate line 322A and the second preliminary front gate line 324A may be formed.

[0069] Reference Fig.13 , an additional insulating pattern 330 may be formed to fill the space between the stacked structure of the first front gate line 322A and the second preliminary front gate line 324A. The additional insulating pattern 330 may include different dielectric materials and may be deposited to cover the Fig.12The additional insulating pattern 330 is formed by recessing the dielectric material of the process result to have a desired thickness. The top surface of the additional insulating pattern 330 may be set lower than the top surface of the second preliminary front gate line 324A and may be set at the same level as the front gate line (see Fig.14 The top surface of the substrate is at the same level or at a higher level than the top surface of the substrate (shown as reference numeral “320”), which will be described in a subsequent process.

[0070] Subsequently, the second preliminary front gate line 324A may be recessed to form a second front gate line 324B having a reduced thickness.

[0071] Reference Fig.14 , a third front gate line 326 may be formed to fill a space formed by the recess of the second preliminary front gate line 324A, ie, a space defined by a side of the gate dielectric layer 210 , a top surface of the second front gate line 324B, and a side of the additional insulating pattern 330 .

[0072] The third front gate line 326 can be connected by Fig.13 The third front gate line 326 may include a material having a first work function, such as polysilicon. The top surface of the third front gate line 326 may be set at the same or similar height as the top surface of the back gate line 160, but the embodiments of the present disclosure are not limited thereto, and the height of the top surface of the third front gate line 326 may be modified differently.

[0073] Through the above-described processes, the front gate line 320 in which the first front gate line 322A, the second front gate line 324B, and the third front gate line 326 are stacked may be formed.

[0074] The first front gate line 322A and the third front gate line 326 may have a smaller work function than the second front gate line 324B. In addition, the first front gate line 322A may be disposed closer to the first source / drain region 122B than the second front gate line 324B, and the third front gate line 326 may be disposed closer to the second source / drain region 126B than the second front gate line 324B. Therefore, as described above, the electric field of the transistor may be reduced and the leakage current caused by the reduced electric field may be reduced.

[0075] Since the subsequent process can be Fig. 9 and Fig.10 The process described in is basically the same, so its detailed description will be omitted.

[0076] The above embodiments can be applied to all semiconductor devices including NMOS transistors, PMOS transistors or CMOS transistors and methods for manufacturing the semiconductor devices. For example, they can also be applied to non-volatile memories (such as flash memory, resistive random access memory (RRAM), phase change random access memory (PRAM), magnetoresistive random access memory (MRAM), etc.), volatile memories (such as dynamic random access memory (DRAM), static random access memory (SRAM), etc.), non-memory (such as logic circuits) and various semiconductor devices (such as CMOS image sensors (CIS).

[0077] According to an embodiment of the present disclosure, a semiconductor device including a transistor capable of increasing integration and improving operation characteristics and a method for manufacturing the semiconductor device may be provided.

[0078] Although the embodiments of the present disclosure have been described with respect to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the present invention as defined in the appended claims. In addition, these embodiments may be combined to form additional embodiments.

Claims

1. A semiconductor device, comprising: a plurality of semiconductor pillars having a first side and a second side facing each other in a first direction and arranged in a second direction intersecting the first direction; a plurality of insulating pillars having a first side and a second side facing each other in the first direction and arranged alternately with the plurality of semiconductor pillars in the second direction; a back gate line formed on the first side of the semiconductor column and the first side of the insulating column and extending along the second direction; as well as a front gate line formed on the second side of the semiconductor column and the second side of the insulating column and extending along the second direction, wherein the semiconductor pillars respectively include protruding portions protruding beyond the insulating pillars in the first direction toward the front gate line, and Wherein, the front gate line surrounds one side of the protruding portion.

2. The semiconductor device according to claim 1, wherein The first side of the semiconductor pillar and the first side of the insulating pillar are disposed on a straight line extending along the second direction.

3. The semiconductor device according to claim 1, wherein The width of the semiconductor column in the first direction is greater than the width of the insulating column.

4. The semiconductor device according to claim 1, wherein: The back gate line directly contacts the semiconductor pillar.

5. The semiconductor device according to claim 1, further comprising: A gate dielectric layer is disposed between the front gate line and the semiconductor pillar.

6. The semiconductor device according to claim 1, wherein The thickness of the back gate line is smaller than the thickness of the front gate line.

7. The semiconductor device according to claim 1, wherein The semiconductor column includes a first source / drain region disposed in a lower portion of the semiconductor column, a second source / drain region disposed in an upper portion of the semiconductor column, and a channel region disposed between the first source / drain region and the second source / drain region, wherein the bottom surface of the back gate line is arranged to be higher than the top surface of the first source / drain region, and A top surface of the back gate line is disposed lower than a bottom surface of the second source / drain region.

8. The semiconductor device according to claim 7, wherein a bottom surface of the front gate line is arranged to be lower than the bottom surface of the back gate line, and A top surface of the front gate line is disposed higher than the top surface of the back gate line.

9. The semiconductor device according to claim 1, wherein: The front gate lines include a first front gate line, a second front gate line located above the first front gate line, and a third front gate line located above the second front gate line, and Wherein, a work function of the first front gate line and a work function of the third front gate line are smaller than a work function of the second front gate line.

10. The semiconductor device according to claim 1, further comprising: a conductive line electrically connected to the semiconductor column below the semiconductor column and extending along the first direction; as well as A storage pattern is electrically connected to the semiconductor pillar over the semiconductor pillar.

11. A semiconductor device comprising: a back gate line having two sides facing each other in a first direction and extending in a second direction crossing the first direction; two line patterns, which are respectively formed on both sides of the back gate line and respectively have first sides facing the back gate line, each of the two line patterns including a plurality of semiconductor pillars and a plurality of insulating pillars alternately arranged in the second direction; as well as Two front gate lines are respectively formed on two second sides of the two line patterns facing the first side in the first direction.

12. The semiconductor device according to claim 11, wherein The back gate line, the two line patterns and the two front gate lines form a first structure, and A plurality of the first structures are repeatedly arranged in the first direction.

13. The semiconductor device according to claim 11, wherein The two line patterns are symmetrical to each other, the back gate line is between the two line patterns, and The two front gate lines are symmetrical to each other, and the back gate line is between the two front gate lines.

14. The semiconductor device according to claim 11, wherein The semiconductor pillar includes a protruding portion protruding beyond the insulating pillar toward the front gate line in the first direction, and Wherein, the front gate line surrounds one side of the protruding portion.

15. The semiconductor device according to claim 11, wherein The first side of the line pattern is disposed on a straight line extending along the second direction, and The second side of the line pattern has an uneven shape.

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