Memory structure and manufacturing method thereof

Abstract

The present invention provides a memory structure and a manufacturing method thereof. The memory structure comprises a first gate, a second gate, a dielectric protrusion, a first spacer, a charge storage layer, a gate dielectric layer, a high dielectric constant layer and a doped region. The first gate and the second gate are arranged on a substrate. The dielectric protrusion is arranged on the substrate between the first gate and the second gate. The first spacer is arranged on the sidewall of the dielectric protrusion. The charge storage layer is arranged between the first gate and the substrate. The gate dielectric layer is arranged between the second gate and the substrate. The high dielectric constant layer is arranged between the first gate and the charge storage layer and between the second gate and the gate dielectric layer. The doped region is arranged in the substrate on both sides of the first gate and on both sides of the second gate.

Description

Technical Field

[0001] The present invention relates to a memory structure, and more particularly to a memory structure including a memory cell having a high-K layer and a silicon-oxide-nitride-oxide-silicon (SONOS) stacking architecture. Background Art

[0002] In the existing memory, a memory cell having a high dielectric constant layer and a SONOS stacking structure may be referred to as a HKSONOS memory cell. In the process of the memory including the HKSONOS memory cell, after forming the gate of the HKSONOS memory cell and the gate of a select transistor or other transistors, a portion of the high dielectric constant layer formed on the substrate is removed, and only the high dielectric constant layer located under the gates is retained.

[0003] However, in the above process, high dielectric constant materials are often left on the substrate between the HKSONOS memory cell and the transistor. As a result, in subsequent processes, the remaining high dielectric constant materials will cause contamination and affect the yield of the final product, and even cause contamination problems to the process equipment. Summary of the invention

[0004] The present invention is directed to a memory structure and a manufacturing method thereof, which can prevent high dielectric constant material from remaining on a substrate.

[0005] The memory structure of the present invention comprises a first gate, a second gate, a dielectric hump, a first spacer, a charge storage layer, a gate dielectric layer, a high dielectric constant layer and a doped region. The first gate and the second gate are arranged on a substrate. The dielectric hump is arranged on the substrate between the first gate and the second gate. The first spacer is arranged on the sidewall of the dielectric hump. The charge storage layer is arranged between the first gate and the substrate. The gate dielectric layer is arranged between the second gate and the substrate. The high dielectric constant layer is arranged between the first gate and the charge storage layer and between the second gate and the gate dielectric layer. The doped region is arranged in the substrate on both sides of the first gate and on both sides of the second gate.

[0006] In an embodiment of the memory structure of the present invention, the material of the first spacer includes silicon nitride.

[0007] In an embodiment of the memory structure of the present invention, the gate dielectric layer extends to connect with the dielectric protrusion.

[0008] In an embodiment of the memory structure of the present invention, the first spacer is located on the gate dielectric layer.

[0009] In an embodiment of the memory structure of the present invention, a second spacer and a third spacer are further included, wherein the second spacer is disposed on the sidewall of the first gate, and the third spacer is disposed on the sidewall of the second gate.

[0010] In an embodiment of the memory structure of the present invention, the charge storage layer is further located between the second spacer and the substrate, and the gate dielectric layer is further located between the third spacer and the substrate.

[0011] In an embodiment of the memory structure of the present invention, the material of the first gate and the second gate includes polysilicon.

[0012] In an embodiment of the memory structure of the present invention, the material of the first gate and the second gate includes metal.

[0013] In one embodiment of the memory structure of the present invention, it also includes a first metal silicide layer and a second metal silicide layer, wherein the first metal silicide layer is arranged on the doped region located on the side of the first gate away from the second gate, and the second metal silicide layer is arranged on the doped region located on the side of the second gate away from the first gate.

[0014] In one embodiment of the memory structure of the present invention, it also includes a first contact and a second contact, wherein the first contact is electrically connected to the doped region located on the side of the first gate away from the second gate, and the second contact is electrically connected to the doped region located on the side of the second gate away from the first gate.

[0015] The manufacturing method of the memory structure of the present invention comprises the following steps. A pad layer is formed on a substrate. A charge storage layer is formed on the substrate and the pad layer. A portion of the pad layer and the charge storage layer above the pad layer are removed so that the remaining pad layer forms a dielectric protrusion. A dielectric layer is formed on the substrate exposed by the charge storage layer and the dielectric protrusion. A first spacer is formed on the sidewall of the dielectric protrusion. A high dielectric constant layer is formed on the substrate, wherein the high dielectric constant layer covers the charge storage layer, the dielectric protrusion, the first spacer and the dielectric layer. A first gate is formed on the high dielectric constant layer on the charge storage layer. A second gate is formed on the high dielectric constant layer on the dielectric layer. A portion of the high dielectric constant layer is removed to retain the high dielectric constant layer below the first gate and below the second gate. Doped regions are formed in the substrate on both sides of the first gate and on both sides of the second gate.

[0016] In an embodiment of the method for manufacturing a memory structure of the present invention, the material of the first spacer includes silicon nitride.

[0017] In one embodiment of the method for manufacturing a memory structure of the present invention, the method for forming the first spacer comprises the following steps: forming a spacer material layer on the charge storage layer, the dielectric protrusion and the dielectric layer; performing an anisotropic etching process to remove the spacer material layer on the top surface of the charge storage layer and the top surface of the dielectric layer.

[0018] In an embodiment of the method for manufacturing the memory structure of the present invention, after removing part of the high dielectric constant layer and before forming the doped region, it further includes forming a second spacer on the sidewall of the first gate and forming a third spacer on the sidewall of the second gate.

[0019] In one embodiment of the method for manufacturing a memory structure of the present invention, the method for forming the second spacer and the third spacer comprises the following steps: forming a spacer material layer on the substrate, wherein the spacer material layer covers the top surface of the first gate and the top surface of the second gate; and removing a portion of the spacer material layer to form the second spacer and the third spacer.

[0020] In one embodiment of the method for manufacturing a memory structure of the present invention, removing part of the spacer material layer comprises the following steps: performing a chemical mechanical polishing process on the spacer material layer to remove part of the spacer material layer; performing an anisotropic etching process on the remaining spacer material layer until the top surface of the first gate and the top surface of the second gate are exposed.

[0021] In an embodiment of the method for manufacturing a memory structure of the present invention, the material of the first gate and the second gate includes polysilicon.

[0022] In one embodiment of the method for manufacturing a memory structure of the present invention, the method further includes the following steps: removing the polysilicon; and forming a metal material on the high dielectric constant layer.

[0023] In one embodiment of the method for manufacturing the memory structure of the present invention, after forming the doped region, it also includes forming a first metal silicide layer on the doped region on the side of the first gate away from the second gate, and forming a second metal silicide layer on the doped region on the side of the second gate away from the first gate.

[0024] In one embodiment of the method for manufacturing the memory structure of the present invention, after forming the doped region, it also includes forming a first contact electrically connected to the doped region located on a side of the first gate away from the second gate, and forming a second contact electrically connected to the doped region located on a side of the second gate away from the first gate.

[0025] In summary, in the manufacturing process of the memory structure of the present invention, the first spacer is formed on the sidewall of the dielectric protrusion between the first gate and the second gate, so that the high dielectric constant layer formed subsequently can be smoothly formed on the sidewall of the dielectric protrusion. Therefore, when the high dielectric constant layer is removed by using the first gate and the second gate as etching masks, the high dielectric constant material can be effectively prevented from remaining around the dielectric protrusion, thereby preventing the residual high dielectric constant material from causing contamination to the subsequent process and the final product. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figures 1A to 1H Schematic diagram of a cross-section of the manufacturing process of the memory structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0027] The following examples are listed and described in detail with reference to the accompanying drawings, but the examples provided are not intended to limit the scope of the present invention. In addition, the drawings are for illustration purposes only and are not drawn to their original size. For ease of understanding, the same components are indicated by the same symbols in the following description.

[0028] The terms "include", "including", "have", etc. used in this document are open terms, which means "including but not limited to".

[0029] When the terms "first", "second", etc. are used to describe components, they are only used to distinguish these components from each other, and do not limit the order or importance of these components. Therefore, in some cases, the first component may also be referred to as the second component, and the second component may also be referred to as the first component, and this does not deviate from the scope of the present invention.

[0030] In addition, directional terms such as "upper", "lower", etc. mentioned herein are only used to refer to the directions of the drawings and are not used to limit the present invention. Therefore, it should be understood that "upper" can be used interchangeably with "lower", and when a component such as a layer or film is placed "on" another component, the component can be placed directly on the other component, or there can be an intermediate component. On the other hand, when a component is said to be placed "directly" on another component, there is no intermediate component between the two.

[0031] In addition, in this article, the range expressed by "a value to another value" is a summary expression method to avoid listing all the values ​​in the range one by one in the specification. Therefore, the description of a specific numerical range covers any value in the numerical range, and covers a smaller numerical range defined by any value in the numerical range.

[0032] Figures 1A to 1H Schematic diagram of a cross-section of the manufacturing process of the memory structure according to an embodiment of the present invention.

[0033] First, please refer to Figure 1A , providing a substrate 100. In this embodiment, the substrate 100 is, for example, a silicon substrate. Then, a pad layer 102 is formed on the substrate 100. In this embodiment, the material of the pad layer 102 is, for example, silicon oxide, and the formation method thereof is, for example, a thermal oxidation process, but the present invention is not limited thereto.

[0034] Next, please refer to Figure 1B , remove the pad layer 102 in the area where the memory cell is to be formed. The method for removing the pad layer 102 in the area where the memory cell is to be formed may include the following steps, but the present invention is not limited thereto. First, a patterned mask layer (not shown) is formed on the substrate 100. The patterned mask layer exposes the area where the memory cell is to be formed. Next, an anisotropic etching process is performed to remove the exposed pad layer 102. Thereafter, the patterned mask layer is removed. After removing the patterned mask layer, a cleaning process may be performed to remove etching byproducts and impurities on the substrate 100. At this time, the corners at the ends of the pad layer 102 will be slightly removed to form rounded corners.

[0035] After removing the pad layer 102 in the area where the memory cell is to be formed, a charge storage layer 104 is formed on the substrate 100. The charge storage layer 104 covers the substrate 100 and the remaining pad layer 102. In the present embodiment, the charge storage layer 104 is, for example, composed of a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer stacked in sequence, i.e., a so-called ONO stacked layer, but the present invention is not limited thereto. In addition, the method for forming the charge storage layer 104 is well known to those skilled in the art and will not be described separately herein.

[0036] Then, please refer to Figure 1C , remove part of the charge storage layer 104, and retain the charge storage layer 104 in the area where the memory cell is to be formed. The method for removing part of the charge storage layer 104 may include the following steps, but the present invention is not limited thereto. First, a patterned mask layer (not shown) is formed on the substrate 100. The patterned mask layer covers the area where the memory cell is to be formed. Next, an anisotropic etching process is performed to remove the exposed charge storage layer 104. Thereafter, the patterned mask layer is removed. In the anisotropic etching process, in addition to removing the exposed charge storage layer 104, the pad layer 102 below is also removed at the same time to expose the substrate 100.

[0037] In the present embodiment, in order to prevent the position of the patterned mask layer from being offset and causing the charge storage layer 104 in the area where the memory cell is to be formed to be removed, the patterned mask layer usually additionally covers the charge storage layer 104 around the area where the memory cell is to be formed. In this way, after the anisotropic etching process, a portion of the charge storage layer 104 and the pad layer 102 located thereunder will be retained around the area where the memory cell is to be formed. In the present embodiment, the pad layer 102 retained around the area where the memory cell is to be formed forms a dielectric protrusion 106, and the charge storage layer 104 covers the top surface and a portion of the sidewall of the dielectric protrusion 106. The top corners of the dielectric protrusion 106 adjacent to the area where the memory cell is to be formed are rounded.

[0038] Next, please refer to Figure 1D , a dielectric layer 108 is formed on the substrate 100 exposed by the charge storage layer 104 and the dielectric protrusion 106, so that the dielectric protrusion 106 is connected to the dielectric layer 108. In the present embodiment, the material of the dielectric layer 108 is, for example, silicon oxide, and the formation method thereof is, for example, a thermal oxidation process or a chemical vapor deposition (CVD) process, but the present invention is not limited thereto. The dielectric layer 108 can be used to form the gate dielectric layer of the transistor in the memory structure of the present embodiment. Thereafter, a spacer material layer 110 is conformally formed on the substrate 100. In the present embodiment, the material of the spacer material layer 110 is, for example, silicon nitride, and the formation method thereof is, for example, a chemical vapor deposition process, but the present invention is not limited thereto.

[0039] Then, please refer to Figure 1E , an anisotropic etching process is performed on the spacer material layer 110 to remove the spacer material layer 110 on the top surface of the charge storage layer 104 and the top surface of the dielectric layer 108, while retaining the spacer material layer 110 located on the sidewall of the dielectric protrusion 106. That is, in the present embodiment, a first spacer 110a is formed on the sidewall of the dielectric protrusion 106, and the first spacer 110a is located on the dielectric layer 108. Since the top corner of the dielectric protrusion 106 adjacent to the area where the memory cell is to be formed is rounded, after the above-mentioned anisotropic etching process, no spacer is formed on the sidewall of the dielectric protrusion 106 adjacent to the area where the memory cell is to be formed.

[0040] After forming the first spacer 110a, a high dielectric constant layer 112 is conformally formed on the substrate 100. The high dielectric constant layer 112 covers the charge storage layer 104, the dielectric protrusion 106, the first spacer 110a, and the dielectric layer 108. In the present embodiment, the high dielectric constant layer 112 refers to a dielectric layer having a dielectric constant greater than 4 in the technical field. The material of the high dielectric constant layer 112 may be aluminum oxide (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), hafnium oxide (HfO2), lanthanum oxide (La2O3), etc., and the present invention is not limited thereto.

[0041] Then, a gate material layer 114 is formed on the high dielectric constant layer 112. In this embodiment, the material of the gate material layer 114 may be polysilicon. The thickness of the gate material layer 114 is, for example, between to After forming the gate material layer 114, the gate material layer 114 may be selectively subjected to a planarization process so that the gate material layer 114 has a flat surface and a desired thickness. In the present embodiment, the planarization process is, for example, a chemical mechanical polishing (CMP) process. In addition, after the planarization process is performed, the gate material layer 114 may be further subjected to an etching-back process depending on actual needs to more accurately control the thickness of the remaining gate material layer 114.

[0042] Next, please refer to Figure 1F, a patterning process is performed on the gate material layer 114 to form a first gate 114a on the high dielectric constant layer 112 on the charge storage layer 104, and a second gate 114b on the high dielectric constant layer 112 on the dielectric layer 108. The first gate 114a can be used as a control gate (controlgate) of the memory cell in the memory structure of this embodiment, and the second gate 114b can be used as a gate (select gate) of the select transistor in the memory structure of this embodiment. Afterwards, an anisotropic etching process is performed using the first gate 114a and the second gate 114b as etching masks to remove part of the high dielectric constant layer 112, and retain the high dielectric constant layer 112 under the first gate 114a and the second gate 114b.

[0043] In the present embodiment, since the dielectric protrusion 106 is formed by an anisotropic etching process, the dielectric protrusion 106 has a substantially vertical sidewall. After the first spacer 110a is formed on the sidewall of the dielectric protrusion 106, since the sidewall of the first spacer 110a is not substantially vertical (usually has a curved surface), Figure 1E In the above steps, the high dielectric constant layer 112 can be formed more smoothly on the sidewalls of the dielectric protrusion 106. Figure 1F In the above steps, when the high dielectric constant layer 112 is removed using the first gate 114a and the second gate 114b as etching masks, the high dielectric constant layer 112 can be effectively prevented from remaining around the dielectric protrusion 106, that is, no high dielectric constant material will remain between the first gate 114a and the second gate 114b, thereby preventing the residual high dielectric constant material from causing contamination to subsequent processes and the final product.

[0044] Then, please refer to Figure 1G , a second spacer 120 is formed on the sidewall of the first gate 114a and a third spacer 122 is formed on the sidewall of the second gate 114b. In this embodiment, the top surface of the second spacer 120 may be coplanar with the top surface of the first gate 114a, and the top surface of the third spacer 122 may be coplanar with the top surface of the second gate 114b.

[0045] The method for forming the second spacer 120 and the third spacer 122 may include the following steps. First, a spacer material layer (not shown) is formed on the substrate 100. The spacer material layer covers the top surface of the first gate 114a and the top surface of the second gate 114b. The material of the spacer material layer is, for example, silicon nitride, and the method for forming the spacer material layer is, for example, a chemical vapor deposition process. Next, a chemical mechanical polishing process is performed on the spacer material layer to remove a portion of the spacer material layer to reduce the thickness of the spacer material layer. Thereafter, an anisotropic etching process is performed on the remaining spacer material layer until the top surface of the first gate 114a and the top surface of the second gate 114b are exposed.

[0046] Next, an etching process is performed to remove the charge storage layer 104 located on both sides of the first gate 114a and the dielectric layer 108 located on both sides of the second gate 114b. In the present embodiment, the first gate 114a, the second spacer 120, the second gate 114b, the third spacer 122 and the first spacer 110a are used as masks to remove the charge storage layer 104 and the dielectric layer 108. Therefore, the retained charge storage layer 104 is located between the second spacer 120 and the substrate 100 in addition to being located between the high dielectric constant layer 112 and the substrate 100, and the retained dielectric layer 108 is located between the third spacer 122 and the substrate 100 and between the first spacer 110a and the substrate 100 in addition to being located between the high dielectric constant layer 112 and the substrate 100. The dielectric layer 108 below the second gate 114b can be used as a gate dielectric layer of the transistor. Furthermore, in the above-mentioned etching process, depending on the etching time, the dielectric protrusion 106 may also be partially removed.

[0047] Afterwards, please refer to Figure 1H An ion implantation process is performed using the first gate 114a, the second spacer 120, the second gate 114b and the third spacer 122 as masks to form doped regions 124 in the substrate 100 on both sides of the first gate 114a and on both sides of the second gate 114b.

[0048] Next, a first metal silicide layer 126 is formed on the doped region 124 on the side of the first gate 114a away from the second gate 114b, and a second metal silicide layer 128 is formed on the doped region 124 on the side of the second gate 114b away from the first gate 114a. In the memory structure of the present embodiment, since the doped region 124 between the first gate 114a and the second gate 114b is floating, it is not necessary to form a metal silicide layer on the doped region 124 between the first gate 114a and the second gate 114b. Afterwards, a first contact 130 connected to the first metal silicide layer 126 and a second contact 132 connected to the second metal silicide layer 128 can be formed. In this way, the memory structure 10 of the present embodiment is completed.

[0049] In the manufacturing process of the memory structure 10 of the present embodiment, the first spacer 110a is formed on the sidewall of the dielectric protrusion 106 between the first gate 114a and the second gate 114b, so that the high dielectric constant layer 112 formed subsequently can be smoothly formed on the sidewall of the dielectric protrusion 106. In this way, when the high dielectric constant layer 112 is removed by using the first gate 114a and the second gate 114b as an etching mask, the high dielectric constant layer 112 can be effectively prevented from remaining around the dielectric protrusion 106, thereby preventing the residual high dielectric constant material from causing contamination to the subsequent process and the final product.

[0050] In addition, Figure 1G In the above steps, after forming the second spacer 120 and the third spacer 122 , a replacement metal gate (RMG) process (also called a gate-last process) may be further performed.

[0051] For example, in the above embodiment, the material of the first gate 114a and the second gate 114b is polysilicon. Therefore, after forming the second spacer 120 and the third spacer 122, the polysilicon material forming the first gate 114a and the second gate 114b can be removed, and then a metal material is filled in the area where the polysilicon material is removed to form a metal layer on the high dielectric constant layer 112 to serve as the first gate 114a and the second gate 114b.

[0052] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory structure, characterized in that: include: A first gate and a second gate are disposed on a substrate; a dielectric protrusion disposed on the substrate between the first gate and the second gate; a first spacer disposed on a sidewall of the dielectric protrusion; A charge storage layer, disposed between the first gate and the substrate; a gate dielectric layer, disposed between the second gate and the substrate; A high dielectric constant layer, disposed between the first gate and the charge storage layer and between the second gate and the gate dielectric layer; as well as Doped regions are disposed in the substrate at both sides of the first gate and at both sides of the second gate.

2. The memory structure according to claim 1, characterized in that: The material of the first spacer includes silicon nitride.

3. The memory structure according to claim 1, characterized in that: The gate dielectric layer extends to connect with the dielectric protrusion.

4. The memory structure according to claim 3, characterized in that: The first spacer is located on the gate dielectric layer.

5. The memory structure according to claim 1, characterized in that: The invention also includes a second spacer and a third spacer, wherein the second spacer is disposed on the sidewall of the first gate, and the third spacer is disposed on the sidewall of the second gate.

6. The memory structure according to claim 5, characterized in that: The charge storage layer is also located between the second spacer and the substrate, and the gate dielectric layer is also located between the third spacer and the substrate.

7. The memory structure according to claim 1, characterized in that: The first gate and the second gate are made of polysilicon.

8. The memory structure according to claim 1, characterized in that: The material of the first gate and the second gate includes metal.

9. The memory structure according to claim 1, characterized in that: It also includes a first metal silicide layer and a second metal silicide layer, wherein the first metal silicide layer is arranged on the doped region located on the side of the first gate away from the second gate, and the second metal silicide layer is arranged on the doped region located on the side of the second gate away from the first gate.

10. The memory structure according to claim 1, characterized in that: It also includes a first contact and a second contact, wherein the first contact is electrically connected to the doped region located on a side of the first gate away from the second gate, and the second contact is electrically connected to the doped region located on a side of the second gate away from the first gate.

11. A method for manufacturing a memory structure, characterized in that: include: forming a cushion layer on a substrate; forming a charge storage layer on the substrate and the pad layer; removing a portion of the pad layer and the charge storage layer thereon, so that the remaining pad layer forms a dielectric protrusion; forming a dielectric layer on the substrate exposed by the charge storage layer and the dielectric protrusion; forming a first spacer on a sidewall of the dielectric protrusion; forming a high dielectric constant layer on the substrate, wherein the high dielectric constant layer covers the charge storage layer, the dielectric protrusion, the first spacer, and the dielectric layer; forming a first gate on the high dielectric constant layer on the charge storage layer; forming a second gate on the high dielectric constant layer on the dielectric layer; removing a portion of the high dielectric constant layer to retain the high dielectric constant layer under the first gate and under the second gate; and Doped regions are formed in the substrate at both sides of the first gate and at both sides of the second gate.

12. The method for manufacturing a memory structure according to claim 11, characterized in that: The material of the first spacer includes silicon nitride.

13. The method for manufacturing a memory structure according to claim 11, characterized in that: The method for forming the first spacer includes: forming a spacer material layer on the charge storage layer, the dielectric protrusions, and the dielectric layer; and An anisotropic etching process is performed to remove the spacer material layer on the top surface of the charge storage layer and on the top surface of the dielectric layer.

14. The method for manufacturing a memory structure according to claim 11, characterized in that: After removing part of the high dielectric constant layer and before forming the doped region, the method further includes forming a second spacer on the sidewall of the first gate and forming a third spacer on the sidewall of the second gate.

15. The method for manufacturing a memory structure according to claim 14, characterized in that: The method of forming the second spacer and the third spacer includes: forming a spacer material layer on the substrate, wherein the spacer material layer covers a top surface of the first gate and a top surface of the second gate; and A portion of the spacer material layer is removed to form the second spacer and the third spacer.

16. The method for manufacturing a memory structure according to claim 15, characterized in that: Removing a portion of the spacer material layer includes: Performing a chemical mechanical polishing process on the spacer material layer to remove a portion of the spacer material layer; and An anisotropic etching process is performed on the remaining spacer material layer until the top surface of the first gate and the top surface of the second gate are exposed.

17. The method for manufacturing a memory structure according to claim 11, characterized in that: The first gate and the second gate are made of polysilicon.

18. The method for manufacturing a memory structure according to claim 17, characterized in that: Also includes: removing the polysilicon; as well as A metal material is formed on the high dielectric constant layer.

19. The method for manufacturing a memory structure according to claim 11, characterized in that: After forming the doped region, the method further includes forming a first metal silicide layer on the doped region on a side of the first gate away from the second gate, and forming a second metal silicide layer on the doped region on a side of the second gate away from the first gate.

20. The method for manufacturing a memory structure according to claim 11, characterized in that: After forming the doped region, the method further includes forming a first contact electrically connected to the doped region on a side of the first gate away from the second gate, and forming a second contact electrically connected to the doped region on a side of the second gate away from the first gate.

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