A high-durability FeNAND device with a microheater and its fabrication method

Abstract

This invention discloses a high-durability FeNAND device with a microheater and its fabrication method, belonging to the field of micro-nano electronics technology. The invention consists of a FeNAND memory and a microheater. The Joule heat generated by the microheater can recover from the fatigue of the FeNAND device caused by write cycles, thereby effectively optimizing the durability of the FeNAND without affecting the storage density of the FeNAND memory. The FeNAND device with the microheater of this invention is compatible with advanced node 3D NAND storage technology, does not introduce additional process costs, has minimal impact on storage density, and can be easily applied to 3D FeNAND storage technology.

Description

Technical Field

[0001] This invention belongs to the field of micro-nano electronics technology, specifically relating to a novel high-durability FeNAND device with a microheater and its fabrication method. Background Technology

[0002] Currently, 3D NAND flash memory based on charge-trapped flash (CTF) has become the mainstream technology in the field of high-density storage. However, with the continuous increase in memory integration and performance requirements, 3D NAND has encountered significant technical challenges in further reducing the vertical spacing. Among these challenges, inter-cell interference and the physical thickness limitation of the oxide spacer layer between adjacent cells have become major bottlenecks. Because CTF technology relies on charge storage mechanisms, charge migration easily occurs when memory cells are stacked tightly in the vertical direction, leading to inter-cell interference problems. In addition, the thickness of the spacer oxide layer between cells is difficult to further reduce, limiting the vertical shrinkage capability of the memory and hindering the realization of higher integration densities.

[0003] To address the aforementioned issues, NAND technology based on hafnium oxide ferroelectric field-effect transistors (FeFETs) (FeNAND for short) is considered one of the most promising candidates for next-generation 3D NAND technology. Unlike traditional CTF technology, FeNAND significantly suppresses charge migration between cells through the bistable polarization characteristics of ferroelectric materials, effectively reducing interference. Simultaneously, FeNAND leverages the lower switching voltage characteristics of ferroelectric materials to achieve lower operating voltages. This allows for further reduction in the vertical height of memory cells and the spacing between cells, resulting in higher integration density in terms of vertical height and significantly improved memory reliability, providing a new technological path for next-generation high-density 3D NAND memory technology.

[0004] Although ferroelectric field-effect transistors (FeFETs) have a smaller storage window compared to traditional charge-trapped flash memory (CTF), recent research on FeFETs with MIFIS (Metal-Insulator-Ferroelectric-Insulator-Semiconductor) structures has made significant progress. By utilizing the trapped charge in the gate interface layer, the storage window has been extended to a maximum of 15V. This technological breakthrough has significantly improved FeFET performance, laying the foundation for its greater potential in practical applications. Benefiting from FeNAND's lower operating voltage, lower power consumption, faster write speeds, and the high-density potential of 3D stacking compared to traditional CTF flash memory, FeNAND has also shown great application potential in novel computing architectures, such as in-memory computing. However, in novel computing architectures requiring frequent writes, FeNAND still faces severe durability issues, becoming a key factor limiting its further development. Especially after the introduction of the gate interface layer, the performance degradation of the memory cell under high-frequency operation is more severe due to the additional charge trapping effect. This phenomenon not only shortens the write / erase cycle life of the cell but also forces FeNAND technology to face a severe trade-off between storage density and reliability. In high-density storage applications, most research focuses on increasing storage density to further improve the integration and performance of storage cells, neglecting the need for synergistic optimization of storage density and durability. This research trend of unilaterally pursuing storage density may lead to durability becoming a key bottleneck for the future practical deployment and widespread application of FeNAND. Therefore, how to balance storage density in FeNAND while solving the long-standing durability challenges has become an urgent technical problem to be solved. Summary of the Invention

[0005] To address the aforementioned requirements of FeNAND technology that balance storage density and durability, this invention proposes a novel high-durability FeNAND device with a microheater and its fabrication method, comprising a FeNAND memory and a microheater surrounding it. The Joule heat generated by the microheater can recover from the fatigue of the FeNAND device caused by write cycles, thereby effectively optimizing the durability of the FeNAND without affecting the storage density of the FeNAND memory. The FeNAND device with a microheater proposed in this invention is compatible with advanced node 3D NAND storage technology processes, introduces no additional process costs, has minimal impact on storage density, and can be easily applied to 3D FeNAND storage technology.

[0006] Specifically, the technical solution of the present invention is as follows:

[0007] A high-durability FeNAND device with a microheater includes a silicon substrate, a gate stack structure, a gate metal electrode, and source and drain regions. The silicon substrate comprises, from bottom to top, a bottom silicon layer, a buried oxide layer, and a top silicon layer. Multiple gate stack structures are disposed above the top silicon layer. Each gate stack structure comprises, from bottom to top, an alumina channel interface layer, a hafnium-zirconium ferroelectric layer, and an alumina gate interface layer. The alumina channel interface layer is located on the top silicon layer, the hafnium-zirconium ferroelectric layer is on the alumina channel interface layer, and the alumina gate interface layer is on the hafnium-zirconium ferroelectric layer. One of the gate stack structures serves as… The gate of the FeNAND device has source and drain regions on both sides of the top silicon layer below the gate stack. The gate stack structure is a gate metal electrode. Other gate stack structures and conductive filaments on them serve as micro heaters. The conductive filaments are wavy or sawtooth-shaped and located on both sides of the gate of the FeNAND device. The top silicon layer is filled with passivation material. The passivation layer contains contact holes for the gate metal electrode, the source and drain regions of the FeNAND device, and the micro heaters. Contact metal fills the contact holes and covers the passivation layer.

[0008] Furthermore, the silicon substrate is a fully depleted SOI wafer, wherein the thickness of the top silicon layer is 10–15 nm, the thickness of the buried oxide layer of silicon dioxide beneath the top silicon layer is 15–30 nm, and the thickness of the bottom silicon layer is approximately 500 μm. In the top silicon layer, a lower concentration of arsenic or phosphorus doping is used for n-type FeNAND, and a lower concentration of boron doping is used for p-type FeNAND.

[0009] Furthermore, the thickness of the alumina channel interface layer is 1–2 nm.

[0010] Furthermore, in the hafnium-zirconium ferroelectric layer, the ratio of hafnium atoms to zirconium atoms is 1:1, and the thickness is 10-20 nm.

[0011] Furthermore, the thickness of the alumina gate interface layer is 3–6 nm.

[0012] Furthermore, the gate metal material can be selected from metallic materials with low resistivity such as TiN, TaN, or W. At the same time, a certain stress needs to be formed on the ferroelectric layer to induce the formation of stable ferroelectricity.

[0013] Furthermore, the source and drain of the FeNAND device are regions formed by implanting high-concentration ions into the top silicon layer. High-concentration arsenic or phosphorus doping is used for n-type FeNAND, and high-concentration boron doping is used for p-type FeNAND.

[0014] Furthermore, the conductive filament of the microheater is made of the same material as the gate metal electrode, namely, a metallic material with good conductivity and high thermal stability such as TiN and W, while also having a small size to provide sufficient Joule heat.

[0015] Furthermore, the passivation layer is made of silicon dioxide and has a thickness of 300–700 nm.

[0016] Furthermore, the contact metal material may include, but is not limited to, materials such as Al, Pt, Cr, Cu, Au, and Ti; the contact metal should have a low resistivity and form a good ohmic contact with the source and drain to reduce contact resistance.

[0017] This invention also provides a method for fabricating a high-durability FeNAND device with a microheater, comprising the following steps:

[0018] (1) Define the active region on the SOI silicon substrate, and then use photoresist as a barrier layer to etch away the top silicon of the non-active region to expose the buried oxide layer underneath, thereby forming isolation between devices, and then remove the photoresist.

[0019] (2) Remove the natural oxide layer on the top silicon surface of the active region silicon substrate with a diluted hydrofluoric acid solution or hydrofluoric acid buffer etcher (BOE).

[0020] (3) An alumina channel interface layer is grown on the top silicon layer of the active region by atomic layer deposition;

[0021] (4) A hafnium zirconium ferroelectric layer is grown on the alumina channel interface layer by atomic layer deposition;

[0022] (5) An alumina gate interface layer is grown on the hafnium zirconium ferroelectric layer by atomic layer deposition;

[0023] (6) On the alumina gate interface layer, the gate metal electrode and conductive filament material are grown by physical vapor deposition (PVD).

[0024] (7) Define the gate metal electrode region and the conductive filament region by electron beam lithography, use electron beam photoresist as a barrier layer, and then dry etch to remove the gate metal electrode and conductive filament material in other regions.

[0025] (8) Using photoresist and gate metal electrode as a barrier layer, the source and drain regions of the FeNAND device are formed on the top silicon on both sides of the gate region of the FeNAND device by self-aligned ion implantation. The middle of the source and drain regions is the channel region of the FeNAND device.

[0026] (9) The entire wafer is subjected to rapid thermal annealing (RTP) to simultaneously activate the ferroelectricity of the hybrid ferroelectric layer and activate the ions implanted into the source and drain regions;

[0027] (10) A silicon dioxide passivation layer is grown on the entire wafer by chemical vapor deposition (CVD);

[0028] (11) Then, the gate, source, drain regions of FeNAND and the contact hole pattern of micro heater are defined by ultraviolet lithography. Photoresist is used as a barrier layer. Dry etching and wet etching are used to remove the silicon dioxide passivation layer of the contact hole region to form a via. Then the photoresist is removed.

[0029] (12) Source, drain, and gate contact metals are grown and deposited on the whole wafer by sputtering, vapor deposition or other physical vapor deposition methods. The contact metals fill the contact holes and cover the surface above the silicon dioxide passivation layer.

[0030] (13) Define the pattern of the contact metal electrodes of the gate, source and drain by ultraviolet lithography, use photoresist as a barrier layer, use dry etching to remove the contact metal of the remaining area, ensure over-etching to the silicon dioxide passivation layer, and then remove the photoresist.

[0031] (14) Finally, alloy annealing is performed to form an ohmic contact between the contact metal and the source / drain.

[0032] Furthermore, in steps (3), (4), and (5), atomic layer deposition (ALD) is preferably used to grow the alumina interface layer and the hafnium-zirconium ferroelectric layer. Trimethylaluminum (TMA), tetra(dimethylamino)hafnium (TDMAHf), tetra(dimethylamino)zirconium (TDMAZr), and water can be used as precursors for aluminum, hafnium, zirconium, and oxygen, respectively. Deposition can be completed in the same ALD step. The growth sequence of the materials and the ratio of the number of atoms in the hafnium-zirconium ferroelectric layer can be controlled by setting the pulse sequence of different components in the program, thereby simplifying the process. The final hafnium-zirconium ferroelectric layer has a hafnium to zirconium atom ratio of 1:1, thus ensuring stable ferroelectricity.

[0033] Furthermore, in step (6), the gate metal electrode and the conductive filament grown by PVD are made of the same metallic material, such as TiN, thereby simplifying the process.

[0034] Furthermore, in step (7), electron beam lithography is used to define a gate region with a smaller width and length, as well as a finer conductive filament region, so that the formed FeNAND device has a higher storage density and the micro heater has a better heating effect.

[0035] Furthermore, in step (8) self-aligned ion implantation, appropriate energy and dosage are required to implant ions into the entire wafer according to the concentration and depth of doping in the desired source and drain, so as to ensure that a source and drain with low resistivity can be formed without damaging other structures.

[0036] Furthermore, the temperature and time of the rapid thermal annealing process in step (9) need to simultaneously meet the conditions for activation of the mixed ferroelectric layer and activation of the source and drain. The temperature and time need to be flexibly adjusted according to the different ferroelectric layer materials, gate materials, implanted ion types and doses. The approximate range is: annealing temperature of 500-900℃ and annealing time of 10-120s.

[0037] Furthermore, in step (14), the alloy annealing temperature is 400-450°C and the time is about 30 minutes.

[0038] The technical effects of this invention are as follows:

[0039] I. By utilizing the Joule heating effect of the current generated by the micro-heater, the performance of fatigued FeNAND devices can be restored, thereby improving the durability of FeNAND devices and extending their service life.

[0040] In this invention, unlike other common FeNAND devices, the proposed high-endurance FeNAND device is surrounded by a microheater. In FeNAND memory devices, during each write operation, the large write electric field causes a large number of trapped charges to be trapped in the gate stack, while new interface traps are also generated. With each write operation, a large amount of interface trap charges accumulate in the gate stack, and a large number of new interface traps are generated. These new interface traps further increase the trapped charges, gradually shielding ferropolarization, leading to a shift in the FeNAND device's threshold voltage, a reduction in the storage window, and performance degradation. However, by utilizing the Joule heating effect generated by the microheater when current is applied, the temperature around the FeNAND device can be increased. Under high temperature, the interface trap charges accumulated in the FeNAND gate stack are detrapped, and the traps in the gate stack are passivated, thereby restoring the performance of the fatigued FeNAND device. Using this endurance recovery method, the endurance of FeNAND devices can be further extended.

[0041] Second, the microheater proposed in this invention is compatible with the integration process of the three-dimensional FeNAND device, without increasing the manufacturing cost. Furthermore, due to its small size, it can maximize the preservation of the storage density of the three-dimensional FeNAND memory. The FeNAND device with microheater proposed in this invention is compatible with the advanced node three-dimensional NAND Flash process and is expected to be incorporated into future high-density three-dimensional FeNAND storage technology, improving its durability. Attached Figure Description

[0042] Figure 1In the figure, (a) is a cross-sectional schematic diagram of a high-durability FeNAND device with a microheater prepared according to an embodiment of the present invention, and (b) is a top view of a high-durability FeNAND device with a microheater prepared according to an embodiment of the present invention.

[0043] Figure 2 This is a schematic diagram illustrating the steps involved in fabricating a high-durability FeNAND device with a microheater according to an embodiment of the present invention, wherein:

[0044] (a) is a cross-sectional view of the active region pattern defined by ultraviolet lithography on an SOI substrate, and then the top silicon layer of the non-active region is removed by dry etching.

[0045] (b) is a cross-sectional view of the aluminum oxide channel interface layer, hafnium zirconium ferroelectric layer and aluminum oxide gate interface layer grown by atomic layer deposition (ALD) based on (a);

[0046] (c) is a cross-sectional view of the gate metal electrode and microheater grown by physical vapor deposition (PVD) methods such as sputtering, based on (b);

[0047] (d) is a cross-sectional view after defining the gate region and microheater pattern by electron beam lithography based on (c), and then removing the gate metal and gate dielectric layer (alumina channel interface layer, hafnium zirconium ferroelectric layer and alumina gate interface layer) of other regions by dry etching.

[0048] (e) is a cross-sectional view of (d) after forming source and drain regions by self-aligned ion implantation and annealing, using photoresist and metal layer as barrier layers;

[0049] (f) is a cross-sectional view of a silicon dioxide passivation layer grown by chemical vapor deposition (CVD) based on (e);

[0050] (g) is based on (f). First, the contact hole pattern is defined by ultraviolet lithography. Then, the silicon dioxide in the contact hole is removed by dry etching and wet etching. Then, the cross-sectional view of the contact metal is grown by physical vapor deposition methods such as sputtering and evaporation.

[0051] (h) is a cross-sectional view of (g) after defining the contact metal electrode pattern using ultraviolet lithography and removing the remaining contact metal using dry etching.

[0052] Figure 1 and Figure 2 middle:

[0053] 1 — Bottom silicon layer of SOI substrate; 2 — Buried oxide layer of SOI substrate

[0054] 3—Top silicon layer of SOI substrate; 4—Alumina channel interface layer

[0055] 5—Hafnium-zirconium ferroelectric layer; 6—Alumina gate interface layer

[0056] 7—Grid metal electrode; 8—Micro heater

[0057] 9—Source 10—Leak

[0058] 11 — Silicon dioxide passivation layer 12 — Contact metal electrode

[0059] Figure 3 The microheater in this embodiment of the invention has a restoring effect on FeNAND devices, wherein:

[0060] (a) is after 10 6 After each write cycle, as the microheater voltage increases, the FeNAND device I... d -V g The curve recovery effect;

[0061] (b) Changes in the extracted threshold voltage and on-state current after recovery as the microheater voltage increases;

[0062] Figure 4 This is the result of a durability test of a FeNAND device with a microheater according to an embodiment of the present invention. Detailed Implementation

[0063] The invention will be further described below with reference to the accompanying drawings and examples.

[0064] like Figure 1 As shown, the FeNAND device with microheater prepared in this embodiment includes SOI substrate bottom silicon 1, SOI substrate buried oxide layer 2, SOI substrate top silicon 3, alumina channel interface layer 4, hafnium zirconium ferroelectric layer 5, alumina gate interface layer 6, gate metal electrode 7, microheater 8, FeNAND device source 9, FeNAND device drain 10, silicon dioxide passivation layer 11, and contact metal electrode 12. The gate stack structure, from bottom to top, includes an alumina channel interface layer, a hafnium-zirconium ferroelectric layer, and an alumina gate interface layer. The alumina channel interface layer 4 is located on the top silicon layer 3, the hafnium-zirconium ferroelectric layer 5 is located on the alumina channel interface layer 4, the alumina gate interface layer 6 is located on the hafnium-zirconium ferroelectric layer 5, the gate metal electrode 7 is located on the gate of the FeNAND device, and the microheater 8 includes a gate stack structure and conductive filaments disposed thereon. The conductive filaments are wavy or sawtooth-shaped and located on both sides of the gate of the FeNAND device. The source 9 and drain 10 of the FeNAND device are located on both sides below the gate of the FeNAND device. The gate, source, and drain contact metal electrodes 12 are respectively connected to the gate metal electrode 9, source 10, drain 11 of the FeNAND device, and the microheater 8.

[0065] The fabrication process of this FeFET is as follows: Figure 2 As shown, it specifically includes:

[0066] 1) The active region pattern is defined on the SOI substrate using ultraviolet lithography. Then, using photoresist as a barrier layer, dry etching is employed to remove the top silicon layer 3 (approximately 12nm thick) of the non-active region, ensuring proper over-etching to expose the underlying buried oxide layer 2 (approximately 20nm thick). This achieves isolation between different FeNAND devices. Finally, the photoresist is removed, as shown below. Figure 2 As shown in (a);

[0067] 2) Use diluted hydrofluoric acid solution or hydrofluoric acid buffered etching solution BHF to remove the natural oxide layer on the top silicon 3 surface of the active region. Pay attention to controlling the etching time to avoid etching away the exposed buried oxide layer of the non-active region.

[0068] 3) Subsequently, an aluminum oxide channel interface layer 4 with a thickness of 2 nm was deposited on the top silicon layer of the active region using atomic layer deposition (ALD);

[0069] 4) A 16 nm thick hafnium-zirconium ferroelectric layer 5 was deposited on the alumina channel interface layer using atomic layer deposition (ALD), wherein the ratio of hafnium atoms to zirconium atoms was 1:1. Figure 2 As shown in (b);

[0070] 5) A 3 nm thick aluminum oxide gate interface layer was deposited on the hafnium zirconium oxide (HZO) ferroelectric layer using atomic layer deposition (ALD) 6;

[0071] 6) A 50 nm thick gate metal material is grown on the alumina gate interface layer using physical vapor deposition (PVD) methods such as evaporation or sputtering. 7, for example... Figure 2 As shown in (c);

[0072] 7) The gate region and microheater pattern are defined using electron beam lithography. Then, using electron beam photoresist as a barrier layer, dry etching is employed to remove the remaining areas not covered by the photoresist and the underlying gate stack structure. Figure 2 As shown in (d), the remaining part consists of the gate metal electrode 7 and the micro heater 8;

[0073] 8) Select appropriate ions for ion implantation across the entire wafer based on either n-type or p-type FeFET, with an energy of 5 keV and an areal dose of 10. 14 cm -2In the gate region, due to the obstruction of photoresist and the gate stack structure, ions are not implanted into the gate structure. Instead, ions on both sides of the gate stack structure are implanted into the top silicon layer 3 to form the source 9 and drain 10 regions. The channel region is located between the source and drain regions. For n-type FeFETs, high-concentration doping with elements such as arsenic or phosphorus can be used to form n-type sources and drains, while for p-type FeFETs, high-concentration doping with elements such as boron can be used to form p-type sources and drains.

[0074] 9) Subsequently, the entire wafer undergoes rapid thermal annealing at a temperature of 700–900℃ for 10–60 seconds. Annealing conditions need to be flexibly adjusted based on the ferroelectric layer doping ratio, gate type, and the type, concentration, and dosage of implanted ions. It is essential to ensure simultaneous activation of the ferroelectricity of the ferroelectric layer and the implanted ions in both the source and drain regions. Figure 2 As shown in (e);

[0075] 10) A relatively thick silicon dioxide passivation layer 11 (approximately 500 nm) is grown over the entire wafer by chemical vapor deposition (CVD), such as... Figure 2 As shown in (f);

[0076] 11) Define the via pattern of the gate metal electrode 9, source 10, and drain 11 regions by ultraviolet lithography, and form vias in the silicon dioxide passivation layer 12 by combining dry etching and wet etching to ensure over-etching to expose the gate metal electrode 7, micro heater 8, source 9, and drain 11 regions, and then remove the photoresist.

[0077] 12) Then, source, drain, and gate contact metal electrodes 12 (approximately 1 μm) are grown across the entire wafer using physical vapor deposition (PVD) methods such as sputtering and evaporation. The contact metal fills the vias and covers the surface of the silicon dioxide passivation layer 11, as shown below. Figure 2 As shown in (g);

[0078] 13) Define the pattern of the contact metal electrode 12 using ultraviolet lithography, use photoresist as a barrier layer, and remove the remaining contact metal using dry etching to ensure over-etching down to the silicon dioxide passivation layer 11. Then remove the photoresist, as shown below. Figure 2 As shown in (h);

[0079] 14) Finally, perform alloy annealing to form an ohmic contact between the contact metal and the source / drain. The alloy annealing temperature is 400–450℃, and the time is about 30 minutes.

[0080] The high-durability FeNAND device with microheater can then be fabricated.

[0081] Figure 3 This illustrates the recovery effect of the microheater prepared according to an example of the present invention on the FeNAND device. As can be seen from (a), after 10... 6After the first write cycle, the FeNAND device experiences fatigue, with a decrease in on-state current and a shift in the threshold voltage towards the negative. Furthermore, as the voltage applied to the microheater increases, the current flowing through the microheater increases, exacerbating the Joule heating effect and increasing the temperature around the FeNAND gate stack. This leads to an increase in the IT of the FeNAND device. d -V g The curve gradually recovers, the on-state current increases, and the threshold voltage shifts in the positive direction, indicating that the microheater can effectively recover the fatigued FeNAND device after cycling. (b) shows the threshold voltage and V of the FeNAND device after recovery by the microheater. g The on-state current at -1V is related to the voltage applied to the microheater. As the microheater voltage increases from 0V to 8V, the threshold voltage of the FeNAND device increases from 0.71V to 1.22V, while V g The on-state current at -1V increased from 2.35μA to 5.72μA.

[0082] Figure 4 These are the durability test results of the FeNAND device with a microheater prepared in the embodiments of the present invention. Without the recovery effect of the microheater, the FeNAND device lasts for 10... 6 After each write cycle, the storage window decreases to approximately 2.0V. However, with the microheater recovery effect, that is, every 10... 6 After each write cycle, a voltage is applied to the microheater for one heating cycle, which constitutes one recovery cycle. After 200 recovery cycles, or 2 × 10⁻⁶ cycles... 8 After each write cycle, the FeNAND device maintains a storage window greater than 2.0V without significant threshold voltage shift. Therefore, the FeNAND device with microheater proposed in this invention improves durability by more than two orders of magnitude compared to FeNAND devices without microheater, effectively optimizing FeNAND durability.

[0083] Finally, it should be noted that the purpose of disclosing the embodiments is to help further understand the present invention. However, those skilled in the art will understand that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the content disclosed in the embodiments, and the scope of protection of the present invention is defined by the scope of the claims.

Claims

1. A high-durability FeNAND device with a microheater, characterized in that, The device includes a silicon substrate, a gate stack structure, a gate metal electrode, and source and drain regions. The silicon substrate, from bottom to top, comprises a bottom silicon layer, a buried oxide layer, and a top silicon layer. Multiple gate stack structures are disposed above the top silicon layer. Each gate stack structure, from bottom to top, includes an alumina channel interface layer, a hafnium-zirconium ferroelectric layer, and an alumina gate interface layer. The alumina channel interface layer is located on the top silicon layer, the hafnium-zirconium ferroelectric layer is on top of the alumina channel interface layer, and the alumina gate interface layer is on top of the hafnium-zirconium ferroelectric layer. One of the gate stack structures serves as the gate of the FeNAND device. The top silicon layer below the gate stack has source and drain regions for the FeNAND device on both sides. The gate stack structure is a gate metal electrode. Other gate stack structures and conductive filaments on them serve as micro heaters. The conductive filaments are wavy or sawtooth-shaped and located on both sides of the gate of the FeNAND device. A passivation layer material is filled on top of the top silicon layer. The passivation layer contains contact holes for the gate metal electrode, the source and drain regions of the FeNAND device, and the micro heaters. The contact metal fills the contact holes and covers the passivation layer.

2. The high-durability FeNAND device with microheater as described in claim 1, characterized in that, The thickness of the alumina channel interface layer in the gate stack structure is 1-2 nm; the ratio of hafnium atoms to zirconium atoms in the hafnium-zirconium ferroelectric layer is 1:1, and its thickness is 10-20 nm; the thickness of the alumina gate interface layer is 3-6 nm.

3. The high-durability FeNAND device with microheater as described in claim 1, characterized in that, The silicon substrate is specifically a fully depleted SOI wafer, wherein the thickness of the top silicon layer is 10-15 nm, the thickness of the buried oxide layer of silicon dioxide under the top silicon layer is 15-30 nm, and the thickness of the bottom silicon layer is within 500 μm. For n-type FeNAND, the top silicon layer is doped with a low concentration of arsenic or phosphorus, and for p-type FeNAND, the top silicon layer is doped with a low concentration of boron.

4. The high-durability FeNAND device with microheater as described in claim 1, characterized in that, The conductive filament of the microheater and the grid metal electrode are made of the same material, such as TiN, TaN, or W metallic materials.

5. The high-durability FeNAND device with microheater as described in claim 1, characterized in that, The source and drain regions of the FeNAND device are regions formed by implanting high concentrations of ions into the top silicon layer. For n-type FeNAND, high concentrations of arsenic or phosphorus doping are used, and for p-type FeNAND, high concentrations of boron doping are used.

6. The high-durability FeNAND device with microheater as described in claim 1, characterized in that, The contact metal material is selected from one of Al, Pt, Cr, Cu, Au, and Ti.

7. The high-durability FeNAND device with microheater as described in claim 1, characterized in that, The passivation layer is made of silicon dioxide and has a thickness of 300–700 nm.

8. A method for fabricating a high-durability FeNAND device with a microheater as described in claim 1, comprising the following steps: 1) Define the active region on the SOI silicon substrate, and then use photoresist as a barrier layer to etch away the top silicon of the non-active region to expose the buried oxide layer underneath, thereby forming isolation between devices, and then remove the photoresist. 2) Remove the native oxide layer on the top silicon surface of the active region silicon substrate using a diluted hydrofluoric acid solution or a hydrofluoric acid buffer etching solution. 3) An alumina channel interface layer is grown on the top silicon layer of the active region using atomic layer deposition; 4) A hafnium zirconium ferroelectric layer is grown on the alumina channel interface layer using atomic layer deposition; 5) An alumina gate interface layer is grown on the hafnium zirconium ferroelectric layer using atomic layer deposition; 6) On the alumina gate interface layer, a gate metal electrode and a conductive filament material are grown using physical vapor deposition. 7) Define the gate metal electrode region and the conductive filament region by electron beam lithography, use electron beam photoresist as a barrier layer, and then dry etch to remove the gate metal electrode and conductive filament material in other regions. 8) Using photoresist and gate metal electrodes as barrier layers, self-aligned ion implantation is used to form the source and drain regions of the FeNAND device on the top silicon layer on both sides of the gate region of the FeNAND device. The channel region of the FeNAND device is located between the source and drain regions. 9) The entire wafer is subjected to rapid thermal annealing, which simultaneously activates the ferroelectricity of the hybrid ferroelectric layer and activates the ions implanted into the source and drain regions; 10) A silicon dioxide passivation layer is grown over the entire wafer by chemical vapor deposition; 11) Define the gate, source, and drain regions of FeNAND and the contact hole pattern of the micro heater by ultraviolet lithography. Use photoresist as a barrier layer, and use dry etching and wet etching to remove the silicon dioxide passivation layer of the contact hole region to form a via. Then remove the photoresist. 12) Source, drain, and gate contact metals are grown and deposited on the entire wafer by sputtering, evaporation, or other physical vapor deposition methods. The contact metals fill the contact holes and cover the surface above the silicon dioxide passivation layer. 13) Define the pattern of the contact metal electrodes of the gate, source, and drain by ultraviolet lithography, use photoresist as a barrier layer, and use dry etching to remove the contact metal in the remaining areas to ensure over-etching to the silicon dioxide passivation layer, and then remove the photoresist. 14) Finally, perform alloy annealing to form an ohmic contact between the contact metal and the source / drain.

9. The preparation method according to claim 8, characterized in that, The rapid thermal annealing temperature in step 9) is 500–900°C, and the annealing time is 10–120 seconds.

10. The preparation method according to claim 8, characterized in that, In step 14), the alloy annealing temperature is 400-450℃ and the time is within 30 minutes.

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