Semiconductor device and method for forming the same

Abstract

The present application provides a semiconductor device and a method for forming the same, wherein the semiconductor device includes a substrate, a control circuit layer located on the substrate, a first conductive plug located on the surface of the control circuit layer, a storage device layer, and a second conductive plug. The storage device layer is located on the first conductive plug, and the storage device layer includes a first address line and a second address line that cross each other in different planes, and the first address line is located on the surface of the first conductive plug. The second conductive plug is an integrated structure located between the second address line and the control circuit layer, and the two ends of the second conductive plug are in contact with the control circuit layer and the second address line, respectively. Therefore, a single etching process can be used to form a through hole of the second conductive plug, and there is no need to form part of the second conductive plug in the process of forming the first conductive plug, and the process of forming part of the second conductive plug in the process of forming the first conductive plug is omitted, so that the part of the second conductive plug can be prevented from being damaged in the process after the first conductive plug is formed.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for forming the same. Background Art

[0002] Semiconductor memory is the foundation of information technology. As a candidate for the next generation of non-volatile semiconductor memory, Phase Change Random Access Memory (PCRAM) has received widespread attention due to its advantages such as high-speed reading, high erasable times, non-volatility, small component size, low power consumption, and resistance to strong vibration and radiation.

[0003] The bit line in the three-dimensional phase change memory is connected to the control circuit through the bit line contact (which can be called the first conductive plug). In order to reduce the difficulty of the etching process, a part of the word line contact will be formed at the same time in the process of forming the bit line contact, that is, the word line contact (which can be called the second conductive plug) is formed in two parts.

[0004] However, in the etching process for removing part of the bit line and part of the storage structure, damage will be caused to the already formed word line contacts. Summary of the invention

[0005] The embodiments of the present application provide a semiconductor device and a method for forming the same, which reduce damage to the second conductive plug, so as to at least partially solve the above-mentioned technical problems.

[0006] The present application provides a semiconductor device, comprising: a substrate; a control circuit layer located on the substrate; a first conductive plug located on the surface of the control circuit layer; a storage device layer located on the first conductive plug, the storage device layer comprising a first address line and a second address line that cross in different planes, the first address line being located on the surface of the first conductive plug; a second conductive plug located between the second address line and the control circuit layer, the two ends of the second conductive plug being in contact with the control circuit layer and the second address line respectively, the second conductive plug being an integral structure.

[0007] In some embodiments, the second conductive plug includes a first end and a second end opposite to each other, the first end is connected to the control circuit layer, the second end is connected to the second address line, and the second conductive plug has a first dimension in a direction parallel to the substrate surface, and the first dimension gradually increases from the first end to the second end.

[0008] In some embodiments, the second conductive plug has a second size in a direction perpendicular to the substrate surface, and a ratio of the second size to the first size of the first end is 5:1 to 8:1.

[0009] In some embodiments, it also includes: a first dielectric layer located on the surface of the control circuit layer, the first conductive plug is located in the first dielectric layer; a second dielectric layer located on the surface of the first dielectric layer, the storage device layer is located in the second dielectric layer, and the second conductive plug is located in the first dielectric layer and the second dielectric layer.

[0010] In some embodiments, the memory device layer further includes: a memory unit located between the first address line and the second address line; the first address line and the memory unit are located in the second dielectric layer, and the second address line is located on a surface of the second dielectric layer.

[0011] The present application also provides a method for forming a semiconductor device, comprising: providing a substrate; forming a control circuit layer on the substrate, the control circuit layer being located in a storage area and a peripheral area; forming a first conductive plug connected to the control circuit layer in the storage area; forming a first address line on a side of the first conductive plug away from the control circuit layer, the first address line being connected to the first conductive plug; forming a storage unit layer on the first address line and in the storage area; forming a second conductive plug connected to the control circuit layer in the peripheral area through an etching process and a deposition process; forming a second address line connected to the second conductive plug on a side of the second conductive plug away from the control circuit layer, the second address line crossing the first address line in a non-planar manner.

[0012] In some embodiments, a method for forming a first conductive plug connected to the control circuit layer in the storage area includes: forming a first dielectric layer on the surface of the control circuit layer; forming a first through hole in the first dielectric layer in the storage area to expose the control circuit layer; and forming the first conductive plug in the first through hole.

[0013] In some embodiments, the method of forming a memory cell layer on the first address line and in the memory area includes: forming an initial memory cell layer on the first address line; removing the initial memory cell layer in the peripheral area and forming a memory cell layer in the memory area.

[0014] In some embodiments, the method for forming a second conductive plug connected to the control circuit layer in the peripheral area includes: after forming the storage unit layer, forming a second dielectric layer in the peripheral area and on the surface of the first dielectric layer; performing an etching process on the second dielectric layer and the first dielectric layer in the peripheral area to form a second through hole exposing the control circuit layer in the peripheral area; and forming the second conductive plug in the second through hole.

[0015] In some embodiments, the method for forming the second address line includes: after forming the second conductive plug, forming a conductive layer on the surface of the second dielectric layer and the surface of the storage unit layer; etching the conductive layer to form a plurality of second address lines, wherein the second address lines are connected to the second conductive plug and cross the first address lines in an eccentric manner.

[0016] In the semiconductor device of the embodiment of the present application, since the first conductive plug is located between the control circuit layer and the first address line, and the second conductive plug is an integrated structure located between the second address line and the control circuit layer, a single etching process can be used to form the through hole of the second conductive plug, without the need to form part of the second conductive plug in the process of forming the first conductive plug. The present application omits the process of forming part of the second conductive plug in the process of forming the first conductive plug, so that the part of the second conductive plug can be prevented from being damaged in the process after the first conductive plug is formed.

[0017] Other features and advantages of the present application will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can obtain other drawings based on these drawings without creative work.

[0019] In order to more completely understand the present application and its beneficial effects, the following description will be given in conjunction with the accompanying drawings, wherein the same figure numbers represent the same parts in the following description.

[0020] Figure 1 is a schematic cross-sectional structural diagram of a semiconductor device provided by an embodiment;

[0021] Figure 2 is a schematic cross-sectional structure diagram of a semiconductor device provided in some embodiments of the present application;

[0022] Figure 3 yes Figure 2 A schematic top view of the structure of the first address line, the second address line, the first conductive plug and the second conductive plug;

[0023] Figure 4 is a schematic flow chart of a method for forming a semiconductor structure provided in some embodiments of the present application;

[0024] Figures 5 to 14 This application Figure 2 and Figure 3 A schematic diagram of the structure of a semiconductor structure during the formation process in an embodiment. DETAILED DESCRIPTION

[0025] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0026] See also Figure 1 , Figure 1 The present invention is a schematic diagram of the cross-sectional structure of a semiconductor device provided by an embodiment.

[0027] The semiconductor device comprises a first connection structure 1 and a second connection structure 2, wherein the first connection structure 1 is located between a control circuit layer 3 and a first address line 4, and the second connection structure 2 comprises a first sub-connection structure 201 and a second sub-connection structure 202, wherein one end of the first sub-connection structure 201 is connected to the control circuit layer 3, and the other end is connected to the second sub-connection structure 202, and the other end of the second sub-connection structure 202 is connected to the second address line 5. The first sub-connection structure 201 and the first connection structure 1 are arranged in the same layer and spaced apart.

[0028] Therefore, the first sub-connection structure 201 and the first connection structure 1 can be formed in the first dielectric layer 6 in the same process. After the first sub-connection structure 201 and the first connection structure 1 are formed, the structure in the peripheral area needs to be removed by an etching process, and then the second dielectric layer 7 is formed in the peripheral area, so that the second sub-connection structure 202 can be formed in the second dielectric layer 7. However, the structure of the first sub-connection structure 201 is easily damaged during the etching process.

[0029] Based on the above reasons, an embodiment of the present application provides a semiconductor device, which includes a substrate; a control circuit layer located on the substrate; a first conductive plug located on the surface of the control circuit layer; a storage device layer located on the first conductive plug, the storage device layer including a first address line and a second address line that cross each other in different planes, the first address line being located on the surface of the first conductive plug; and a second conductive plug located between the second address line and the control circuit layer, the two ends of the second conductive plug being in contact with the control circuit layer and the second address line respectively, and the second conductive plug being an integral structure.

[0030] Since the first conductive plug is located between the control circuit layer and the first address line, and the second conductive plug is an integrated structure located between the second address line and the control circuit layer, a single etching process can be used to form the through hole of the second conductive plug, without the need to form part of the second conductive plug in the process of forming the first conductive plug. Figure 1 The process of forming the first sub-connection structure in the process of forming the first connection structure is equivalent to omitting the process of forming part of the second conductive plug in the process of forming the first conductive plug, thereby avoiding damage to the part of the second conductive plug caused by the process after forming the first conductive plug.

[0031] The structure of the semiconductor device provided in the embodiments of the present application is described below with reference to the accompanying drawings.

[0032] See also Figure 2 and Figure 3 , Figure 2 is a schematic cross-sectional structure diagram of a semiconductor device provided in some embodiments of the present application, Figure 3 yes Figure 2 A schematic diagram of a top view of the first address line, the second address line, the first conductive plug and the second conductive plug.

[0033] The semiconductor device 100 includes a substrate 10, a control circuit layer 20, a first conductive plug 30, a memory device layer 40, and a second conductive plug 50. The control circuit layer 20 is located on the substrate 10, and the first conductive plug 30 is located on the surface of the control circuit layer 20. The memory device layer 40 is located on the first conductive plug 30, and the memory device layer 40 includes a first address line 41 and a second address line 42 that cross in different planes. The first address line 41 is located on the surface of the first conductive plug 30. The second conductive plug 50 is located between the second address line 42 and the control circuit layer 20, and the two ends of the second conductive plug 50 are in contact with the control circuit layer 20 and the second address line 42 respectively, and the second conductive plug 50 is an integral structure.

[0034] The second conductive plug 50 is an integrated structure, which means that the second conductive plug 50 is a whole and is formed in one piece, rather than being formed in upper and lower sections.

[0035] The substrate 10 may be a semiconductor substrate, for example, silicon (Si), germanium (Ge), SiGe substrate, silicon on insulator (SOI) or germanium on insulator (GOI), etc. In some embodiments, the semiconductor substrate may also be a substrate 10 including other element semiconductors or compound semiconductors, and may also be a stacked structure, such as Si / SiGe, etc.

[0036] The control circuit layer 20 may include a device structure (not shown) located on the substrate 10, an electrical interconnection structure 21 electrically connected to the device structure, and a third dielectric layer 22 located on the substrate 10. The device structure and the electrical interconnection structure 21 are located in the third dielectric layer 22.

[0037] The device structure may include structures such as transistors, capacitors, resistors, and inductors. The transistor may include a complementary metal oxide semiconductor (CMOS) transistor.

[0038] The electrical interconnection structure 21 may be located at a side of the device structure away from the substrate 10 . The electrical interconnection structure 21 may include at least one layer of metal interconnection structure. The material of the metal interconnection structure may include metal copper.

[0039] The third dielectric layer 22 is located on the substrate 10, the device structure and the electrical interconnection structure 21 are located in the third dielectric layer 22, and the surface of the electrical interconnection structure 21 may be exposed. The material of the third dielectric layer 22 may include an insulating material, such as at least one of oxide and nitride.

[0040] The first conductive plug 30 is electrically connected to at least one of the device structure and the electrical interconnection structure 21, that is, the first conductive plug 30 can be directly electrically connected to the device structure, or directly electrically connected to the electrical interconnection structure 21, or a part of the first conductive plug 30 can be electrically connected to the device structure, and another part of the first conductive plug 30 can be electrically connected to the electrical interconnection structure 21. Thus, the electrical connection between the first address line 41 and the device structure can be achieved, that is, the signal transmission of the first address line 41 by the control circuit layer 20 can be achieved.

[0041] In some embodiments, the first conductive plug 30 is an integral structure, which means that the first conductive plug 30 is a whole, formed in one piece, rather than being formed in upper and lower sections.

[0042] In some embodiments, the first conductive plug 30 may include a first conductive column and a first barrier layer (not shown), wherein the first conductive column is connected between the first address line 41 and the control circuit layer 20, and the first barrier layer is located on the sidewall surface of the first conductive column. For example, the first barrier layer may surround the sidewall surface of the first conductive column.

[0043] The second conductive plug 50 is electrically connected to at least one of the device structure and the electrical interconnection structure 21, that is, the second conductive plug 50 can be directly electrically connected to the device structure, or directly electrically connected to the electrical interconnection structure 21, or a part of the second conductive plug 50 can be electrically connected to the device structure, and another part of the second conductive plug 50 can be electrically connected to the electrical interconnection structure 21. Thus, the electrical connection between the second address line 42 and the device structure can be realized, that is, the signal transmission of the control circuit layer 20 to the second address line 42 can be realized. Moreover, the electrical connection between one second address line 42 and the control circuit layer 20 can be realized through one second conductive plug 50.

[0044] Since the first conductive plug 30 and the second conductive plug 50 are located at different positions and are both integral structures, the first conductive plug 30 and the second conductive plug 50 are formed separately, and part of the second conductive plug 50 is not formed in the process of forming the first conductive plug 30, which can avoid damage to the second conductive plug 50 caused by the process after forming the first conductive plug 30.

[0045] In some embodiments, the second conductive plug 50 may include a second conductive pillar and a second barrier layer (not shown), the second conductive pillar being connected between the second address line 42 and the control circuit layer 20, and the second barrier layer being located on the sidewall surface of the second conductive pillar. For example, the second barrier layer may surround the sidewall surface of the second conductive pillar.

[0046] The materials of the first conductive pillar and the second conductive pillar may include tungsten, and the materials of the first barrier layer and the second barrier layer may each include an insulating material, such as at least one of an oxide and a nitride.

[0047] If the second conductive plug 50 is damaged by an external process, the second barrier layer is easily damaged, causing the copper in the metal interconnect structure to diffuse into the second barrier layer, thereby causing leakage between adjacent second conductive plugs 50. The semiconductor device 100 provided in the embodiment of the present application omits the process of forming part of the second conductive plug 50 in the process of forming the first conductive plug 30 in terms of process architecture, so that the damage to the stability of the second barrier layer of the second conductive plug 50 caused by the external process can be effectively controlled, thereby reducing the leakage between adjacent second conductive plugs 50.

[0048] In some embodiments, the second conductive plug 50 includes a first end 51 and a second end 52 opposite to each other, the first end 51 is connected to the control circuit layer 20, and the second end 52 is connected to the second address line 42. The second conductive plug 50 has a first size W1 in a direction parallel to the surface of the substrate 10 (first direction X), and the first size W1 gradually increases from the first end 51 to the second end 52, that is, Figure 2 The first size W1 of the second conductive plug 50 gradually increases from bottom to top, and the first size W1 of the first end 51 is smaller than the first size W1 of the second end 52. Therefore, the through hole of the second conductive plug 50 can be formed by a single etching process.

[0049] In some embodiments, the first conductive plug 30 includes a third end 31 and a fourth end 32 opposite to each other, the third end 31 is connected to the control circuit layer 20, and the fourth end 32 is connected to the first address line 41. The first conductive plug 30 has a third size W3 in a direction parallel to the surface of the substrate 10 (the first direction X), and the third size W3 gradually increases from the third end 31 to the fourth end 32, that is, Figure 2 The third dimension W3 of the first conductive plug 30 gradually increases from bottom to top, and the third dimension W3 of the third end 31 is smaller than the third dimension W3 of the fourth end 32. Therefore, the through hole of the first conductive plug 30 can be formed by a single etching process.

[0050] In some embodiments, the third size W3 of the third end 31 is different from the first size W1 of the first end 51 , that is, the bottom area of ​​the first conductive plug 30 is different from the bottom area of ​​the second conductive plug 50 .

[0051] The semiconductor device 100 may further include a first dielectric layer 60 and a second dielectric layer 70, wherein the first dielectric layer 60 is located on the surface of the control circuit layer 20, and the first conductive plug 30 is located in the first dielectric layer 60; the second dielectric layer 70 is located on the surface of the first dielectric layer 60, the storage device layer 40 is located in the second dielectric layer 70, and the second conductive plug 50 is located in the first dielectric layer 60 and the second dielectric layer 70.

[0052] In some embodiments, the first conductive plug 30 may penetrate the first dielectric layer 60 along a direction perpendicular to the substrate 10 (third direction Z), and the second conductive plug 50 may penetrate the second dielectric layer 70 and the first dielectric layer 60 along a direction perpendicular to the substrate 10 (third direction Z). The materials of the first dielectric layer 60 and the second dielectric layer 70 may be the same, and both may be insulating materials.

[0053] The memory device layer 40 may further include a memory cell 43 and an isolation layer located between adjacent memory cells 43, wherein the memory cell 43 is located between the first address line 41 and the second address line 42 and at the intersection of the first address line 41 and the second address line 42. The first address line 41 and the memory cell 43 are located in the second dielectric layer 70, and the upper surface of the memory cell 43 is exposed, and the second address line 42 is located on the surface of the second dielectric layer 70 and connected to the upper surface of the memory cell 43. It can also be said that the first address line 41 and the memory cell 43 are both arranged adjacent to the second dielectric layer 70.

[0054] In some embodiments, the semiconductor device 100 may include a plurality of storage areas 101 disposed at intervals, and a peripheral area 102 located between adjacent storage areas 101. The storage unit 43, the first address line 41 and the first conductive plug 30 are located in the storage area 101, and the second dielectric layer 70 and the second conductive plug 50 are located in the peripheral area 102.

[0055] Taking phase change memory as an example, the memory cell 43 may include a first electrode, a gating layer, a second electrode, a phase change memory layer and a third electrode. The materials of the first electrode, the second electrode and the third electrode may be the same and may include carbon. The material of the gating layer may include Znx Te y ,Ge x Te y , Nb x O y 、Si x As y 、As x Te y Etc. The material of the phase change memory layer may include, for example, a chalcogenide-based material including any one of four elements of oxygen (O), sulfur (S), selenium (Se), and tellurium (Te) forming Group VIA of the periodic table.

[0056] like Figure 2 As shown, taking the selection-only memory as an example, the memory cell 43 may include a first electrode 431 , a gate layer 432 and a second electrode 433 .

[0057] For the selective memory only, the thickness of its storage unit 43 is greatly reduced compared with the thickness of the storage unit 43 in the phase change memory, so the size of the second conductive plug 50 in the direction perpendicular to the surface of the substrate 10 (the third direction Z) is greatly reduced, so that the aspect ratio of the second conductive plug 50 is reduced, and the controllability of the etching process for forming the second conductive plug 50 is increased, and the second conductive plug 50 can be formed in one piece with only one etching process.

[0058] In some embodiments, the second conductive plug 50 has a second size W2 in a direction perpendicular to the surface of the substrate 10 (third direction Z), and a ratio of the second size W2 to the first size W1 of the first end 51 is 5:1-8:1.

[0059] Accordingly, the present invention also provides a method for forming a semiconductor device. Figure 4 , Figure 4 1 is a schematic flow chart of a method for forming a semiconductor structure provided in some embodiments of the present application, the method comprising:

[0060] Step S1, providing a substrate;

[0061] Step S2, forming a control circuit layer on the substrate, wherein the control circuit layer is located in the storage area and the peripheral area;

[0062] Step S3, forming a first conductive plug connected to the control circuit layer in the storage area;

[0063] Step S4, forming a first address line on a side of the first conductive plug away from the control circuit layer, wherein the first address line is connected to the first conductive plug;

[0064] Step S5, forming a storage unit layer on the first address line and in the storage area;

[0065] Step S6, forming a second conductive plug connected to the control circuit layer in the peripheral area through an etching process and a deposition process;

[0066] Step S7: forming a second address line connected to the second conductive plug on a side of the second conductive plug away from the control circuit layer, wherein the second address line crosses the first address line in a non-planar manner.

[0067] In the method for forming the semiconductor device, the second conductive plug is not formed during the process of forming the first conductive plug, and the first conductive plug and the second conductive plug are formed separately, so the process of forming the storage device layer will not affect the second conductive plug.

[0068] The following combination Figures 5 to 14 A method for forming this semiconductor structure will be described. Figures 5 to 14 This application Figure 2 and Figure 3 A schematic diagram of the structure of a semiconductor structure during the formation process in an embodiment.

[0069] Step S1: forming a substrate 10. Figure 5 .

[0070] The substrate 10 may be a semiconductor substrate, for example, silicon (Si), germanium (Ge), SiGe substrate, silicon on insulator (SOI) or germanium on insulator (GOI), etc. In some embodiments, the semiconductor substrate may also be a substrate 10 including other element semiconductors or compound semiconductors, and may also be a stacked structure, such as Si / SiGe, etc.

[0071] Step S2: forming a control circuit layer 20 on the substrate 10, wherein the control circuit layer 20 is located in the storage area 101 and the peripheral area 102. Figure 5 .

[0072] In some embodiments, the substrate 10 may include a storage area 101 and a peripheral area 102. Specifically, a plurality of the storage areas 101 are arranged at intervals, and the peripheral area 102 is located between two adjacent storage areas 101.

[0073] The control circuit layer 20 may include a device structure (not shown) located on the substrate 10, an electrical interconnection structure 21 electrically connected to the device structure, and a third dielectric layer 22 located on the substrate 10. The device structure and the electrical interconnection structure 21 are located in the third dielectric layer 22. The first conductive plug 30 is electrically connected to one or both of the device structure and the electrical interconnection structure 21.

[0074] The method for forming the control circuit layer 20 includes: forming a first sub-dielectric layer (not shown) on the substrate 10; forming a device structure on the first sub-dielectric layer; forming a second sub-dielectric layer on the device structure, the second sub-dielectric layer and the first sub-dielectric layer forming a third dielectric layer 22; and forming an electrical interconnection structure 21 in the second sub-dielectric layer.

[0075] It is understood that the electrical interconnect structure 21 may include at least one layer of metal interconnect structure. Figure 5 Only a portion of the metal interconnect structure of the uppermost layer of the electrical interconnect structure 21 is shown.

[0076] Step S3: forming a first conductive plug 30 connected to the control circuit layer 20 in the storage area 101. Figure 5 and Figure 6 , Figure 6 yes Figure 5 FIG. 1 is a schematic top view of the first conductive plug 30. FIG.

[0077] Step S3 may include: forming a first dielectric layer 60 on the surface of the control circuit layer 20 ; forming a first through hole 33 exposing the control circuit layer 20 in the first dielectric layer 60 in the storage area 101 ; and forming the first conductive plug 30 in the first through hole 33 .

[0078] The process of forming the first dielectric layer 60 includes: forming a first initial dielectric layer on the surface of the control circuit layer 20 and the first conductive plug 30 , and planarizing the first initial dielectric layer until the first conductive plug 30 is exposed.

[0079] The formation process of the first initial dielectric layer includes chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) such as thermal oxidation, evaporation, sputtering, etc. The process of planarizing the first initial dielectric layer includes a chemical mechanical polishing process or an etching back process.

[0080] The process of forming the first through hole 33 includes: forming a patterned mask layer on the first dielectric layer 60 ; and performing an etching process on the first dielectric layer 60 using the patterned mask layer as a mask to form the first through hole 33 .

[0081] The process of forming the patterned mask layer includes a photolithography process, and the patterned mask layer includes at least silicon nitride; the etching process performed on the first dielectric layer 60 includes an anisotropic dry etching process.

[0082] The method for forming the first conductive plug 30 in the first through hole 33 includes: forming a first barrier layer (not shown) in the first through hole 33; etching the bottom of the first barrier layer to form a first opening exposing the control circuit layer 20; forming a first conductive column (not shown) in the first opening and on the side wall surface of the first barrier layer, and the first conductive column is connected to the control circuit layer 20.

[0083] The method for forming the first conductive pillar includes: depositing a first conductive material in the first through hole 33 and on the first dielectric layer 60 ; and planarizing the first conductive material until the first dielectric layer 60 is exposed.

[0084] The process of depositing the first conductive material includes chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) such as thermal oxidation, evaporation, sputtering, etc. The process of planarizing the first conductive material includes a chemical mechanical polishing process or an etch-back process.

[0085] In some embodiments, Figure 6 As shown, there are a plurality of first conductive plugs 30 , which are arranged at intervals along a first direction X parallel to the substrate 10 .

[0086] It should be noted that, for the sake of simplicity, the cross-sectional view of the present application only illustrates one first conductive plug 30 .

[0087] Step S4: forming a first address line 41 on a side of the first conductive plug 30 away from the control circuit layer 20, wherein the first address line 41 is connected to the first conductive plug 30. Figure 7 to Figure 12 .

[0088] Step S5: forming a storage unit layer 43b on the first address line 41 and in the storage area 101. Figure 7 to Figure 12 .

[0089] In some embodiments, step S4 and step S5 are performed in the same process, that is, the memory cell layer and the first address line are performed in the same process, as follows.

[0090] See also Figure 7 and Figure 8 , forming a first initial address line 41a and an initial storage unit layer 43a on the first dielectric layer 60. Figure 8 yes Figure 7FIG. 4 is a schematic diagram of a top view of the structure of the first initial address line 41 a.

[0091] The method for forming the first initial address line 41a and the initial storage unit layer 43a includes: forming a first address line material layer on the first dielectric layer 60; forming a storage material layer on the first address line material layer; etching the storage material layer and the first address line material layer to form the first initial address line 41a and the initial storage unit layer 43a.

[0092] The process of forming the first address line material layer and the storage material layer may include any of the above-mentioned deposition processes. The process of etching the storage material layer and the first address line material layer includes a self-aligned double patterning process (SADP), so that the patterns of the first initial address line 41a and the initial storage unit layer 43a overlap each other, and are Figure 6 Ring shape shown.

[0093] See also Fig. 9 and Fig.10 , removing the initial memory cell layer 43a located in the peripheral area 102, as well as the first initial address line 41a and both ends of the initial memory cell layer 43a. Fig.10 yes Fig. 9 FIG. 8 is a schematic top view of the structure of the patterned mask layer 80 .

[0094] The method for removing the initial memory cell layer 43a located in the peripheral area 102, and the first initial address line 41a and both ends of the initial memory cell layer 43a includes: forming a patterned mask layer 80 (such as Figure 7 As shown), the opening of the patterned mask layer 80 exposes the peripheral area 102 and both ends of the first initial address line 41a and the initial storage unit layer 43a; the first initial address line 41a and the initial storage unit layer 43a are etched using the patterned mask layer 80 as a mask to form the first address line 41 and the storage unit layer 43b.

[0095] Among them, a ring-shaped first initial address line 41a forms two first address lines 41 arranged at intervals (as shown below): Fig.12 As shown in FIG. 4 , a ring-shaped initial memory cell layer 43a forms two memory cell layers 43b arranged at intervals. A plurality of first address lines 41 are connected to a plurality of first conductive plugs 30 in a one-to-one correspondence, and a plurality of memory cell layers 43b overlap with a plurality of first address lines 41 in an upper and lower manner.

[0096] In one embodiment, during the process of forming the first conductive plug 30, a conductive plug (with the same structure as the first conductive plug 30) is also formed in the peripheral area 102, and then another conductive plug is formed on the conductive plug to connect the second address line 42 and the control circuit layer 20. Therefore, after forming the first conductive plug 30, Fig. 9 The etching process (forming the first address line 41 and removing the structure of the peripheral area 102) can easily damage the conductive plug formed in the peripheral area 102. In the process of forming the first conductive plug 30, the embodiment of the present application does not form a part of the second conductive plug 50 in advance in the peripheral area 102, but Fig. 9 The integrated second conductive plug 50 is formed after the etching process, thereby avoiding damage to the second conductive plug 50 by the etching process.

[0097] Step S6: A second conductive plug 50 connected to the control circuit layer 20 is formed in the peripheral area 102 through an etching process and a deposition process. Figure 11 to Figure 14 , 12 is Fig.11 A schematic diagram of a top view of the first address line 41 and the first conductive plug 30, Fig.14 yes Fig.13 FIG. 4 is a schematic top view of the first address line 41 , the first conductive plug 30 , and the second conductive plug 50 .

[0098] Step S6 may include: after forming the storage unit layer 43b, forming a second dielectric layer 70 located on the first dielectric layer 60 in the peripheral area 102; performing an etching process on the second dielectric layer 70 and the first dielectric layer 60 to form a second through hole 53 exposing the control circuit layer 20 in the peripheral area 102; and forming the second conductive plug 50 in the second through hole 53.

[0099] See also Fig.11 and Fig.12 The method for forming the second dielectric layer 70 includes: removing the patterned mask layer 80; forming a second initial dielectric layer on the storage unit layer 43b and the first dielectric layer 60; and planarizing the second initial dielectric layer until the storage unit layer 43b is exposed.

[0100] See also Fig.13 and Fig.14 The process of forming the second through hole 53 includes anisotropic dry etching.

[0101] The method for forming the second conductive plug 50 in the second through hole 53 includes: forming a second barrier layer (not shown) in the second through hole 53; etching the bottom of the second barrier layer to form a second opening exposing the control circuit layer 20; forming a second conductive column (not shown) in the second opening and on the side wall surface of the second barrier layer, and the second conductive column is connected to the control circuit layer 20.

[0102] The method for forming the second conductive pillar includes: depositing a second conductive material in the second through hole 53 and on the second dielectric layer 70 ; and planarizing the second conductive material until the second dielectric layer 70 is exposed.

[0103] The process of depositing the second conductive material includes chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) such as thermal oxidation, evaporation, sputtering, etc. The process of planarizing the second conductive material includes a chemical mechanical polishing process or an etch-back process.

[0104] In some embodiments, the second conductive plugs 50 may be arranged along the second direction Y at intervals.

[0105] Step S7: forming a second address line 42 connected to the second conductive plug 50 on a side of the second conductive plug 50 away from the control circuit layer 20, wherein the second address line 42 crosses the first address line 41 in a non-planar manner. Figure 2 and Figure 3 .

[0106] The method for forming the second address line 42 includes: after forming the second conductive plug 50, forming a conductive layer on the surface of the second dielectric layer 70 and the surface of the storage unit layer 43b; etching the conductive layer to form a plurality of second address lines 42, wherein the second address line 42 is connected to the second conductive plug 50 and crosses the first address line 41 in a different plane.

[0107] The method for forming a semiconductor device may further include: forming the memory cell layer 43 b to be spaced apart along the second direction Y.

[0108] In some embodiments, the etching process of the memory cell layer 43 b and the etching process of the conductive layer may be performed using a self-aligned double patterning process.

[0109] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0110] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0111] The embodiments, implementation methods and related technical features of the present application can be combined and replaced with each other without conflict.

[0112] The above are only preferred embodiments of the present application and do not constitute any form of limitation to the present application. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A semiconductor device, characterized in that: include: substrate; A control circuit layer, located on the substrate; A first conductive plug located on the surface of the control circuit layer; A memory device layer located on the first conductive plug, the memory device layer comprising a first address line and a second address line that cross each other in different planes, the first address line being located on a surface of the first conductive plug; A second conductive plug is located between the second address line and the control circuit layer, two ends of the second conductive plug are in contact with the control circuit layer and the second address line respectively, and the second conductive plug is an integrated structure.

2. The semiconductor device according to claim 1, wherein: The second conductive plug includes a first end and a second end opposite to each other, the first end is connected to the control circuit layer, the second end is connected to the second address line, and the second conductive plug has a first size in a direction parallel to the substrate surface, and the first size gradually increases from the first end to the second end.

3. The semiconductor device according to claim 2, characterized in that The second conductive plug has a second size in a direction perpendicular to the substrate surface, and a ratio of the second size to the first size of the first end is 5:1 to 8:

1.

4. The semiconductor device according to claim 1, wherein: Also includes: a first dielectric layer located on the surface of the control circuit layer, wherein the first conductive plug is located in the first dielectric layer; A second dielectric layer is located on the surface of the first dielectric layer, the storage device layer is located in the second dielectric layer, and the second conductive plug is located in the first dielectric layer and the second dielectric layer.

5. The semiconductor device according to claim 4, characterized in that The memory device layer further includes: a memory cell located between the first address line and the second address line; The first address line and the storage unit are located in the second dielectric layer, and the second address line is located on the surface of the second dielectric layer.

6. A method for forming a semiconductor device, characterized in that: include: providing a substrate; forming a control circuit layer on the substrate, wherein the control circuit layer is located in the storage area and the peripheral area; forming a first conductive plug connected to the control circuit layer in the storage area; forming a first address line on a side of the first conductive plug away from the control circuit layer, wherein the first address line is connected to the first conductive plug; forming a storage unit layer on the first address line and in the storage area; Forming a second conductive plug connected to the control circuit layer in the peripheral area through an etching process and a deposition process; A second address line connected to the second conductive plug is formed on a side of the second conductive plug away from the control circuit layer, and the second address line crosses the first address line in a non-planar manner.

7. The method for forming a semiconductor device according to claim 6, wherein: The method of forming a first conductive plug connected to the control circuit layer in the storage area includes: forming a first dielectric layer on the surface of the control circuit layer; forming a first through hole in the first dielectric layer in the storage area to expose the control circuit layer; The first conductive plug is formed in the first through hole.

8. The method for forming a semiconductor device according to claim 7, wherein: The method of forming a storage unit layer on the first address line and in the storage area comprises: forming an initial memory cell layer on the first address line; An initial memory cell layer located in the peripheral area is removed to form a memory cell layer located in the memory area.

9. The method for forming a semiconductor device according to claim 8, wherein: The method of forming a second conductive plug connected to the control circuit layer in the peripheral area includes: After forming the storage unit layer, forming a second dielectric layer in the peripheral region and on the surface of the first dielectric layer; Performing an etching process on the second dielectric layer and the first dielectric layer in the peripheral area to form a second through hole exposing the control circuit layer in the peripheral area; The second conductive plug is formed in the second through hole.

10. The method for forming a semiconductor device according to claim 9, wherein: The method of forming the second address line includes: After forming the second conductive plug, forming a conductive layer on the surface of the second dielectric layer and the surface of the storage unit layer; The conductive layer is etched to form a plurality of second address lines, wherein the second address lines are connected to the second conductive plugs and cross the first address lines at different planes.

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