Method for manufacturing semiconductor device

Abstract

The present application provides a method for manufacturing a semiconductor device, the method comprising: forming a body region and a source region in a semiconductor layer, the semiconductor layer comprising a first surface and a second surface opposite to each other; forming a first trench in the semiconductor layer; forming a second trench in the first trench, the lateral dimension of the second trench being smaller than the lateral dimension of the first trench; forming a buried layer in the semiconductor layer via the second trench, wherein the buried layer is adjacent to the bottom of a trench gate, and the lateral dimension of the buried layer is smaller than the lateral dimension of the trench gate. The method for manufacturing a semiconductor device of the present application forms a buried layer having a lateral dimension smaller than the lateral dimension of the trench at the bottom of the first trench in a self-aligned manner, which not only reduces the obstruction of the buried layer to the flow of carriers, but also reduces the requirement for the lateral dimension of the trench gate.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, and more specifically, to a method for manufacturing a semiconductor device with a trench gate structure. Background Art

[0002] In power semiconductor devices, the electric field of a vertical transistor with a trench gate is concentrated at the corner of the bottom of the trench gate, resulting in poor withstand voltage and reliability. In order to effectively disperse the electric field concentrated at the corner of the bottom of the trench gate, the industry has adopted many methods, among which the more traditional method is to form a buried layer under the bottom of the trench gate to protect the bottom of the trench gate.

[0003] However, in order to better protect the bottom of the trench gate, the lateral size of the buried layer needs to be larger than the lateral size of the trench gate. A wider buried layer will hinder the flow direction of current, thereby causing an increase in on-resistance. Summary of the invention

[0004] In view of the above problems, the purpose of the present application is to provide a method for manufacturing a semiconductor device, which forms a buried layer with a lateral dimension smaller than the lateral dimension of the trench at the bottom of the first trench in a self-aligned manner, thereby not only reducing the obstruction of the buried layer to the flow of carriers, but also reducing the requirements for the lateral dimension of the trench gate.

[0005] According to one aspect of an embodiment of the present application, a method for manufacturing a semiconductor device is provided, comprising: forming a body region and a source region in a semiconductor layer, the semiconductor layer comprising a first surface and a second surface opposite to each other, the body region and the source region being located on a side of the semiconductor layer close to the first surface; forming a first trench in the semiconductor layer; forming a second trench in the first trench, the lateral dimension of the second trench being smaller than the lateral dimension of the first trench; forming a buried layer in the semiconductor layer via the second trench, wherein the buried layer is adjacent to a bottom of the trench gate, and the lateral dimension of the buried layer is smaller than the lateral dimension of the trench gate.

[0006] Optionally, the step of forming the second trench in the first trench includes: forming a blocking layer on a sidewall of the first trench, wherein the blocking layer forms the second trench along the first trench.

[0007] Optionally, the step of forming a blocking layer on the side wall of the first trench includes: forming a mask layer on the first surface of the semiconductor layer; forming a first trench in the semiconductor layer via the mask layer; forming a blocking layer on the upper surface of the first trench and the mask layer, the blocking layer forming a second trench along the first trench; and removing the blocking layer on the upper surface of the mask layer and the blocking layer at the bottom of the second trench.

[0008] Optionally, an ion implantation process is used to form a buried layer in the semiconductor layer via the second trench, and the energy of an energy beam of the ion implantation process is less than 1 MeV.

[0009] Optionally, a lateral dimension of the buried layer is less than 1 um.

[0010] Optionally, a depth of the bottom of the buried layer in the semiconductor layer from the first surface to the second surface is less than or equal to a depth of the bottom of the doped region in the semiconductor layer from the first surface to the second surface.

[0011] Optionally, after the step of forming a buried layer in the semiconductor layer via the second trench, the method further includes: removing the blocking layer and the mask layer; forming a trench gate in the first trench; forming an interlayer dielectric layer and a first conductive layer on the first surface of the semiconductor layer, wherein the interlayer dielectric layer isolates the trench gate and the first conductive layer; and forming a second conductive layer on the second surface of the semiconductor layer.

[0012] Optionally, the material of the blocking layer includes polysilicon, oxide and nitride.

[0013] Optionally, the step of forming a body region and a source region in the semiconductor layer further includes: forming a body contact region and a doped region in the semiconductor layer.

[0014] Optionally, the semiconductor layer includes a SiC semiconductor layer or a Si semiconductor layer.

[0015] The technical solution of this application has the following beneficial effects:

[0016] The manufacturing method of the semiconductor device provided by the present application, compared with the semiconductor device in which the buried layer is formed first and then the groove is formed, the lateral dimension of the first groove in the semiconductor device of the present application is smaller, so that more grooves can be formed in the same area. In the epitaxial layer at the bottom of the trench gate of the semiconductor device, a buried layer is formed, and the lateral dimension of the buried layer is smaller than the lateral dimension of the trench gate, so the buried layer will not cause too much obstruction to the circuit path. Compared with the device in which the lateral dimension of the buried layer is larger than the lateral dimension of the trench gate, the on-resistance of the semiconductor device of the present application is smaller.

[0017] The present application provides a method for manufacturing a semiconductor device. In the manufacturing method, a first trench is first formed, and then a shielding layer is formed on the sidewalls in the first trench. The lateral dimension of the first trench is reduced via the shielding layer to form a second trench, and then ion implantation is performed via the second trench to form a buried layer. The buried layer formed by the aforementioned self-alignment method can certainly achieve the purpose of having a lateral dimension smaller than the lateral dimension of the first trench, and at the same time, there is no need to additionally expand the lateral dimension of the first trench, thereby achieving the purpose of forming more transistors or channels in the same area.

[0018] Furthermore, for some existing semiconductor devices, the manufacturing method of the present application can be compatible and achieve a buried layer with a smaller lateral size without changing the size of the device, thereby reducing the barrier of the buried layer to the flow of carriers and thereby reducing the on-resistance of the device.

[0019] Furthermore, the lateral dimension of the buried layer is smaller than the lateral dimension of the first trench, and the body region and the source region in the semiconductor device can be arranged on both sides of the trench gate and connected to the side walls of the trench gate, so that both sides of the trench gate can be used as conductive channels, reducing the resistance of the device in the on state.

[0020] Furthermore, doping regions may be provided on both sides of the trench gate, thereby improving the problem of electric field concentration at the corners of the trench gate and increasing the voltage resistance at the corners of the trench gate. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present application, rather than limiting the present application.

[0022] Figure 1 A schematic cross-sectional structure diagram of a semiconductor device according to an embodiment of the present application is shown;

[0023] Figure 2 A flow chart showing a method for manufacturing a semiconductor device according to an embodiment of the present application;

[0024] Figure 3a to Figure 3g Schematic cross-sectional views of various stages in a method for manufacturing a semiconductor device according to an embodiment of the present application are shown. DETAILED DESCRIPTION

[0025] The present application will be described in more detail below with reference to the accompanying drawings. In each of the drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the various parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown. For the sake of simplicity, the semiconductor structure obtained after several steps can be described in one figure.

[0026] It should be understood that when describing the structure of a device, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may mean that it is directly on the other layer or another region, or that other layers or regions are included between it and the other layer or another region. Furthermore, if the device is turned over, the layer or a region will be "below" or "beneath" another layer or another region.

[0027] If the purpose is to describe the situation of being directly on another layer or another area, this article will use expressions such as "directly on..." or "on... and adjacent to...".

[0028] The power device generally includes an active component region, an edge termination region, and a crack-stop or shielding region. The active component region includes an active component array. The present application relates to an active component structure. The size of the active component may vary depending on product requirements, and there may be a body region between active components in the active component region.

[0029] Many specific details of the present application are described below, such as device structure, materials, dimensions, processing technology and techniques, so as to make the present application more clearly understood. However, as those skilled in the art will appreciate, the present application may be implemented without following these specific details.

[0030] Figure 1 A schematic cross-sectional structure diagram of a semiconductor device according to an embodiment of the present application is shown.

[0031] like Figure 1 As shown, the semiconductor device of the present application includes a semiconductor layer 100, a plurality of trench gates 150, an interlayer dielectric layer 170, a first conductive layer 181, and a second conductive layer 182. The semiconductor layer 100 has a first surface and a second surface opposite to each other, the first conductive layer 181 is located on the first surface, and the second conductive layer 182 is located on the second surface. The semiconductor layer 100 includes a plurality of trenches, which extend from the first surface to the second surface into the semiconductor layer 100.

[0032] The semiconductor layer is, for example, a Si, SiC, GaN, Ga2O3, Al2O3 substrate or a stacked structure consisting of a substrate and an epitaxial layer. However, the embodiments of the present application are not limited thereto, and those skilled in the art can make other settings for the material and number of layers of the semiconductor layer as needed, such as other wide bandgap semiconductor materials.

[0033] In the present application, the semiconductor layer 100 includes, for example, a substrate 110, an epitaxial layer 120, a body region 131, a source region 160, a body contact region 132, a doped region 141, and a buried layer 142. Specifically, the epitaxial layer 120 is located above the substrate 110, a trench extends from a first surface to a second surface of the semiconductor layer 100 into the epitaxial layer 120, and a plurality of trench gates 150 are located in corresponding trenches in the semiconductor layer 100. The source region 160 is located on both sides of the trench gate 150 and extends from the first surface to the second surface of the semiconductor layer 100, and the source region 160 is adjacent to the sidewall of the trench gate 150; the body region 131 is adjacent to the lower surface of the source region 160 and the sidewall of the trench gate 150, and at least part of the epitaxial layer 120 is located between the body region 131 and the second surface of the semiconductor layer 100; the body contact region 132 is located on the side of the source region 160 away from the trench gate 150, and the sidewall of the body contact region 132 is adjacent to the source region 160, and the lower surface is adjacent to the upper surface of the body region 131. Optionally, the source region 160 and the body contact region 132 can be adjacent, or can be adjacent. The doped region 141 is located below the body region 131, and the upper surface of the doped region 141 is adjacent to the lower surface of the body region 131, while the lateral dimension of the doped region 141 is smaller than the lateral dimension of the body region 131, the doped region 141 is not adjacent to the trench gate 150, and at least part of the epitaxial layer 120 is located between the doped region 141 and the trench gate 150; the buried layer 142 is located below the trench gate 150, and the upper surface of the buried layer 142 is adjacent to the lower surface of the trench gate 150, the lateral dimension of the buried layer 142 is smaller than the lateral dimension of the trench gate 150, and the bottom corner of the trench gate 150 is not surrounded by the buried layer 142.

[0034] The trench gate 150 includes a gate dielectric layer 151 and a gate conductor 152. The gate dielectric layer 151 covers the inner surface of the trench, and the gate conductor 152 is located in the trench. The gate dielectric layer 151 is located between the semiconductor layer 100 and the gate conductor 152, and is used to separate the semiconductor layer 100 from the gate conductor 152. The width direction of the trench gate 150 is a first direction, such as the X-axis direction, the depth direction is a second direction, such as the Z-axis direction, and the length direction is a third direction, such as the Y-axis direction. Optionally, the first direction, the second direction, and the third direction are perpendicular to each other.

[0035] In this embodiment, Figure 1The trench gate 150 in the semiconductor device shown is, for example, a deep trench structure, that is, the depth of the trench gate 150 is greater than the width. The depth of the bottom surface of the doped region 141 from the first surface to the second surface of the semiconductor layer 100 is greater than the depth of the bottom of the trench gate 150 from the first surface to the second surface of the semiconductor layer 100. The depth of the bottom surface of the buried layer 142 from the first surface to the second surface of the semiconductor layer 100 is greater than the depth of the bottom of the trench gate 150 from the first surface to the second surface of the semiconductor layer 100, and is less than or equal to the depth of the bottom surface of the doped region 141 from the first surface to the second surface of the semiconductor layer 100.

[0036] The trench gate 150 , the buried layer 142 , the source region 160 , the body region 131 , the body contact region 132 , and the doped region 141 all extend along the third direction.

[0037] The interlayer dielectric layer 170 is located on the first surface of the semiconductor layer 100 and covers the upper surface of the trench gate 150. The first conductive layer 181 serves as a source electrode, covers the first surface of the semiconductor layer 100 and the interlayer dielectric layer 170, and is adjacent to at least a portion of the upper surface of the source region 160. The substrate 110 serves as a drain region, and the second conductive layer 182 serves as a drain electrode, and the second conductive layer 182 covers the lower surface of the substrate 110.

[0038] In this embodiment, along the first direction, a plurality of trench gates 150 are arranged at intervals, and the body region 131 and the source region 160 are located between adjacent trench gates 150 .

[0039] In this embodiment, the source region 160, the epitaxial layer 120 and the substrate 110 are of the first conductivity type, the buried layer 142, the doped region 141, the body region 131 and the body contact region 132 are of the second conductivity type, and the doping concentration of the body contact region 132 is greater than the doping concentration of the body region 131. The first conductivity type is opposite to the second conductivity type. The first conductivity type is one of the P type and the N type, and the second conductivity type is the other of the P type and the N type.

[0040] The semiconductor device of this embodiment can be used as a metal-oxide-semiconductor field-effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET), and can also be used as an insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, IGBT), for example, a drain contact region is set on the second surface 102 of the semiconductor layer, and the conductivity type of the drain contact region is set to the first conductivity type or the second conductivity type. However, the embodiment of the present application is not limited to this, and those skilled in the art can perform other settings on the conductivity type of each region in the semiconductor layer as needed to use the semiconductor device as a MOSFET or an IGBT.

[0041] In this embodiment, when the device is turned on, the body region 131 and the portion adjacent to the side wall of the trench gate 150 are inverted to form a channel, and carriers flow in from the first conductive layer 181 , then flow through the source region 160 and the channel to the epitaxial layer 120 , and finally flow out from the second conductive layer 182 .

[0042] In the semiconductor device of the present application, compared with a semiconductor device in which a buried layer is formed first and then a trench is formed, the lateral size of the trench of the present application can be reduced, so that more channels can be formed in the same area. In the epitaxial layer at the bottom of the trench gate of the semiconductor device, a buried layer is formed, and the lateral size of the buried layer is smaller than the lateral size of the trench gate, so the buried layer will not cause too much obstruction to the circuit path. Compared with a device in which the lateral size of the buried layer is larger than the lateral size of the trench gate, the on-resistance of the semiconductor device of the present application is smaller.

[0043] Figure 2 A flow chart showing a method for manufacturing a semiconductor device according to an embodiment of the present application; Figure 3a to Figure 3g The cross-sectional schematic diagrams of various stages in the method for manufacturing a semiconductor device according to an embodiment of the present application are shown. Figure 2 , Figure 3a to Figure 3g The manufacturing method of the semiconductor device of the present application is described in detail.

[0044] Step S201: forming an epitaxial layer on a substrate by using an epitaxial process, and sequentially forming a doped region, a body region, a source region and a body contact region in the epitaxial layer by using an ion implantation process.

[0045] In this step, an epitaxial layer 120 is formed on the substrate 110 by an epitaxial process, and the thickness of the epitaxial layer 120 is greater than the thickness of the substrate 110. Since the epitaxial layer 120 is formed by the epitaxial process, the epitaxial layer 120 has the same lattice orientation as the substrate 110.

[0046] The epitaxial layer 120 and the substrate 110 form a semiconductor layer 100 .

[0047] Furthermore, an ion implantation process is used to sequentially form a doped region 141, a body region 131, a source region 160 and a body contact region 132 in the epitaxial layer 120, such as Figure 3a Specifically, since the depth of the doped region 141 in the epitaxial layer 120 is greater than the depth of the body region 131 in the epitaxial layer 120, the ion implantation energy when forming the doped region 141 is greater than the ion implantation energy when forming the body region 131. In addition, the source region 160 and the body contact region 132 have different doping types and therefore cannot be formed at the same time.

[0048] Step S202: forming a mask layer on the first surface of the semiconductor layer.

[0049] In this step, a photoresist layer is formed on the first surface of the semiconductor layer 100, and then the photoresist layer is patterned by exposure and development processes to form a mask layer 101. The mask layer 101 has a groove 102, which is located in the mask layer corresponding to the epitaxial layer 120 between adjacent doping regions 141, and is used to form a groove, such as Figure 3b shown.

[0050] Step S203: forming a first trench in the semiconductor layer through the mask layer.

[0051] In this step, an etching process, such as dry etching, including ion milling etching, plasma etching, reactive ion etching, laser ablation, or wet etching or vapor etching, is used to form a first trench 103 in the semiconductor layer 100 through the mask layer 101. Figure 3c shown.

[0052] The first trench 103 penetrates the source region 160 and the body region 131 and extends into the epitaxial layer 120 below the body region 131 . The portion of the first trench 103 located in the epitaxial layer 12 is located between adjacent doped regions 141 . The doped regions 141 and the first trench 103 are separated by the epitaxial layer 120 .

[0053] In the present application, the first trench 103 can be a wide trench or a narrow trench. The wide trench and the narrow trench are determined by, for example, the ratio of the depth-to-width ratio of the trench. The lateral dimension of the first trench 103 is, for example, greater than or equal to 1 um.

[0054] Step S204: forming a blocking layer on the sidewall of the first trench.

[0055] In this step, a deposition process, such as physical vapor deposition, chemical vapor deposition, etc., is first used to deposit a shielding layer 104 on the surface of the mask layer 101 and the sidewall and bottom of the first trench 103. Figure 3d shown.

[0056] The portion of the blocking layer 104 located in the first trench 103 covers the sidewall and the bottom of the first trench 103 , and forms a second trench 105 with a smaller lateral dimension.

[0057] Further, the shielding layer 104 on the surface of the mask layer 101 and the shielding layer 104 at the bottom of the second trench 105 are removed, so that the remaining shielding layer 104 only covers the sidewall of the first trench 103 and exposes the bottom of the second trench 105, as shown in FIG. Figure 3e The bottom of the second groove 105 is a part of the bottom of the first groove 103 .

[0058] In this embodiment, the material of the shielding layer 104 includes polysilicon, nitride, oxide, etc. The shielding layer 104 is used to reduce the lateral size of the first trench 103, thereby forming a second trench 105 with a smaller lateral size; on the other hand, it serves as a mask layer during the ion implantation process to prevent the formation of unnecessary doping regions in the semiconductor layer 100 on the sidewalls of the trench.

[0059] Step S205: forming a buried layer at the bottom of the second trench.

[0060] In this step, an ion implantation process is used, and only the bottom of the second trench 105 is implanted with ions into the semiconductor layer 100, thereby forming a buried layer 142. Figure 3f shown.

[0061] Since the shielding layer 104 forms the second trench 105 with a smaller lateral dimension, the lateral dimension of the buried layer 142 formed by ion implantation through the second trench 105 is related to the lateral dimension of the second trench 104, and both are smaller than the lateral dimension of the first trench 103. Therefore, the lateral dimension of the second trench 105 and the lateral dimension of the buried layer 142 can be adjusted by adjusting the thickness of the shielding layer 104 on the sidewall of the first trench 103. In this embodiment, the lateral dimension of the buried layer 142 is, for example, less than 1um.

[0062] In addition, in the process of performing ion implantation through the second trench 105 to form the buried layer 142, since the buried layer 142 is located in the semiconductor layer 100 at the bottom of the second trench 105, on the one hand, there will be no alignment problem between the buried layer 142 and the middle of the bottom of the first trench 103, and there is no need to increase the lateral dimension of the first trench 103; on the other hand, an ion implantation process with an ion beam energy below 1MeV can be used, and at the same time, the lateral straggle of the buried layer 142 formed in this way will be weakened, so that the buried layer 142 will not have a lateral dimension larger than the lateral dimension of the first trench 103 due to lateral diffusion.

[0063] The buried layer 142 formed in this step has a depth from the first surface to the second surface of the semiconductor layer 100 that is greater than the depth of the bottom of the trench gate 150 from the first surface to the second surface of the semiconductor layer 100, and is less than or equal to the depth of the bottom of the doped region 141 from the first surface to the second surface of the semiconductor layer 100.

[0064] Step S206 : forming a trench gate in the first trench, and forming an interlayer dielectric layer 170 , a first conductive layer 181 , and a second conductive layer 182 .

[0065] In this step, the shielding layer 104 and the mask layer 101 are first removed. Figure 3gAs shown, a gate dielectric layer 151 and a gate conductor 152 are sequentially formed in the first trench 103, and an interlayer dielectric layer 170, a first conductive layer 181 and a second conductive layer 182 are formed on the semiconductor layer 100. Figure 1 shown.

[0066] An interlayer dielectric layer 170 and a first conductive layer 181 are formed on the first surface of the semiconductor layer 100 , and a second conductive layer 182 is formed on the second surface of the semiconductor layer 100 . The interlayer dielectric layer 170 isolates the first conductive layer 181 and the trench gate 150 .

[0067] The manufacturing method of the semiconductor device provided by the present application, compared with the semiconductor device in which the buried layer is formed first and then the groove is formed, the lateral dimension of the first groove in the semiconductor device of the present application is smaller, so that more grooves can be formed in the same area. In the epitaxial layer at the bottom of the trench gate of the semiconductor device, a buried layer is formed, and the lateral dimension of the buried layer is smaller than the lateral dimension of the trench gate, so the buried layer will not cause too much obstruction to the circuit path. Compared with the device in which the lateral dimension of the buried layer is larger than the lateral dimension of the trench gate, the on-resistance of the semiconductor device of the present application is smaller.

[0068] The present application provides a method for manufacturing a semiconductor device. In the manufacturing method, a first trench is first formed, and then a shielding layer is formed on the sidewalls in the first trench. The lateral dimension of the first trench is reduced via the shielding layer to form a second trench, and then ion implantation is performed via the second trench to form a buried layer. The buried layer formed by the aforementioned self-alignment method can certainly achieve the purpose of having a lateral dimension smaller than the lateral dimension of the first trench, and at the same time, there is no need to additionally expand the lateral dimension of the first trench, thereby achieving the purpose of forming more transistors or channels in the same area.

[0069] Furthermore, for some existing semiconductor devices, the manufacturing method of the present application can be compatible and achieve a buried layer with a smaller lateral size without changing the size of the device, thereby reducing the barrier of the buried layer to the flow of carriers and thereby reducing the on-resistance of the device.

[0070] Furthermore, the lateral dimension of the buried layer is smaller than the lateral dimension of the first trench, and the body region and the source region in the semiconductor device can be arranged on both sides of the trench gate and connected to the side walls of the trench gate, so that both sides of the trench gate can be used as conductive channels, reducing the resistance of the device in the on state.

[0071] Furthermore, doping regions may be provided on both sides of the trench gate, thereby improving the problem of electric field concentration at the corners of the trench gate and increasing the voltage resistance at the corners of the trench gate.

[0072] The embodiments of the present application are described above. However, these embodiments are only for illustrative purposes and are not intended to limit the scope of the present application. The scope of the present application is limited by the attached claims and their equivalents. Without departing from the scope of the present application, those skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present application.

Claims

1. A method for manufacturing a semiconductor device, comprising: forming a body region and a source region in a semiconductor layer, wherein the semiconductor layer comprises a first surface and a second surface opposite to each other, and the body region and the source region are located on a side of the semiconductor layer close to the first surface; forming a first trench in the semiconductor layer; forming a second groove in the first groove, wherein the lateral dimension of the second groove is smaller than the lateral dimension of the first groove; forming a buried layer in the semiconductor layer via the second trench, The buried layer is adjacent to the bottom of the trench gate, and the lateral dimension of the buried layer is smaller than the lateral dimension of the trench gate.

2. The manufacturing method according to claim 1, wherein: The step of forming a second groove in the first groove comprises: A blocking layer is formed on the sidewall of the first trench, and the blocking layer forms the second trench along the first trench.

3. The manufacturing method according to claim 2, wherein: The step of forming a blocking layer on the sidewall of the first trench comprises: forming a mask layer on the first surface of the semiconductor layer; forming a first trench in the semiconductor layer via the mask layer; forming a blocking layer in the first trench and on the upper surface of the mask layer, wherein the blocking layer forms a second trench along the first trench; The blocking layer on the upper surface of the mask layer and the blocking layer at the bottom of the second trench are removed.

4. The manufacturing method according to claim 1, wherein: An ion implantation process is used to form a buried layer in the semiconductor layer through the second trench, and the energy of an energy beam of the ion implantation process is less than 1 MeV.

5. The manufacturing method according to any one of claims 1 to 4, wherein: The lateral dimension of the buried layer is less than 1 um.

6. The manufacturing method according to any one of claims 1 to 4, wherein: A depth of the bottom of the buried layer from the first surface to the second surface in the semiconductor layer is less than or equal to a depth of the bottom of the doped region from the first surface to the second surface in the semiconductor layer.

7. The manufacturing method according to claim 3, wherein: After the step of forming a buried layer in the semiconductor layer via the second trench, the method further includes: removing the blocking layer and the mask layer; forming a trench gate in the first trench; forming an interlayer dielectric layer and a first conductive layer on the first surface of the semiconductor layer, wherein the interlayer dielectric layer isolates the trench gate and the first conductive layer; A second conductive layer is formed on the second surface of the semiconductor layer.

8. The manufacturing method according to claim 2, wherein: The material of the blocking layer includes polysilicon, oxide and nitride.

9. The manufacturing method according to claim 1, wherein: The step of forming a body region and a source region in the semiconductor layer further includes: A body contact region and a doped region are formed in the semiconductor layer.

10. The manufacturing method according to claim 1, wherein: The semiconductor layer includes a SiC semiconductor layer or a Si semiconductor layer.

Images