Deep trench field effect transistor and method for manufacturing the same

Abstract

The present invention provides a deep trench field effect transistor and a preparation method thereof, comprising: forming a trench in a substrate; filling an insulating layer in the trench; removing the insulating layer at the top of the trench to form a first trench portion; etching the insulating layer to form a second trench portion in the insulating layer that is connected to the first trench portion; forming a gate dielectric layer on the sidewall of the first trench portion; filling a gate layer in the first trench portion and the second trench portion; forming an isolation layer on the substrate, and forming a contact hole in the isolation layer and the substrate; forming an upper metal layer on the contact hole and the isolation layer. When the device is forward-conducted, an electron accumulation layer can be formed on the sidewall of the insulating layer, thereby effectively reducing the on-resistance of the device. The gate layer can simultaneously fill the first trench portion and the second trench portion through only one deposition process, which can effectively save process costs.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor integrated circuit design and manufacture, and in particular relates to a deep trench field effect transistor and a preparation method thereof. Background Art

[0002] Power transistors are generally used to control the reasonable operation of power electronic devices and provide high-power output to the load through power electronic devices. Power transistors have been widely used to control power output, and high-frequency high-power transistors are used in the scanning circuits of electronic equipment, such as color TVs, monitors, oscilloscopes, horizontal scanning circuits of large game consoles, video amplifier circuits, transmitter power amplifiers, etc.

[0003] Power devices usually work under high voltage and high current conditions, and generally have the characteristics of high withstand voltage, large operating current, and large self-dissipated power. Therefore, there are certain differences in use from general low-power devices. In order to make the function of the switching device work well, the power semiconductor field effect transistor needs to meet two basic requirements: 1) When the device is in the on state, it can have a very low on-resistance to minimize the power loss of the device itself; 2) When the device is in the off state, it can have a sufficiently high reverse breakdown voltage.

[0004] Existing power transistors generally adopt superjunction transistor structure. However, the preparation process of superjunction transistor is complicated. Due to the influence of annealing and other processes, the mutual diffusion of ions in the superjunction easily leads to a large deviation between the doping concentration and the actual value. The breakdown voltage of the superjunction transistor is sensitive to the ion doping concentration, which greatly increases the difficulty of the manufacturing process, especially in the manufacturing process of high doping concentration and low junction width devices. Furthermore, superjunction power transistors are generally used in high-voltage or medium-high voltage circuits. Since the width of superjunction power transistors has certain limitations, it is difficult to realize general superjunction power transistors for circuits less than 180V.

[0005] The deep trench shielded gate field effect transistor has a high reverse breakdown voltage and a relatively low on-resistance. However, due to the withstand voltage requirement, it requires a thick drift region, which also limits the further reduction of its on-resistance. Therefore, it is difficult for the existing deep trench shielded gate field effect transistor to further reduce its on-resistance. At the same time, the preparation process of the deep trench shielded gate field effect transistor is relatively complicated. For example, the polysilicon of the deep trench needs to be deposited in two steps, and additional steps such as grinding, etching, oxidation, etc. are required, which is costly.

[0006] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention

[0007] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a deep trench field effect transistor and a method for preparing the same, so as to solve the problem in the prior art that it is difficult to further reduce the on-resistance of the deep trench field effect transistor and the high process cost.

[0008] To achieve the above-mentioned purpose and other related purposes, the present invention provides a method for preparing a deep trench field effect transistor, the preparation method comprising the following steps: 1) providing a substrate and forming a trench in the substrate; 2) filling an insulating layer in the trench; 3) removing the insulating layer at the top of the trench to form a first trench portion at the top of the trench; 4) etching the insulating layer below the first trench portion to form a second trench portion in the insulating layer that is connected to the first trench portion; 5) forming a gate dielectric layer on the sidewall of the first trench portion; 6) filling a gate layer in the first trench portion and the second trench portion; 7) forming an isolation layer on the substrate, and forming a contact hole in the isolation layer and the substrate; 8) forming an upper metal layer on the contact hole and the isolation layer.

[0009] Optionally, the depth of the first groove is 0.6 micrometers to 2.5 micrometers.

[0010] Optionally, forming the gate dielectric layer on the sidewall of the first groove portion includes: growing an oxide layer on the sidewall of the first groove portion by a thermal oxidation process, wherein the oxide layer has a thickness of 300 angstroms to 1000 angstroms.

[0011] Optionally, forming the second groove portion includes: defining a pattern of the second groove portion by a photolithography process; etching the second groove portion in the insulating layer by an etching process, and retaining the insulating layer on the side walls and bottom of the second groove portion; wherein the thickness of the insulating layer retained on the side walls and bottom of the second groove portion is 2 to 10 times the thickness of the gate dielectric layer.

[0012] Optionally, the thickness of the insulating layer retained on the sidewall and the bottom of the second groove portion is 500 angstroms to 3000 angstroms.

[0013] Optionally, the preparation method further comprises the steps of: forming a well region on the surface of the substrate by an ion implantation process; forming a source region on the surface of the well region by an ion implantation process; wherein the ions implanted into the well region include boron, and the implantation dose is 6e12cm -2 ~2e13cm -2 The injection energy is 70kev~300kev; the source region is injected with arsenic ions, and the injection dose is 1e15 cm -2 ~2e16 cm-2 , the injection energy is 60kev~200kev.

[0014] Optionally, a depth of the first groove portion is greater than a depth of the well region.

[0015] Optionally, forming a contact hole in the isolation layer and the substrate includes: defining a pattern of the contact hole by a photolithography process; first etching the isolation layer to expose the substrate by an etching process, and then etching the substrate to form a contact hole, wherein the contact hole extends into the well region, and the depth of the contact hole embedded in the substrate is 0.3 microns to 0.6 microns.

[0016] Optionally, the upper metal layer is in contact with the well region and the source region at the same time, and the deposition thickness of the upper metal layer is 2 microns to 8 microns.

[0017] The present invention also provides a deep trench field effect transistor, comprising: a substrate, in which a trench is arranged; an insulating layer, arranged in the trench, the insulating layer at the top of the trench is removed to form a first trench portion, and part of the insulating layer below the first trench portion is removed to form a second trench portion extending from the first trench portion to the insulating layer, and the first trench portion is connected to the second trench portion; a gate dielectric layer, arranged on the side wall of the first trench portion; a gate layer, arranged in the first trench portion and the second trench portion; an isolation layer, arranged on the substrate, and contact holes are formed in the isolation layer and the substrate; and an upper metal layer, arranged on the contact hole and the isolation layer.

[0018] Optionally, a well region is further formed in the substrate, an active region is further formed in the well region, a depth of the first groove portion is greater than a depth of the well region, and a depth of the first groove portion is 0.6 micrometers to 2.5 micrometers.

[0019] Optionally, the gate dielectric layer is an oxide layer formed on the sidewall of the first groove portion by thermal oxidation, and the thickness of the oxide layer is 300 angstroms to 1000 angstroms.

[0020] Optionally, the thickness of the insulating layer retained between the sidewall and the bottom of the second groove and the substrate is 2 to 10 times the thickness of the gate dielectric layer, and the thickness of the retained insulating layer is 500 angstroms to 3000 angstroms.

[0021] Optionally, the contact hole is embedded in the substrate to a depth of 0.3 micrometers to 0.6 micrometers, the upper metal layer is in contact with the well region and the source region at the same time, and the deposition thickness of the upper metal layer is 2 micrometers to 8 micrometers.

[0022] As described above, the deep trench field effect transistor and the method for manufacturing the same of the present invention have the following beneficial effects: In the deep trench field effect transistor of the present invention, the gate layer is filled in the first groove part and the second groove part at the same time. The gate layer in the first groove part is used to realize the conduction and shutdown of the device. Since the gate layer in the second groove part is electrically connected to the gate layer in the first groove part, an electron accumulation layer can be formed on the side wall of the insulating layer when the device is forwardly conducted, thereby effectively reducing the on-resistance of the device. When the device withstands reverse voltage, since the insulating layer on the side wall of the second groove part is thicker, the gate layer and the insulating layer in the second groove part form a field plate, which can assist in depleting the drift region, making the electric field distribution in the drift region more uniform, thereby effectively improving the withstand voltage performance of the device.

[0023] The gate layers of the first groove portion and the second groove portion in the deep groove of the present invention are integrated, and the first groove portion and the second groove portion can be filled simultaneously through only one deposition process, which can effectively save process costs compared with traditional shielded gate field effect transistors. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The included drawings are used to provide a further understanding of the embodiments of the present application, which constitute a part of the specification, are used to illustrate the implementation of the present application, and together with the text description, explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application.

[0025] Figure 1 to Figure 10 It is a schematic structural diagram showing the steps of the method for preparing a deep trench field effect transistor according to an embodiment of the present invention.

[0026] Fig.11 It is a schematic diagram showing the principle of forming an electron accumulation layer in a deep trench field effect transistor according to an embodiment of the present invention.

[0027] Explanation of component numbers: 101 substrate, 102 trench, 103 insulating layer, 104 first groove portion, 105 second groove portion, 106 gate dielectric layer, 107 gate layer, 108 well region, 109 source region, 110 isolation layer, 111 contact hole, 112 upper metal layer, 201 electron accumulation layer. DETAILED DESCRIPTION

[0028] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0029] It should be emphasized that the term “include / comprises” when used herein refers to the presence of features, integers, steps or components, but does not exclude the presence or addition of one or more other features, integers, steps or components.

[0030] Features described and / or illustrated with respect to one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0031] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic view is only an example, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional space dimensions of length, width and depth should be included.

[0032] For ease of description, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0033] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0034] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0035] like Figure 1 to Figure 11 As shown, this embodiment provides a method for preparing a deep trench field effect transistor, and the preparation method comprises the following steps: like Figure 1 As shown, step 1 is first performed to provide a substrate 101 and form a groove 102 in the substrate 101.

[0036] In one embodiment, the substrate 101 may be a semiconductor substrate such as a single crystal silicon substrate, a silicon carbide substrate, a silicon germanium substrate, etc. In this embodiment, the substrate 101 is a single crystal silicon substrate.

[0037] In some embodiments, forming a groove 102 in the substrate 101 includes: defining the groove 102 pattern by a photolithography process, forming the groove 102 by dry etching, the dry etching may be, for example, reactive ion etching RIE, the etching gas may include a mixed gas such as Cl2, HBr, O2, N2, etc., the etching depth of the groove 102 may be, for example, 2 to 20 microns, specifically 2 microns, 3 microns, 5 microns or 10 microns, etc. The width of the groove 102 may be, for example, 0.8 microns to 6 microns, specifically 1 micron, 2 microns, 3 microns, 5 microns, etc. The sidewalls of the groove 102 are preferably vertical sidewalls, but in some embodiments, the sidewalls of the groove 102 may have a certain inclination angle, for example, 85° to 89°. The bottom of the groove 102 is preferably an arc bottom, and the top angle of the groove 102 is preferably a rounded corner to improve the withstand voltage performance of the final device.

[0038] like Figure 2 As shown, step 2 is then performed to fill the trench 102 with an insulating layer 103 .

[0039] In some embodiments, chemical vapor deposition (CVD) or atomic layer deposition (ALD) may be used to fill the insulating layer 103 in the trench 102. The insulating layer 103 may be made of silicon oxide, silicon nitride, silicon oxynitride, etc. In this embodiment, the insulating layer 103 is silicon oxide. After the deposition is completed, the excess insulating material on the surface may be removed by chemical mechanical polishing (CMP) or dry etching.

[0040] like Figure 3 As shown, step 3 is then performed to remove the insulating layer 103 at the top of the trench 102 to form a first groove portion 104 at the top of the trench 102.

[0041] In some embodiments, the insulating layer 103 at the top of the trench 102 can be removed by selective etching without a mask to form a first groove portion 104 at the top of the trench 102. The depth of the first groove portion 104 can be, for example, 0.6 micrometers to 2.5 micrometers, and the specific depth can be 0.8 micrometers, 1.2 micrometers, 1.8 micrometers or 2.2 micrometers, etc. The selective etching process can use wet etching (such as diluted HF solution) or dry etching, such as using CF4 / CHF3 gas with a ratio of 3:1 as a reaction gas for dry etching.

[0042] like Figure 4 As shown, step 4 is then performed to etch the insulating layer 103 below the first groove portion 104 to form a second groove portion 105 in the insulating layer 103 that is connected to the first groove portion 104 .

[0043] In some embodiments, the pattern of the second groove 105 can be defined by a photolithography process, and then the insulating layer 103 below the first groove 104 is etched by anisotropic etching (such as RIE, the reaction gases are SF6 and C4F8) to form a second groove 105 connected to the first groove 104. A certain thickness of the insulating layer 103 is retained between the second groove 105 and the substrate 101. The thickness of the retained insulating layer 103 is greater than the thickness of the gate dielectric layer 106 formed subsequently. The insulating layer 103 retained on the sidewall and bottom of the second groove 105 is preferably 2 to 10 times the thickness of the gate dielectric layer 106, for example, 3 times, 5 times, 8 times, etc. The thickness of the retained insulating layer 103 is larger than that of the gate dielectric layer 106. Therefore, the retained insulating layer 103 has a higher voltage resistance than the gate dielectric layer 106. After etching, the thickness of the insulating layer 103 retained on the sidewall and bottom of the second groove 105 can be 500 angstroms to 3000 angstroms, preferably 800 angstroms, 1200 angstroms or 1600 angstroms, which is 2 to 10 times the thickness of the subsequent gate dielectric layer 106. For example, when the gate dielectric layer 106 is 500 angstroms, the thickness of the retained insulating layer 103 can be 1000 angstroms to 3000 angstroms. When the device is forward-conducting, the carrier concentration formed on the outer surface of the insulating layer 103 is lower than the carrier concentration on the gate dielectric surface, but a carrier accumulation layer of a certain concentration can be formed on the sidewall of the insulating layer 103, thereby effectively reducing the on-resistance of the device.

[0044] like Figure 5 As shown, step 5 is then performed to form a gate dielectric layer 106 on the sidewall of the first groove portion 104.

[0045] In some embodiments, an oxide layer may be grown on the sidewall of the first groove 104 by a thermal oxidation process as a gate dielectric, the oxidation temperature may be 850°C to 1100°C, the time may be 30 minutes to 180 minutes, and the thickness of the gate dielectric layer 106 may be 300 angstroms to 1000 angstroms, preferably 500 angstroms, 700 angstroms or 900 angstroms. In other embodiments, the gate dielectric layer 106 may also be silicon oxynitride (SiON) or a high-k dielectric (such as HfO2, Al2O3, etc.).

[0046] like Figure 6~Figure 8 As shown, step 6 is then performed to fill the gate layer 107 in the first groove 104 and the second groove 105.

[0047] In some embodiments, Figure 6 As shown, the first groove 104 and the second groove 105 are filled with gate material, and the gate material includes doped polysilicon, metal (such as TiN, TaN) or metal silicide (such as WSi2), etc. The filling process can use low pressure chemical vapor deposition (LPCVD) to fill polysilicon or physical vapor deposition (PVD) to fill metal, and then remove excess gate material through a process such as chemical mechanical polishing (CMP).

[0048] like Figure 7~Figure 8 As shown, the preparation method also includes the steps of: like Figure 7 As shown, a well region 108 is formed on the surface of the substrate 101 by an ion implantation process, and annealing is performed. The rapid thermal annealing (RTA) temperature is, for example, 900° C. to 1050° C., and the time is 10 seconds to 60 seconds.

[0049] like Figure 8 As shown, a source region 109 is formed on the surface of the well region 108 by an ion implantation process, and annealing is performed. The rapid thermal annealing (RTA) temperature is, for example, 900° C. to 1050° C., and the time is 10 seconds to 60 seconds.

[0050] The ions implanted into the well region 108 include boron, and the implantation dose is 6e12cm -2 ~2e13cm -2 (e.g. 1e13 cm -2 , 1.5e13 cm -2 ), the implantation energy is 70kev~300kev (preferably 100keV, 200keV); the implanted ions in the source region 109 include arsenic, and the implantation dose is 1e15 cm -2 ~2e16 cm -2 (e.g. 5e15 cm -2 , 1e16 cm -2 ), the injection energy is 60keV~200keV (preferably 80keV, 150keV).

[0051] In this embodiment, the depth of the first groove portion 104 needs to be greater than the depth of the well region 108 . For example, when the depth of the well region 108 is 0.5 micrometers, the depth of the first groove portion 104 is preferably greater than or equal to 0.6 micrometers.

[0052] like Fig. 9 As shown, step 7 is then performed to form an isolation layer 110 on the substrate 101 and form a contact hole 111 in the isolation layer 110 and the substrate 101.

[0053] In some embodiments, the isolation layer 110 may be silicon oxide or silicon nitride, etc. The silicon oxide may be deposited by a PECVD process or the silicon nitride may be deposited by a LPCVD process.

[0054] In some embodiments, the contact hole 111 may be formed by a two-step etching process: First, the pattern of the contact hole 111 is defined by a photolithography process.

[0055] Then, a first step of etching the isolation layer 110 to the surface of the substrate 101 is performed, and the reaction gas may be CF4 / CHF3 gas with a ratio of 2:1.

[0056] Finally, the second step is to etch the substrate 101 to form a contact hole 111. The depth of the contact hole 111 embedded in the substrate 101 is 0.3 micrometers to 0.6 micrometers, preferably 0.4 micrometers or 0.5 micrometers. Preferably, the bottom of the contact hole 111 extends into the well region 108, and the distance between the contact hole 111 and the bottom of the well region 108 is greater than 0.1 micrometers.

[0057] like Fig.10 As shown, step 8 is finally performed to form an upper metal layer 112 on the contact hole 111 and the isolation layer 110 .

[0058] In some embodiments, an upper metal layer 112 may be formed on the contact hole 111 and the isolation layer 110 by sputtering or electroplating, and the material of the metal layer may be Al, Cu, or W. The thickness of the metal layer may be 2 to 8 microns, specifically 3 microns, 5 microns, or 7 microns, and the metal layer contacts the well region 108 and the source region 109 at the same time.

[0059] In some embodiments, the preparation method may further include forming a drain region and a lower metal layer on the back side of the substrate 101 .

[0060] like Fig.10 As shown, the present embodiment further provides a deep trench field effect transistor, which can be prepared by the preparation method listed above, and the deep trench field effect transistor includes: a substrate 101, in which a trench 102 is provided; an insulating layer 103, which is provided in the trench 102, wherein the insulating layer 103 at the top of the trench 102 is removed to form a first trench portion 104, and a portion of the insulating layer 103 below the first trench portion 104 is removed to form a second trench portion 105 extending from the first trench portion 104 to the inside of the insulating layer 103, wherein the first trench portion 104 is connected to the second trench portion 105; a gate dielectric layer 106, which is provided on the sidewall of the first trench portion 104; a gate layer 107, which is provided in the first trench portion 104 and the second trench portion 105; an isolation layer 110, which is provided on the substrate 101, and a contact hole 111 is formed in the isolation layer 110 and the substrate 101; and an upper metal layer, which is provided on the contact hole 111 and the isolation layer 110.

[0061] In one embodiment, a well region 108 is further formed in the substrate 101 , an active region 109 is further formed in the well region 108 , the depth of the first groove 104 is greater than the depth of the well region 108 , and the depth of the first groove 104 is 0.6 microns to 2.5 microns.

[0062] In one embodiment, the gate dielectric layer 106 is an oxide layer formed on the sidewall of the first groove portion 104 by thermal oxidation, and the thickness of the oxide layer is 300 angstroms to 1000 angstroms.

[0063] In one embodiment, the thickness of the insulating layer 103 retained between the sidewall and the bottom of the second groove 105 and the substrate 101 is 2 to 10 times the thickness of the gate dielectric layer 106 , and the thickness of the retained insulating layer 103 is 500 angstroms to 3000 angstroms.

[0064] In one embodiment, the contact hole 111 is embedded in the substrate 101 to a depth of 0.3 micrometers to 0.6 micrometers, the upper metal layer 112 is in contact with both the well region 108 and the source region 109 , and the deposition thickness of the upper metal layer 112 is 2 micrometers to 8 micrometers.

[0065] like Fig.11 As shown, in the deep trench field effect transistor of the present invention, the gate layer 107 is filled in the first groove portion 104 and the second groove portion 105 at the same time, and the gate layer 107 of the first groove portion 104 is used to realize the conduction and shutdown of the device. Since the gate layer 107 in the second groove portion 105 is electrically connected to the gate layer 107 in the first groove portion 104, when the device is forwardly conducted, a conductive channel with a larger width can be formed on the side wall of the gate dielectric layer 106 with a smaller thickness, and an electron accumulation layer 201 with a certain width can be formed on the side wall of the insulating layer 103 with a larger thickness, thereby effectively reducing the on-resistance of the device. As for the reverse withstand voltage of the device, since the retained insulating layer 103 is thicker than the gate dielectric layer 106, the retained insulating layer 103 has a higher withstand voltage capability than the gate dielectric layer 106, thereby ensuring that the device has sufficient withstand voltage capability. Furthermore, the gate layer 107 and the insulating layer 103 in the second groove 105 form a field plate, which can assist in depleting the drift region, making the electric field distribution in the drift region more uniform, and further improving the withstand voltage performance of the device.

[0066] As described above, the deep trench field effect transistor and the method for manufacturing the same of the present invention have the following beneficial effects: In the deep trench field effect transistor of the present invention, the gate layer 107 is filled in the first groove portion 104 and the second groove portion 105 at the same time. The gate layer 107 of the first groove portion 104 is used to realize the conduction and shutdown of the device. Since the gate layer 107 in the second groove portion 105 is electrically connected to the gate layer 107 in the first groove portion 104, when the device is forwardly conducted, an electron accumulation layer 201 can be formed on the side wall of the insulating layer 103, thereby effectively reducing the on-resistance of the device. When the device withstands reverse voltage, since the insulating layer 103 on the side wall of the second groove portion 105 is thicker, the gate layer 107 in the second groove portion 105 and the insulating layer 103 form a field plate, which can assist in depleting the drift region, making the electric field distribution in the drift region more uniform, thereby effectively improving the withstand voltage performance of the device.

[0067] The gate layer 107 of the first groove portion 104 and the second groove portion 105 in the deep groove of the present invention is integrated, and the first groove portion 104 and the second groove portion 105 can be filled simultaneously through only one deposition process, which can effectively save process costs compared to traditional shielded gate field effect transistors.

[0068] Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0069] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for preparing a deep trench field effect transistor, characterized in that: The preparation method comprises: providing a substrate, in which a trench is formed; filling an insulating layer in the trench; removing the insulating layer at the top of the trench to form a first groove portion at the top of the trench; Etching the insulating layer below the first groove portion to form a second groove portion in the insulating layer that is connected to the first groove portion; forming a gate dielectric layer on the sidewalls of the first groove; filling a gate layer in the first groove portion and the second groove portion; forming an isolation layer on the substrate, and forming contact holes in the isolation layer and the substrate; An upper metal layer is formed on the contact hole and the isolation layer.

2. The method for preparing a deep trench field effect transistor according to claim 1, characterized in that: The depth of the first groove is 0.6 micrometers to 2.5 micrometers.

3. The method for preparing a deep trench field effect transistor according to claim 1, characterized in that: Forming a gate dielectric layer on the sidewall of the first groove portion includes: growing an oxide layer on the sidewall of the first groove portion by a thermal oxidation process, wherein the oxide layer has a thickness of 300 angstroms to 1000 angstroms.

4. The method for preparing a deep trench field effect transistor according to claim 1, characterized in that: Forming the second groove portion includes: Defining a pattern of the second groove portion by a photolithography process; Etching a second groove portion in the insulating layer by an etching process, wherein the insulating layer remains on the sidewall and bottom of the second groove portion; The thickness of the insulating layer retained on the sidewall and the bottom of the second groove portion is 2 to 10 times the thickness of the gate dielectric layer.

5. The method for preparing a deep trench field effect transistor according to claim 4, characterized in that: The thickness of the insulating layer retained on the sidewall and bottom of the second groove portion is 500 angstroms to 3000 angstroms.

6. The method for preparing a deep trench field effect transistor according to claim 1, characterized in that: Also includes the steps: forming a well region on the surface of the substrate by an ion implantation process; forming a source region on the surface of the well region by an ion implantation process; The ions implanted into the well region include boron, and the implantation dose is 6e12cm -2 ~2e13cm -2 The injection energy is 70kev~300kev; the source region is injected with arsenic ions, and the injection dose is 1e15 cm -2 ~2e16 cm -2 , the injection energy is 60kev~200kev.

7. The method for preparing a deep trench field effect transistor according to claim 6, characterized in that: The depth of the first groove portion is greater than the depth of the well region.

8. The method for preparing a deep trench field effect transistor according to claim 6, characterized in that: Forming contact holes in the isolation layer and the substrate includes: Defining the pattern of the contact holes by photolithography; The isolation layer is first etched through an etching process until the substrate is exposed, and then the substrate is etched to form a contact hole, wherein the contact hole extends into the well region, and the depth of the contact hole embedded in the substrate is 0.3 micrometer to 0.6 micrometer.

9. The method for preparing a deep trench field effect transistor according to claim 8, characterized in that: The upper metal layer is in contact with the well region and the source region at the same time, and the deposition thickness of the upper metal layer is 2 micrometers to 8 micrometers.

10. A deep trench field effect transistor, characterized in that: include: A substrate having a groove therein; an insulating layer disposed in the groove, wherein the insulating layer at the top of the groove is removed to form a first groove portion, and a portion of the insulating layer below the first groove portion is removed to form a second groove portion extending from the first groove portion into the insulating layer, wherein the first groove portion is connected to the second groove portion; A gate dielectric layer is disposed on a side wall of the first groove; A gate layer is disposed in the first groove portion and the second groove portion; An isolation layer, disposed on the substrate, wherein contact holes are formed in the isolation layer and the substrate; An upper metal layer is disposed on the contact hole and the isolation layer.

11. The deep trench field effect transistor according to claim 10, characterized in that: A well region is also formed in the substrate, and an active region is also formed in the well region. The depth of the first groove portion is greater than the depth of the well region, and the depth of the first groove portion is 0.6 micrometers to 2.5 micrometers.

12. The deep trench field effect transistor according to claim 11, characterized in that: The contact hole is embedded in the substrate to a depth of 0.3 micrometers to 0.6 micrometers, the upper metal layer is in contact with the well region and the source region at the same time, and the deposition thickness of the upper metal layer is 2 micrometers to 8 micrometers.

13. The deep trench field effect transistor according to claim 10, characterized in that: The gate dielectric layer is an oxide layer formed on the sidewall of the first groove by thermal oxidation, and the thickness of the oxide layer is 300 angstroms to 1000 angstroms.

14. The deep trench field effect transistor according to claim 10, characterized in that: The thickness of the insulating layer retained between the sidewall and the bottom of the second groove and the substrate is 2 to 10 times the thickness of the gate dielectric layer, and the thickness of the retained insulating layer is 500 angstroms to 3000 angstroms.

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