A semiconductor device and a method for manufacturing the same

Abstract

The present invention provides a semiconductor device and a manufacturing method thereof. The semiconductor device includes: a substrate in which device trenches are provided; a field oxide layer provided on the sidewalls of the device trenches, the field oxide layer having a stepped structure, and the width of the stepped structure decreasing along the direction away from the first surface of the substrate, where the first surface is the surface of the substrate where the device trenches are formed; a drift region provided in the substrate, the drift region connected to the field oxide layer and the drift region being wrapped outside the field oxide layer, where the width of the drift region decreases along the direction away from the first surface of the substrate and the ion doping concentration of the drift region decreases; and a polysilicon layer filled in the device trenches and the polysilicon layer connected to the field oxide layer. The present invention provides a semiconductor device and a manufacturing method thereof, which can effectively improve the breakdown voltage performance of the device, reduce the device size, lower the on-resistance of the device, and bidirectionally optimize the relationship between the breakdown voltage capability and the on-resistance of the device.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] The BCD (Bipolar-CMOS-DMOS) process integrates transistors, CMOS and DMOS devices on the same chip, realizing the integration of devices with different performances on the same chip. The BCD process combines the advantages of high transconductance and strong load driving capability of bipolar devices, high integration and low power consumption of CMOS, and DMOS working in switching mode with extremely low power consumption. With market demand and industrial development, high-voltage DMOS devices have higher requirements for low on-resistance and high breakdown voltage.

[0003] In laterally diffused metal oxide semiconductors, improving the voltage resistance of the device will sacrifice the device area, and the high breakdown voltage and low on-resistance of the semiconductor device cannot be achieved at the same time. Summary of the invention

[0004] The object of the present invention is to provide a semiconductor device and a method for manufacturing the same, which can effectively improve the voltage withstand performance of the device, reduce the device size, reduce the on-resistance of the device, and bidirectionally optimize the relationship between the voltage withstand capability and the on-resistance of the device.

[0005] In order to solve the above technical problems, the present invention is achieved through the following technical solutions:

[0006] The present invention provides a semiconductor device, comprising:

[0007] A substrate, wherein a device trench is provided in the substrate;

[0008] A field oxide layer is disposed on a groove wall of the device groove, the field oxide layer has a stepped structure, and a width of the stepped structure decreases along a direction away from a first surface of the substrate, wherein the first surface is a surface of the substrate forming the device groove;

[0009] a drift region, disposed in the substrate, the drift region connected to the field oxide layer, and the drift region wrapped outside the field oxide layer, wherein along a direction away from the first surface of the substrate, the width of the drift region decreases, and the ion doping concentration of the drift region decreases; and

[0010] A polysilicon layer is filled in the device trench, and the polysilicon layer is connected to the field oxide layer.

[0011] In an embodiment of the present invention, surfaces of the field oxide layer, the drift region, the substrate and the polysilicon layer are flush.

[0012] In an embodiment of the present invention, along a direction perpendicular to the surface of the substrate, the dielectric constant of the field oxide layer varies in a stepped manner.

[0013] In an embodiment of the present invention, the semiconductor device includes a plurality of shallow trench isolation structures disposed in the substrate, and the plurality of shallow trench isolation structures partition a plurality of active regions in the substrate, wherein the drift region is disposed in the active region.

[0014] In an embodiment of the present invention, the semiconductor device includes:

[0015] A first type of deep well region disposed in the substrate, wherein the doping ion types of the first type of deep well region and the drift region are the same; and

[0016] A second type of deep well region disposed in the substrate, the second type of deep well region being disposed on the first type of deep well region and connected to the first type of deep well region, wherein the drift region is disposed on the second type of deep well region and connected to the second type of deep well region, and wherein the doping ion types of the second type of deep well region and the drift region are different.

[0017] In an embodiment of the present invention, the semiconductor device includes a body region disposed in the second type of deep well region, the body region being connected to the drift region, and wherein the doping ion types of the body region and the second type of deep well region are the same.

[0018] In an embodiment of the present invention, the device trench passes through the body region and the first type of deep well region and extends below the first type of deep well region, and the polysilicon layer extends along a direction perpendicular to the first surface and towards the second surface of the substrate, wherein the first surface and the second surface are parallel, one end of the polysilicon layer is flush with the first surface, and the other end of the polysilicon layer extends below the first type of deep well region.

[0019] In an embodiment of the present invention, the semiconductor device includes:

[0020] A first well region disposed in the substrate, the first well region being located in the active region outside the drift region and connected to the second type of deep well region; and

[0021] A second well region disposed in the substrate, the second well region being located in the active region outside the first well region and connected to the first type of deep well region.

[0022] In an embodiment of the present invention, the polysilicon layer has a symmetry plane, the semiconductor device is a symmetric structure, and the semiconductor device is symmetric about the symmetry plane, wherein the drift region is symmetric about the symmetry plane, and the field oxide layer is symmetric about the symmetry plane.

[0023] The present invention provides a method for manufacturing a semiconductor device, comprising the following steps:

[0024] Providing a substrate;

[0025] Gradually forming device trenches in the substrate, and while gradually forming the device trenches, forming a field oxide layer on the sidewalls of the device trenches, wherein the field oxide layer has a stepped structure, and along the direction away from the first surface of the substrate, the width of the stepped structure decreases, wherein the first surface is the surface of the substrate where the device trenches are formed;

[0026] While gradually forming the device trenches, gradually forming a plurality of doped regions in the substrate;

[0027] After annealing treatment, the plurality of doped regions form a drift region, wherein the drift region is connected to the field oxide layer, and the drift region is wrapped outside the field oxide layer, wherein along the direction away from the first surface of the substrate, the width of the drift region decreases, and the ion doping concentration of the drift region decreases; and

[0028] Filling the device trenches to form a polysilicon layer, wherein the polysilicon layer is connected to the field oxide layer.

[0029] In an embodiment of the present invention, the steps of gradually forming the device trenches, the field oxide layer and the drift region include:

[0030] Forming a current dielectric layer on the exposed surface of the substrate and the surface of the previous dielectric layer;

[0031] Etching the current dielectric layer and the substrate to form a current transition trench, wherein when forming the current transition trench, the current dielectric layer located on the sidewalls of the previous transition trench is retained;

[0032] Injecting ions into the substrate to form a doped region;

[0033] Wherein, a plurality of doped regions are connected to form the drift region, and the current dielectric layers on the sidewalls of the plurality of transition trenches are connected to form the field oxide layer.

[0034] As described above, the present invention provides a semiconductor device and a manufacturing method thereof, and its unexpected technical effects are as follows: the present invention provides a field oxide layer with a stepped structure, and is paired with a drift region having a concentration gradient, wherein while the concentration gradient of the drift region decreases, the region width also decreases, and at the same time, the cross-sectional area of the field oxide layer also decreases, so as to effectively improve the breakdown voltage performance of the semiconductor device under the condition that the call area of the semiconductor device remains unchanged. And the present invention can reduce the device size and lower the on-resistance of the device while ensuring the longitudinal breakdown voltage performance of the device, not only optimizing the device breakdown voltage, but also reducing the on-resistance of the device, and bi-directionally optimizing the relationship between the device breakdown voltage and the on-resistance. And according to the manufacturing method of the semiconductor structure provided by the present invention, while forming the concentration gradient of the drift region, a field oxide layer with a stepped structure is formed, the process is mature, the forming yield of the semiconductor device can be improved, and the process controllability is high, which can effectively reduce device defects.

[0035] Of course, it is not necessary for any product implementing the present invention to achieve all the above advantages simultaneously. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for describing the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention, and those of ordinary skill in the art can also obtain other drawings based on these drawings without creative efforts.

[0037] Figure 1 It is a schematic structural diagram of forming a first type of deep well region and a second type of deep well region in an embodiment of the present invention.

[0038] Figure 2 It is a schematic structural diagram of forming a shallow trench isolation structure in an embodiment of the present invention.

[0039] Figure 3 It is a schematic structural diagram of forming an interlayer dielectric layer and a hard mask layer in an embodiment of the present invention.

[0040] Figure 4 It is a schematic structural diagram of forming a process trench in an embodiment of the present invention.

[0041] Figure 5 It is a schematic structural diagram of forming a first dielectric layer in an embodiment of the present invention.

[0042] Figure 6 It is a schematic structural diagram of forming a first segment of trench in an embodiment of the present invention.

[0043] Figure 7 It is a schematic structural diagram of forming a second dielectric layer in an embodiment of the present invention.

[0044] Figure 8 Schematic diagram of the structure for forming the second trench in an embodiment of the present invention.

[0045] Figure 9 Schematic diagram of the structure for forming the third dielectric layer in an embodiment of the present invention.

[0046] Figure 10 Schematic diagram of the structure for forming the third trench in an embodiment of the present invention.

[0047] Figure 11 Schematic diagram of the structure for forming the fourth dielectric layer in an embodiment of the present invention.

[0048] Figure 12 Schematic diagram of the structure for forming the fourth trench in an embodiment of the present invention.

[0049] Figure 13 Schematic diagram of the structure for forming the fifth dielectric layer in an embodiment of the present invention.

[0050] Figure 14 Schematic diagram of the structure for forming the fifth trench in an embodiment of the present invention.

[0051] Figure 15 Schematic diagram of the structure for forming the reserved gate oxide layer in an embodiment of the present invention.

[0052] Figure 16 Schematic diagram of the structure for etching and removing the reserved gate oxide layer in an embodiment of the present invention.

[0053] Figure 17 Schematic diagram of the structure for forming the gate oxide layer in an embodiment of the present invention.

[0054] Figure 18 Schematic diagram of the structure for forming the drift region in an embodiment of the present invention.

[0055] Figure 19 Schematic diagram of the structure for forming the polysilicon layer in an embodiment of the present invention.

[0056] Figure 20 Schematic diagram of the semiconductor structure in an embodiment of the present invention.

[0057] Figure 21 Cross-sectional structure schematic diagram of a semiconductor device in an embodiment of the present invention.

[0058] Figure 22 Layout structure schematic diagram of a semiconductor device from a top-down perspective in an embodiment of the present invention.

[0059] Figure 23 Electrode structure schematic diagram of a semiconductor device in an embodiment of the present invention.

[0060] In the figure: 100, substrate; 101, first type of deep well region; 102, second type of deep well region; 103, shallow trench isolation structure; 104, first doped region; 105, second doped region; 106, third doped region; 107, fourth doped region; 108, body region; 109, first well region; 110, second well region; 111, electrode doped region; 112, base doped region; 113, silicide layer; 201, interlayer dielectric layer; 202, hard mask layer; 203, first dielectric layer; 204, process trench; 2041, first transition trench; 2042, second transition trench; 2043, third transition trench; 2044, fourth transition trench; 2045, fifth transition trench; 205, second dielectric layer; 206, third dielectric layer; 207, fourth dielectric layer; 208, fifth dielectric layer; 209, reserved gate oxide layer; 210, gate oxide layer; 211, polysilicon layer; 300, photoresist layer; 400, contact electrode; 10, drift region; 20, field oxide layer; S, source; B, base; D, drain; G, gate. Detailed implementation manners

[0061] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0062] Please refer to Figure 1 As shown, the present invention provides a method for manufacturing a semiconductor device. First, a substrate 100 is provided, and a first type of deep well region 101 is formed in the substrate 100. Then, a second type of deep well region 102 is formed in the substrate 100. Among them, the substrate 100 is, for example, a silicon substrate for forming a semiconductor device. The substrate 100 may include a substrate and a silicon layer disposed above the substrate. The substrate is, for example, silicon (Si), silicon carbide (SiC), sapphire (Al 2 O 3 ), gallium arsenide (GaAs), lithium aluminate (LiAlO 2), etc. semiconductor substrate materials, and a silicon layer is formed above the substrate. In this embodiment, the substrate 100 is, for example, a P-type semiconductor. Pentavalent ions, such as phosphorus ions, are implanted into the substrate 100 to form a first type of deep well region 101. Then, trivalent ions, such as boron ions, are implanted into the substrate 100 to form a second type of deep well region 102. In this embodiment, the second type of deep well region 102 is located above the first type of deep well region 101 and is connected to the first type of deep well region 101. It should be noted that both the first type of deep well region 101 and the second type of deep well region 102 are deep well structures, and the first type of deep well region 101 and the second type of deep well region 102 are located in the substrate 100. The present invention does not limit the depths of the first type of deep well region 101 and the second type of deep well region 102 in the substrate 100.

[0063] Please refer to Figures 1 to 3 As shown, in an embodiment of the present invention, a plurality of shallow trench isolation structures 103 are formed in the substrate 100, an interlayer dielectric layer 201 is formed on the substrate 100, and a hard mask layer 202 is formed on the interlayer dielectric layer 201. Among them, the process of forming the shallow trench isolation structures 103 is a shallow trench isolation process (Shallow Trench Isolation, STI). The plurality of shallow trench isolation structures 103 divide the substrate 100 into a plurality of active regions. In this embodiment, the active region above the second type of deep well region 102 is a process region. Among them, the plurality of shallow trench isolation structures 103 are distributed on both sides of the process region, and the shallow trench isolation structures 103 located on both sides of the process region are symmetrically distributed with respect to a symmetry plane of the second type of deep well region 102. In this embodiment, the processes of forming the interlayer dielectric layer 201 and the hard mask layer 202 are chemical vapor deposition (Chemical Vapor Deposition, CVD) or plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD), etc. Among them, the interlayer dielectric layer 201 is silicon oxide, and the hard mask layer 202 is silicon nitride. The present invention does not limit the thicknesses of the interlayer dielectric layer 201 and the hard mask layer 202.

[0064] Please refer to Figures 1 to 4As shown, in an embodiment of the present invention, the hard mask layer 202 and the interlayer dielectric layer 201 are etched to form a process trench 204. In this embodiment, first, a photoresist material is coated on the hard mask layer 202, and then the photoresist material is patterned by exposure and development to form a photoresist layer 300. Using the photoresist layer 300 as a mask, a part of the hard mask layer 202 and a part of the interlayer dielectric layer 201 are removed by dry etching to form a process trench 204. In this embodiment, the process trench 204 is located on the process area. After etching is completed, the photoresist layer 300 can be directly washed away. Then, using the hard mask layer 202 and the interlayer dielectric layer 201 as masks, pentavalent ions, such as phosphorus ions, are implanted into the substrate 100 to form a first doped region 104. In this embodiment, the first doped region 104 is located within the process area, and the depth of the first doped region 104 in the substrate 100 can be greater than the depth of the shallow trench isolation structure 103 in the substrate 100. In this embodiment, in the step of forming the first doped region 104, the injection direction of the ions is inclined implantation. The present invention does not limit the inclination angle. After ion implantation, the width W2 of the first doped region 104 is greater than the cross-sectional width W1 of the process trench 204, such as Figure 4 shown.

[0065] Please refer to Figures 4 to 6 As shown, in an embodiment of the present invention, after the first doped region 104 is formed, a first dielectric layer 203 is formed on the hard mask layer 202 and in the process trench 204. Then, the first dielectric layer 203 and a part of the substrate 100 are etched to form a first transition trench 2041. Then, using the hard mask layer 202 and the interlayer dielectric layer 201 as masks, pentavalent ions, such as phosphorus ions, are implanted into the substrate 100 to form a second doped region 105. In this embodiment, silicon oxide is deposited on the surface of the hard mask layer 202 and the sidewalls of the process trench 204 by chemical vapor deposition or plasma-enhanced chemical vapor deposition to form the first dielectric layer 203, where the sidewalls of the process trench 204 include part of the sidewalls of the hard mask layer 202, part of the sidewalls of the interlayer dielectric layer 201, and the exposed surface of the substrate 100. Then, the first dielectric layer 203 located on the surface of the hard mask layer 202 and a part of the first dielectric layer 203 located on the substrate 100 are etched away, and then the substrate 100 is etched to deepen the process trench 204 and form a first transition trench 2041. The etching step is dry etching and can be carried out in multiple steps.

[0066] Please refer to Figures 4 to 6As shown, in an embodiment of the present invention, the process of forming the first transition trench 2041 is described as the first etching step of the substrate 100. The first etching depth of the substrate 100 is equal to the implantation depth of the first doping region 104. In this embodiment, the second doping region 105 is connected to the first doping region 104, and the ion concentration of the second doping region 105 is lower than that of the first doping region 104. In this embodiment, the width W3 of the second doping region 105 is smaller than the width W2 of the first doping region 104, and the width W3 of the second doping region 105 is smaller than the cross-sectional length of the process trench 204. The first doping region 104 is symmetric about the symmetry plane of the second type of deep well region 102, and the second doping region 105 is symmetric about the symmetry plane of the second type of deep well region 102. In this embodiment, the first doping region 104 covers the second doping region 105.

[0067] Please refer to Figures 4 to 6 As shown, in an embodiment of the present invention, in the etching steps of the hard mask layer 202, the interlayer dielectric layer 201, and the substrate 100, a part of the first dielectric layer 203 on the substrate 100 will not be completely removed. Specifically, the dielectric material on the sidewall of the process trench 204 will not be removed by etching but will be retained on the sidewall of the process trench 204. Therefore, in the ion implantation process of forming the second doping region 105, the first dielectric layer 203 will also act as a mask for ion implantation to help form the second doping region 105. In this embodiment, in the ion implantation process of forming the second doping region 105, the ion injection direction is vertical injection, so as to form a width difference between the second doping region 105 and the first doping region 104, thereby forming a stepped shape of the doping region, and still maintaining that the second doping region 105 and the first doping region 104 have the same symmetry plane. It should be noted that in this embodiment, the bottom surface of the first transition trench 2041 is the surface of the second doping region 105, and the sidewall of the first transition trench 2041 includes the exposed surface of the first dielectric layer 203 and the exposed sidewall of the first doping region 104.

[0068] Please refer to Figures 6 to 8As shown, in an embodiment of the present invention, after forming the second doped region 105, a second dielectric layer 205 is formed on the surface of the hard mask layer 202 and the sidewalls of the first transition trench 2041. Then, the second dielectric layer 205 and the substrate 100 are etched to form a second transition trench 2042. Then, pentavalent ions, such as phosphorus ions, are implanted into the substrate 100 to form a third doped region 106. In this embodiment, silicon oxide is deposited on the surface of the hard mask layer 202 and the sidewalls of the first transition trench 2041 by chemical vapor deposition or plasma-enhanced chemical vapor deposition to form the second dielectric layer 205. The sidewalls of the first transition trench 2041 include the exposed surface of the first dielectric layer 203 and the exposed surface of the substrate 100. The present invention does not limit the thickness of the second dielectric layer 205. Then, the second dielectric layer 205 located on the surface of the hard mask layer 202 and the part of the second dielectric layer 205 located on the substrate 100 are etched away, and then the substrate 100 is etched to deepen the first transition trench 2041 and form a second transition trench 2042. The etching step is dry etching and can be carried out in multiple steps.

[0069] Please refer to Figures 6 to 8 As shown, in an embodiment of the present invention, the process of forming the second transition trench 2042 is described as the second etching step of the substrate 100. Among them, the etching depth of the second etching of the substrate 100 is equal to the implantation depth of the second doped region 105. In this embodiment, the third doped region 106 is connected to the second doped region 105, and the ion concentration of the third doped region 106 is lower than that of the second doped region 105. In this embodiment, the width W4 of the third doped region 106 is smaller than the width W3 of the second doped region 105, and the second doped region 105 covers the third doped region 106. In this embodiment, the third doped region 106 is symmetric about the symmetry plane of the second type of deep well region 102. In the step of forming the second transition trench 2042, specifically, the dielectric material on the sidewalls of the first transition trench 2041 is not etched away but is retained on the sidewalls of the first transition trench 2041. Therefore, in the ion implantation process of forming the third doped region 106, the second dielectric layer 205 also serves as a mask for ion implantation to help form the third doped region 106. In this embodiment, in the ion implantation process of forming the third doped region 106, the ion injection direction is vertical injection. The second dielectric layer 205 covers a part of the surface of the second doped region 105. Therefore, after ion implantation, a width difference is formed between the second doped region 105 and the third doped region 106, thereby forming a stepped shape between the third doped region 106 and the second doped region 105. Among them, the third doped region 106, the second doped region 105, and the first doped region 104 have the same symmetry plane.

[0070] Please refer to Figures 8 to 10As shown, in an embodiment of the present invention, after forming the third doped region 106, a third dielectric layer 206 is formed on the surface of the hard mask layer 202 and the sidewalls of the second transition trench 2042. Then, the third dielectric layer 206 and the substrate 100 are etched to form a third transition trench 2043. Then, pentavalent ions, such as phosphorus ions, are implanted into the substrate 100 to form a fourth doped region 107. In this embodiment, silicon oxide is deposited on the surface of the hard mask layer 202 and the sidewalls of the second transition trench 2042 by chemical vapor deposition or plasma enhanced chemical vapor deposition to form the third dielectric layer 206. The sidewalls of the second transition trench 2042 include the exposed surface of the second dielectric layer 205 and the exposed surface of the substrate 100. The present invention does not limit the thickness of the third dielectric layer 206. Then, the third dielectric layer 206 on the hard mask layer 202 and a part of the third dielectric layer 206 on the substrate 100 are etched away, and then the substrate 100 is etched to deepen the second transition trench 2042 and form a third transition trench 2043. The etching step is dry etching and can be carried out in multiple steps.

[0071] Please refer to Figures 8 to 10As shown, in an embodiment of the present invention, the process of forming the third transition trench 2043 is described as the third etching step of the substrate 100. Among them, the etching depth of the third time of the substrate 100 is equal to the implantation depth of the third doped region 106. In this embodiment, the fourth doped region 107 is connected to the third doped region 106, and the ion concentration of the fourth doped region 107 is lower than that of the third doped region 106. In this embodiment, the width W5 of the fourth doped region 107 is smaller than the width W4 of the third doped region 106, and the third doped region 106 covers the fourth doped region 107. In this embodiment, the fourth doped region 107 is symmetric about the symmetry plane of the second type of deep well region 102. In the step of forming the third transition trench 2043, specifically, the dielectric material on the side wall of the second transition trench 2042 is not removed by etching, but is retained on the side wall of the second transition trench 2042. Therefore, in the ion implantation process of forming the fourth doped region 107, the third dielectric layer 206 also serves as a mask for ion implantation to help form the fourth doped region 107. In this embodiment, in the ion implantation process of forming the fourth doped region 107, the ion injection direction is vertical injection. The third dielectric layer 206 covers a part of the surface of the third doped region 106. Therefore, after ion implantation, a width difference is formed between the third doped region 106 and the fourth doped region 107, so as to form a stepped shape between the fourth doped region 107 and the third doped region 106. Among them, the fourth doped region 107, the third doped region 106, the second doped region 105, and the first doped region 104 have the same symmetry plane. In this embodiment, the fourth doped region 107 is connected to the second type of deep well region 102, and specifically, the fourth doped region 107 is connected to two second type of deep well regions 102.

[0072] Please refer to Figures 10 to 12 As shown, in an embodiment of the present invention, after forming the fourth doped region 107, a fourth dielectric layer 207 is formed on the surface of the hard mask layer 202 and the side wall of the third transition trench 2043. Then, the fourth dielectric layer 207 and the substrate 100 are etched to form a fourth transition trench 2044. Then, trivalent ions, such as boron ions, are implanted into the substrate 100 to form a body region 108. In this embodiment, silicon oxide is deposited on the surface of the hard mask layer 202 and the side wall of the third transition trench 2043 by chemical vapor deposition or plasma enhanced chemical vapor deposition to form the fourth dielectric layer 207. The side wall of the third transition trench 2043 includes the exposed surface of the third dielectric layer 206 and the exposed surface of the substrate 100. The present invention does not limit the thickness of the fourth dielectric layer 207. Then, the fourth dielectric layer 207 on the hard mask layer 202 and a part of the fourth dielectric layer 207 on the substrate 100 are etched away, and then the substrate 100 is etched to deepen the third transition trench 2043 to form a fourth transition trench 2044. The etching step is dry etching and can be carried out in multiple steps.

[0073] Please refer to Figures 10 to 12 As shown, in an embodiment of the present invention, the process of forming the fourth transition trench 2044 is described as the fourth etching step of the substrate 100. Among them, the etching depth of the fourth time of the substrate 100 is equal to the implantation depth of the fourth doping region 107. In this embodiment, the body region 108 is connected to the fourth doping region 107, and the body region 108 is connected to the first type of deep well region 101, and the body region 108 is connected to the second type of deep well region 102. Among them, the body region 108 is arranged between two second type of deep well regions 102. In this embodiment, the width W6 of the body region 108 is smaller than the width W5 of the fourth doping region 107, where the fourth doping region 107 covers the body region 108. In this embodiment, the body region 108 is symmetric about the symmetry plane of the second type of deep well region 102. In the step of forming the fourth transition trench 2044, specifically, the dielectric material on the side wall of the third transition trench 2043 will not be removed by etching, but is retained on the side wall of the third transition trench 2043. Therefore, in the ion implantation process of forming the body region 108, the fourth dielectric layer 207 will also serve as a mask for ion implantation to help form the body region 108. In this embodiment, in the ion implantation process of forming the body region 108, the ion injection direction is vertical injection. The fourth dielectric layer 207 covers a part of the surface of the fourth doping region 107. Therefore, after ion implantation, a width difference is formed between the fourth doping region 107 and the body region 108, thereby forming a stepped shape between the body region 108 and the fourth doping region 107. Among them, the body region 108, the fourth doping region 107, the third doping region 106, the second doping region 105, and the first doping region 104 have the same symmetry plane.

[0074] Please refer to Figures 12 to 14 As shown, in an embodiment of the present invention, after forming the body region 108, a fifth dielectric layer 208 is formed on the surface of the hard mask layer 202 and the side wall of the fourth transition trench 2044. Then, the fifth dielectric layer 208 and the substrate 100 are etched to form a fifth transition trench 2045. In this embodiment, silicon oxide is deposited on the surface of the hard mask layer 202 and the side wall of the fourth transition trench 2044 by chemical vapor deposition or plasma enhanced chemical vapor deposition, thereby forming the fifth dielectric layer 208. Among them, the side wall of the fourth transition trench 2044 includes the exposed surface of the fourth dielectric layer 207 and the exposed surface of the substrate 100. The present invention does not limit the thickness of the fifth dielectric layer 208. Then, the fifth dielectric layer 208 on the hard mask layer 202 and a part of the fifth dielectric layer 208 on the substrate 100 are etched away, and then the substrate 100 is etched, thereby deepening the fourth transition trench 2044 to form the fifth transition trench 2045. Among them, the etching step is dry etching and can be carried out in multiple steps.

[0075] Please refer toFigures 12 to 14 As shown, in an embodiment of the present invention, the process of forming the fifth transition trench 2045 is described as the fifth etching step of the substrate 100. Among them, the etching depth of the fifth time of the substrate 100 is greater than the ion implantation depth of the body region 108 and the first type of deep trench region 101. The fifth transition trench 2045 penetrates through the first type of deep trench region 101 and extends below the first type of deep trench region 101. In this embodiment, the width W6 of the body region 108 is greater than the width W7 of the fifth transition trench 2045. In the step of forming the fifth transition trench 2045, specifically, the dielectric material on the side wall of the fourth transition trench 2044 is not removed by etching but is retained on the side wall of the fourth transition trench 2044.

[0076] Please refer to Figures 14 to 16 As shown, in an embodiment of the present invention, after forming the fifth transition trench 2045, a reserved gate oxide layer 209 is formed on the hard mask layer 202 and the side wall of the fifth transition trench 2045. Then, the reserved gate oxide layer 209 is etched, and only the part of the reserved gate oxide layer 209 located at the bottom of the fifth transition trench 2045 is retained. In this embodiment, silicon oxide can be deposited on the surface of the hard mask layer 202 and the side wall of the third transition trench 2043 by chemical vapor deposition or plasma enhanced chemical vapor deposition to form the reserved gate oxide layer 209. It should be noted that the first dielectric layer 203, the second dielectric layer 205, the third dielectric layer 206, the fourth dielectric layer 207, and the fifth dielectric layer 208 form a stacked structure. When the reserved gate oxide layer 209 is deposited, the reserved gate oxide layer 209 also covers the stacked structure. Then, the reserved gate oxide layer 209 on the hard mask layer 202, the reserved gate oxide layer 209 on the stacked structure, and the reserved gate oxide layer 209 on the side wall of the fifth transition trench 2045 are etched by dry etching.

[0077] Please refer to Figures 16 to 19As shown, in an embodiment of the present invention, a gate oxide layer 210 is formed on the hard mask layer 202 and on the sidewalls of the fifth transition trench 2045. In this embodiment, silicon dioxide is deposited on the hard mask layer 202 and on the sidewalls of the fifth transition trench 2045 by chemical vapor deposition or plasma enhanced chemical vapor deposition or rapid thermal oxidation, thereby forming the gate oxide layer 210. The formed gate oxide layer 210 covers the reserved gate oxide layer 209. After removing the reserved gate oxide layer 209, the newly grown gate oxide layer 210 has better uniformity and better thickness consistency. The part of the reserved gate oxide layer 209 remaining at the bottom of the fifth transition trench 2045 can prevent voids from occurring in the deep trench film growth. After forming the gate oxide layer 210, the semiconductor device is annealed, so that the doping ions of the first doping region 104, the second doping region 105, the third doping region 106, and the fourth doping region 107 diffuse, and the doping regions originally distributed in a gradient manner can be distributed in a gradual change manner to form the drift region 10. In this embodiment, the ion concentration of the drift region 10 decreases along the direction close to the first type of deep well region 101, and the width of the drift region 10 decreases along the direction close to the first type of deep well region 101. Among them, the first dielectric layer 203, the second dielectric layer 205, the third dielectric layer 206, the fourth dielectric layer 207, and the fifth dielectric layer 208 are of the same material. Therefore, with annealing and time, the oxides deposited at different times can fuse with each other, thereby forming a more complete whole, that is, forming the field oxide layer 20.

[0078] Please refer to Figures 18 to 20As shown, in an embodiment of the present invention, a polysilicon layer 211 is then formed on the gate oxide layer 210, and the fifth transition trench 2045 is filled. In this embodiment, polysilicon is deposited on the gate oxide layer 210 by chemical vapor deposition or plasma enhanced chemical vapor deposition, filling the fifth transition trench 2045, and a polysilicon film-like structure is formed on the gate oxide layer 210 on the hard mask layer 202. With annealing and time, the oxides deposited at different times can fuse with each other to form a more complete whole, that is, the field oxide layer 20 is formed. Among them, the first dielectric layer 203, the second dielectric layer 205, the third dielectric layer 206, the fourth dielectric layer 207, and the fifth dielectric layer 208 can be materials with different dielectric constants. In this embodiment, the dielectric constants of the first dielectric layer 203, the second dielectric layer 205, the third dielectric layer 206, the fourth dielectric layer 207, and the fifth dielectric layer 208 change stepwise, and specifically can decrease stepwise. Since the depths of the first dielectric layer 203, the second dielectric layer 205, the third dielectric layer 206, the fourth dielectric layer 207, and the fifth dielectric layer 208 increase in sequence, in the finally formed field oxide layer 20, along the direction perpendicular to the surface of the substrate 100, the dielectric constant of the field oxide layer 20 changes stepwise. Specifically, in the direction away from the first surface of the substrate 100, the dielectric constant of the field oxide layer 20 can decrease stepwise. In this embodiment, after the polysilicon layer 211 is formed, the hard mask layer 202 and the interlayer dielectric layer 201 are removed, exposing the surface of the substrate 100, and making the surface of the polysilicon layer 211 flush with the surface of the substrate 100. In this embodiment, the polysilicon layer 211 above the hard mask layer 202, the gate oxide layer 210 above the hard mask layer 202, the hard mask layer 202, and the interlayer dielectric layer 201 are sequentially polished and removed by chemical mechanical polishing (CMP). While the hard mask layer 202 and the interlayer dielectric layer 201 are removed by chemical mechanical polishing, the field oxide layer 20 above the substrate 100 is also being polished and removed synchronously, and the polysilicon layer 211 in the fifth transition trench 2045 and above the substrate 100 is also being polished and removed synchronously. The polishing stop layer of the chemical mechanical polishing is the surface of the substrate 100. After polishing is completed, the surfaces of the substrate 100, the shallow trench isolation structure 103, the field oxide layer 20, and the polysilicon layer 211 are flush, as Figure 20 shown. After grinding is completed, the surface of the drift region 10 is also exposed.

[0079] Please refer to Figure 20As shown, in an embodiment of the present invention, the present invention provides a semiconductor structure, which includes a substrate 100, a field oxide layer 20, a drift region 10, and a polysilicon layer 211. A device trench is provided in the substrate 100, and the trench wall of the device trench is the trench wall of the substrate 100 that accommodates the field oxide layer 20. The device trench is not formed in one step, but is gradually formed along with the process of forming the field oxide layer 20. In this embodiment, the field oxide layer 20 is provided on the trench wall of the device trench. The field oxide layer 20 has a stepped structure, and the width of the stepped structure of the field oxide layer 20 decreases along the direction away from the first surface of the substrate 100. The substrate 100 has a first surface and a second surface. The first surface is the surface where the fifth transition trench 2045 is formed, and the first surface is away from the first type of deep well region 101, and the second surface is close to the first type of deep well region 101. In this embodiment, the drift region 10 is provided in the substrate 100. The drift region 10 is connected to the field oxide layer 20, and the drift region 10 is wrapped outside the field oxide layer 20. Along the direction away from the first surface of the substrate 100, the width of the drift region 10 decreases, and the ion doping concentration of the drift region 10 decreases. In this embodiment, the polysilicon layer 211 is filled in the device trench, and the polysilicon layer 211 is connected to the field oxide layer 20. Specifically, the polysilicon layer 211 is filled in the fifth transition trench 2045.

[0080] Please refer to Figures 20 to 22As shown, in an embodiment of the present invention, based on the semiconductor structure provided by the present invention, a semiconductor device is further formed. After forming the polysilicon layer 211, a first well region 109 and a second well region 110 are formed in the substrate 100. In this embodiment, trivalent ions, such as boron ions, are implanted into the substrate 100 to form the first well region 109. Pentavalent ions, such as phosphorus ions, are implanted into the substrate 100 to form the second well region 110. In this embodiment, the first well region 109 extends along a direction perpendicular to the first surface of the substrate 100 and extends to the surface of the second type of deep well region 102. The second well region 110 extends along a direction perpendicular to the first surface of the substrate 100 and extends to the surface of the first type of deep well region 101. Then, an electrode doping region 111 is formed in the second well region 110 and the drift region 10. In this embodiment, pentavalent ions, such as phosphorus ions, are implanted into the second well region 110 and the drift region 10 to form the electrode doping region 111. A base doping region 112 is formed in the first well region 109. In this embodiment, trivalent ions, such as boron ions, are implanted into the first well region 109 to form the base doping region 112. In this embodiment, the depth of the electrode doping region 111 in the substrate 100 is less than the depth of the shallow trench isolation structure 103 in the substrate 100. In this embodiment, the cross-sectional area of the first type of deep well region 101 is equal to that of the semiconductor device. The second type of deep well region 102 is rectangular, and the body region 108 is disposed in the second type of deep well region 102, and the body region 108 is a rectangular shape distributed with the same center as the second type of deep well region 102. In this embodiment, the first well region 109 and the second well region 110 are distributed in a zigzag shape, wherein the polysilicon layer 211 is rectangular and may specifically be square, and the center of the polysilicon layer 211 is the symmetry center of the semiconductor device.

[0081] Please refer to Figures 21 to 23As shown, in an embodiment of the present invention, a silicide layer 113 is then formed in the electrode doping region 111, the base doping region 112, and the polysilicon layer 211. In this embodiment, a metal can be deposited on the substrate 100 by Physical Vapor Deposition (PVD), such as depositing metal materials such as cobalt, titanium, and nickel to form a metal layer. Then, the metal layer is annealed to cause the silicon substrate and the metal to react to form the silicide layer 113. In this embodiment, the silicide layer 113 is formed on the upper portions of the electrode doping region 111 and the base doping region 112. After the silicide layer 113 is formed, a contact electrode 400 is formed on the silicide layer 113, thereby forming an electrical connection structure of the semiconductor device. In this embodiment, the contact electrode 400 is a Contact (CT). In this embodiment, the contact electrode 400 connected to the silicide layer 113 on the polysilicon layer 211 is the gate G. The contact electrode 400 connected to the silicide layer 113 in the second well region 110 is the source S. The contact electrode 400 connected to the silicide layer 113 in the first well region 109 is the base B. The contact electrode 400 connected to the silicide layer 113 in the drift region 10 is the drain D. In this embodiment, the drain D is located between the base B and the gate G, and the base B is located between the drain D and the source S. The specific use of the semiconductor device of the present invention is not limited, and the contact electrode 400 can be called according to the integrated circuit design.

[0082] The present invention provides a semiconductor device and a manufacturing method thereof, and its unexpected technical effect is as follows: The present invention provides a field oxide layer with a stepped structure and is paired with a drift region having a concentration gradient. While the concentration gradient of the drift region decreases, the region width also decreases, and at the same time, the cross-sectional area of the field oxide layer also decreases. Thus, under the condition that the call area of the semiconductor device remains unchanged, the breakdown voltage performance of the semiconductor device is effectively improved. Moreover, the present invention can reduce the device size and lower the on-resistance of the device while ensuring the longitudinal breakdown voltage performance of the device. It can not only optimize the breakdown voltage of the device but also reduce the on-resistance of the device, and bidirectionally optimizes the relationship between the breakdown voltage and the on-resistance of the device. And according to the manufacturing method of the semiconductor structure provided by the present invention, while forming the concentration gradient of the drift region, a field oxide layer with a stepped structure is formed. The process is mature, which can improve the forming yield of the semiconductor device, and the process controllability is high, which can effectively reduce device defects.

[0083] The embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and variations can be made according to the content of this specification. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of the present invention, so that those skilled in the art can well understand and utilize the present invention. The present invention is only limited by the claims and their full scope and equivalents.

Claims

1. A semiconductor device, characterized in that: include: A substrate, wherein a device trench is provided in the substrate; A field oxide layer is disposed on a groove wall of the device groove, the field oxide layer has a stepped structure, and a width of the stepped structure decreases along a direction away from a first surface of the substrate, wherein the first surface is a surface of the substrate forming the device groove; A drift region is disposed in the substrate, the drift region is connected to the field oxide layer, and the drift region is wrapped outside the field oxide layer, wherein along a direction away from the first surface of the substrate, the width of the drift region decreases, and the ion doping concentration of the drift region decreases; as well as A polysilicon layer is filled in the device trench, and the polysilicon layer is connected to the field oxide layer.

2. A semiconductor device according to claim 1, characterized in that: Surfaces of the field oxide layer, the drift region, the substrate, and the polysilicon layer are flush.

3. A semiconductor device according to claim 1, characterized in that: The dielectric constant of the field oxide layer decreases stepwise in a direction away from the first surface of the substrate.

4. A semiconductor device according to claim 1, characterized in that: The semiconductor device comprises a plurality of shallow trench isolation structures, wherein the shallow trench isolation structures are arranged in the substrate, and the plurality of shallow trench isolation structures separate a plurality of active regions in the substrate, wherein the drift region is arranged in the active region.

5. A semiconductor device according to claim 4, characterized in that: The semiconductor device comprises: A first type deep well region is disposed in the substrate, wherein the first type deep well region and the drift region are doped with the same ion type; and A second type of deep well region is arranged in the substrate, the second type of deep well region is arranged on the first type of deep well region and connected to the first type of deep well region, wherein the drift region is arranged on the second type of deep well region and connected to the second type of deep well region, wherein the doping ion types of the second type of deep well region and the drift region are different.

6. A semiconductor device according to claim 5, characterized in that: The semiconductor device includes a body region, which is arranged between two of the second-type deep well regions, and the body region is connected to the first-type deep well region and the second-type deep well region, and the body region is connected to the drift region, wherein the body region and the second-type deep well region have the same doping ion type.

7. A semiconductor device according to claim 6, characterized in that: The device trench passes through the body region and the first type deep well region and extends to below the first type deep well region, and the polysilicon layer extends along a direction perpendicular to the first surface and toward the second surface of the substrate, wherein the first surface and the second surface are parallel, wherein one end of the polysilicon layer is flush with the first surface, and the other end of the polysilicon layer extends to below the first type deep well region.

8. A semiconductor device according to claim 5, characterized in that: The semiconductor device comprises: a first well region, disposed in the substrate, the first well region being located in the active region outside the drift region, and the first well region being connected to the second-type deep well region, wherein the first well region and the second-type deep well region have the same doping ion type; and A second well region is arranged in the substrate, the second well region is located in the active region outside the first well region, and the second well region is connected to the first type of deep well region, wherein the second well region and the first type of deep well region have the same doping ion type.

9. A semiconductor device according to claim 1, characterized in that: The polysilicon layer has a symmetry plane, the semiconductor device is a symmetrical structure, and the semiconductor device is symmetrical about the symmetry plane, wherein the drift region is symmetrical about the symmetry plane, and the field oxide layer is symmetrical about the symmetry plane.

10. A method for manufacturing a semiconductor device, characterized in that: The following steps are involved: providing a substrate; Stepwise forming a device trench in the substrate, while gradually forming the device trench, forming a field oxide layer on the trench wall of the device trench, wherein the field oxide layer has a step structure, and the width of the step structure decreases along a direction away from a first surface of the substrate, wherein the first surface is a surface of the substrate on which the device trench is formed; While gradually forming the device trenches, gradually forming a plurality of doped regions in the substrate; After the annealing treatment, the plurality of doped regions form a drift region, wherein the drift region is connected to the field oxide layer and the drift region is wrapped outside the field oxide layer, wherein along a direction away from the first surface of the substrate, the width of the drift region decreases, and the ion doping concentration of the drift region decreases; and The device trench is filled to form a polysilicon layer, wherein the polysilicon layer is connected to the field oxide layer.

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